A photodetector and its fabrication method

Abstract

This invention discloses a photodetector, comprising a substrate, a low-dimensional semiconductor layer on the substrate, a first electrode, a second electrode, and a local gate. The first and second electrodes are located at opposite ends of the low-dimensional semiconductor layer, forming a channel region between them. The local gate is located within the channel region and has a distance between it and the first and second electrodes. A local gate dielectric is present between the local gate and the low-dimensional semiconductor layer, and the width of the local gate dielectric is greater than or equal to the width of the local gate. This invention introduces localized bandgap in the channel through electrostatic doping of the local gate, forming a local barrier, suppressing carrier tunneling, reducing dark current, and thus improving photodetection performance.

Description

Technical Field

[0001] This invention relates to an optoelectronic device and its fabrication method, and more particularly to a carbon nanotube photodetector and its fabrication method. Background Technology

[0002] Infrared photoelectric detection is a very important direction in the field of optical detection. In the field of short-wave infrared detection, although traditional infrared detectors and materials have good performance, their fabrication process is complex, it is difficult to fabricate high-quality materials on a large scale, and there are bottlenecks such as difficulty in highly integrating with silicon-based readout amplifier circuits and high price, which make it difficult to apply on a large scale. Low-cost, high-performance infrared detection that is easy to integrate at room temperature for short-wave infrared has not been well realized.

[0003] Carbon nanotubes, as a representative of one-dimensional semiconductor materials, possess unique and excellent electrical, optical, and thermal properties, and are considered representative for constructing nanoscale integrated electronic devices. However, in carbon nanotube thin film systems prepared by solution purification methods, the low work function metals are difficult to form good ohmic contacts due to the influence of polymers wrapped around the carbon nanotubes and the surface, resulting in a large reverse-biased dark current. Furthermore, asymmetric contact carbon nanotube photodetectors exhibit a higher dark current level during reverse-biased operation compared to traditional PIN structure photodetectors. With the increase in dark current, the diode's noise current increases, the detectivity decreases, and the detection performance deteriorates. Summary of the Invention

[0004] This invention provides an infrared photodetector and its manufacturing method, which can reduce dark current and improve detection performance.

[0005] In a first aspect, embodiments of the present invention provide a photodetector substrate and a low-dimensional semiconductor layer on the substrate;

[0006] Substrate and low-dimensional semiconductor layer on the substrate;

[0007] The first electrode and the second electrode are located at opposite ends of the low-dimensional semiconductor layer, forming a channel region between the first electrode and the second electrode, and the first electrode and the second electrode are made of different materials.

[0008] A local gate structure is located at the center of the channel region, having a distance between the first electrode and the second electrode. The local gate structure includes a local gate and a local gate dielectric, with the local gate dielectric located between the local gate and the low-dimensional semiconductor layer.

[0009] In one possible implementation of the first aspect, the local gate structure is a local bottom gate structure located between the substrate and the low-dimensional semiconductor layer.

[0010] In one possible implementation of the first aspect, the local gate and the local gate dielectric are embedded in the substrate such that the local gate dielectric and the substrate are in the same plane.

[0011] In one possible implementation of the first aspect, the local gate is a local top gate structure located above a low-dimensional semiconductor layer.

[0012] In one possible implementation of the first aspect, the substrate includes at least one of a SiO2 / Si substrate, a quartz substrate, an Al2O3 substrate, a glass substrate, or a polymer substrate.

[0013] In one possible implementation of the first aspect, the low-dimensional semiconductor layer includes at least one of carbon nanotubes, silicon nanowires, and nanowires of group II-VI elements, nanowires of group III-V elements, or two-dimensional layered semiconductor materials, wherein the carbon nanotubes are further preferably single-walled carbon nanotubes, multi-walled carbon nanotubes, network carbon nanotubes, or carbon nanotube arrays, and the two-dimensional layered semiconductor material is further preferably black phosphorus or molybdenum disulfide.

[0014] In one possible implementation of the first aspect, the distance between the local gate and the first electrode and the electrode is greater than or equal to 20 nm.

[0015] In one possible implementation of the first aspect, the width of the local gate is 10%-90% of the width of the channel region.

[0016] In one possible implementation of the first aspect, the local gate is selected from one of hafnium (Hf), aluminum (Al), titanium (Ti), palladium (Pd) or gold (Au), or an alloy or stack of the aforementioned metals.

[0017] In one possible implementation of the first aspect, the gate dielectric includes at least one of hafnium oxide (HfO2), aluminum oxide (Al2O3), yttrium oxide (Y2O3), zirconium oxide (ZrO2), or boron nitride.

[0018] In one possible implementation of the first aspect, the first electrode is a high work function metal, including one of palladium (Pd), molybdenum (Mo), nickel (Ni) or cobalt (Co), or an alloy or stack of the above metals.

[0019] In one possible implementation of the first aspect, the second electrode is a low work function metal, including one of scandium (Sc), hafnium (Hf), yttrium (Y) or erbium (Er) or an alloy or stack of the above metals.

[0020] Secondly, embodiments of the present invention propose a method for fabricating a photodetector, the specific steps of which are as follows:

[0021] A substrate is provided, and a low-dimensional semiconductor layer is formed on the substrate;

[0022] A first electrode pattern is defined on a low-dimensional semiconductor layer, and a first metal layer is deposited on the first electrode pattern to form a first electrode; further, a second electrode pattern is defined on the low-dimensional semiconductor layer, and a second electrode metal layer is formed on the second electrode pattern to form a second electrode;

[0023] A local gate dielectric is formed on the low-dimensional semiconductor layer channel region between the first electrode and the second electrode, and a local gate is further formed on the local gate dielectric.

[0024] In one possible implementation of the second aspect, another local gate dielectric is formed on the local gate, forming a three-layer local gate structure of gate dielectric / gate metal / gate dielectric.

[0025] Thirdly, embodiments of the present invention provide a method for fabricating a photodetector, the specific steps of which are as follows:

[0026] Provide a substrate;

[0027] A local gate and a local gate dielectric are formed on a substrate, and then a low-dimensional semiconductor layer is formed on the local gate and the gate dielectric.

[0028] A first electrode pattern is defined on a low-dimensional semiconductor layer, and a first metal layer is deposited on the first electrode pattern to form a first electrode; further, a second electrode pattern is defined on the low-dimensional semiconductor layer, and a second electrode metal layer is formed on the second electrode pattern to form a second electrode.

[0029] In one possible implementation of the third aspect, a localized groove is formed in the substrate by photolithography, and the localized gate electrode and the localized gate dielectric are embedded in the localized groove, such that the localized gate dielectric and the substrate are on the same plane.

[0030] In this embodiment of the invention, the photodetector introduces local band bending in the channel through the electrostatic doping effect of the local gate, forming a local barrier to suppress carrier tunneling. The carbon nanotube photodiode does not rely on external voltage to drive and control the behavior of carriers, but relies on the electric field formed by the band bending in the vicinity of the gold semiconductor contact within a range of about tens of nanometers to separate photogenerated excitons. Thus, the local gate structure of this invention can reduce the dark current of the device with minimal loss or change in photocurrent, improve the zero bias differential resistance, and enhance the detection performance of the carbon nanotube infrared photodetector. Attached Figure Description

[0031] The invention can be better understood from the following description of specific embodiments of the invention taken in conjunction with the accompanying drawings, wherein the same or similar reference numerals denote the same or similar features.

[0032] Figure 1 This is a schematic diagram of a local top grid structure embodiment of the present invention;

[0033] Figure 2 This is a three-dimensional structural diagram of a local top grid structure embodiment of the present invention;

[0034] Figure 3 This is a schematic diagram of a local bottom grid structure embodiment of the present invention;

[0035] Figure 4 This is a schematic diagram of an embodiment of the embedded local bottom gate structure of the present invention;

[0036] Figure 5 This is a schematic diagram of the formation of a carbon nanotube layer on a substrate according to an embodiment of the present invention;

[0037] Figure 6 This is a schematic diagram of the formation of the first electrode according to an embodiment of the present invention;

[0038] Figure 7 This is a schematic diagram of the formation of the second electrode according to an embodiment of the present invention;

[0039] Figure 8 This is a schematic diagram of the bottom local gate medium formed according to an embodiment of the present invention;

[0040] Figure 9 This is a schematic diagram of the bottom local gate electrode formation according to an embodiment of the present invention;

[0041] Figure 10 This is a schematic diagram of the band structure in an embodiment of the present invention;

[0042] Figure 11 This is the IV curve of different local gate voltages under dark state with a gate voltage of 0V in an embodiment of the present invention;

[0043] Figure 12 for Figure 11 The corresponding zero-bias differential resistance extracted;

[0044] Figure 13 This is the IV curve of different local gate voltages at a bottom gate voltage of 20V in the dark state according to an embodiment of the present invention;

[0045] Figure 14 for Figure 13 The corresponding zero-bias differential resistance extracted;

[0046] Figure 15 The IV curve of the bottom grid at 20V under illumination; Detailed Implementation

[0047] Embodiments of the present invention will now be described in detail with reference to the accompanying drawings. In the drawings, the same elements are represented by the same reference numerals, and the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown. For simplicity, the semiconductor structure obtained after several steps can be depicted in a single figure.

[0048] It should be understood that when describing the structure of a device, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above another layer or region, or that there are other layers or regions between it and another layer or region. Furthermore, if the device is flipped, that layer or region will be located "below" or "under" another layer or region.

[0049] To describe a situation where A is directly above another layer or region, this document will use the expressions "A is directly above B" or "A is above and adjacent to B". In this application, "A is directly located in B" means that A is located in B and A is directly adjacent to B, rather than A being located in a doped region formed in B.

[0050] This embodiment describes an infrared photodetector with an asymmetric structure, such as... Figure 1 As shown, the infrared photodetector has a Si / SiO2 substrate, which includes a heavily doped silicon substrate 101 and a SiO2 dielectric layer 102 thereon. In other embodiments, a quartz substrate, Al2O3 substrate, glass substrate, or polymer substrate may also be used. A low-dimensional semiconductor layer 103 is provided on the SiO2 dielectric layer 102, which in this embodiment uses single-walled carbon nanotubes. In other embodiments, the low-dimensional semiconductor layer includes at least one of carbon nanotubes, silicon nanowires, and group II-VI element nanowires, group III-V element nanowires, or two-dimensional layered semiconductor materials. Further, the carbon nanotubes may be multi-walled carbon nanotubes, network carbon nanotubes, or carbon nanotube arrays, and the two-dimensional layered semiconductor material may further be black phosphorus or molybdenum disulfide.

[0051] The low-dimensional semiconductor layer 103 has a first electrode 104 and a second electrode 105 at both ends. The first electrode is a high work function metal, such as one of palladium (Pd), molybdenum (Mo), nickel (Ni), or cobalt (Co), or an alloy or stack of the above metals. In this embodiment, palladium (Pd) is used as the first electrode, and its thickness is 10 nm. In other embodiments, the thickness of the palladium (Pd) metal can be adjusted between 10 nm and 120 nm. The second electrode is a low work function metal, such as one of scandium (Sc), hafnium (Hf), yttrium (Y), or erbium (Er), or an alloy or stack of the above metals. In this embodiment, scandium (Sc) is used as the second electrode, and its thickness is 10 nm. In other embodiments, the thickness of the scandium (Sc) metal can be adjusted between 10 nm and 120 nm. The first and second electrodes are made of different metals to form an asymmetric structure. The role of the asymmetric metal electrodes is to form a barrier-free contact between the metal palladium (Pd) and scandium (Sc) and the carbon nanotube. By adjusting the work function of the metal, an undoped carbon nanotube diode can be realized.

[0052] The low-dimensional semiconductor layer between the first and second electrodes forms the channel region of the photodetector. A local gate 107 is located within this channel region, with a distance L between the local gate 107 and the first and second electrodes. Exciton dynamics simulations reveal that excitons primarily separate within a 10nm range close to the electrodes; this 10nm range represents the effective exciton separation region. To avoid affecting effective exciton separation, the newly constructed local gate needs a distance greater than 10nm from the electrodes; in this embodiment, this distance is 20nm. In other embodiments, the local gate 107 can be located at other positions within the channel region, beyond 20nm from the first and second electrodes. The maximum 90% ratio of the local gate to the channel width is also based on this consideration. 10% is taken into account for the local gate's modulation effect; currently, dark current modulation effects are poor below 10% width.

[0053] A local gate dielectric layer 106 is provided between the local gate 107 and the channel layer. The lateral width of the local gate dielectric layer 106 is greater than the width of the local gate 107 to ensure that the local gate electrode 107 does not leak current. In some other embodiments, the lateral width of the local gate dielectric layer 106 may also be equal to the width of the local gate. In this embodiment, the width of the local gate 107 is 10% of the channel width; in other embodiments, the width of the local gate can be in the range of 10%-90%. In this embodiment, the material of the local gate dielectric 106 is hafnium oxide (HfO2). In other embodiments, the local gate dielectric is at least one of hafnium oxide (HfO2), aluminum oxide (Al2O3), yttrium oxide (Y2O3), zirconium oxide (ZrO2), or boron nitride, or a stack of the above materials. In another embodiment, another gate dielectric layer may be overlaid on the aforementioned local gate 107. In this embodiment, the gate dielectric layer is an oxide layer, forming a sandwich structure of gate dielectric / gate metal / gate dielectric. In other embodiments, the gate dielectric may also be a two-dimensional insulating material (e.g., boron nitride), an organic material, or a combination thereof.

[0054] Furthermore, the photodetector is coated with a 20nm thick Al2O3 encapsulation medium 108, which encapsulates the low-dimensional semiconductor layer 103, the local gate 107, the local gate dielectric 106, the first electrode 104, and the second electrode 105. In other embodiments, the encapsulation medium 108 may also be spin-coated glass (SOG) or silicon nitride (SiN). x The structure consists of silicon dioxide (SiO2), with a thickness ranging from 10 nm to 2 μm. A three-dimensional schematic diagram of the final device structure can be found in [reference needed]. Figure 2 .

[0055] In another embodiment, the aforementioned local gate is a bottom gate structure, specifically as follows: Figure 3 As shown, a localized bottom gate 207 is formed on a Si / SiO2 substrate, and a localized gate dielectric 206 is formed on the localized bottom gate 207, the width of which is greater than the width of the localized bottom gate 207. Further, a single-walled carbon nanotube layer 203 is formed on the above structure, along with a first electrode 204 and a second electrode 205 located at both ends of the single-walled carbon nanotube layer 203. Then, an encapsulation dielectric 208 is coated onto the single-walled carbon nanotube layer, ultimately forming a photodetector with a localized bottom gate. The material selection for each layer can be the same as that for the aforementioned top gate structure.

[0056] In another embodiment, such as Figure 4As shown, a localized bottom gate 307 is embedded in a Si / SiO2 substrate, and a localized gate dielectric 306 embedded in the substrate is located at a position corresponding to the localized bottom gate 307. The width of the localized gate dielectric 306 is greater than or equal to the width of the localized bottom gate 307, and the localized gate dielectric 306 and the substrate are on the same plane. Subsequently, a single-walled carbon nanotube layer 303 is formed on the aforementioned plane, and a first electrode 304 and a second electrode 305 are located at both ends of the single-walled carbon nanotube layer 303. Then, an encapsulation dielectric 308 is coated on the single-walled carbon nanotube layer, ultimately forming a photodetector with a localized bottom gate. The material selection of the above layers can be the same as that of the aforementioned top gate structure.

[0057] Another embodiment of the present invention describes a method for fabricating the aforementioned asymmetric infrared photodetector. First, a Si / SiO2 substrate is provided. A carbon nanotube layer is obtained on the Si / SiO2 substrate by chemical vapor deposition (CVD) or by dropping a dispersed carbon nanotube solution onto the substrate, thereby forming a low-dimensional semiconductor layer 103. Figure 5 As shown. In another embodiment, 3 nm of yttrium metal can be deposited, oxidized at 200°C for 20 minutes, and washed in 1:10 hydrochloric acid for 15 minutes to remove surface polymers. In another embodiment, the above-mentioned carbon nanotube layer can be formed by a Czochralski method. First, a carbon nanotube solution is prepared, and the carbon nanotubes are dissolved in one or more halogenated hydrocarbons, preferably organic solvents such as chloroform, dichloroethane, trichloroethane, chlorobenzene, dichlorobenzene, and bromobenzene. Then, the above-mentioned Si / SiO2 substrate is clamped on a Czochralski machine and immersed in the above-mentioned carbon nanotube solution. Subsequently, the carbon nanotube layer is formed on the substrate by Czochralski, thereby forming a low-dimensional semiconductor layer 103.

[0058] A photoresist is coated on the aforementioned low-dimensional semiconductor layer 103 and a palladium (Pd) electrode pattern is formed by photolithography or electron beam lithography. The photolithographically lithographic sample is placed in an electronic or thermal evaporation system, and a 90nm thick metal Pd thin film is deposited after vacuuming. Subsequently, the sample is placed in acetone for stripping to remove the residual metal layer.

[0059] A scandium (Sc) electrode pattern is formed on a low-dimensional semiconductor layer 103 by photoresist coating and photolithography or electron beam lithography. The photolithographically patterned sample is then placed into a magnetron sputtering system, using metallic scandium (Sc) with a purity of over 98% as the target material, and the vacuum is evacuated to 5 × 10⁻⁶. -6 To obtain an asymmetric diode structure, a pre-sputtering process is first used to further remove oxides from the surface of the scandium (Sc) target. Then, a 90 nm thick layer of metallic scandium (Sc) is sputtered at a rate of 1 A / s. In another embodiment, electron beam evaporation can be used to obtain metallic scandium (Sc).

[0060] Based on the fabricated asymmetric diode, a localized gate dielectric pattern is defined in the channel using photolithography or electron beam lithography. The gate dielectric is grown using atomic layer deposition (ALD), chemical vapor deposition (CVD), or transfer methods, and residual dielectric is removed by stripping. In another embodiment, a full-surface gate dielectric layer can be grown first, then the localized gate dielectric pattern is defined using photolithography or electron beam lithography, followed by etching to form the localized gate dielectric. Subsequently, the localized gate electrode pattern is defined using photolithography or electron beam lithography, and metal is deposited by electron beam evaporation, magnetron sputtering, or thermal evaporation, finally stripped to form the localized gate electrode. In another embodiment, the localized top-gate process can also employ a self-aligned approach, i.e., metal is deposited directly after gate dielectric growth, followed by stripping.

[0061] In another embodiment, after forming the local gate electrode, another local gate dielectric can be further formed on it, forming a three-layer local gate structure of gate dielectric / gate metal / gate dielectric, wherein the other local gate dielectric is an oxide layer. In some other embodiments, the gate dielectric can also be a two-dimensional insulating material (e.g., boron nitride), an organic material, or a combination thereof. Finally, an encapsulation dielectric layer is formed on the aforementioned local gate by chemical vapor deposition.

[0062] In another embodiment, an asymmetric photodiode with a bottom-gate structure is fabricated using a local bottom-gate process. First, a Si / SiO2 substrate is provided. A local bottom-gate electrode pattern is defined using photolithography or electron beam lithography. Then, metal is deposited using electron beam evaporation, magnetron sputtering, or thermal evaporation to form the local bottom-gate electrode. Subsequently, a gate dielectric is grown using atomic layer deposition (ALD), chemical vapor deposition (CVD), or transfer. After transferring carbon nanotubes, asymmetric contact electrodes are fabricated. In another embodiment, an embedded buried gate structure can be used. First, a Si / SiO2 substrate is provided. Then, a local bottom-gate pattern is defined on the SiO2. This pattern is then etched to form a groove structure. Metal is deposited in the groove structure using electron beam evaporation, magnetron sputtering, or thermal evaporation to form the local bottom-gate electrode. Then, a gate dielectric is grown using atomic layer deposition (ALD) or chemical vapor deposition (CVD). Finally, chemical mechanical polishing (CMP) is used to bring the gate dielectric and the SiO2 substrate to the same plane. Then, carbon nanotubes are grown on the surface via chemical vapor deposition (CVD) or by dropping a dispersed carbon nanotube solution onto the surface to obtain carbon nanotubes on a Si / SiO2 substrate. Alternatively, 3 nm of yttrium is deposited, oxidized at 200°C for 20 minutes, and then washed in 1:10 hydrochloric acid for 15 minutes to remove surface polymers. Next, palladium (Pd) electrode patterns and scandium (Sc) are formed on the surface of the carbon nanotube layer, using the same formation process as the aforementioned top-gate structure. Finally, a 50 nm layer of Al2O3 encapsulation medium is grown on the obtained surface structure via atomic layer deposition (ALD).

[0063] Localized gate structures are used in carbon nanotube photodiodes. Through the electrostatic doping effect of the localized gate, local band bending is introduced in the channel, forming a local barrier, which suppresses carrier tunneling, reduces dark current, and improves detection performance. Figure 11 This is the IV curve in the dark state. It shows that at 0V gate voltage, the introduction of the local gate suppresses the dark current of the device, and the dark current gradually decreases with changing gate voltage, approaching saturation at a gate voltage of 1.5V. Further, the differential resistance at zero bias voltage can be extracted based on the dark state curve. Figure 12 As shown, the introduction of a local gate can increase the zero-bias differential resistance by an order of magnitude. Figure 13 The IV curve is for a 20V gate voltage, similar to that for a 0V gate voltage. It can be seen that the local gate can effectively suppress dark current, and the zero bias differential resistance of the device is increased by an order of magnitude. Figure 14 The curves are IV curves under illumination, and the photocurrent is not significantly affected by changes in the local gate voltage.

[0064] Although the present invention has been described in detail above with general descriptions and specific embodiments, modifications or improvements can be made to it, which will be obvious to those skilled in the art. Therefore, all such modifications or improvements made without departing from the spirit of the present invention fall within the scope of protection claimed by the present invention.

Claims

1. A photodetector, comprising: The application relates to a photodetector, comprising: a substrate and a low-dimensional semiconductor layer on the substrate, the low-dimensional semiconductor layer comprising carbon nanotubes; a first electrode and a second electrode, respectively located at two ends of the low-dimensional semiconductor layer, a channel region being formed between the first electrode and the second electrode, and the first electrode and the second electrode having different materials, the first electrode being a high work function metal, comprising one of palladium (Pd), molybdenum (Mo), nickel (Ni) or cobalt (Co) or an alloy or a stack composed of the above-mentioned metals; the second electrode being a low work function metal, comprising one of scandium (Sc), hafnium (Hf), yttrium (Y) or erbium (Er) or an alloy or a stack composed of the above-mentioned metals; a local gate structure, the local gate structure being located at a central position on the channel region and having a spacing from the first electrode and the second electrode, the local gate structure comprising a local gate and a local gate dielectric, the local gate dielectric being located between the local gate and the low-dimensional semiconductor layer; the spacing of the local gate from the first electrode and the second electrode being greater than or equal to 20 nm, and the width of the local gate being 10%-90% of the width of the channel region. The local gate structure is a local bottom gate structure located between the substrate and the low-dimensional semiconductor layer. The local gate and the local gate dielectric are embedded in the substrate, so that the local gate dielectric is in the same plane as the substrate. The local gate structure is a local top gate structure located above the low-dimensional semiconductor layer. There is another local gate dielectric layer above the local gate, forming a three-layer local gate structure of gate dielectric / gate metal / gate dielectric.

2. The photodetector of claim 1, wherein, The substrate comprises at least one of a SiO2 / Si substrate, a quartz substrate, an Al2O3 substrate, a glass substrate or a polymer substrate.

3. The photodetector of claim 2, wherein, The low-dimensional semiconductor layer comprises at least one of carbon nanotubes, silicon nanowires and II-VI element nanowires, III-V element nanowires or two-dimensional layered semiconductor materials, the carbon nanotubes being single-walled carbon nanotubes, multi-walled carbon nanotubes, networked carbon nanotubes or carbon nanotube arrays, and the two-dimensional layered semiconductor material being black phosphorus or molybdenum disulfide.

4. The photodetector of claim 1, wherein, The local gate is selected from one of hafnium (Hf), aluminum (Al), titanium (Ti), palladium (Pd) or gold (Au) or an alloy or a stack composed of the above-mentioned metals.

5. The photodetector of claim 4, wherein, The local gate dielectric comprises at least one of hafnium oxide (HfO2), aluminum oxide (Al2O3), yttrium oxide (Y2O3), zirconium oxide (ZrO2) or boron nitride (BN).

6. The photodetector of claim 1, wherein, 10. A method for manufacturing a photodetector according to any one of claims 1-3, comprising: providing a substrate and forming a low-dimensional semiconductor layer on the substrate, the low-dimensional semiconductor layer comprising carbon nanotubes; defining a first electrode pattern on the low-dimensional semiconductor layer, depositing a first metal layer on the first electrode pattern to form a first electrode; and further defining a second electrode pattern on the low-dimensional semiconductor layer, forming a second electrode metal layer on the second electrode pattern to form a second electrode.

7. The photodetector of claim 1, wherein, ​ 8. The photodetector of any one of claims 1-6, wherein, ​ 9. The photodetector of claim 1, wherein, ​ ​ ​ ​ A local gate dielectric is formed on a low-dimensional semiconductor layer channel region between the first electrode and the second electrode, and a local gate electrode is further formed on the local gate dielectric, the distance between the local gate electrode and the first electrode and the second electrode is greater than or equal to 20 nm, and the width of the local gate electrode is 10%-90% of the width of the channel region.

11. The method of fabricating a photodetector of claim 10, wherein, A further local gate dielectric is further formed on the local gate electrode to form a gate dielectric / gate metal / gate dielectric three-layer local gate structure.

12. A method for manufacturing a photodetector as claimed in claim 1 or 4, characterized in that, a substrate is provided; a local gate electrode and a local gate dielectric are formed on the substrate, and then a low-dimensional semiconductor layer is formed on the local gate electrode and the gate dielectric, the low-dimensional semiconductor layer comprising carbon nanotubes; a first electrode pattern is defined on the low-dimensional semiconductor layer, a first metal layer is deposited on the first electrode pattern to form a first electrode; and a second electrode pattern is further defined on the low-dimensional semiconductor layer, a second electrode metal layer is formed on the second electrode pattern to form a second electrode; the distance between the local gate electrode and the first electrode and the second electrode is greater than or equal to 20 nm, and the width of the local gate electrode is 10%-90% of the width of the channel region.

13. The method of fabricating a photodetector of claim 12, wherein, a local recess is formed in the substrate by a photolithography process, and the local gate electrode and the local gate dielectric are embedded in the local recess, and the local gate dielectric is in the same plane as the substrate.

Images