Semiconductor element and method for manufacturing the same

Abstract

A semiconductor device and a method of fabricating the same are disclosed. The method of fabricating the semiconductor device includes forming a magnetic tunneling junction (MTJ) on a substrate, forming a first spin orbit torque (SOT) layer on the MTJ, forming a protective layer on the MTJ, forming a second SOT layer on the first SOT layer and the protective layer, and patterning the second SOT layer and the protective layer.

Description

Technical Field

[0001] This invention relates to a method for manufacturing semiconductor devices, and more particularly to a method for manufacturing magnetoresistive random access memory (MRAM) devices. Background Technology

[0002] Magnetoresistance (MR) is the effect of a material's resistance changing with the application of a magnetic field. Its physical quantity is defined as the rate of change of resistance, calculated by dividing the resistance difference (with and without a magnetic field) by the original resistance. Currently, the magnetoresistance effect has been successfully applied in hard disk manufacturing, demonstrating significant commercial value. Furthermore, by utilizing the characteristic that giant magnetoresistance materials have different resistance values ​​under different magnetization states, magnetic random access memory (MRAM) can be fabricated, offering the advantage of retaining stored data even without power.

[0003] The aforementioned magnetoresistive effect is also applied in the field of magnetic field sensing, such as in the electronic compass components of mobile phones that integrate with the Global Positioning System (GPS) to provide users with information such as their location. Currently, various magnetic field sensing technologies are available on the market, such as anisotropic magnetoresistive (AMR) sensing elements, giant magnetoresistive (GMR) sensing elements, and magnetic tunneling junction (MTJ) sensing elements. However, these existing technologies typically have drawbacks, including larger chip area, higher manufacturing costs, higher power consumption, insufficient sensitivity, and susceptibility to temperature changes, necessitating further improvements. Summary of the Invention

[0004] One embodiment of the present invention discloses a method for fabricating a semiconductor device, which first forms a magnetic tunneling junction (MTJ) on a substrate, then forms a first spinorbit torque (SOT) layer on the MTJ, forms a protective layer next to the MTJ, forms a second SOT layer on the first SOT layer and the protective layer, and then patterns the second SOT layer and the protective layer.

[0005] Another embodiment of the present invention discloses a semiconductor device, which mainly includes a magnetic tunneling junction (MTJ) disposed on a substrate, a first spin orbit torque (SOT) layer disposed on the MTJ, a protective layer surrounding the MTJ, and a second SOT layer disposed on the first SOT layer and the protective layer. Attached Figure Description

[0006] Figures 1 to 10 This is a schematic diagram illustrating a method for fabricating an MRAM cell according to an embodiment of the present invention.

[0007] Explanation of main component symbols

[0008] 12: Base

[0009] 14: MRAM region

[0010] 16: Logical Area

[0011] 18: Interlayer dielectric layer

[0012] 20: Metal interconnect structure

[0013] 22: Metal interconnect structure

[0014] 24: Intermetallic dielectric layer

[0015] 26: Metal interconnects

[0016] 28: Stop Layer

[0017] 30: Intermetallic dielectric layer

[0018] 32: Metal interconnects

[0019] 34: Barrier Layer

[0020] 36: Metal layer

[0021] 38: Lower electrode

[0022] 40: MTJ stacked structure

[0023] 42: Upper electrode

[0024] 44: First SOT layer

[0025] 46: Patterned Mask

[0026] 48:MTJ

[0027] 50: Covering layer

[0028] 52: Protective layer

[0029] 54: Second SOT layer

[0030] 56: Intermetallic dielectric layer

[0031] 58: Metal interconnects

[0032] 60: Stop Layer

[0033] 62: Intermetallic dielectric layer

[0034] 64: Metal interconnects Detailed Implementation

[0035] Please refer to Figures 1 to 10 , Figures 1 to 10 This is a schematic diagram illustrating a method for fabricating an MRAM cell according to an embodiment of the present invention. Figure 1 As shown, a substrate 12 is first provided, for example, a substrate 12 made of a semiconductor material, wherein the semiconductor material can be selected from the group consisting of silicon, germanium, silicon-germanium composite, silicon carbide, gallium arsenide, etc., and an MRAM region 14 and a logic region 16 are preferably defined on the substrate 12.

[0036] The substrate 12 may contain active (active) devices such as metal-oxide-semiconductor (MOS) transistors, passive (passive) devices, conductive layers, and dielectric layers such as interlayer dielectric (ILD) 16 covering it. More specifically, the substrate 12 may contain planar or non-planar (such as fin structure transistors) MOS transistor devices, wherein the MOS transistors may include gate structures (such as metal gates) and source / drain regions, spacers, epitaxial layers, contact hole etch stop layers, and other transistor elements. The interlayer dielectric layer 18 may be disposed on the substrate 12 and cover the MOS transistors, and the interlayer dielectric layer 18 may have multiple contact plugs electrically connecting the gate and / or source / drain regions of the MOS transistors. Since the fabrication processes of planar or non-planar transistors and interlayer dielectric layers are well known in the art, they will not be described in detail here.

[0037] Then, metal interconnect structures 20 and 22 are sequentially formed on the interlayer dielectric layer 18 to electrically connect the aforementioned contact plug. The metal interconnect structure 20 includes an intermetal dielectric layer 24 and a metal interconnect 26 embedded in the intermetal dielectric layer 24. The metal interconnect structure 22 includes a stop layer 28, an intermetal dielectric layer 30 and a metal interconnect 32 embedded in the stop layer 28 and the intermetal dielectric layer 30.

[0038] In this embodiment, each metal interconnect 26 in the metal interconnect structure 20 preferably includes a trench conductor, and the metal interconnect 32 in the MRAM region 14 of the metal interconnect structure 22 includes a via conductor. Furthermore, each metal interconnect 26 and 32 in the metal interconnect structures 20 and 22 can be embedded in the inter-metal dielectric layers 24 and 30 and / or the stop layer 28 and electrically connected to each other using a single damascene fabrication process or a double damascene fabrication process. For example, each metal interconnect 26 and 32 may further include a barrier layer 34 and a metal layer 36, wherein the barrier layer 34 can be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), and the metal layer 36 can be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium-aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc., but is not limited thereto. Since single-damascene or dual-damascene fabrication processes are well-known in the art, they will not be described in detail here. Furthermore, in this example, the metal layer 36 in the metal interconnect 26 preferably contains copper, the metal layer 36 in the metal interconnect 32 preferably contains tungsten, the intermetallic dielectric layers 24 and 30 preferably contain silicon oxide such as tetraethylorthosilicate (TEOS), and the stop layer 28 contains a nitrogen-doped carbide (NDC), silicon nitride, or silicon carbon nitride (SiCN), but is not limited thereto.

[0039] Next, a lower electrode 38, an MTJ stack structure 40, an upper electrode 42, a first spin orbit torque (SOT) layer 44, and a patterned mask 46 are formed on the metal interconnect structure 22. In this embodiment, the MTJ stack structure 40 can be formed by first sequentially forming a pinned layer, a barrier layer, and a free layer on the lower electrode 38. In this embodiment, the lower electrode 38 and the upper electrode 42 preferably contain conductive materials, such as, but not limited to, tantalum (Ta), tantalum nitride (TaN), platinum (Pt), copper (Cu), gold (Au), and aluminum (Al). The pinned layer may contain ferromagnetic materials such as, but not limited to, cobalt-iron-boron (CoFeB), cobalt-iron (CoFe), iron (Fe), and cobalt (Co). In addition, the fixing layer can also be made of antiferromagnetic (AFM) materials, such as iron-manganese (FeMn), platinum-manganese (PtMn), iridium-manganese (IrMn), and nickel oxide (NiO), to fix or restrict the magnetic moment direction of adjacent layers. The barrier layer can be made of insulating materials containing oxides, such as aluminum oxide (AlO). x The free layer can be made of ferromagnetic materials, such as iron, cobalt, nickel, or their alloys, such as cobalt-iron-boron (CoFeB), but is not limited to these. The magnetization direction of the free layer can be "freely" changed by an external magnetic field. In this embodiment, the first SOT layer 44 is preferably a channel for a spin orbit torque (SOT) MRAM, therefore its material can include tantalum (Ta), tungsten (W), platinum (Pt), hafnium (Hf), bismuth selenide (Bi). x Se 1-x (or a combination thereof). The patterned mask 46 may contain conductive or dielectric materials, such as, but not limited to, titanium nitride.

[0040] Subsequently, as Figures 1 to 2As shown, using a patterned mask 46 as a mask, one or more etching processes are performed to remove a portion of the first SOT layer 44, a portion of the upper electrode 42, a portion of the MTJ stack structure 40, a portion of the lower electrode 38, and a portion of the intermetallic dielectric layer 30 to form multiple MTJs 48 in the MRAM region 14, and then the patterned mask 46 is removed. It is worth noting that the etching process performed on the patterned upper electrode 42, MTJ stack structure 40, lower electrode 38, and intermetallic dielectric layer 30 in this embodiment may include reactive ion etching (RIE) and / or ion beam etching (IBE). Due to the characteristics of the ion beam etching process, the remaining upper surface of the intermetallic dielectric layer 30 is preferably slightly lower than the upper surface of the metal interconnect 32, and the upper surface of the intermetallic dielectric layer 30 preferably presents an arc or curved surface. It should also be noted that when removing part of the intermetallic dielectric layer 30 using the ion beam etching process in this embodiment, part of the metal interconnects 32 can be removed at the same time, so that the metal interconnects 32 form an inclined sidewall near the junction of MTJ 48.

[0041] A masking layer 50 is then formed on the MTJ 48, covering the surface of the intermetallic dielectric layer 30 of the MRAM region 14 and the logic region 16. In this embodiment, the masking layer 50 preferably comprises silicon nitride, but other dielectric materials such as, but not limited to, silicon oxide, silicon oxynitride, or silicon carbide may be selected according to the fabrication process requirements.

[0042] Then as Figure 3 As shown, an atomic layer deposition (ALD) process is performed in conjunction with an etch-back process to form a protective layer 52 covering the intermetallic dielectric layer 30 of the MTJ 48 and the logic region 16. In this embodiment, the protective layer 52 preferably comprises silicon oxide, but is not limited to this. Furthermore, it should be noted that after removing part of the protective layer 52 and part of the masking layer 50 using the etch-back process in this stage, the top surface of the remaining protective layer 52 is preferably flush with the top surface of the masking layer 50 but slightly lower than the top surface of the first SOT layer 44, so that the first SOT layer 44 slightly protrudes from the protective layer 52.

[0043] Subsequently, as Figure 4 As shown, a second SOT layer 54 is formed on the first SOT layer 44 and the protective layer 52. In this embodiment, the second SOT layer 54 and the first SOT layer 44 preferably contain the same material, wherein the second SOT layer 54 also serves as a channel for a spin orbit torque (SOT) MRAM, and therefore its material may include tantalum (Ta), tungsten (W), platinum (Pt), hafnium (Hf), bismuth selenide (Bi). x Se1-x (or a combination thereof.) It should also be noted that the second SOT layer 54 formed in this stage is preferably conformally disposed on the surface of the first SOT layer 44 and the protective layer 52. Therefore, the top surface of the second SOT layer 54 disposed above the protective layer 52 is preferably lower than the top surface of the second SOT layer 54 disposed directly above the first SOT layer 44.

[0044] like Figure 5 As shown, a pattern transfer process is then performed, using a patterned mask (not shown) as a mask to remove part of the second SOT layer 54 located on the protective layer 52, so that the remaining second SOT layer 54 is still located on the protective layer 52 on both sides of the first SOT layer 44.

[0045] Subsequently, as Figure 6 As shown, another patterning process is performed, for example, using the remaining second SOT layer 54 as a mask to remove part of the protective layer 52, part of the masking layer 50 and part of the intermetallic dielectric layer 30, wherein the remaining intermetallic dielectric layer 30 still extends from the MRAM region 14 to the logic region 16.

[0046] like Figure 7 As shown, an intermetallic dielectric layer 56 is then formed on the second SOT layer 54 and the intermetallic dielectric layers 30 on both sides. The intermetallic dielectric layer 56 is preferably conformally disposed on the second SOT layer 54, and the intermetallic dielectric layer 56 includes an ultra-low dielectric constant dielectric layer, which may include, for example, a porous dielectric material such as, but not limited to, silicon carbide (SiOC) or silicon carbide hydrogen (SiOCH).

[0047] like Figure 8 As shown, a planarization process is then performed, for example, a chemical mechanical polishing (CMP) process or an etch-back process can be used to remove part of the intermetallic dielectric layer 56, but the top surface of the remaining intermetallic dielectric layer 56 is still higher than the top surface of the second SOT layer 54.

[0048] Subsequently, as Figure 9As shown, a pattern transfer fabrication process is performed, for example, by using a patterned mask (not shown) to remove part of the inter-metal dielectric layer 56, part of the inter-metal dielectric layer 30, and part of the stop layer 28 between MRAM region 14 and logic region 16 to form contact holes (not shown) and expose the underlying metal interconnects 26. Then, the contact holes are filled with the desired metal material, such as a barrier layer material including titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc., and a low-resistance metal layer selected from low-resistance materials or combinations thereof, such as tungsten (W), copper (Cu), aluminum (Al), titanium-aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc. Next, a planarization fabrication process is performed, for example, by chemical mechanical polishing to remove part of the metal material to form contact plugs or metal interconnects 58 electrically connecting the metal interconnects 26 within the contact holes.

[0049] like Figure 10 As shown, a stop layer 60 is first formed in the MRAM region 14 and the logic region 16, covering the intermetallic dielectric layer 56 and the metal interconnects 58. An intermetallic dielectric layer 62 is then formed on the stop layer 60. One or more photolithography and etching processes are performed to remove part of the intermetallic dielectric layer 62 and part of the stop layer 60 in the MRAM region 14 and the logic region, forming contact holes (not shown). Next, conductive material is filled into each contact hole, and a planarization process such as CMP is used to form metal interconnects 64 in the MRAM region 14 and the logic region 16, respectively, electrically connecting the underlying MTJ 48 and the metal interconnects 58. Preferably, the metal interconnects 64 in the MRAM region 14 directly contact the underlying second SOT layer 54, while the metal interconnects 64 in the logic region 16 contact the underlying metal interconnects 58.

[0050] In this embodiment, stop layer 60 and stop layer 28 may contain the same or different materials, both of which can be selected from the group consisting of nitrogen-doped carbide (NDC), silicon nitride, and silicon carbon nitride (SiCN). As with the aforementioned metal interconnects, the metal interconnects 64 disposed within the intermetallic dielectric layer 62 can be embedded within the intermetallic dielectric layer 62 using a single damascene fabrication process or a double damascene fabrication process. For example, the metal interconnects 64 may further include a barrier layer and a metal layer, wherein the barrier layer can be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), while the metal layer can be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium-aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc., but is not limited thereto. Since single-damascene or dual-damascene fabrication processes are well-known in the art, they will not be described in detail here. This completes the fabrication of a semiconductor element according to an embodiment of the present invention.

[0051] Please refer to again Figure 10 , Figure 10 A schematic diagram of the structure of a semiconductor device according to an embodiment of the present invention is also disclosed. For example... Figure 10 As shown, the semiconductor device mainly includes an MTJ 48 disposed on a substrate 12, a first SOT layer 44 disposed on the MTJ 48, a cover layer 50 disposed next to the MTJ 48, a protective layer 52 surrounding the cover layer 50 and the MTJ 48, a second SOT layer 54 disposed on the first SOT layer 44 and the protective layer 52, an intermetallic dielectric layer 56 surrounding the protective layer 52 and the cover layer 50, an intermetallic dielectric layer 62 disposed on the MTJ 48 and the intermetallic dielectric layer 56, and a metal interconnect 64 disposed within the intermetallic dielectric layer 62 and electrically connected to the MTJ 48.

[0052] In detail, the top surfaces of the cover layer 50 and the protective layer 52 are slightly lower than the top surface of the first SOT layer 44. The sidewalls of the first SOT layer 44 are flush with the sidewalls of the lower electrode 38, MTJ 48 and the upper electrode 42. The sidewalls of the second SOT layer 54 are flush with the sidewalls of the protective layer 52 and the cover layer 50. The top surface of the second SOT layer 54 located above the protective layer 52 is lower than the top surface of the second SOT layer 54 located above the first SOT layer 44.

[0053] It should also be noted that although the top surface of the intermetallic dielectric layer 56 surrounding the second SOT layer 54 in this embodiment is slightly higher than the top surface of the second SOT layer 54, it is not limited thereto. In other embodiments of the present invention, the top surface of the second SOT layer 54 may be exposed, or even slightly lower than, the top surface of the second SOT layer 54, during the aforementioned planarization process when part of the intermetallic dielectric layer 56 is removed. In other words, the top surface of the intermetallic dielectric layer 56 may be higher than the top surface of the second SOT layer 54 located directly above the first SOT layer 44, flush with the top surface of the second SOT layer 54 located directly above the first SOT layer 44, or flush with the top surface of the second SOT layer 54 located directly above the protective layer 52. These variations are all within the scope of the present invention.

[0054] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, Include: A magnetic tunnel junction is formed on the substrate; A first spin-orbit torque layer is formed on the magnetic tunneling junction; A protective layer is formed next to the magnetic tunnel junction; A second spin-orbit torque layer is formed on the first spin-orbit torque layer and the protective layer; and The second spin-orbit torque layer is patterned so that the remaining second spin-orbit torque layer is disposed on the protective layer on both sides of the first spin-orbit torque layer, and the remaining second spin-orbit torque layer is used as a mask to pattern the protective layer; the top surface of the second spin-orbit torque layer disposed above the protective layer is lower than the top surface of the second spin-orbit torque layer disposed above the first spin-orbit torque layer.

2. The method of claim 1, wherein the substrate comprises an MRAM region and a logic region, the method comprising: A first intermetallic dielectric layer is formed on the substrate; A first metal interconnect is formed within the first metal inter-dielectric layer; The magnetic tunnel junction is formed on the first metal interconnect. A masking layer is formed on the first spin-orbit torque layer and the first intermetallic dielectric layer; The protective layer is formed on the covering layer; The second spin-orbit torque layer is formed on the first spin-orbit torque layer and the protective layer; The second spin-orbit torque layer, the protective layer, the cover layer, and the first intermetallic dielectric layer are patterned. A second intermetallic dielectric layer is formed on the second spin-orbit torque layer and the first intermetallic dielectric layer; The first metal interconnect is formed in the MRAM region and the third metal interconnect is formed in the logic region; as well as A stop layer is formed on the second intermetallic dielectric layer, the second intermetallic interconnect, and the third intermetallic interconnect.

3. The method of claim 2, wherein the top surface of the second metal interconnect is flush with the top surface of the third metal interconnect and the second metal inter-dielectric layer.

4. The method of claim 2, wherein the top surface of the covering layer is lower than the top surface of the first spin-orbit torque layer.

5. The method of claim 2, wherein the second spin-orbit torque layer sidewall is flush with the cover layer sidewall.

6. The method of claim 1, wherein the top surface of the protective layer is lower than the top surface of the first spin-orbit torque layer.

7. The method of claim 1, wherein the first spin-orbit torque layer sidewall is flush with the magnetic tunnel junction sidewall.

8. The method of claim 1, wherein the second spin-orbit torque layer sidewall is flush with the protective layer sidewall.

9. A semiconductor element, characterized in that, Include: A magnetic tunnel junction is disposed on a substrate; A first spin-orbit torque layer is disposed on the magnetic tunnel junction; A protective layer surrounds the magnetic tunnel junction; and A second spin-orbit torque layer is disposed on the first spin-orbit torque layer and the protective layer; the sidewall of the second spin-orbit torque layer is flush with the protective layer; the top surface of the second spin-orbit torque layer disposed above the protective layer is lower than the top surface of the second spin-orbit torque layer disposed above the first spin-orbit torque layer.

10. The semiconductor element of claim 9, further comprising: A first intermetallic dielectric layer is disposed on the substrate; The first metal interconnect is disposed within the first metal inter-dielectric layer; The magnetic tunneling junction is located on the first metal internal interconnect; A shielding layer is disposed beside the magnetic tunnel junction; and A second intermetallic dielectric layer surrounds the protective layer and the shielding layer.

11. The semiconductor device of claim 10, wherein the top surface of the masking layer is lower than the top surface of the first spin-orbit torque layer.

12. The semiconductor device of claim 10, wherein the second spin-orbit torque layer sidewall is flush with the masking layer sidewall.

13. The semiconductor device of claim 9, wherein the top surface of the protective layer is lower than the top surface of the first spin-orbit torque layer.

14. The semiconductor device of claim 9, wherein the first spin-orbit torque layer sidewall is flush with the magnetic tunnel junction sidewall.

15. The semiconductor device of claim 9, wherein the second spin-orbit torque layer sidewall is flush with the protective layer sidewall.

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