A high-efficiency three-phase PFC rectifier circuit and control method compatible with boost and buck control

Abstract

The application discloses a high-efficiency three-phase PFC rectifier circuit and a control method compatible with boost and buck control, and the circuit comprises an input filter circuit, a power switch circuit, an output filter circuit and a control circuit. Through the implementation of the application, six groups of reversely connected MOS transistors are used in the power switch circuit, thereby solving the problem that only boost control or buck control can be realized and the output voltage adjustment range of the DC side is small in the prior art. A MOS transistor is added to the rectifier output end to form an inductive current freewheeling loop, the conduction power loss of the rectifier during freewheeling is significantly reduced, the converter efficiency is greatly improved, the rectifier can be used in high-power application occasions, and compared with a traditional three-phase Boost PFC rectifier or a Buck PFC rectifier, the application has the advantages of simple structure, wide input voltage range, high conversion efficiency, high power factor, simple control, low cost and the like.

Description

Technical Field

[0001] This invention belongs to the field of power electronics technology, specifically relating to a high-efficiency three-phase PFC rectifier circuit and control method compatible with both boost and buck control. Background Technology

[0002] With the widespread use of power electronic devices, especially those with low power factor, a large number of harmonics are generated in the power grid, affecting power quality and grid losses, and in severe cases, causing equipment malfunctions or even damage. Applying power factor correction technology to power electronic devices can effectively reduce the impact of harmonics on the power grid and improve equipment efficiency. Therefore, high-performance three-phase rectifiers are particularly important. Furthermore, the AC output voltage of generators in multi-electric aircraft typically varies by 3 to 5 times or even more. Generally, the wider the input voltage range, the lower the conversion efficiency of the power converter. Therefore, there is an urgent need for high-efficiency power converter technology that can adapt to a wide voltage range input while also suppressing grid harmonics.

[0003] Currently, in the field of three-phase rectifiers, when operating in buck mode, to prevent discontinuous DC-side inductor current, a bridge arm must be continuously connected at all times. This means that the three bridge arms form a freewheeling circuit for the inductor current, resulting in low efficiency and making it unsuitable for high-power applications. Therefore, in applications requiring a wide input voltage range, high power factor, and high conversion efficiency, existing topologies cannot meet the requirements. Summary of the Invention

[0004] To address the aforementioned technical problems, this invention provides a high-efficiency three-phase PFC rectifier circuit and control method compatible with both boost and buck control.

[0005] The present invention is achieved through the following technical solutions.

[0006] The present invention provides a high-efficiency three-phase PFC rectifier circuit compatible with boost and buck control, including an input filter circuit, a power switch circuit, an output filter circuit, and a control circuit. The input filter circuit is connected to the power switch circuit, the power switch circuit is connected to the output filter circuit, and the output terminal of the control circuit is connected to the power switch circuit. The input filter circuit includes inductors La, Lb, and Lc, and capacitors Ca, Cb, and Cc; the power switching circuit includes a power bridge circuit and a freewheeling circuit. The power bridge circuit includes power MOSFETs Qa1, Qa2, Qa3, Qa4, Qb1, Qb2, Qb3, Qb4, Qc1, Qc2, Qc3, and Qc4; the freewheeling circuit includes a power MOSFET Qd; the output filter circuit includes inductor Ldc and capacitor Co. One end of the inductor La is connected to the A-phase voltage, and the other end is connected to one end of the capacitor Ca; one end of the inductor Lb is connected to the B-phase voltage, and the other end is connected to one end of the capacitor Cb; one end of the inductor Lc is connected to the C-phase voltage, and the other end is connected to one end of the capacitor Cc; the other ends of the capacitor Ca, the other ends of the capacitor Cb, and the other ends of the capacitor Cc are connected together. One end of the inductor Ldc is connected to one end of the capacitor Co, and the other end of the inductor Ldc and the other end of the capacitor Co are respectively connected to the control circuit. The drain of power MOSFET Qa1 is connected to the other end of inductor Ldc; the source of power MOSFET Qa1 is connected to the source of power MOSFET Qa2; the drain of power MOSFET Qa2 is connected to the other end of inductor La; and the gate of power MOSFET Qa1 is connected to the gate of power MOSFET Qa2. The drain of power MOSFET Qa3 is connected to the other end of inductor La; the source of power MOSFET Qa3 is connected to the source of power MOSFET Qa4; the drain of power MOSFET Qa4 is connected to the other end of capacitor Co; and the gate of power MOSFET Qa3 is connected to the gate of power MOSFET Qa4. Similarly, the drain of power MOSFET Qb1 is connected to the other end of inductor Ldc; the source of power MOSFET Qb1 is connected to the source of power MOSFET Qb2; the drain of power MOSFET Qb2 is connected to the other end of inductor Lb; and the gate of power MOSFET Qb1 is connected to the gate of power MOSFET Qb2. The drain of power MOSFET Qb3 is connected to the other end of inductor Lb. The sources of power MOSFETs Qb3 and Qb4 are connected, the drain of Qb4 is connected to the other end of capacitor Co, and the gate of Qb3 is connected to the gate of Qb4. The drain of power MOSFET Qc1 is connected to the other end of inductor Ldc, the source of Qc1 is connected to the source of power MOSFET Qc2, the drain of Qc2 is connected to the other end of inductor Lc, and the gate of Qc1 is connected to the gate of Qc2. The drain of power MOSFET Qc3 is connected to the other end of inductor Lc, the source of Qc3 is connected to the source of power MOSFET Qc4, the drain of Qc4 is connected to the other end of capacitor Co, and the gate of Qc3 is connected to the gate of Qc4. The drain of power MOSFET Qd is connected to the other end of inductor Ldc, and the source of Qd is connected to the other end of capacitor Co.

[0007] Furthermore, it also includes an auxiliary power supply, which is connected to the control circuit.

[0008] Furthermore, the other end of the inductor Ldc is connected to an auxiliary power supply.

[0009] Furthermore, the other end of the capacitor Co is connected to an auxiliary power supply.

[0010] Furthermore, it also includes a resistor RL, which is connected in parallel with a capacitor Co.

[0011] Furthermore, the control circuit has a three-phase input voltage signal and a three-phase input current signal at its input terminal, and a power switch circuit at its output terminal.

[0012] A control method for a high-efficiency three-phase PFC rectifier circuit compatible with both boost and buck control includes the following steps: Step 1: Determine the numerical relationship between the three-phase input voltage and the DC output voltage setting value Vref of the three-phase PFC rectifier; Step 2: Based on the numerical relationships obtained in Step 1, switch between boost control, buck control, and synchronous rectification control operating modes, specifically as follows: When the DC output voltage setting value Vref is satisfied At that time, the three-phase rectifier converter operates in buck mode; When the DC output voltage setting value Vref is satisfied At that time, the three-phase rectifier converter operates in boost mode; When the DC output voltage setting value Vref is satisfied At that time, the three-phase rectifier converter operates in synchronous rectification mode; Where Vref is the DC output voltage setting value, Um is the peak line voltage of the rectifier's three-phase input voltage, and ΔU% represents the fluctuation range of the grid voltage.

[0013] Furthermore, the three-phase input voltages have the same amplitude, but their phases differ by 120° sequentially.

[0014] The beneficial effects of this invention are as follows: By using six sets of reverse-connected MOSFETs in the bridge arms of a three-phase PFC rectifier, a high power factor on the grid side and adaptability to a wide input AC voltage range are achieved. The corresponding control method solves the problem in existing technologies where only boost or buck control is possible, resulting in a small DC-side output voltage adjustment range. For this three-phase PFC rectifier compatible with both boost and buck control, when the bridge arm MOSFETs are turned off, the input and output are isolated, and there is no current path. In the circuit of this invention, the direct-through condition of the upper and lower bridge arms of the same phase is a normal operating state and will not damage the rectifier. Therefore, it has a low starting current and reliable short-circuit current suppression capability. When the three-phase rectifier operates in buck mode, to prevent discontinuous DC-side inductor current, a freewheeling circuit is constructed using component Qd. This reduces the freewheeling loss to 1 / 4 of the freewheeling loss using the bridge arms, greatly improving converter efficiency, reducing the difficulty of product heat dissipation design, and improving reliability, making it suitable for high-power applications. Compared with traditional three-phase Boost PFC rectifiers or Buck PFC rectifiers, this invention has outstanding advantages such as simple structure, wide grid-side input voltage range, high conversion efficiency, high power factor, simple control, and low cost. Attached Figure Description

[0015] Figure 1 This is a block diagram of the circuit topology of the present invention; Figure 2 This is the power bridge circuit diagram of the present invention; Figure 3 This is a block diagram illustrating the rectifier control principle of the present invention; Figure 4 This is the output control logic diagram for the rectifier buck mode of the present invention. Detailed Implementation

[0016] The technical solution of the present invention is further described below, but the scope of protection is not limited to what is described.

[0017] like Figure 1-2As shown, a high-efficiency three-phase PFC rectifier circuit compatible with boost and buck control includes an input filter circuit, a power switch circuit, an output filter circuit, and a control circuit. The input filter circuit is connected to the power switch circuit, the power switch circuit is connected to the output filter circuit, and the output terminal of the control circuit is connected to the power switch circuit. The input filter circuit includes inductors La, Lb, and Lc, and capacitors Ca, Cb, and Cc. The power switch circuit includes a power bridge circuit and a freewheeling circuit. The power bridge circuit includes power MOSFETs Qa1, Qa2, Qa3, Qa4, Qb1, and Qc. The circuit includes power MOSFETs Qb2, Qb3, Qb4, Qc1, Qc2, Qc3, and Qc4; a freewheeling circuit includes power MOSFET Qd; and an output filter circuit includes inductor Ldc and capacitor Co. One end of inductor La is connected to phase A voltage, and the other end is connected to one end of capacitor Ca. One end of inductor Lb is connected to phase B voltage, and the other end is connected to one end of capacitor Cb. One end of inductor Lc is connected to phase C voltage, and the other end is connected to one end of capacitor Cc. The other ends of capacitors Ca, Cb, and Cc are connected together. One end of inductor Ldc is connected to... One end of capacitor Co is connected to the control circuit, and the other end of inductor Ldc and capacitor Co are respectively connected to the control circuit. The drain of power MOSFET Qa1 is connected to the other end of inductor Ldc, the source of power MOSFET Qa1 is connected to the source of power MOSFET Qa2, the drain of power MOSFET Qa2 is connected to the other end of inductor La, and the gate of power MOSFET Qa1 is connected to the gate of power MOSFET Qa2. The drain of power MOSFET Qa3 is connected to the other end of inductor La, the source of power MOSFET Qa3 is connected to the source of power MOSFET Qa4, and the drain of power MOSFET Qa4 is connected to the other end of capacitor Co. The gate of transistor 3 is connected to the gate of power MOSFET Qa4; the drain of power MOSFET Qb1 is connected to the other end of inductor Ldc; the source of power MOSFET Qb1 is connected to the source of power MOSFET Qb2; the drain of power MOSFET Qb2 is connected to the other end of inductor Lb; the gate of power MOSFET Qb1 is connected to the gate of power MOSFET Qb2; the drain of power MOSFET Qb3 is connected to the other end of inductor Lb; the source of power MOSFET Qb3 is connected to the source of power MOSFET Qb4; the drain of power MOSFET Qb4 is connected to the other end of capacitor Co; the gate of power MOSFET Qb3 is connected to the gate of power MOSFET Qb4.The drain of power MOSFET Qc1 is connected to the other end of inductor Ldc; the source of power MOSFET Qc1 is connected to the source of power MOSFET Qc2; the drain of power MOSFET Qc2 is connected to the other end of inductor Lc; and the gate of power MOSFET Qc1 is connected to the gate of power MOSFET Qc2. The drain of power MOSFET Qc3 is connected to the other end of inductor Lc; the source of power MOSFET Qc3 is connected to the source of power MOSFET Qc4; the drain of power MOSFET Qc4 is connected to the other end of capacitor Co; and the gate of power MOSFET Qc3 is connected to the gate of power MOSFET Qc4. The drain of power MOSFET Qd is connected to the other end of inductor Ldc; and the source of power MOSFET Qd is connected to the other end of capacitor Co.

[0018] It also includes an auxiliary power supply, which is connected to the control circuit; the other ends of inductor Ldc and capacitor Co are both connected to the auxiliary power supply. It also includes a resistor RL, which is connected in parallel with capacitor Co. The control circuit input terminals receive three-phase input voltage and three-phase input current signals, and the output terminal is connected to a power switching circuit.

[0019] In use, the three-phase AC power supply is connected to the input filter circuit. The output terminal of the input filter circuit is connected to the three-phase rectifier network. The output terminal of the three-phase rectifier is connected to the freewheeling circuit. The downstream end of the freewheeling circuit is connected to the output filter circuit. A load is connected between the positive and negative terminals of the output of the output filter circuit.

[0020] The operating state of the rectifier is determined by the three-phase input voltage on the AC side and the switching states of the rectifier bridge transistors. Therefore, when analyzing the working principle of this rectifier, the switching states of the rectifier bridge transistors must be analyzed first. The control method of this rectifier is implemented according to the following steps: Step 1: Determine the numerical relationship between the three-phase input voltage and the DC output voltage setting value Vref of the three-phase PFC rectifier; Step 2: Based on the numerical relationships obtained in Step 1, switch between boost control, buck control, and synchronous rectification control operating modes, specifically as follows: When the DC output voltage setting value Vref is satisfied At this time, the three-phase rectifier converter operates in buck mode; when the DC output voltage setpoint Vref satisfies At this time, the three-phase rectifier converter operates in boost mode; when the DC output voltage setpoint Vref satisfies At that time, the three-phase rectifier converter operates in synchronous rectification mode; Where Vref is the DC output voltage setting value, Um is the peak line voltage of the rectifier's three-phase input voltage, and ΔU% represents the fluctuation range of the grid voltage. The three-phase input voltages have the same amplitude and are sequentially 120° out of phase.

[0021] To facilitate the analysis of the entire operation of the rectifier, the following assumptions are made: 1. The three-phase voltages VA, VB, and VC on the grid side have the same amplitude and are 120° out of phase; 2. The saturation problem of the input inductor is not considered; 3. The dead time of the power switching transistors is not considered; 4. The three-phase rectifier operates at unity power factor.

[0022] When the rectifier operates in boost mode, it is powered by... Figure 1 and Figure 2 As shown in the rectifier main circuit structure, the rectifier has three bridge arms: A, B, and C. The switching signals of the upper and lower bridge arms of each phase satisfy a complementary logic relationship. To prevent overcurrent problems caused by bridge arm shoot-through, a dead time needs to be set for the drive signals of the switching transistors on the same bridge arm. The drive signal of the three-phase rectifier is obtained by comparing a sinusoidal modulated wave with a triangular carrier wave; this signal is called a binary logic signal. For PWM modulation, since each bridge arm has two switching modes, namely, the upper bridge arm is on or the lower bridge arm is on, it is described using a binary logic switching function pk (k=a, b, c), i.e. (1) When pk=1, the upper bridge arm switch is turned on; when pk=-1, the lower bridge arm switch is turned on. Thus, the six bridge arm switches have a total of 2³=8 possible operating modes. When synthesizing the target vector, selecting an appropriate zero state can minimize the switching state transitions and make the system operation more stable.

[0023] (2) In equation (2), Xa, Xb, and Xc represent the time during which the high-level conduction is maintained within one switching cycle.

[0024] When the rectifier operates in buck mode, a freewheeling circuit for the inductor current is formed through component Qd to prevent discontinuous DC-side inductor current.

[0025] Since binary logic signals cannot represent the situation where a bridge arm is shoot-through, a new switching logic signal is needed for control. This signal is called the ternary logic signal δ. k (k=a,b,c) can be represented as: (3) According to the ternary logic signal expression shown in equation (3), there are 9 operating modes for the three-phase rectifier step-down operation. When the ternary logic signal is all 0, component Qd is turned on. The voltage drop of component Qd is only 1 / 4 of the voltage drop when using the same bridge arm freewheeling mode. Therefore, the DC side can choose to perform synchronous freewheeling through component Qd instead of the traditional zero vector freewheeling mode. This not only eliminates the logic control links such as 60° interval judgment and zero state judgment, but also significantly reduces the conduction power loss of the rectifier and ensures that the DC side inductor current always has a path. During the switching state switching process of a modulation wave cycle, in order to reduce switching losses, the principle of minimizing the number of switching times of the switching transistor during each operating mode transition should also be followed when selecting the switching transistor state.

[0026] (4) Figure 1 A PFC circuit topology compatible with three-phase boost and buck control is presented. Figure 2 This is a three-phase full-bridge circuit diagram, where VA, VB, and VC are the grid-side phase voltages; ia, ib, and ic are the grid-side phase currents; isa, isb, and isc are the AC-side currents; inductors La, Lb, and Lc, and capacitors Ca, Cb, and Cc constitute the grid-side LC filter, which filters out high-frequency harmonics on the AC side, making the grid phase current sinusoidal, and acts as an energy storage inductor when the rectifier is boosting; on each half-bridge arm, components Qx1 and Qx2 are connected in reverse series to enhance the reverse blocking capability of the switching transistors; to prevent discontinuous DC-side inductor current, a freewheeling circuit is formed through component Qd; the DC-side inductor Ldc and capacitor Co work together to ensure stable output voltage and current. Vdc is the DC-side output voltage; iLdc is the DC-side inductor current; idc is the DC current; and RL is the load resistance.

[0027] The three-phase rectifier network includes six sets of reverse-connected MOSFETs. The drain of power MOSFET Qx1 is connected to the input of the DC-side filter circuit; the source of power MOSFET Qx1 is connected to the source of power MOSFET Qx2; the drain of power MOSFET Qx2 is connected to the output of the AC-side filter circuit; and the gate of power MOSFET Qx1 is connected to the gate of power MOSFET Qx2. The drain of power MOSFET Qx3 is connected to the output of the AC-side filter circuit; the source of power MOSFET Qx3 is connected to the source of power MOSFET Qx4; the drain of power MOSFET Qx4 is connected to the negative terminal of the DC side; and the gate of power MOSFET Qx3 is connected to the gate of power MOSFET Qx4. Here, x represents a, b, and c. Power MOSFETs Qx1 and Qx2 are switched on and off simultaneously, and the gates of power MOSFETs Qx3 and Qx4 are switched on and off simultaneously. When the gate of the power MOSFET is not driven, power MOSFETs Qx1 and Qx3 can prevent current from flowing from the DC output terminal to the AC input terminal.

[0028] When the three-phase rectifier operates in boost mode, the switching signals of the upper and lower arms of each phase satisfy a complementary logic relationship. To prevent overcurrent problems caused by arm shoot-through, a dead time is set for the drive signals of the switching transistors on the same arm. The drive signal of the three-phase rectifier is obtained by comparing a sinusoidal modulated wave with a triangular carrier wave. At any given time, only the upper arm or the lower arm of each phase is turned on.

[0029] When the three-phase rectifier operates in buck mode, and the three-valued logic signal is all 0, component Qd is turned on, ensuring that the DC-side inductor current always has a path. During the switching state transition process of one modulation wave cycle, in order to reduce switching losses, the principle of minimizing the number of switching transistor switching times during each operating mode transition should be followed when selecting the switching transistor state.

[0030] This invention reduces the freewheeling current loss to one-quarter of that of using a bridge arm by adding a MOSFET to the rectifier output to form an inductor current freewheeling circuit. This not only eliminates the need for logic control steps such as 60° interval judgment and zero-state judgment, but also significantly reduces the rectifier's conduction power loss, greatly improving converter efficiency and making it suitable for high-power applications. Compared to traditional three-phase Boost PFC rectifiers or Buck PFC rectifiers, this invention has significant advantages such as simple structure, wide grid-side input voltage range, high conversion efficiency, high power factor, simple control, and low cost.

Claims

1. A high-efficiency three-phase PFC rectifier circuit compatible with both boost and buck control, characterized in that: It includes an input filter circuit, a power switch circuit, an output filter circuit, and a control circuit. The input filter circuit is connected to the power switch circuit, the power switch circuit is connected to the output filter circuit, and the output terminal of the control circuit is connected to the power switch circuit. The input filter circuit includes inductors La, Lb, and Lc, and capacitors Ca, Cb, and Cc; the power switching circuit includes a power bridge circuit and a freewheeling circuit. The power bridge circuit includes power MOSFETs Qa1, Qa2, Qa3, Qa4, Qb1, Qb2, Qb3, Qb4, Qc1, Qc2, Qc3, and Qc4; the freewheeling circuit includes a power MOSFET Qd; the output filter circuit includes inductor Ldc and capacitor Co. One end of the inductor La is connected to the A-phase voltage, and the other end is connected to one end of the capacitor Ca; one end of the inductor Lb is connected to the B-phase voltage, and the other end is connected to one end of the capacitor Cb; one end of the inductor Lc is connected to the C-phase voltage, and the other end is connected to one end of the capacitor Cc; the other ends of the capacitor Ca, the other ends of the capacitor Cb, and the other ends of the capacitor Cc are connected together. One end of the inductor Ldc is connected to one end of the capacitor Co, and the other end of the inductor Ldc and the other end of the capacitor Co are respectively connected to the control circuit. The drain of power MOSFET Qa1 is connected to the other end of inductor Ldc; the source of power MOSFET Qa1 is connected to the source of power MOSFET Qa2; the drain of power MOSFET Qa2 is connected to the other end of inductor La; and the gate of power MOSFET Qa1 is connected to the gate of power MOSFET Qa2. The drain of power MOSFET Qa3 is connected to the other end of inductor La; the source of power MOSFET Qa3 is connected to the source of power MOSFET Qa4; the drain of power MOSFET Qa4 is connected to the other end of capacitor Co; and the gate of power MOSFET Qa3 is connected to the gate of power MOSFET Qa4. Similarly, the drain of power MOSFET Qb1 is connected to the other end of inductor Ldc; the source of power MOSFET Qb1 is connected to the source of power MOSFET Qb2; the drain of power MOSFET Qb2 is connected to the other end of inductor Lb; and the gate of power MOSFET Qb1 is connected to the gate of power MOSFET Qb2. The drain of power MOSFET Qb3 is connected to the other end of inductor Lb. The sources of power MOSFETs Qb3 and Qb4 are connected, the drain of Qb4 is connected to the other end of capacitor Co, and the gate of Qb3 is connected to the gate of Qb4. The drain of power MOSFET Qc1 is connected to the other end of inductor Ldc, the source of Qc1 is connected to the source of power MOSFET Qc2, the drain of Qc2 is connected to the other end of inductor Lc, and the gate of Qc1 is connected to the gate of Qc2. The drain of power MOSFET Qc3 is connected to the other end of inductor Lc, the source of Qc3 is connected to the source of power MOSFET Qc4, the drain of Qc4 is connected to the other end of capacitor Co, and the gate of Qc3 is connected to the gate of Qc4. The drain of power MOSFET Qd is connected to the other end of inductor Ldc, and the source of Qd is connected to the other end of capacitor Co.

2. The high-efficiency three-phase PFC rectifier circuit compatible with boost and buck control as described in claim 1, characterized in that: It also includes an auxiliary power supply, which is connected to the control circuit.

3. The high-efficiency three-phase PFC rectifier circuit compatible with boost and buck control as described in claim 2, characterized in that: The other end of the inductor Ldc is connected to the auxiliary power supply.

4. The high-efficiency three-phase PFC rectifier circuit compatible with boost and buck control as described in claim 2, characterized in that: The other end of the capacitor Co is connected to an auxiliary power supply.

5. The high-efficiency three-phase PFC rectifier circuit compatible with boost and buck control as described in claim 1, characterized in that: It also includes a resistor RL, which is connected in parallel with a capacitor Co.

6. The high-efficiency three-phase PFC rectifier circuit compatible with boost and buck control as described in claim 1, characterized in that: The control circuit is connected to a three-phase input voltage signal and a three-phase input current signal at its input terminal, and to a power switch circuit at its output terminal.

7. The control method for a high-efficiency three-phase PFC rectifier circuit compatible with both boost and buck control as described in any one of claims 1-6, characterized in that... Includes the following steps: Step 1: Determine the numerical relationship between the three-phase input voltage and the DC output voltage setting value Vref of the three-phase PFC rectifier; Step 2: Based on the numerical relationships obtained in Step 1, switch between boost control, buck control, and synchronous rectification control operating modes, specifically as follows: When the DC output voltage setting value Vref is satisfied At that time, the three-phase rectifier converter operates in buck mode; When the DC output voltage setting value Vref is satisfied At that time, the three-phase rectifier converter operates in boost mode; When the DC output voltage setting value Vref is satisfied At that time, the three-phase rectifier converter operates in synchronous rectification mode; Where Vref is the DC output voltage setting value, Um is the peak line voltage of the rectifier's three-phase input voltage, and ΔU% represents the fluctuation range of the grid voltage.

8. The control method for a high-efficiency three-phase PFC rectifier circuit compatible with boost and buck control as described in claim 7, characterized in that: The three-phase input voltages have the same amplitude, but their phases differ by 120° sequentially.

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