Counter-based sense amplifier method for memory cells

Abstract

The present application relates to a counter-based sensing amplifier method for memory cells. The counter-based read algorithm can comprise the following phases: - storing in a counter associated with a memory cell array a value of the number of bits having a predetermined logic value of the data bits stored in the memory array; - reading from the counter the value corresponding to the number of bits having the predetermined logic value; - reading the data stored in the memory cell array by applying a ramp of bias voltages; - counting the number of bits having the predetermined logic value during the data read phase; - stopping the data read phase when the number of bits having the predetermined logic value is equal to the value stored in the counter.

Description

[0001] Cross-reference

[0002] This patent application is the national phase application of International Patent Application No. PCT / IB2020 / 000082, filed on March 3, 2020, entitled “Counter-based Sense Amplifier Method for Memory Cells” by Muzzetto et al., which is assigned to the assignee and whose entire contents are expressly incorporated herein by reference. Technical Field

[0003] The technical field relates to a counter-based sense amplifier method for memory cells. Background Technology

[0004] The following content generally relates to operating memory arrays and more specifically to counter-based sense amplifier methods for memory cells.

[0005] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming different states of the memory device. For example, a binary device has two states, typically represented by logic "1" or logic "0". In other systems, more than two states can be stored. To access the stored information, components of the electronic device can read or sense the stored states in the memory device. To store information, components of the electronic device can write to or program the states in the memory device.

[0006] Various types of memory devices exist, including magnetic hard disk drives, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), and others. Memory devices can be volatile or non-volatile. Non-volatile memory cells can maintain their stored logical state for extended periods, even in the absence of external power. Volatile memory cells may lose their stored state over time unless periodically refreshed by an external power source.

[0007] Typically, improvements to memory devices can include increasing memory cell density, improving read / write speeds, enhancing reliability, extending data retention, reducing power consumption, or reducing manufacturing costs, among other metrics. When memory cells exhibit variable electrical characteristics in a particular memory device with a three-dimensional (3D) array of memory cells, more robust read techniques may be required to increase memory cell performance and reliability. Summary of the Invention

[0008] A counter-based sense amplifier method for reading memory cells is described. In some instances, the method may include: storing in a counter associated with an array of memory cells a value representing the number of bits having predetermined logic values ​​stored in the array; reading from the counter the value corresponding to the number of bits having the predetermined logic values; reading data stored in the array of memory cells by applying a slope of bias voltage; counting the number of bits having the predetermined logic values ​​during a data read phase; and stopping the data read phase when the number of bits having the predetermined logic values ​​equals the value stored in the counter.

[0009] A method for reliably reading memory cells in a vertical 3D memory device is described. In some instances, the method may include: storing a value in a counter associated with a codeword of the memory cell, indicating the number of bits of the codeword having a predetermined logic value; reading the contents of the counter before reading the contents of the codeword; initiating a counter reading phase during a pre-charge phase of the codeword; and stopping the codeword reading phase when the number of bits having the predetermined logic value corresponds to the contents of the counter.

[0010] Describe a device. In some instances, the device may include a memory device comprising at least one memory array including one or more memory cell arrays, and a memory controller supporting a counter-based sense amplifier method for reading the memory cells, comprising: at least one codeword in the memory array, comprising data bits having associated parity bits and a counter having associated ECC bits.

[0011] Describe a device. In some instances, the device may include a memory device comprising at least one memory array including one or more memory cell arrays, and a memory controller supporting a counter-based sense amplifier method for reading the memory cells, comprising: a set of bit-flipping units for each codeword of the memory array, for encoding manipulated stored data up to the desired number of bits in a logical value. Attached Figure Description

[0012] Figure 1Examples of memory device diagrams illustrating a three-dimensional (3D) array of memory cells supporting a counter-based sense amplifier method for memory cells according to embodiments of the present disclosure.

[0013] Figure 2 Examples of 3D memory arrays that support a counter-based sense amplifier method for memory cells according to embodiments of this disclosure are described.

[0014] Figure 3 The description includes examples of memory pages that support codeword components of a counter-based sense amplifier method for reading memory cells according to embodiments of the present disclosure.

[0015] Figure 4 The description includes another example of an improved memory page that supports an extended codeword component of a counter-based sense amplifier method for reading memory cells according to embodiments of the present disclosure.

[0016] Figure 4A To and Figure 3 A schematic diagram of the structure of the counting register associated with the memory page.

[0017] Figure 5 A block diagram illustrating an apparatus supporting a counter-based sense amplifier method for reading memory cells according to embodiments of the present disclosure.

[0018] Figure 6 The illustration shows a schematic diagram of a read algorithm that operates according to the method of this disclosure to implement the read phase of the memory counter in parallel with the read phase of the memory codeword.

[0019] Figure 7 A block diagram is shown illustrating the programming phase of preparing the memory device of this disclosure for operation according to the disclosed sensing method.

[0020] Figure 8 The illustration shows a schematic diagram of a read algorithm that operates according to the method of this disclosure to implement the read phase of the memory counter in parallel with the read phase of the memory codeword and an additional final attempt and repeated sensing phase.

[0021] Figure 9 A block diagram illustrating the read phase of a memory device performed according to the method of this disclosure.

[0022] Figure 10 The description is based on the method of this disclosure and corresponds to Figure 8 A block diagram of the alternative read phase of a memory device in an example.

[0023] Figure 11 A few graphs are provided to illustrate the increased reliability of the reading phase using the method of this disclosure.

[0024] Figure 12 This diagram presents a time-varying comparison of the distribution of memory cells detectable during the read phase in two different general-purpose memory pages, XXX and ZZZ, based on known solutions.

[0025] Figure 13 A time-varying diagram showing the distribution of memory cells detectable during the read phase in two different general-purpose memory pages XXX and ZZZ according to embodiments of the present disclosure.

[0026] Figure 14 This diagram illustrates the distribution of memory cells over time that can be detected during the read phase using a bias read voltage with a variable slope.

[0027] Figure 15 A block diagram of a memory system is shown, based on an example disclosed herein, that supports a counter-based sense amplifier method for memory cells.

[0028] Figure 16 and 17 The flowchart illustrates one or more methods supporting a counter-based sense amplifier method for memory cells, based on examples disclosed herein. Detailed Implementation

[0029] As is known in this technical field, phase-change memories (PCMs) utilize a class of materials that have the property of switching between two phases (more precisely, an amorphous disordered phase and a crystalline or polycrystalline ordered phase) with dissimilar electrical properties associated with two different crystalline structures of the material. The two phases are therefore associated with significantly different resistivity values.

[0030] Phase change material elements exhibit resistivity values ​​depending on their phase, which can be associated with different logical states. The resistivity of a phase change material in an amorphous phase is higher than that in a crystalline phase. Variations in partial crystallinity are also possible, resulting in intermediate resistivity values ​​between those in a (fully) amorphous phase and those in a (fully) crystalline phase.

[0031] Ideally, all memory cells (hereinafter referred to as "PCM cells") of a PCM memory device should provide the same (nominal) resistivity (and therefore the same threshold voltage, which is the voltage to be applied to the memory cell to conduct current) for the same logic state. However, since different PCM cells programmed to the same logic state actually exhibit different resistivity values ​​due to several factors (such as variations in the electrical properties of the phase change material caused by performing multiple read / write operations and / or by manufacturing tolerances), each logic state is actually associated with a corresponding resistivity distribution (typically a Gaussian distribution), and therefore with a corresponding threshold voltage distribution.

[0032] To assess the logic state of a PCM cell, a read operation is performed to determine which threshold voltage distribution the PCM cell's threshold voltage belongs to. For example, a read voltage (VDM) can be applied to the PCM cell, and the logic state of the PCM cell can be assessed based on the presence or absence of a current in response to the read voltage, the presence or absence of which depends on the PCM cell's threshold voltage.

[0033] Referring to a binary PCM memory device (which provides two threshold voltage distributions (e.g., a first threshold voltage distribution corresponding to a set state and a second threshold voltage distribution corresponding to a reset state, wherein the threshold voltage of the first threshold voltage distribution is lower than the threshold voltage of the second threshold voltage distribution)), the value of the read voltage VDM is advantageously selected to be higher than the higher threshold voltage of the first threshold voltage distribution and lower than the lower threshold voltage of the second threshold voltage distribution.

[0034] PCM memory devices are adversely affected by the change in the resistivity of PCM cells over time after their last programming (popularly termed "drift"). In practice, once a PCM cell is programmed to a logic state corresponding to its resistivity value, the cell's resistivity tends to increase over time in a manner dependent on several factors (such as the operating temperature of the PCM memory device—the higher the temperature, the faster the resistivity increases over time)), and the resistivity corresponds to the programmed logic state (PCM cells programmed to higher resistivity values ​​experience faster resistivity time drift compared to PCM cells programmed to lower resistivity values). This resistivity time drift, in turn, causes a drift in the threshold voltage distribution, which correspondingly shifts over time since the last programming operation.

[0035] If the threshold voltage distribution drifts particularly high because the PCM memory device has not been programmed for a long time, then the value of the read voltage previously selected for the read operation may no longer be able to determine which threshold voltage distribution the PCM cell's threshold voltage belongs to.

[0036] Drift and cycling are window budget devaluers that led to the rollout of VDM and the degradation of technology memory capabilities.

[0037] A solution has been suggested (e.g., in US 8,553,453) to use a ramp generator to read PCM memory cells and measure a timer for each page, thereby generating timing events that allow page bits to be read based on a voltage ramp. A switching detector is used to prevent the ramp from rising. This solution is relatively inexpensive but non-deterministic and is based on the assumption that the cell distribution has a known shape (i.e., Gaussian); furthermore, the cell distribution is affected by circuit noise depending on the implementation.

[0038] Another solution (e.g., in US 8,913,426) has been suggested to generate a digital voltage ramp that further adds soft information to the ramp by referencing known type-state measurements. This solution requires the use of a check table and ECC overflow with soft correction.

[0039] Unlike known solutions, the method disclosed in this specification begins by considering that ECC feedback information is often insufficient for the correct reading of memory cell contents. This occurs, for example, due to errors attributed to cells read as "0", or vice versa.

[0040] For example, in a balanced memory word storage containing a number of logic values ​​"1" corresponding to logic value "0", reading at least N / 2 cells would be necessary. However, if the cell storing "0" is not properly programmed, that cell will be read as "1", and the read phase will return N / 2 cells read as "1", but one of them should be an incorrect cell storing "0". Simultaneously, the read phase will return N / 2 cells read as "0", one of which stores "1". Therefore, if a cell is corrupted, it will generate two errors. For this reason, ECC1 is insufficient to correct this error. The same applies to ECC2, which will not correct two errors because two corrupted cells generate four errors, and so on.

[0041] Given the above examples, it should be clear that feedback from the ECC alone is insufficient, but the method of this disclosure teaches to follow a more complex read algorithm that requires feedback from the ECC during the reading of the number of units corresponding to N (“1”) minus N (ECC). This algorithm will produce the minimum number of feedback requests from the ECC with the lowest possible read time.

[0042] The method disclosed herein uses a codeword portion (hereinafter also referred to as a counter) with bits protected by ECC or other mechanisms (such as a voting scheme with two units per bit); this method requires only modifications to the programming mechanism that stores the contents of the counter during the storage of the codeword. The codeword may contain information to be used during the read phase, such as topology, ECC.

[0043] The read phase of the counter content (e.g., bits in the codeword counter section) is activated during the leak balancing phase of the memory cell, while the read algorithm is activated during the regular read phase of the memory cell.

[0044] This disclosure relates to a novel and more efficient solution based on a counter-sensor amplifier method for reading memory cells in 3D memory devices. This solution allows for a reduction in the voltage applied to the memory cell during the read phase, thus reducing the stress applied to the memory cell and further reducing the power required to generate the bias voltage.

[0045] The proposed technology is largely based on two steps: a first step at the programming stage and a second step at the sensing stage.

[0046] During the programming phase, it is recommended to use bit flipping (BF) to set the type of the memory codeword to mostly (>50%) logic zero (with high Vth) or logic one (with low Vth). In other words, a counter is used to detect the number of cells that have been programmed with logic values ​​"0" or "1" in a given codeword.

[0047] More specifically, by using bit flips that can reverse cell programming, it is possible to focus counting activity on logic values ​​or other parameters. As an example only, during the precharge phase, when the programming phase begins, bit flips are used to obtain at least 50% of the cells programmed with the logic value "1".

[0048] In other words, if the distribution of programmed cells indicates that 30% of the cells are programmed with the logic value "0", then it is possible to use bit flipping to obtain an indication that 70% of the memory cells are programmed with the relative logic value "1".

[0049] This solution is particularly suitable for situations where word line drops (i.e., IR drops) exist and allows for faster programming and lower power consumption per bit.

[0050] However, it should be noted that this first pass via the bit-flip encoder is optional and can be selected depending on the physical implementation and where it is preferred for the reliability of the unit.

[0051] At this point, based on the written and stored data, after possible BF manipulation, the number of programmed logic values ​​"1" can be counted and this value can be reliably written into a counter memory portion containing ECC bits, for example, storing the value with protected dual cells (data / data#). Therefore, the technology disclosed herein proposes storing a value corresponding to the number of cells programmed with a certain logic value (e.g., logic value "1") in a reliable counter with associated ECC bits.

[0052] As an alternative, using BF manipulation, if the codeword should contain all even numbers of programmed logic values ​​"1" and "0", then using balanced 50-50%+ balanced ECC encoding would be possible. In this case, the counter unit would not be strictly necessary and no downloading (WIP) would be required, but this alternative would generally require a larger initial BF manipulation.

[0053] At this point, all bits of the codeword are written (regardless of its initial state), thus obtaining the iso-usage codeword.

[0054] During the subsequent sensing phase, it has been decided to first read the contents of the counter by applying a fast ramp with a bias voltage and downloading the counter unit, while performing other operations on the main codeword (such as leakage compensation). This reading phase allows the information stored in the counter to be obtained first.

[0055] Other data units are biased accordingly and simultaneously with the read operation on the counter; therefore, the data bits of the memory array are biased during the voltage ramp on the counter. Furthermore, the application of different very fast ramps is possible due to the differential counter structure.

[0056] Now, the main ramp on the data memory cell rises and counts precisely until the target number of cells programmed with low Vth (i.e., to the logic value "1") is written into the counter, then the read phase stops.

[0057] Whenever a cell is triggered, it automatically disconnects to reduce IR outages while simultaneously decrementing a counter containing the value corresponding to the number of cells with the stated logic value.

[0058] Therefore, in order to outline the deterministic counter-based sensing amplifier method of this disclosure, we may say that it includes the following steps or stages:

[0059] - A counter associated with the memory cell array stores a value representing the number of bits having predetermined logical values ​​of data bits stored in the array;

[0060] - Read the content or value corresponding to the number of bits having the predetermined logic value from the counter;

[0061] - Data stored in the memory cell array is read by applying a bias voltage ramp;

[0062] - Count the number of bits having the predetermined logic value during the data reading phase;

[0063] - The data reading phase stops when the number of bits with the predetermined logic value equals the value (e.g., its content) stored in the counter.

[0064] The storage phase in the counter includes first using a bit-flipping phase to switch the number of bits with a predetermined logic value to obtain 50% of the data bits with that logic value.

[0065] Furthermore, the counter read phase (which may sometimes be the first read phase) is performed by a fast bias voltage ramp on the counter, while simultaneously initiating a pre-charging or line leakage compensation phase for the data bit portion of the memory cell array.

[0066] This disclosure further relates to a memory device comprising at least one or more memory cell arrays and a memory controller supporting a counter-based sense amplifier method for reading memory cells, including:

[0067] - A set of bit-flipping cells for each codeword of the memory array to encode the manipulated stored data up to the desired number of bits of a logical value.

[0068] Bit-flipping cells are protected by a 3D cross-point cell voting scheme or by differential 3D cross-point cells with ECC bits, for example, storing bit-flipped values ​​with protected dual cells (BF / BF#).

[0069] Furthermore, the memory device includes a counter for each codeword, wherein the number of bits corresponding to codewords having the same logic value is recorded.

[0070] The features and advantages of the counter-based sense amplifier method of this disclosure will be discussed in detail in the following paragraphs; however, for a better understanding of the entire disclosure, the physical structure of the memory device to which the read technique is applied will first be appropriately described. This will first refer to Figure 1 and 2 conduct.

[0071] As is known, memory cells can exhibit non-uniform variable electrical characteristics in some cases, which can originate from various factors, including statistical process variations, cyclic events (e.g., read or write operations on the memory cell), or drift (e.g., changes in the resistance of chalcogenide alloys). Due to drift alone, it is necessary to increase the bias voltage used during the read phase. Of course, the techniques employed in this disclosure allow for a reduction in the VDM value, thereby improving read interference immunity.

[0072] The counter-based sense amplifier method for memory cells disclosed herein provides a reliable and robust read technique, wherein reading a set of user data (e.g., codewords, pages) is performed by tracking the number of memory cells activated in response to a read voltage applied to the memory cells. In some cases, the counter-based read algorithm can use a predetermined number to determine whether a memory cell associated with a first logic state has been considered when reading user data. Additionally, the counter-based read algorithm can determine the total number of memory cells associated with the first logic state when reading user data.

[0073] In some aspects, counter-based read algorithms reduce or eliminate the corresponding set of read reference memory cells that may exist in a memory device. Read reference memory cells can be attributed to various reasons that they do not share common electrical characteristics with the majority of memory cells storing user data, such as different processing conditions (e.g., non-uniform loading patterns of plasma density), different cyclic events, etc. Therefore, the corresponding set of read reference memory cells may not provide a reliable reference scheme during read operations.

[0074] The counter-based read algorithm technique disclosed herein may include an encoding scheme applied to user data to determine a predetermined number of bits in the encoded user data having a given logical state (e.g., logical state 1) before storing the encoded user data in memory cells. The encoding scheme may include adding multiple extra bits (which may also be referred to as parity bits) to the user data during the encoding process. In some embodiments, the counter-based read algorithm may use different encoding schemes that, when storing user data, store count information corresponding to the total number of bits in the user data having a given logical state (e.g., logical state 1) in multiple memory cells. In some cases, the count information may be stored as a binary number representing the total number of bits in the user data having a given logical state. In other cases, the count information may be encoded in a weighted form with a given weight (e.g., 20%, 30%, 50% (i.e., half of the memory cells storing the count information have a given logical state), 75%).

[0075] In some aspects, the memory device may include a 3D architecture (e.g., a 3DXPoint for storing user data). TM PCM cell array in memory. 3D XPoint TM In the architecture, a PCM cell (which may also be referred to as a 3DXP memory cell) may represent a first logic state (e.g., logic state 1) associated with a first set of threshold voltages or a second logic state (e.g., logic state 0) associated with a second set of threshold voltages. In some embodiments, logic state 1 (e.g., a set state of the PCM cell, which may also be referred to as a set cell or bit) corresponds to a set of threshold voltages that are lower than the set of threshold voltages associated with logic state 0 (e.g., a reset state of the PCM cell, which may also be referred to as a reset cell or bit).

[0076] Counter-based read algorithms may involve applying a voltage (e.g., a read voltage) to a memory array configured to activate a set of memory cells containing encoded user data. The voltage may increase at a constant rate over time. In some cases, the read voltage has a monotonically increasing step shape, such that a first voltage is applied in a first time period, followed by a second, different voltage in a second time period. The applied read voltage can activate a series of switching events by activating the set of memory cells storing the encoded user data. Switching events can be attributed to a memory cell turning on (e.g., conducting a significant current) when the applied voltage across the memory cell exceeds its threshold voltage. Counter-based read algorithms can track the number of memory cells that turn on (e.g., activate) in response to the read voltage.

[0077] When user data has been encoded with a predetermined number of memory cells having a first logic state (e.g., logic state 1), a counter-based read algorithm compares the number of activated memory cells with the predetermined number stored in the memory device. When the number of activated memory cells is less than the predetermined number, the counter-based read algorithm continues to apply (e.g., increase) a read voltage to the memory array while tracking any additional activated memory cells (e.g., until the number of activated memory cells matches the predetermined number). When the number of activated memory cells matches the predetermined number, the counter-based read algorithm stops applying a read voltage to the memory array and determines that all activated memory cells encoding the user data have the first logic state. Additionally, the counter-based read algorithm determines that the remaining memory cells encoding the user data (e.g., memory cells not in use when the number of activated memory cells matches the predetermined number) have a second logic state (e.g., logic state 0).

[0078] When user data has been encoded with an additional set of memory cells storing calculated information corresponding to the total number of bits in the user data having a first logical state (e.g., logical state 1), a counter-based read algorithm can read the calculated information from the additional set of memory cells to identify the total number. The total number can be stored in the memory device to provide a criterion for whether the read voltage can continue or stop when tracking the number of activated memory cells of the user data in response to a read voltage. When the number of activated memory cells is less than the total number, the counter-based read algorithm can continue to apply (e.g., increase) the read voltage to the memory array while tracking the additional activated memory cells until the number of activated memory cells matches the total number. When the number of activated memory cells of the user data matches the total number, the counter-based read algorithm can stop applying the read voltage to the memory array and determine that all activated memory cells of the user data have a first logical state (e.g., the set state of a PCM cell). Additionally, the counter-based read algorithm can determine that the remaining memory cells of the user data (e.g., memory cells not in use when the number of activated memory cells matches a predetermined number) have a second logical state (e.g., the reset state of a PCM cell).

[0079] In some cases, the counting information is encoded to a fixed number of bits that previously had a first logical state (e.g., logical state 1) in an additional set of memory cells. As an example, half of the additional set of memory cells may be configured to have logical state 1 to represent the counting information. During a read operation, a counter-based read algorithm can track the number of active memory cells in the additional set of memory cells to determine whether to consider all memory cells in the additional set of memory cells having logical state 1. When all memory cells in the additional set of memory cells have been considered (e.g., activated), the counter-based read algorithm technique can set a flag in the memory device and extract the counting information from the additional set of memory cells. The counting information may be stored in a register in the memory device, and the flag may indicate that the counting information in the register is a valid representation (e.g., in binary format) of the total number of bits in user data presenting a first logical state (e.g., logical state 1). The counting information in the register can then be used to track the number of active memory cells in the user data in a similar manner as described above. In some embodiments, a different read voltage may be applied to the additional set of memory cells compared to the memory cells storing the user data. Alternatively, a single read voltage may be applied to both the additional set of memory cells and the memory cells storing user data.

[0080] The features of the present disclosure described above are further described below in the context of memory arrays in a memory device. Specific non-limiting examples are then described to illustrate various features of a counter-based sense amplifier method for memory cells according to some embodiments (e.g., a memory array including PCM cells or 3DXP memory cells). These and other features of the present disclosure are further illustrated and described with reference to device diagrams, system diagrams, and flowcharts relating to a counter-based sense amplifier method for memory cells. However, as will be appreciated by those skilled in the art, other alternatives and variations are considered and fall within the scope of this disclosure.

[0081] Figure 1 An example memory device 100 according to an embodiment of the present disclosure is described. The memory device 100 may also be referred to as an electronic memory device. Figure 1 This is an illustrative representation of the various components and features of the memory device 100. Therefore, it should be understood that the components and features of the memory device 100 are shown to illustrate functional interrelationships, and their actual physical locations within the memory device 100 may not be indicated. Figure 1 In an illustrative example, memory device 100 includes a 3D memory array 102. The 3D memory array 102 includes memory cells 105 programmable to store different states. In some embodiments, each memory cell 105 is programmable to store two states, represented as logic 0 and logic 1. In some embodiments, memory cells 105 may be configured to store more than two logic states. In some embodiments, memory cells 105 may include PCM cells (e.g., 3DXP memory cells). Although included in Figure 1 Some elements are marked with numerical indicators, while other corresponding elements are not marked, but these elements are also, or should be understood, used to increase the visibility and clarity of the depicted features.

[0082] The 3D memory array 102 may comprise two or more two two-dimensional (2D) memory arrays formed adjacent to each other (e.g., one after another or adjacent to each other). Compared to 2D arrays, this can increase the number of memory cells 105 that can be placed or created on a single die or substrate, which in turn can reduce manufacturing costs or increase the performance of the memory device, or both. Figure 1 In the example depicted, the 3D memory array 102 comprises two levels of memory cells 105; however, the number of levels is not limited to two. The levels may be aligned or positioned such that the memory cells 105 can be aligned (exactly or substantially overlapping) across the levels, thereby forming a memory cell stack 145. In some cases, the memory cell stack 145 may contain PCM cells (e.g., 3DXP memory cells) placed on top of one another.

[0083] In some embodiments, each row of memory cells 105 is connected to access lines 110, and each column of memory cells 105 is connected to bit lines 115. Access lines 110 and bit lines 115 may be substantially perpendicular to each other and may create an array of memory cells. Figure 1 As shown, two memory cells 105 in the memory cell stack 145 can share a common conductive line, such as bit line 115. That is, bit line 115 can electronically communicate with the bottom electrode of the upper memory cell 105 and the top electrode of the lower memory cell 105. In other embodiments, each of the memory cells 105 (e.g., upper memory cell, lower memory cell) can be configured with its own bit line. In such cases, the memory cells can be separated by an insulating layer. Other configurations are possible; for example, a third layer can share access line 110 with the lower layer. Generally, a memory cell 105 can be located at the intersection of two conductive lines (e.g., access line 110 and bit line 115). This intersection point can be referred to as the address of the memory cell. The target memory cell 105 may be a memory cell 105 located at the intersection of the power access line 110 and the bit line 115; that is, the access line 110 and the bit line 115 may be powered to read or write to the memory cell 105 at their intersection. Other memory cells 105 that are electronically communicated with the same access line 110 or bit line 115 (e.g., connected to the same access line 110 or bit line 115) may be referred to as non-target memory cells 105.

[0084] As discussed above, electrodes may be coupled to memory cell 105 and access line 110 or bit line 115. The term electrode may refer to an electrical conductor and, in some cases, may serve as an electrical contact to memory cell 105. Electrodes may comprise traces, wires, conductive lines, conductive layers, or the like that providing a conductive path between elements or components of memory device 100. In some embodiments, memory cell 105 may comprise a chalcogenide alloy located between a first electrode and a second electrode. One side of the first electrode may be coupled to access line 110 and the other side of the first electrode may be coupled to the chalcogenide alloy. Additionally, one side of the second electrode may be coupled to bit line 115 and the other side of the second electrode may be coupled to the chalcogenide alloy. The first and second electrodes may be made of the same material (e.g., carbon) or different materials. In other embodiments, memory cell 105 may include additional electrodes to divide the chalcogenide alloy into sections such as... Figure 2 The two parts are depicted. The first part of the chalcogenide alloy may have a different composition than the second part of the chalcogenide alloy. In some embodiments, the first part of the chalcogenide alloy may have a different function than the second part of the chalcogenide alloy. The additional electrode may be made of the same material (e.g., carbon) or different from the first and / or second electrodes.

[0085] Operations such as reading and writing can be performed on memory cell 105 by powering or selecting access line 110 and digital line 115. In some embodiments, access line 110 may also be referred to as word line 110, and bit line 115 may also be referred to as digital line 115. References to word line and bit line or the like are interchangeable without loss of understanding or operation. Powering or selecting word line 110 or digital line 115 may include applying a voltage to the respective line. Word line 110 and digital line 115 may be made of a conductive material, such as metals (e.g., copper (Cu), aluminum (Al), gold (Au), tungsten (W), titanium (Ti)), metal alloys, carbon, conductive doped semiconductors or other conductive materials, alloys, compounds, etc.

[0086] In some architectures, the logic storage devices (e.g., capacitors, resistors) of memory cell 105 can be electrically isolated from digital line 115 via a select component. Word line 110 can be connected to and control the select component. For example, the select component can be a transistor, and word line 110 can be connected to the gate of the transistor. Powering word line 110 creates an electrical connection or a closed loop between the logic storage devices of memory cell 105 and their corresponding digital line 115. Digital line 115 can then be accessed to read from or write to memory cell 105. After selecting memory cell 105, the resulting signal can be used to determine the stored logic state. In some cases, the first logic state may correspond to no current or a negligible current, while the second logic state may correspond to a finite current. In some cases, memory cell 105 may contain a 3DXP memory cell or a self-select memory (SSM) cell (both having two terminals) and may not require a corresponding select component. Therefore, one terminal of the 3DXP memory cell or SSM cell can be electrically connected to word line 110, and the other terminal of the 3DXP memory cell or SSM cell can be electrically connected to digital line 115.

[0087] Access to memory cell 105 can be controlled via row decoder 120 and column decoder 130. For example, row decoder 120 can receive row addresses from memory controller 140 and power the appropriate word lines 110 based on the received row addresses. Similarly, column decoder 130 can receive column addresses from memory controller 140 and power the appropriate digital lines 115. For example, 3D memory array 102 may include multiple word lines 110 labeled WL_B1 (or WL_T1) to WL_BM (or WL_TM) and multiple digital lines 115 labeled DL_1 to DL_N, where M and N depend on the array size. Therefore, by powering word lines 110 and digital lines 115, such as WL_B2 and DL_3, memory cell 105 can be accessed at their intersection.

[0088] After access, the memory cell 105 can be read or sensed by the sensing component 125 to determine the storage state of the memory cell 105. For example, a voltage can be applied to the memory cell 105 (using the corresponding word line 110 and bit line 115), and the presence of the resulting current can depend on the applied voltage and threshold voltage of the memory cell 105. In some cases, more than one voltage can be applied. Additionally, if no current is generated by the applied voltage, other voltages can be applied until the current is detected by the sensing component 125. By evaluating the voltage that generates the current, the stored logic state of the memory cell 105 can be determined. In some cases, the voltage can ramp up in magnitude until current flow is detected (e.g., the memory cell 105 is turned on, switched on, conducts current, or becomes active). In other cases, predetermined voltages can be applied sequentially until current is detected. Similarly, current can be applied to the memory cell 105, and the magnitude of the voltage used to generate the current can depend on the resistance or threshold voltage of the memory cell 105.

[0089] Sensing component 125 may include various transistors or amplifiers to detect and amplify the difference in signals, which may be referred to as latch. The detected logic state of memory cell 105 can then be output as output 135 via column decoder 130. In some cases, sensing component 125 may be part of column decoder 130 or row decoder 120. Alternatively, sensing component 125 may be connected to or in electronic communication with column decoder 130 or row decoder 120. Figure 1 Alternative options for arranging the sensing component 125-a (shown in dashed box) are also shown. Those skilled in the art will understand that the sensing component can be associated with a column decoder or a row decoder without losing its functional purpose.

[0090] Memory cell 105 can be set or written by similarly powering the associated word line 110 and digital line 115, and at least one logic value can be stored in memory cell 105. Column decoder 130 or row decoder 120 can accept data to be written to one or more memory cells 105, for example, input / output 135.

[0091] In some memory architectures, accessing memory cell 105 can degrade or destroy the stored logic state, and a rewrite or refresh operation can be performed to return the initial logic state to memory cell 105. For example, in DRAM, capacitors can partially or completely discharge during a sensing operation, thereby destroying the stored logic state. Therefore, the logic state can be rewritten after the sensing operation. Additionally, powering a single word line 110 can cause all memory cells 105 in the row to discharge; therefore, some or all of the memory cells 105 in the row may need to be rewritten. However, in non-volatile memories such as SSM, PCM (e.g., 3DXP memory), FeRAM, or 3D NAND memory, accessing memory cell 105 may not destroy the logic state, and therefore, memory cell 105 may not need to be rewritten after access.

[0092] The memory controller 140 can control the operation (e.g., read, write, rewrite, refresh, discharge) of the memory cell 105 via various components (e.g., row decoder 120, column decoder 130, and sensing component 125). In some cases, one or more of the row decoder 120, column decoder 130, and sensing component 125 may be co-located with the memory controller 140. The memory controller 140 can generate row address signals and column address signals to power the desired word lines 110 and digital lines 115. The memory controller 140 can also generate and control various voltages or currents used during the operation of the memory device 100.

[0093] Memory controller 140 may receive user data via input / output 135. In some embodiments, memory controller 140 encodes user data to satisfy a condition before storing the user data in memory cell 105. The condition is satisfied when the encoded user data has a predetermined number of bits that represent a given logical state (e.g., logical state 1). As an example, the encoded user data may be configured to have 50% of the memory cells storing the encoded user data to represent logical state 1, while the other 50% of the memory cells represent logical state 0. During the encoding process, memory controller 140 may add a certain number of bits (e.g., parity bits) to the user data to determine a predetermined number of memory cells to represent the given logical state. As a result of adding parity bits, the encoded user data may have more bits than the user data. Memory controller 140 may store a predetermined number in a register. In some embodiments, different percentage values ​​(e.g., 40%, 60%, 75%) of the memory cells representing logical state 1 may be used during the encoding process.

[0094] The memory controller 140 can apply a read voltage to the memory array 102 to activate a group of memory cells 105 containing a predetermined number of bits of encoded user data exhibiting a given logical state. The read voltage can have a constant increasing rate or a monotonically increasing step shape. When the read voltage applied across a memory cell 105 exceeds its threshold voltage, the applied read voltage can activate a subset of the memory cells 105 containing the encoded user data due to the applied read voltage. The memory controller 140 can track the number of activated memory cells 105 and compare the number with a predetermined number stored in a register. When the number of activated memory cells 105 matches the predetermined number, the memory controller 140 can determine that all memory cells exhibiting the given logical state are considered to be from the group of memory cells containing encoded user data and stop applying the read voltage. Subsequently, the memory controller 140 can determine that all activated memory cells 105 have the given logical state.

[0095] Generally, the amplitude, shape, polarity, and / or duration of the applied voltage or current discussed herein may be adjusted or changed and may vary for the various operations discussed in the operating memory device 100. Furthermore, one, more, or all of the memory cells 105 within the memory array 102 may be accessed simultaneously; for example, more or all cells of the memory array 102 may be accessed during a reset operation in which all or a group of memory cells 105 are set to a single logic state.

[0096] Figure 2 This describes an example of a memory array 202 that supports a counter-based sense amplifier method for memory cells according to embodiments of the present disclosure. The memory array 202 may be a reference. Figure 1 An example of a portion of the described memory array 102. (e.g.) Figure 2 As depicted, the memory array 202 comprises various materials to construct memory cells 105-a. Each memory cell 105-a is stacked in a vertical direction (e.g., perpendicular to the substrate) to create a memory cell stack (e.g., memory cell stack 145). Memory cell 105-a may be used as a reference. Figure 1 An example of the described memory cell 105. The memory array 202 can therefore be referred to as a 3D memory array. The architecture of the memory array 202 can be referred to as a crosspoint architecture. Although Figure 2 Some of the elements contained herein are marked with numerical indicators, while other corresponding elements are not marked, but in the effort to improve the visibility and clarity of the depicted features, the elements are the same or will be understood as similar.

[0097] Memory array 202 also includes word line 110-a and bit line 115-a, which may be referenced. Figure 1 Examples of word line 110 and bit line 115 described. Figure 2 The description of the material between the character line 110-a and the position line 115-a depicted in the text can be represented as follows: Figure 1 The lower portion of memory cell 105 in the memory array 202 includes electrodes 205, logic memory elements 210, selector device elements 220, and a substrate 225. In some instances, a single component comprising a chalcogenide alloy (not shown, replacing selector device element 220, logic memory element 210, and electrode 205-b) can serve as both a logic memory element and a selector device. Electrode 205-a is electronically communicable to bit line 115-a, and electrode 205-c is electronically communicable to word line 110-a.

[0098] The insulating material depicting the empty space can be both electrically and thermally insulating. As described above, in PCM technology, various logic states can be stored by changing the resistance of the logic storage element 210 in memory cell 105-a, which in turn presents different threshold voltages of memory cell 105-a. In some cases, storing various logic states involves passing current through memory cell 105-a, heating the logic storage element 210 in memory cell 105-a, or melting (e.g., completely or partially) the material of the logic storage element 210 in memory cell 105-a. Other memory mechanisms, such as threshold voltage modulation, can be utilized in chalcogenide-based memories.

[0099] In some cases, memory array 202 may comprise an array of memory cell stacks, and each memory cell stack may comprise a plurality of memory cells 105-a. Memory array 202 may be fabricated by forming a stack of conductive materials (e.g., word lines 110-a), wherein each conductive material is separated from adjacent conductive materials by an electrically insulating material. The electrically insulating material may comprise an oxide or nitride material, such as silicon oxide, silicon nitride, or other electrically insulating materials. These materials may be formed over a substrate 225 (e.g., a silicon wafer or any other semiconductor or oxide substrate). Subsequently, various process steps may be used to form the material between word lines 110-a and bit lines 115-a, such that each memory cell 105-a can be coupled to both word lines 110-a and bit lines 115-a.

[0100] Selector device element 220 may be connected to logic memory element 210 via electrode 205-b. In some instances, the positioning of selector device element 220 and logic memory element 210 may be flipped. A composite stack including selector device element 220, electrode 205-b, and logic memory element 210 may be connected to word line 110-a via electrode 205-c and to bit line 115-a via electrode 205-a. Selector device element 220 may assist in selecting a specific memory cell 105-a or help prevent stray current from flowing through an unselected memory cell 105-a adjacent to the selected memory cell 105-a. Selector device element 220 may include electrically nonlinear components (e.g., non-ohmic components), such as metal-insulator-metal (MIM) junctions, bidirectional threshold switches (OTS) or metal-semiconductor-metal (MSM) switches, and other types of two-terminal selector devices, such as diodes. In some cases, the selector device element comprises a chalcogenide alloy. In some instances, the selector device comprises an alloy of selenium (Se), arsenic (As), silicon (Si), and germanium (Ge).

[0101] As discussed above, Figure 2 The memory cell 105-a may contain a material with variable resistance. Variable resistance material can refer to various material systems, including, for example, metal oxides, chalcogenides, and the like. Chalcogenide materials are materials or alloys containing at least one of the elements sulfur (S), tellurium (Te), or selenium (Se). Many chalcogenide alloys are possible; for example, germanium-antimony-tellurium alloy (Ge-Sb-Te) is a chalcogenide material. Other chalcogenide alloys not explicitly described herein may also be used.

[0102] To establish a low-resistance state, memory cell 105-a can be heated by transferring current through it. Heating caused by current flowing through a material with finite resistance can be termed Joule or Ohmic heating. Joule heating can therefore be correlated with the resistance of the electrodes or phase change material. Heating the phase change material to a high temperature (but below its melting temperature) can cause the phase change material to crystallize and form a low-resistance state. In some cases, memory cell 105-a can be heated by means other than Joule heating (e.g., by using a laser). To establish a high-resistance state, the phase change material can be heated above its melting temperature, for example, by Joule heating. The amorphous structure of the molten material can be quenched or locked by abruptly removing the applied current to rapidly cool the phase change material.

[0103] In some cases, memory cell 105-a may exhibit different electrical characteristics after multiple cycles of operation (e.g., a series of read or write operations). For example, if memory cell 105-a is relatively new compared to memory cell 105-a that has undergone a large number of read or write operations (e.g., a PCM cell using a small number of read or write operations), then the threshold voltage of memory cell 105-a (e.g., PCM cell) corresponding to logic state 1 may be different after receiving the same programming pulse (e.g., setting programming pulse) to store logic state 1. Additionally, in some cases, the chalcogenide material in memory cell 105-a (e.g., logic storage element 210) may experience a change in its resistance (also referred to as drift) after the chalcogenide material is programmed (e.g., crystallized or quenched) during a write operation. This change in resistance can cause a change in the threshold voltage of memory cell 105-a and may, after a certain period of time, prevent accurate reading of information from memory cell 105-a (e.g., PCM cell). In some embodiments, the amount of change may vary with ambient temperature.

[0104] When memory cell 105-a (e.g., a PCM cell) exhibits the different electrical characteristics described above, a counter-based read algorithm technique can provide robust read capabilities. In some embodiments, memory cell 105-a may be configured to store encoded user data comprising modified user data (or, in some cases, initial user data) and a plurality of parity bits (which may be added thereto). In some cases, the encoded user data stored in memory cell 105-a has been modified to include a predetermined number of bits having a logic state of 1. The number of bits having a logic state of 1 may vary depending on the encoding scheme used. In some cases, the number of bits having a logic state of 1 may be 50% (or other percentage) of the bits containing the encoded user data. In some embodiments, memory cell 105-a may be configured to store user data, and an additional set of memory cells 105-a may be configured to store counting information. The counting information may represent the number of bits in the user data having a logic state of 1. In some cases, the counting information may be pre-read to extract the number of bits in the user data having a logic state of 1 before reading the user data. Alternatively, the counting information can be determined when reading user data. The counter-based read algorithm utilizes an encoding scheme that provides a precise number of memory cells 105-a with a logic state of 1, which enables the counter-based read algorithm to accurately read user data regardless of the different electrical characteristics of the memory cells described above.

[0105] Now let's refer to Figure 3 An example is shown, illustrating a memory page corresponding to an extended codeword component.

[0106] Figure 3 The description includes an example of a conventional memory page containing a data portion 300 of one or more codewords CW having their own parity bit 302.

[0107] We can consider the combination of data portion 300 and parity bit 302 to form the entire correctable codeword, which in this example is regarded as a sixteen-bit codeword.

[0108] The remaining portion of the memory page consists of a group 304 of counter cells with associated parity protection and a bit-flip (BF) encoder 306. This bit flip can contain K bits and be appended to a codeword.

[0109] If the codeword contains a relatively small data portion of 300, then the counter bits have a proportionally higher impact. However, when using larger data bits, the corresponding counter has a smaller impact.

[0110] Now, for a specific instance only, let us assume that the codeword CW (which, after correction, is merged with the new data and parity) is formed by the following sequence of logical values: 0010011101001000

[0112] This sequence is stored in BankReadWriteBuffer(BRWBuff).

[0113] The corresponding BF encoder 306 is given, for example, by BF = 0, thus obtaining a combined two-bit differential value (0, 1). The BF encoder can be read as a dual unit or as a voting scheme superimposed on a dual unit.

[0114] The target counter is given by six logic values ​​(i.e., 6xd), implemented by the sequence 110xb, where its inverted value 001 gives the following result:

[0115] (1,0)(1,0)(0,1)

[0116] Therefore, written to Figure 3 The information segments in the entire array shown are composed of the following:

[0117] BF + Counters + Codewords

[0118] 01+101001+0010011101001000

[0119] The sensing phase can begin by calculating all logic values ​​"1" and comparing them with the values ​​given by the six bits contained in the counter section 304 6xd. Then, if no cell error is found, the reading phase can be stopped.

[0120] Of course, the memory array disclosed above containing codewords can be further improved and modified according to this disclosure, adding additional information to the codewords, such as information about the topology, previous pulse information, write status, etc.

[0121] For example, refer to Figure 4 Instances of this can reveal the existence of additional bit groups containing this extra CW information. Further attention should be paid to... Figure 4 The memory page shown represents a single patch, in other words, a structure containing a maximum number of bits that can be read in parallel with a single read operation of the sense amplifier.

[0122] Reducing the number of individual structures that can be read through a single read action is crucial for reducing the power involved during the bias phase.

[0123] Figure 4 The description includes an example of an improved memory page comprising one or more codewords CW and its own parity bit 402, a data portion 400, and an additional unit group 410 dedicated to supercodeword information.

[0124] The codeword information contained in the memory section 410 may include: the write status with or without the last cycle modification; the minimum value of the last low programming voltage Vth; the maximum value of the last low programming voltage Vth; the minimum value of the last high programming voltage Vth; the maximum value of the last high programming voltage Vth; and previously read information.

[0125] The above list of codeword information may not be intended to be exhaustive, but should be considered as voltage distribution information intended to optimize performance (i.e., read speed) or supply power or reliability or utilization in download mode, etc.

[0126] The counter-based sense amplifier method for the memory cells of this disclosure requires the use of a counter during the read phase, but the computation algorithm can operate in parallel with signal generation.

[0127] In addition, the counter can be ECC protected (e.g., dedicating four bits to protect up to eleven bits). Specifically, the detection power should be greater than the correction power.

[0128] The counter can be differential, double differential (coarse cell), etc.

[0129] A reference voltage Vref is not required for the counter reading phase because a bias voltage ramp is used, and the reading stops once the count value is determined, thus avoiding stress on the counter unit.

[0130] Furthermore, if the codewords are balanced (i.e., 50-50%), then we don't even need to store the count, but only the encoding, because we must expect N / 2 logic values ​​to be set to "1" or "0". This second method will be disclosed later.

[0131] However, as will be understood in the following paragraphs of this disclosure, the use of a counter does not imply a burden in terms of access time, as the counter read phase can be performed in parallel during the precharge phase while sensing regular data units.

[0132] Figure 4A This describes an example of the structure of a counter register associated with a memory codeword of this disclosure. Counter 404 corresponds to... Figure 4 The schematic box 404 contains two differential data units interconnected according to 3DXP technology (in other words: data <1> and data <0> With reverse cell data # <1> And data# <0> The first inverter 420 and the second inverter 430 are located between them.

[0133] Let's consider this now. Figure 5 Examples of memory devices that illustrate the methods of this disclosure.

[0134] More specifically, Figure 5 A block diagram 500 illustrates a memory array 505 supporting a counter-based sense amplifier method for reading memory cells according to embodiments of the present disclosure. The memory array 505 may be referred to as an electronic memory device and may be an example of a component of a memory device as described herein.

[0135] Memory array 505 may include one or more memory cells 510, a memory controller 515, word lines 520, a reference component 530, a sensing component 535, a digital line 540, and a latch 545. These components may communicate electronically with each other and perform one or more of the functions described herein. In some cases, memory cell 510 may include 3DXP memory cells. In some aspects, memory controller 515 may include a bias component 550 and a timing component 555. In some embodiments, sensing component 535 may serve as reference component 530. In other cases, reference component 530 may be optional.

[0136] The memory controller 515 can be connected to word lines 520, digital lines 540, and sensing components 535 (which may be referenced). Figure 1 and 2 (Examples of the described word line 110, digital line 115, and sensing component 125) Electronic communication. The components of the memory array 505 can communicate electronically with each other and can perform reference... Figure 3 and 4The described functional aspects. In some cases, the reference component 530, the sensing component 535, and the latch 545 may be components of the memory controller 515.

[0137] In some embodiments, digital line 540 communicates electronically with sensing component 535 and memory cell 510. Memory cell 510 may be written with logical states (e.g., a first, second, or third logical state). Word line 520 may communicate electronically with memory controller 515 and memory cell 510. Sensing component 535 may communicate electronically with memory controller 515, digital line 540, latch 545, and reference line 560. Reference component 530 may communicate electronically with memory controller 515 and reference line 560. Sensing control line 565 may communicate electronically with sensing component 535 and memory controller 515. In addition to components not listed above, these components may also communicate electronically with other components, connections, or buses both inside and outside the memory array 505.

[0138] The memory controller 515 can be configured to power the word line 520 or digital line 540 by applying voltage to those various nodes. For example, the bias component 550 can be configured to apply voltage to operate the memory cell 510 to read or write to the memory cell 510, as described above. In some cases, the memory controller 515 may include a row decoder, a column decoder, or both, as described herein. This allows the memory controller 515 to access, as shown in [reference] Figure 1 The illustrated memory cells 105. The bias component 550 may also provide voltage to the reference component 530 to generate a reference signal for the sensing component 535. Additionally, the bias component 550 may provide voltage for operating the sensing component 535.

[0139] In some embodiments, the memory controller 515 may perform its operations using timing component 555. For example, timing component 555 may control the timing of various word line selections or bit line biases, including timing for switching and voltage application to perform the memory functions discussed herein (e.g., read and write). In some cases, timing component 555 may control the operation of bias component 550.

[0140] Reference component 530 may include various components for generating a reference signal for sensing component 535. Reference component 530 may include circuitry configured to generate the reference signal. In some cases, reference component 530 may be implemented using other 3DXP memory cells. Sensing component 535 may compare a signal from memory cell 510 (via digital line 540) with the reference signal from reference component 530. After determining a logic state, the sensing component may then store an output in latch 545, where the output can be used according to the operation of the electronic device, of which memory array 505 is part. Sensing component 535 may include a sensing amplifier in electronic communication with latch 545 and memory cell 510.

[0141] At least some of the memory controller 515 and / or its various sub-components can be implemented in hardware, processor-executed software, firmware, or any combination thereof. If implemented as processor-executed software, the functionality of at least some of the memory controller 515 and / or its various sub-components can be performed by a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described in this disclosure. At least some of the memory controller 515 and / or its various sub-components can be physically located at various locations, including portions distributed such that functionality is implemented by one or more physical means at different physical locations. In some embodiments, according to various embodiments of this disclosure, at least some of the memory controller 515 and / or its various sub-components can be separate and distinct components. In other instances, at least some of the memory controller 515 and / or its various sub-components may be combined with one or more other hardware components, including (but not limited to): I / O components, transceivers, network servers, another computing device, one or more other components described in this disclosure, or combinations thereof according to various embodiments of this disclosure.

[0142] Memory controller 515 may apply a voltage (e.g., a read voltage) to a memory array configured to activate a set of memory cells containing encoded user data during a read operation. The voltage may increase at a constant rate over time. Memory controller 515 may track the number of memory cells that are activated (e.g., turned on) in response to the read voltage. In some embodiments, when a predetermined number of memory cells with a first logic state have been encoded with the user data, memory controller 515 may compare the number of activated memory cells with a predetermined number stored in the memory device. When the number of activated memory cells matches the predetermined number, memory controller 515 may stop applying the read voltage to the memory array and determine that all activated memory cells containing the encoded user data have a first logic state (e.g., a set state of a PCM cell). Additionally, memory controller 515 may determine that the remaining memory cells containing the encoded user data (e.g., memory cells not in operation when the number of activated memory cells matches the predetermined number) have a second logic state (e.g., a reset state of a PCM cell).

[0143] Now see Figure 6 Its public report describes a scheme 600 that starts from the initial stage 610 and performs time-scheduled actions through a sensing algorithm and according to the disclosed method, wherein line X pre-charging of 3DXP memory cells is typically performed.

[0144] Simultaneously, a full X and Y line precharge is performed on the surface mount of counter section 404. This precharge phase 620 is immediately followed by a counter bit read phase 640 executed using a fast ramp of bias voltage.

[0145] At the same time, if it can be passed Figure 6 According to the timeline, the data bits of the codeword are submitted to the line leakage compensation stage 630. The compensation stage is necessary in this type of memory to align the internal current and leakage current of the sensing circuit.

[0146] Therefore, these actions will be performed in the vertical cross-point memory device under any circumstances, and the time involved in this stage 630 does not extend to the read stage involved in reading the contents of the counter section.

[0147] The subsequent stage 650 precharges the line Y of the memory cell, followed by a slow ramp 660 of the bias read voltage applied to the data bits of the codeword.

[0148] The entire sensing and reading operation is completed in approximately 75 ns.

[0149] Figure 7The diagram shows a sequence of actions performed during the unique programming phase of the report to set the values ​​of the codewords with associated parity and ECC bits and the bits of the codewords that report the same logic value.

[0150] The first input action is represented by box 710, where the programmed algorithm takes care of the input data. The new data is merged with the previously corrected data in the buffer BankReadWriteBuffer (BRWBuff). The new ECC parity bit is calculated during this stage.

[0151] The algorithm continues to calculate the number of zeros in box 720, thereby setting the bit to flip the BF information.

[0152] Next, in box 730, the data is manipulated according to the BF value. If BF is a single bit (i.e., BF = 1), then the data is completely reversed; conversely, if the block of data to be written is divided into more codewords or portions, then BF can contain more bits. Different specifications can be obviously used.

[0153] The algorithm continues in block 740, which represents the stage where a program target counter with corresponding data and a data # is stored. Counter protection is implemented in this stage, thereby calculating the counter ECC parity check written into the cell.

[0154] The final programming stage is schematically shown in box 750, where the main codewords "0" and "1" are programmed. In other words, the entire codeword is written to track time; since various cells have drift over time, the writing of all cells includes a reset stage to set the same drift.

[0155] It should be noted that ensuring the error probability is below a predetermined threshold would be reasonable and measures should be taken to achieve this goal.

[0156] In this regard, let's refer to... Figure 8 As can be seen from the illustrative example, the sensing algorithm may rely on ECC1, where the trial and repetition phases are shown in box 870.

[0157] Figure 8 The public report describes a scheme 800 that, starting from the initial stage 810, uses a sensing algorithm and performs time-scheduled actions according to the disclosed method, typically performing line X pre-charging of 3DXP memory cells in the initial stage 810.

[0158] Simultaneously, a full X and Y line precharge is performed on the 404 surface mount of the counter section. For example... Figure 6 As seen in the examples, this precharge phase 820 is followed by a counter bit read phase 840 executed by a fast ramp of the bias voltage.

[0159] At the same time, if it can be passed Figure 8 According to the timeline, the data bits of the codeword are submitted to the line leakage compensation stage 830 to align the internal current and leakage current of the sensing circuit.

[0160] Therefore, these actions will be performed in the vertical cross-point memory device under any circumstances, and the time involved in this stage 830 does not extend to the read stage involved in reading the contents of the counter section.

[0161] The subsequent stage 850 precharges the line Y of the memory cell, followed by a slow ramp 860 of the bias read voltage applied to the data bits of the codeword to grow or increase.

[0162] During the ramp-up phase of this slow ramp used for the bias voltage, the parallel operation phase of trial and repetition shown in block 870 is also performed simultaneously.

[0163] The entire sensing and reading operation is completed in approximately 100 ns.

[0164] It is important to note that a single physical failure (of a logic value programmed in a memory cell) requires two logic bits to correct. Therefore, the Trial and Repeat (TnR) method performed in stage 870 is suitable for restoring correctability using ECC1.

[0165] In practice, ECC1 must reliably detect more than two bit errors and correct only one bit.

[0166] We can assume, for example, that we count N-1 bits and check the ECC1 status. If no error is found, then sensing stops. Later, if this is the case, then sensing is repeated by counting up more than two steps; in other words, counting up to N+1 bits. In other words, with possible correction power ECC1, all codewords with fewer than N-1 read logic values ​​"1" and codewords with more than N+1 read logic values ​​"1" cannot be corrected. Therefore, the entire range outside the interval [N-1, N+1] is unusable for correction, and there is no practical tool for reading more than N+1 bits.

[0167] Now, since ECC1 can correct the final error, in all other cases, the TnR method will require ECC2 to couple the repair bit with multiple (N-2, N, N+2) bits. In other words, if the ECC2 algorithm with higher detection power is needed to correct two bits, then a codeword presenting N-2, N, or N+2 logic values ​​"1" should be considered useful. Therefore, the N-2 codeword must be verified, and if the N-2 codeword is incorrect, the check will continue until an N-bit or N+2-bit codeword or the first correct codeword is reached. Once N+2 bits are reached, the check must stop because a codeword with more than N+2 logic values ​​"1" is incorrect. The last 1 will be the 1 with the highest probability of being correct.

[0168] Finally, it should be noted that the trial and repeat (TnR) sensing phase 870 using ECC1 can be pre-started when a certain threshold of the trigger is reached.

[0169] Figure 9 A block diagram 900 illustrates the sensing and reading phases of a memory cell performed via a read algorithm.

[0170] The first stage is illustrated by box 910, in which cells of the relevant counter register are read to obtain the number of bits of a codeword having one of two logical values ​​(e.g., logical value "1").

[0171] In stage 920, the counter register is downloaded and the value of Vref for the bias memory cell is set. The value of the bias voltage Vref allows the slope of the bias voltage ramp to be defined.

[0172] Now, the slope polarity is adjusted based on the value of the bit-flipping cell. For example, if the logic value of the BF cell is zero, then the Vref slope is set from top to bottom and the target counter register equals the target counter cell value. The slope polarity can depend on many factors, such as whether we need to read a logic value "0" or "1", or whether it is more convenient to use the read cell direction or the opposite direction. Therefore, in this stage, the slope rise is set and can even differ in two different read stages of the same device. Conversely, if the logic value of the BF cell is one, then the Vref slope is set from bottom to top and the target counter register is not equal to the target counter cell value.

[0173] Box 930 illustrates that the Vref value (regardless of whether it rises from the top, falls from the bottom, or vice versa) is also used to trigger the counter's unit. Clearly, under different sensing conditions, the situation can be reversed, with the same or opposite rising slope when BF=1.

[0174] Next, in test phase 940, it is compared whether the number of triggered memory cells is still less than the value contained in the associated or corresponding counter. If the value downloaded from the counter has not yet been reached, then the read phase continues and the test phase is repeated.

[0175] Conversely, if that value has been reached, the ramp-up stops and the reading phase terminates.

[0176] Figure 10 The illustration is a block diagram 1000 showing a schematic diagram of the sensing and reading phase of a memory cell performed via an alternative embodiment of the read algorithm, still based on the principles of this disclosure.

[0177] The first stage is illustrated by box 1010, in which cells of the relevant counter register are read to obtain the value of the number of bits of a codeword having one of two logical values ​​(e.g., the logical value "1").

[0178] In stage 1020, the counter register is downloaded and the value of Vref for the bias memory cell is set. The value of the bias voltage Vref allows the slope of the bias voltage ramp to be defined.

[0179] As in Figure 9 In this example, the polarity of the ramp is adjusted based on the value of the bit-flipping cell. For instance, if the logic value of the BF cell is zero, then the Vref slope is set from top to bottom and the target counter register equals the target counter cell value. Conversely, if the logic value of the BF cell is one, then the Vref slope is set from bottom to top and the target counter register does not equal the target counter cell value.

[0180] Box 1030 explains that the Vref value (regardless of whether it rises from the top, rises from the bottom, or vice versa) is also used to trigger the counter's cell.

[0181] Next, in test phase 1040, it is compared whether the number of triggered memory cells is still less than the value contained in the associated or corresponding counter minus 1 [N-1]. This value corresponds to the number of counters N minus the ECC correction power. If the value [N-1] downloaded from the counter has not yet been reached, then the read phase continues and the test phase is repeated.

[0182] When this value [N-1] is reached, an additional test is performed in box 1050 to check if the ECC1 value is correct. If the answer is yes, then the ramp-up stops and the read phase terminates in box 1060. This means that the memory cell is not stressed by a higher bias voltage, and a higher bias voltage is not used to continue the already completed read phase.

[0183] Conversely, if the answer is negative, then a possible error involving at least three bits may have occurred. Figure 8 The Trial and Repeat (TNR) mechanism shown in the diagram is activated. In this case, an additional test is performed in block 1070, where the number of triggered memory cells is compared to whether it is still less than the value contained in the associated or corresponding counter plus 1 [N+1]. However, this additional and extended read process is of low probability and can only be activated at rare occurrences.

[0184] The method disclosed in this paper has the significant advantage of avoiding the setting of a fixed bias voltage value, because the read phase is performed using an increased voltage that does not rise to the maximum value touched without affecting the memory cell at most times.

[0185] Figure 11 This diagram illustrates a small increase in cost for manufacturing memory devices configured to manage counter cells associated with corresponding codewords. The horizontal axis relates to the number of cells per memory page, while the vertical axis indicates the percentage increase in algorithmic cost considering super-memory bits for different counter complexities.

[0186] The curve shown indicates increased reliability in the direction indicated by the central arrow. Of course, trade-offs can be found in the configuration of coarse cells (2X, 3X); differential coarse cells, ECC1, differential ECC1, balancing codes, and / or wear equalization processes.

[0187] As the possible numerical indications suggest, a 128-byte page would involve a reasonable increase of 2.48% in overall manufacturing costs. Specifically, for a 128-byte memory page with differential ECC1 protected cells, this fact demonstrates that the proposed method and memory architecture offer a simple design and relatively minimal cost.

[0188] Furthermore, by adding N or more bit-flipping BF units, the maximum number of zeros can be appropriately increased, thus reducing the bit error rate due to the switching distribution (low Vth). It would be possible to reduce the number of bits to be checked in a single codeword or to keep that number a relatively low percentage by, for example, increasing the number of bit-flipping units.

[0189] The method disclosed herein provides a deterministic approach that is independent of the distribution shape (Gaussian versus non-Gaussian) of the stored cells; furthermore, by employing ramped operation with lower voltages, reset interference can be managed more appropriately on average.

[0190] The reference voltage Vref can be set after the first and fast read pulses focused on the counter section; therefore, the reference voltage is set for each codeword.

[0191] This is only for comparison with known solutions. Figure 12This diagram shows a time-varying distribution of cells detectable in two different general-purpose memory pages XXX and ZZZ, each containing 128 bits and having different sensitivities to bias read voltages, during the read phase.

[0192] In the upper diagram associated with page XXX, the possible distribution 1210 is indicated by the eighty (80) bits with logic value “1” and the remaining forty-eight (48) bits with logic value “0”.

[0193] In embodiments of this disclosure, the memory cell exhibits an electrical response to a first voltage. For example, in one embodiment, the memory cell may switch or not switch in response to a predetermined increase in voltage value.

[0194] In one embodiment, whether a given memory cell switches in response to the predetermined voltage value depends, for example, whether the memory cell is programmed to a logic value 1 or a logic value 0, and whether the memory cell exhibits a threshold voltage within an overlapping range between distributions.

[0195] In embodiments of this disclosure, if the applied voltage has an amount greater than a presented threshold voltage, then the memory cell switches in response to the applied voltage. Therefore, the plurality of memory cells may be grouped based on their response to the first voltage, including: memory cells programmed with logic 1 that switch in response to the first voltage; or memory cells programmed with logic 0 that do not switch in response to the first voltage.

[0196] exist Figure 12 In the diagram, the slope 1250 indicates the voltage ramp increase during the read phase, while the expanded distribution of cells in memory page XXX is shown by WC being fixed and the time difference Δ required to read all 80 cells with logic value "1".

[0197] The lower diagram relates to another page, ZZZ, where the distribution of cells with relative logic values ​​"1" and "0" is different. In this case, the correction read phase may fail because the time difference Δ will also include cells with logic value "0".

[0198] Figure 13 The comparison is shown in the presence of Figure 12 The image shows a similar read phase performed on two different memory pages XXX and ZZZ with the same distribution. Figure 12 The diagram shows that the slope of the increased bias voltage at 1350 corresponds to the slope of the previous diagram at 1250.

[0199] in this way Figure 13 As shown, WC is the maximum time tRCD required to complete the reading of a given codeword. Under the presence of an extended or longer distribution, this represents the number of eighty units with a logic value of "1" completed at time t1.

[0200] Conversely, in the distribution shown with respect to memory page ZZZ, the read phase of eighty cells with logic value "1" is completed at time tx, so a correct read phase is obtained in the shorter time frame because tx < t1.

[0201] Reference is now made to Figure 14 of the example, it can be understood that the method according to the present disclosure, which uses an increasing bias voltage with different slopes, can properly affect successful reading.

[0202] Figure 14 shows a conventional ramp 1450, which corresponds to the conventional ramp in the prior Figure 12 and 13 ramp 1350 or 1250, which has a predetermined conventional slope. If we imagine modifying this slope at time t0 to accelerate the rising of the ramp (as reported by the inclined line 1410), we will obtain a correct read result, but we will place excessive stress on the memory cells without obtaining an effective advantage.

[0203] Conversely, if we reduce the rising rate of the ramp (as reported by another inclined line 1470), we will get a single read failure that will be compensated by ECC correction. However, in this case, the electrical stress on the memory cells will be appropriate, and satisfactory read results are obtained, thereby increasing the cycle life of the memory device.

[0204] Possible failures in the read phase are all outside the maximum time frame set by the selection of the reference voltage.

[0205] When the WC is affected by noise, only reducing the slew rate can affect the read phase, while slowing down has no effect.

[0206] Figure 14 the possible uncertainty that can be regarded as the rising slope results in Figure 12 system instead of Figure 13 system is an indication of a 1 failure. If we have applied a fixed time difference Δ, the reached voltage value Vref in Figure 12 the system will be slope * Δ, which will vary; conversely, in the case of the counter of the present disclosure, the voltage value Vref maintains its value for the read phase of N cells containing logic "1" and exhibits certain immunity to slope uncertainty.

[0207] Finally, we can briefly outline a few aspects of the memory structure and reading method of the present disclosure: the first is the manipulation of encoding write data until the desired number of zeros (or ones) by using an appropriate set (1 to N bits) of bit flip information according to each codeword.

[0208] In addition, the BF unit is protected by a vertical 3D intersection unit voting scheme or by a differential unit (BF / BF#) with ECC bits.

[0209] The storage algorithm is configured to analyze and manipulate the write pattern to store the number of zeros (or ones) into the target counter.

[0210] Those counters are associated with the corresponding codewords and are also implemented through vertical 3D intersection memory cells.

[0211] It should be noted that the target counter is implemented through a vertical 3D crosspoint differential cell protected by ECC bits (two cells per bit).

[0212] As an alternative, the target counter can be implemented using a voting scheme based on vertical 3D intersection units, which can be considered as a protection scheme including ECC bits.

[0213] The target counter cell is read during the pre-charge phase of the associated data cell using a ramp-up scheme from low to high cell voltage.

[0214] As an alternative, the target counter unit can be read using a fixed VDM scheme.

[0215] Even the data unit of the codeword is read using the previously read target counter information to stop the bias voltage ramp on the data unit by a ramp scheme from low to high unit voltage (detecting low Vth units).

[0216] Finally, the "soft" information is triggered and stored in an additional latch for each sensing amplifier for subsequent use in soft ECC technology.

[0217] The more basic read algorithm uses an ECC correction scheme when counting codewords for the N value, while the alternative read algorithm uses a trial and repeat soft engine to pre-trigger ECC1 when counting N-1 values, and if ECC1 cannot correct the N-1 steps, then the count continues until N+1 values.

[0218] As an alternative, a more robust correction scheme is employed. Additionally, the reading algorithm can be used to pre-trigger ECC2 with the soft engine when counting N-2 and N. If ECC2 cannot correct the N-2 and N steps, then the count continues until N+2.

[0219] Additional codeword information (such as topology, last Vref, read parameters (start, stop, test #, etc.), write status, etc.) can also be stored in the associated register.

[0220] Some examples of the methods and apparatus described above may further include processes, features, components, or instructions for determining, at least in part, the total number of memory cells having a first logical state based on a set of values. Some examples of the methods and apparatus described above may further include processes, features, components, or instructions for updating a counter to a first count value.

[0221] Figure 15 A block diagram 1500 illustrates a memory system 1520 supporting a counter-based sense amplifier method for memory cells, according to an example disclosed herein. The memory system 1520 may be as described in the references... Figures 1 to 14 Examples of aspects of the described memory system. Memory system 1520 or its various components may be examples of means for performing various aspects of the counter-based sense amplifier method for memory cells as described herein. For example, memory system 1520 may include storage component 1525, counter read component 1530, data read component 1535, counting component 1540, stop component 1545, start component 1550, codeword component 1555, bit flip component 1560, compare component 1565, codeword read component 1570, test component 1575, or any combination thereof. Each of these components may communicate directly or indirectly with each other (e.g., via one or more buses).

[0222] According to the examples disclosed herein, memory system 1520 may support reading memory cells. Storage component 1525 may be configured or otherwise supported to store in a counter associated with the memory cell array a value for the number of bits having a predetermined logical value stored in the array. Counter read component 1530 may be configured or otherwise supported to read from the counter a value corresponding to the number of bits having the predetermined logical value. Data read component 1535 may be configured or otherwise supported to read data stored in the memory cell array by applying a ramp of bias voltage. Counting component 1540 may be configured or otherwise supported to count the number of bits having the predetermined logical value during a data read phase. Stop component 1545 may be configured or otherwise supported to stop the data read phase when the number of bits having the predetermined logical value equals the value stored in the counter.

[0223] In some instances, the counter stores the number of bits that first undergo a bit-flipping phase to obtain a predetermined logic value having no less than 50% of the data bits.

[0224] In some instances, the bit-flipping stage is used to encode data in a 50-50% balanced format.

[0225] In some instances, the read counter is executed via a fast bias voltage ramp on the counter, while simultaneously initiating a bias precharge or line leakage compensation phase for the data bit portion of the memory cell array.

[0226] In some instances, there are data bits with associated parity bits and counters with associated ECC bits.

[0227] In some instances, the codeword further includes a set of bit-flipping units with corresponding ECC bits.

[0228] In some instances, a data bit cell is automatically disconnected whenever it is triggered.

[0229] In some instances, whenever a data bit cell is triggered, a counter that decrements by a value corresponding to the number of cells having the predetermined logic value is simultaneously decremented.

[0230] In some instances, the read counter and data read phase are executed using a voltage ramp with the same slope.

[0231] In some instances, the final contents of the trigger unit are stored in an additional latch for each sense amplifier for subsequent use in soft ECC technology.

[0232] In some instances, the parallel operation of attempting and repeating ECC occurs during the data reading phase.

[0233] In some instances, the parallel operation of ECC2 is attempted and repeated during the data reading phase of the N-2, N, and N+2 cells of the codeword in the array.

[0234] In some instances, storage component 1525 may be configured or otherwise supported to include means for storing the number of bits of a codeword having a predetermined logic value in a counter associated with the codeword of the memory cell. In some instances, counter read component 1530 may be configured or otherwise supported to include means for reading the contents of the counter before reading the contents of the codeword. Start component 1550 may be configured or otherwise supported to include means for initiating a counter read phase during a precharge phase of the codeword. In some instances, stop component 1545 may be configured or otherwise supported to include means for stopping the codeword read phase when the number of bits having the predetermined logic value corresponds to the contents of the counter.

[0235] In some instances, the bit-flipping component 1560 may be configured or otherwise supported for a component used in the bit-flipping stage to obtain a predetermined number of bits having a predetermined logical value of not less than 50% of the data.

[0236] In some instances, the bit-flipping stage is used to encode data in a 50-50% balanced format.

[0237] In some instances, reading the counter's contents is performed via a fast bias voltage ramp, simultaneously with the bias pre-charge or line leakage compensation phase of the start codeword.

[0238] In some instances, the comparison component 1565 may be configured or otherwise support a component for comparing the number of cells read from the codeword and having the predetermined logic value with the content read from the counter. In some instances, the codeword reading component 1570 may be configured or otherwise support a component for repeatedly reading the codeword until a moment when the number of cells corresponds to the content of the counter.

[0239] In some instances, the counter read phase and the codeword read phase are performed using voltage ramps with the same slope.

[0240] In some instances, the parallel operation of the trial and repeat algorithm with ECC occurs during the data reading phase and the codeword reading phase.

[0241] In some instances, the trial and repeat algorithm and ECC1 can be initiated based on reaching a certain threshold of the triggering unit.

[0242] In some instances, a reference voltage Vref is not required for the counter read phase because a bias voltage ramp is used, and the counter read phase stops once the value is determined.

[0243] In some instances, test component 1575 may be configured or otherwise supported as a component for ECC1 testing after a number N-1 codeword data units have been read.

[0244] Figure 16 The illustration shows a flowchart of method 1600, which supports a counter-based sense amplifier method for memory cells according to examples disclosed herein. Operation of method 1600 can be implemented by a memory system or its components as described herein. For example, operation of method 1600 can be achieved by... (See reference...) Figures 1 to 15 The described memory system performs the function. In some instances, the memory system may execute a set of instructions to control the functional elements of the device to perform the described function. Alternatively, the memory system may use dedicated hardware to perform aspects of the described function.

[0245] At 1605, the method may include storing a value in a counter associated with the memory cell array a value representing the number of bits having predetermined logical values ​​of data bits stored in the array. The operation of 1605 may be performed according to examples as disclosed herein. In some examples, aspects of the operation of 1605 may be as described in references... Figure 15 The described storage component 1525 is executed.

[0246] At 1610, the method may include reading a value from the counter corresponding to the number of bits having the predetermined logic value. The operation of 1610 may be performed according to examples as disclosed herein. In some instances, aspects of the operation of 1610 may be as described in references... Figure 15 The counter reading component 1530 described is executed.

[0247] At 1615, the method may include reading data stored in the memory cell array by applying a ramp of bias voltage. The operation of 1615 may be performed according to examples as disclosed herein. In some examples, aspects of the operation of 1615 may be as described in references... Figure 15 The described data reading component 1535 is executed.

[0248] At 1620, the method may include counting the number of bits having the predetermined logic value during the data read phase. The operation of 1620 may be performed according to examples as disclosed herein. In some instances, aspects of the operation of 1620 may be as described in references... Figure 15 The described counting component 1540 is executed.

[0249] At 1625, the method may include stopping the data reading phase when the number of bits having the predetermined logic value is equal to the value stored in the counter. The operation of 1625 may be performed according to examples as disclosed herein. In some instances, aspects of the operation of 1625 may be as described in references... Figure 15 The described stop component 1545 is executed.

[0250] In some instances, the device as described herein may perform one or more methods, such as method 1600. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) or any combination thereof for performing aspects of this disclosure:

[0251] Aspect 1: A method, apparatus, or non-transitory computer-readable medium comprising operations, features, circuits, logic, components, or instructions, or any combination thereof, for performing: storing in a counter associated with a memory cell array a value for the number of bits having predetermined logic values ​​stored in the array; reading from the counter a value corresponding to the number of bits having the predetermined logic values; reading data stored in the memory cell array by applying a slope of a bias voltage; counting the number of bits having the predetermined logic values ​​during a data read phase; and stopping the data read phase when the number of bits having the predetermined logic values ​​equals the value stored in the counter.

[0252] Aspect 2: The method, apparatus, or non-transitory computer-readable medium according to aspect 1, wherein the counter stores the number of bits that first use a bit-flipping stage to obtain a predetermined logic value having not less than 50% of the data bits.

[0253] Aspect 3: The method, apparatus, or non-transitory computer-readable medium according to aspect 2, wherein the bit-flipping stage is used to encode data in a 50-50% balanced format.

[0254] Aspect 4: The method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 3, wherein the read counter is executed by a fast bias voltage ramp on the counter, while simultaneously initiating a bias pre-charge or line leakage compensation phase for the data bit portion of the memory cell array.

[0255] Aspect 5: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 4, wherein data bits have associated parity bits and a counter has associated ECC bits.

[0256] Aspect 6: The method, apparatus, or non-transitory computer-readable medium according to aspect 5, wherein the codeword further comprises a set of bit-flipping units having corresponding ECC bits.

[0257] Aspect 7: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 6, wherein a unit of data bit is automatically disconnected whenever triggered.

[0258] Aspect 8: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 7, wherein whenever a unit of a data bit is triggered, a counter whose value is decremented simultaneously includes a value corresponding to the number of units having the predetermined logic value.

[0259] Aspect 9: The method, apparatus or non-transitory computer-readable medium according to any one of aspects 1 to 8, wherein the read counter and the data read phase are performed by voltage ramps having the same slope.

[0260] Aspect 10: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 9, wherein the contents last triggered by the triggering unit are stored in an additional latch for each sensing amplifier for subsequent use in soft ECC technology.

[0261] Aspect 11: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 10, wherein the parallel operation of attempting and repeating ECC occurs during the data reading phase.

[0262] Aspect 12: The method, apparatus, or non-transitory computer-readable medium according to aspect 11, wherein the attempt and repetition of parallel operation of ECC2 is during the data reading phase of the N-2, N, and N+2 units of the codeword of the array.

[0263] Figure 17 The illustration shows a flowchart of method 1700, which supports a counter-based sense amplifier method for memory cells according to examples disclosed herein. Operation of method 1700 can be implemented by a memory system or its components as described herein. For example, operation of method 1700 can be achieved by... (See reference...) Figures 1 to 15 The described memory system performs the function. In some instances, the memory system may execute a set of instructions to control the functional elements of the device to perform the described function. Alternatively, the memory system may use dedicated hardware to perform aspects of the described function.

[0264] At 1705, the method may include storing a value in a counter associated with the codeword of the memory cell for the number of bits of the codeword having a predetermined logic value. The operation of 1705 may be performed according to examples as disclosed herein. In some examples, aspects of the operation of 1705 may be as described in references... Figure 15 The described storage component 1525 is executed.

[0265] At 1710, the method may include reading the contents of a counter before reading the contents of a codeword. The operation of 1710 may be performed according to examples disclosed herein. In some instances, aspects of the operation of 1710 may be as described in references... Figure 15 The counter reading component 1530 described is executed.

[0266] At 1715, the method may include a start counter read phase during the precharge phase of the codeword. The operation of 1715 may be performed according to examples as disclosed herein. In some instances, aspects of the operation of 1715 may be as described in references... Figure 15 The described starting component 1550 is executed.

[0267] At 1720, the method may include stopping the codeword reading phase when the number of bits having the predetermined logic value corresponds to the contents of a counter. The operation of 1720 may be performed according to examples as disclosed herein. In some instances, aspects of the operation of 1720 may be as described in the references... Figure 15 The described stop component 1545 is executed.

[0268] In some instances, the device as described herein may perform one or more methods, such as method 1700. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) or any combination thereof for performing aspects of this disclosure:

[0269] Aspect 13: A method, apparatus, or non-transitory computer-readable medium comprising operations, features, circuits, logic, components, or instructions, or any combination thereof, for performing: storing in a counter a value for the number of bits of a codeword having a predetermined logic value in a counter associated with a codeword of a memory cell; reading the contents of the counter before reading the contents of the codeword; initiating a counter reading phase during a pre-charge phase of the codeword; and stopping the codeword reading phase when the number of bits having the predetermined logic value corresponds to the contents of the counter.

[0270] Aspect 14: The method, apparatus, or non-transitory computer-readable medium according to aspect 13 further includes an operation, feature, circuit, logic, component, or instruction, or any combination thereof, for a bit-flipping phase to obtain a predetermined number of bits having a predetermined logic value having not less than 50% of the data.

[0271] Aspect 15: The method, apparatus, or non-transitory computer-readable medium according to aspect 14, wherein the bit-flipping phase is used to encode data in a 50-50% balanced format.

[0272] Aspect 16: The method, apparatus or non-transitory computer-readable medium according to any one of aspects 13 to 15, wherein reading the contents of the counter is performed by a fast bias voltage ramp, while a bias pre-charge or line leakage compensation phase of the start codeword is performed.

[0273] Aspect 17: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 13 to 16 further comprises an operation, feature, circuit, logic, component, or instruction or any combination thereof for performing: a comparison between the number of units read from a codeword and having the predetermined logic value and the content read from a counter; and the repeated reading of the codeword until a moment when the number of units corresponds to the content of the counter.

[0274] Aspect 18: The method, apparatus, or non-transitory computer-readable medium according to aspect 17, wherein the counter reading phase and the codeword reading phase are performed by voltage ramps having the same slope.

[0275] Aspect 19: The method, apparatus or non-transitory computer-readable medium according to any one of aspects 13 to 18, wherein the parallel operation of the trial and repetition algorithm and ECC occurs during the data reading phase and the codeword reading phase.

[0276] Aspect 20: The method, device, or non-transitory computer-readable medium according to aspect 19, wherein the trial and repetition algorithm and ECC1 may be initiated based on reaching a certain threshold of the triggering unit.

[0277] Aspect 21: The method, apparatus or non-transitory computer-readable medium according to any one of aspects 13 to 20, wherein a reference voltage Vref is not required for the counter reading phase, because a bias voltage ramp is used and the counter reading phase is stopped once a value has been determined.

[0278] Aspect 22: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 13 to 21 further includes an operation, feature, circuit, logic, component, or instruction, or any combination thereof, for ECC1 testing after a number N-1 of codeword data units have been read.

[0279] It should be noted that the methods described above describe possible implementations, and the operations and steps may be rearranged or otherwise modified, and other implementations are possible. Furthermore, embodiments combining two or more of the methods may be used.

[0280] Describe a device. The following provides an overview of various aspects of the device as described herein:

[0281] Aspect 1: A memory device comprising at least one memory array including one or more memory cell arrays, and a memory controller supporting a counter-based sense amplifier method for reading memory cells, comprising: at least one codeword in the memory array, comprising data bits having associated parity bits and a counter having associated ECC bits.

[0282] Aspect 2: The memory device according to aspect 1, wherein the codeword further comprises at least one set of bit-flipping units having corresponding ECC bits.

[0283] Aspect 3: The memory device according to aspect 2, wherein the set of bit-flipping cells is protected by a 3D crosspoint cell voting scheme or by a differential 3D crosspoint cell with ECC.

[0284] Aspect 4: The memory device according to any one of aspects 2 to 3, wherein the set of bit-flipping units comprises a number of 1 to N units calculated based on the length of the codeword.

[0285] Aspect 5: A memory device according to any one of aspects 1 to 4, wherein the memory cell includes a vertical 3D intersection memory cell.

[0286] Aspect 6: The memory device according to any one of aspects 1 to 5, wherein the counter is implemented through a memory cell of the data bits of the codeword.

[0287] Aspect 7: The memory device according to any one of aspects 1 to 6, wherein the contents last triggered by the trigger unit are stored in an additional latch for each sense amplifier for subsequent use in soft ECC technology.

[0288] Aspect 8: A memory device according to any one of aspects 1 to 7, wherein the memory controller is configured to execute the counter read phase in parallel with the bias precharge or line leakage compensation phase of the data bits of the codeword.

[0289] Describe a device. The following provides an overview of various aspects of the device as described herein:

[0290] Aspect 9: A memory device comprising at least one memory array including one or more memory cell arrays, and a memory controller supporting a counter-based sense amplifier method for reading memory cells, comprising: a set of bit-flipping units for each codeword of the memory array, for encoding manipulated stored data up to the desired number of bits in a logic value.

[0291] Aspect 10: The memory device according to aspect 9, wherein the set of bit-flipping units for each codeword is protected by a 3D crosspoint unit voting scheme or by a differential 3D crosspoint unit with ECC.

[0292] Aspect 11: The memory device according to any one of aspects 9 to 10 further includes a counter for each codeword, wherein the number of bits corresponding to codewords having the same logic value is recorded.

[0293] Aspect 12: The memory device according to aspect 11, wherein the memory controller is configured to read the contents of the counter and the contents of the codeword using a bias voltage ramp having the same slope.

[0294] Aspect 13: A memory device according to any one of aspects 9 to 12, comprising an extended codeword including the set of bit-flipping units, a counter protected by a parity bit, data bits having corresponding parity bits, and other codeword information.

[0295] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced in the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, those skilled in the art will understand that the signal may represent a bus of signals, wherein the bus may have multiple bit widths.

[0296] Chalcogenide materials can be materials or alloys containing at least one of the elements S, Se, and Te. The phase change materials discussed in this paper can be chalcogenide materials. Chalcogenide materials can be alloys containing the following elements: S, Se, Te, Ge, As, Al, Sb, Au, indium (In), gallium (Ga), tin (Sn), bismuth (Bi), palladium (Pd), cobalt (Co), oxygen (O), silver (Ag), nickel (Ni), and platinum (Pt). Example chalcogenide materials and alloys may include, but are not limited to: Ge-Te, In-Se, Sb-Te, Ga-Sb, In-Sb, As-Te, Al-Te, Ge-Sb-Te, Te-Ge-A s, In-Sb-Te, Te-Sn-Se, Ge-Se-Ga, Bi-Se-Sb, Ga-Se-Te, Sn-Sb-Te, In-Sb-Ge, Te-Ge-Sb-S, T e-Ge-Sn-O, Te-Ge-Sn-Au, Pd-Te-Ge-Sn, In-Se-Ti-Co, Ge-Sb-Te-Pd, Ge-Sb-Te-Co, Sb-Te-B i-Se, Ag-In-Sb-Te, Ge-Sb-Se-Te, Ge-Sn-Sb-Te, Ge-Te-Sn-Ni, Ge-Te-Sn-Pd or Ge-Te-Sn-Pt. As used herein, hyphenated chemical composition designations indicate elements contained in a particular compound or alloy and are intended to represent all stoichiometry involving the indicated element. For example, Ge-Te may contain Ge x Te yWhere x and y can be any positive integers. Other examples of variable resistivity materials may include binary metal oxide materials or mixed-valence oxides comprising two or more metals (e.g., transition metals, alkaline earth metals, and / or rare earth metals). Embodiments are not limited to specific variable resistivity materials or materials associated with memory elements of memory cells. For example, other examples of variable resistivity materials may be used to form memory elements and may comprise chalcogenide materials, giant magnetoresistive materials, or polymer-based materials, plus others.

[0297] The device comprising the memory device 100 discussed herein can be formed on a semiconductor substrate, such as silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In others, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a subregion of the substrate can be controlled by doping with various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0298] The descriptions herein, illustrated with reference to the accompanying drawings, depict exemplary configurations and do not represent all implementable or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description" and does not imply "preferred" or "superior to other examples." The detailed description includes specific details intended to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some cases, well-known structures and arrangements are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0299] In the accompanying drawings, similar components or features may have the same reference numerals. Additionally, various components of the same type may be distinguished by using a dash followed by a second reference numeral to differentiate them among similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components that have the same first reference numeral but are independent of the second reference numeral.

[0300] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored as one or more instructions or code on or transmitted via a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functions may also be physically located in various locations, including distributed implementations such that portions of the functions are implemented in different physical locations.

[0301] The description herein is provided to enable those skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but should be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A counter-based sensing amplifier method for reading memory cells, comprising: During the programming phase, a value for the number of bits having predetermined logical values ​​of data bits stored in the array is stored in a counter associated with the memory cell array; Read the value corresponding to the number of bits having the predetermined logic value from the counter; Data stored in the memory cell array is read by applying a bias voltage ramp; During the data reading phase, count the number of bits having the predetermined logic value; and The data reading phase stops when the number of bits having the predetermined logic value equals the value stored in the counter.

2. The method of claim 1, wherein the storage in the counter comprises: During the bit-flipping phase, the number of bits having the predetermined logic value is obtained, the number of bits including at least 50% of the data bits.

3. The method of claim 2, wherein the bit-flipping stage is used to encode data that achieves a 50-50% balanced pattern.

4. The method of claim 1, wherein reading the counter is performed by a fast bias voltage ramp on the counter, while simultaneously initiating a bias precharge or line leakage compensation phase for the data bit portion of the memory cell array.

5. The method of claim 1, wherein the memory cell array comprises at least one codeword including data bits having associated parity bits and a counter having associated ECC bits.

6. The method of claim 5, wherein the codeword further comprises a set of bit-flipping units having corresponding ECC bits.

7. The method of claim 1, wherein, in response to a trigger, the unit of the data bit is automatically disconnected.

8. The method of claim 1, wherein in response to a cell being triggered, the counter comprising decrementing the value corresponding to the number of cells having the predetermined logic value.

9. The method of claim 1, wherein reading the counter and the data reading phase are performed by voltage ramps having the same slope.

10. The method of claim 1, wherein the last contents of the trigger unit are stored in an additional latch for each sensing amplifier for subsequent use in soft ECC technology.

11. The method of claim 1, further comprising: During the data reading phase, parallel operations of attempting and repeating ECC are performed.

12. The method of claim 11, further comprising: During the data read phase of the N-2, N, and N+2 units of the codeword in the array, parallel operations of attempting and repeating ECC2 are performed.

13. A method for reliably reading memory cells in a vertical 3D memory device, comprising: During the programming phase, the number of bits of the codeword having a predetermined logic value is stored in a counter associated with the codeword in the memory cell; Read the content of the counter before reading the content of the codeword; The counter reading phase begins during the pre-charging phase of the codeword; and The codeword reading phase stops when the number of bits with the predetermined logic value corresponds to the content of the counter.

14. The method of claim 13, further comprising: During the bit-flipping phase, the number of bits having the predetermined logic value is obtained, the number of bits comprising at least 50% of the data.

15. The method of claim 14, wherein the bit-flipping stage is used to encode data in a 50-50% balanced format.

16. The method of claim 13, wherein reading the contents of the counter is performed by a fast bias voltage ramp, while simultaneously initiating a bias precharge or line leakage compensation phase for the codeword.

17. The method of claim 13, further comprising: A comparison is made between the number of units read from the codeword and having the predetermined logic value and the content read from the counter; and The reading of the codeword is repeated until the number of units corresponds to the content.

18. The method of claim 17, wherein the counter reading phase and the codeword reading phase are performed by voltage ramps having the same slope.

19. The method of claim 13, further comprising: During the data reading phase and the codeword reading phase, the trial and repetition algorithm and ECC are performed in parallel.

20. The method of claim 19, further comprising: Based on the number of thresholds reached by the triggered unit, the initial attempt and repetition algorithm are used in conjunction with ECC1.

21. The method of claim 13, wherein performing the counter reading phase comprises: The counter reading phase is performed, and the counter reading phase is stopped once the value has been determined, based at least in part on the use of a bias voltage ramp, without the need for a reference voltage Vref.

22. The method of claim 13, further comprising: Perform the ECC1 test after N-1 codeword data units have been read.

23. A memory device comprising at least one memory array including one or more memory cell arrays, and a memory controller supporting a counter-based sense amplifier method for reading the memory cells according to any one of claims 1-12, comprising: At least one codeword in the memory array includes data bits with associated parity bits and a counter with associated ECC bits.

24. The memory device of claim 23, wherein the codeword further comprises at least one set of bit-flipping units having corresponding ECC bits.

25. The memory device of claim 24, wherein the set of bit-flipping cells is protected by a 3D crosspoint cell voting scheme or by a differential 3D crosspoint cell with ECC.

26. The memory device of claim 24, wherein the set of bit-flipping units comprises a number of 1 to N units calculated based on the length of the codeword.

27. The memory device of claim 23, wherein the memory cell comprises a vertical 3D intersection memory cell.

28. The memory device of claim 23, wherein the counter is implemented via the memory cell of the data bits of the codeword.

29. The memory device of claim 23, wherein the contents last triggered by the trigger unit are stored in an additional latch for each sense amplifier for subsequent use in soft ECC technology.

30. The memory device of claim 23, wherein the memory controller is configured to perform a counter read phase in parallel with a bias precharge or line leakage compensation phase of the data bits of the codeword.

31. A memory device comprising at least one memory array including one or more memory cell arrays, and a memory controller supporting a counter-based sense amplifier method for reading the memory cells according to any one of claims 1-12, comprising: A set of bit-flipping units for each codeword of the memory array, used to encode manipulated stored data up to the desired number of bits in a logical value.

32. The memory device of claim 31, wherein the set of bit-flipping units for each codeword is protected by a 3D crosspoint unit voting scheme or by a differential 3D crosspoint unit with ECC.

33. The memory device of claim 31, further comprising a counter for each codeword, wherein the number of bits corresponding to codewords having the same logic value is recorded.

34. The memory device of claim 33, wherein the memory controller is configured to read the contents of the counter and the contents of the codeword using a bias voltage ramp having the same slope.

35. The memory device of claim 31, comprising an extended codeword including the set of bit-flipping units, a counter protected by a parity bit, data bits having corresponding parity bits, and other codeword information.

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