Verification system

Abstract

The application provides a verification system, which comprises a reference model module, a reference model interface module and a score board module, wherein the reference model module is used for predicting timing logic according to to-be-tested data to obtain first predicted data; the reference model interface module is connected with a first end of the reference model module, the reference model interface module is used for predicting combinational logic for the first predicted data, and the reference model interface module is further used for sending second predicted data to the reference model module, so that the reference model module adjusts the first predicted data according to the second predicted data to obtain adjusted expected data; the score board module is connected with a second end of the reference model module, the score board is used for connecting an output end of a to-be-tested design module, the score board module is used for receiving actual data and expected data, and the to-be-tested design module is verified according to the expected data and the actual data. The stability of the verification system is high, and the debugging efficiency is high.

Description

Technical Field

[0001] This application relates to the field of chip verification technology, and more specifically, to a verification system. Background Technology

[0002] Existing verification methodologies such as UVM (Universal Verification Methodology) and VMM (Verification Methodology Manual) involve the detector handing over transactions monitored by the bus to a reference model. The reference model then predicts the logic function of the design under test (DUT). The reference model needs to predict the output of the DUT. However, if a scenario requires predicting the output for every clock cycle, the reference model of this verification scheme must simultaneously implement a large number of group logic and sequential logic, requiring a large amount of delay (e.g., #0) to construct the reference model. If the DUT design has a large number of functional modules, this method of adding a large amount of delay is obviously inappropriate.

[0003] The information disclosed in the background section is only intended to enhance the understanding of the background art of the art described herein. Therefore, the background art may contain information that does not constitute prior art known to those skilled in the art in this country. Summary of the Invention

[0004] The main objective of this application is to provide a verification system to address the problems of poor stability and low debugging efficiency caused by relying solely on reference models for prediction in the prior art.

[0005] According to one aspect of the present invention, a verification system is provided, the verification system comprising a reference model module, a reference model interface module, and a scoring board module, wherein the reference model module is used to predict timing logic based on test data to obtain first predicted data, the test data being initial data to be calculated; the reference model interface module is connected to a first end of the reference model module, the reference model interface module is used to predict combinational logic based on the first predicted data to obtain second predicted data, the reference model interface module is further used to send the second predicted data to the reference model module, so that the reference model module adjusts the first predicted data based on the second predicted data to obtain expected data; the scoring board module is connected to a second end of the reference model module, the scoring board module is used to connect to the output end of a design under test module, the scoring board module is used to receive actual data and the expected data, and to verify the design under test module based on the expected data and the actual data, the design under test module is used to receive the test data, and the design under test module is further used to calculate the actual data based on the test data.

[0006] Optionally, the reference model interface module implements the prediction of the combinational logic through the assignment statement assign() or always@(*).

[0007] Optionally, the verification system further includes a first proxy module, a first end of which is connected to the input end of the design under test module, a second end of which is connected to the second end of the reference model module, the first proxy module being used to send the test data to the design under test module, and the first proxy module also being used to send the test data to the reference model module.

[0008] Optionally, the verification system further includes a second proxy module. The input end of the second proxy module is connected to the output end of the design under test module, and the output end of the second proxy module is connected to the scoreboard module. The second proxy module is used to receive the actual data output by the design under test module, and the second proxy module is also used to send the actual data to the scoreboard module.

[0009] Optionally, the second agent module includes a first monitoring module, wherein the input terminal of the first monitoring module is the input terminal of the second agent module, and the output terminal of the first monitoring module is the output terminal of the second agent module.

[0010] Optionally, the first proxy module sends out the test data, so that the design under test module receives the test data through the bus, and the bus is also used to transmit the actual data sent by the design under test module to the second proxy module.

[0011] Optionally, the first agent module includes an stimulus generation module and a driving module, wherein the stimulus generation module is used to send out the test data; the input terminal of the driving module is connected to the stimulus generation module, the output terminal of the driving module is connected to the input terminal of the design under test module, the driving module is used to receive the test data sent by the stimulus generation module, and the driving module is also used to send the test data to the design under test module.

[0012] Optionally, the first proxy module further includes a second monitoring module, the input terminal of which is connected to the input terminal of the design under test module, the output terminal of which is the output terminal of the first proxy module, and the second monitoring module is used to send the test data to the reference model module.

[0013] Optionally, the reference model module and the reference model interface module implement the transmission of the first prediction data and the second prediction data through a predetermined mechanism, the predetermined mechanism including uvm_config_db.

[0014] Optionally, if the expected data matches the actual data, the scoreboard module is further configured to issue verification success data; if the expected data does not match the actual data, the scoreboard module is further configured to issue verification failure data.

[0015] In this embodiment of the invention, the verification system includes a reference model module, a reference model interface module, and a scoring board module. The reference model module is used to predict timing logic based on test data to obtain first predicted data, where the test data is initial data to be calculated. The reference model interface module is connected to a first end of the reference model module and is used to predict combinational logic on the first predicted data to obtain second predicted data. The reference model interface module is also used to send the second predicted data to the reference model module, so that the reference model module adjusts the first predicted data according to the second predicted data to obtain adjusted expected data. The scoring board module is connected to a second end of the reference model module and is used to connect to the output end of the design under test module. The scoring board module receives actual data and the expected data, and verifies the design under test module based on the expected data and the actual data. The design under test module receives the test data and is also used to calculate the actual data based on the test data. Compared to existing technologies that rely solely on reference models for prediction, resulting in poor stability and low debugging efficiency, the verification system of this application addresses these issues. It uses a reference model module to predict the timing logic of the data to be tested, and a reference model interface module to predict the combinational logic of the first predicted data. The system then sends the second predicted data obtained by the reference model interface module back to the reference model module. This allows the reference model module to adjust the first predicted data based on the second predicted data from the reference model interface module. Ultimately, the expected data is predicted jointly by both the reference model module and the reference model interface module. By implementing data sharing between the reference model interface module and the reference model module, they can make predictions based on each other's results. This ensures faster and more accurate acquisition of the expected data, avoids signal contention issues when both combinational and timing logic are required, and solves the problems of poor stability and low debugging efficiency caused by using only a reference model for prediction in existing technologies. This ensures both high stability and high debugging efficiency for the verification system. Attached Figure Description

[0016] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0017] Figure 1A schematic diagram of a verification system according to an embodiment of this application is shown.

[0018] The above figures include the following reference numerals:

[0019] 10. Verification system; 20. Design under test module; 101. Reference model module; 102. Reference model interface module; 103. Scoreboard module; 104. First agent module; 105. Second agent module; 106. First monitoring module; 107. Excitation generation module; 108. Drive module; 109. Second monitoring module; 201. Bus. Detailed Implementation

[0020] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0021] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present application.

[0022] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0023] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be an intermediate element present. Furthermore, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element via a third element.

[0024] As mentioned in the background section, the existing technology that relies solely on a reference model for prediction suffers from poor stability and low debugging efficiency. To address these issues, a typical implementation of this application provides a verification system.

[0025] According to embodiments of this application, such as Figure 1 As shown, a verification system 10 is provided. The verification system 10 includes a reference model module 101, a reference model interface module 102, and a scoring board module 103. The reference model module 101 is used to predict timing logic based on test data to obtain first predicted data. The test data is the initial data to be calculated. The reference model interface module 102 is connected to a first end of the reference model module 101. The reference model interface module 102 is used to predict combinational logic based on the first predicted data to obtain second predicted data. The reference model interface module 102 is also used to send the second predicted data to the reference model module 101. The model module 101 is configured to adjust the first prediction data based on the second prediction data to obtain the expected data. The scoring board module 103 is connected to the second end of the reference model module 101 and is connected to the output end of the design under test module 20. The scoring board module 103 is used to receive the actual data and the expected data, and to verify the design under test module 20 based on the expected data and the actual data. The design under test module 20 is used to receive the test data and to calculate the actual data based on the test data.

[0026] The aforementioned verification system includes a reference model module, a reference model interface module, and a scoring board module. The reference model module performs timing logic prediction based on the test data to obtain first predicted data, where the test data is the initial data to be calculated. The reference model interface module is connected to the first end of the reference model module and performs combinational logic prediction on the first predicted data to obtain second predicted data. The reference model interface module also sends the second predicted data to the reference model module, allowing the reference model module to adjust the first predicted data based on the second predicted data to obtain adjusted expected data. The scoring board module is connected to the second end of the reference model module and is connected to the output end of the design under test (DUT). The scoring board module receives actual data and the expected data, and verifies the DUT based on the expected data and the actual data. The DUT receives the test data and also calculates the actual data based on the test data. Compared to the problems of poor stability and low debugging efficiency caused by relying solely on a reference model for prediction in existing technologies, the verification system of this application uses the reference model module to predict the timing logic of the test data, the reference model interface module to predict the combinational logic of the first predicted data, and sends the second predicted data obtained by the reference model interface module to the reference model module. This allows the reference model module to adjust the first predicted data based on the second predicted data sent by the reference model interface module. The final predicted expected data is obtained jointly by the reference model module and the reference model interface module. By implementing data sharing between the reference model interface module and the reference model module, they can make predictions based on each other's prediction results, ensuring that the expected data can be obtained quickly and accurately. This avoids the signal competition problem when both combinational and timing logic need to be performed simultaneously, solving the problems of poor stability and low debugging efficiency caused by relying solely on a reference model for prediction in existing technologies. This ensures high stability and high debugging efficiency for the verification system.

[0027] Currently, the main approach involves passing the detected transactions to a reference model module, where the logic functionality of the Design Under Test (DUT) is predicted. This reference model module needs to predict the output of the DUT. However, if a scenario requires predicting the output for every clock cycle, it necessitates simultaneously predicting a large amount of combinational and sequential logic. This necessitates significant delays (e.g., #0) for constructing the reference model. If the DUT contains numerous functional modules, the combinational logic becomes embedded within the sequential logic, violating the realities of simulation. The verification system proposed in this application addresses this by adding a reference model interface module (Reference_Interface), where the prediction of combinational logic is performed, and the prediction of sequential logic is performed within the reference model module. The aforementioned timing logic prediction, and the aforementioned reference model interface module and the aforementioned reference model module make predictions based on each other's prediction results, to realize data interaction between the aforementioned reference model interface module and the aforementioned reference model module, to achieve accurate prediction of the aforementioned expected data, so that the subsequent verification of the aforementioned design under test module based on the aforementioned expected data and the aforementioned actual data is faster and more accurate. Since the aforementioned verification system of this application avoids the signal competition problem when combining combinational logic and timing logic are used simultaneously in the prior art, it ensures that the aforementioned verification system has high stability. Since the prediction of the aforementioned timing logic and the aforementioned combinational logic can be executed separately, the accuracy of the aforementioned design under test module can be verified more quickly, ensuring that the verification environment debugging efficiency of the aforementioned verification system is high.

[0028] Specifically, for the aforementioned design-under-test (DUT) modules that require real-time and accurate prediction results, the reference model module and the reference model interface module interact to jointly achieve automatic prediction of the logical functions of the DUT modules by the entire verification environment. The prediction of combinational logic is implemented in the reference model interface module, and the prediction of sequential logic is implemented in the reference model module. This can effectively avoid reference model timing problems caused by simulator scheduling. In addition, the introduction of the reference model interface module makes the debugging of the entire reference model module more visual, that is, it allows direct inspection of the waveforms of signals in the reference model interface module. This ensures high debugging efficiency of the verification environment of the verification system, as well as high reusability and stability of the verification environment.

[0029] According to a specific embodiment of this application, the reference model interface module implements the prediction of the combinational logic using the assignment statement `assign()` or `always@(*)`. Implementing the prediction of the combinational logic in the reference model interface module using the assignment statement `assign()` or `always@(*)` ensures high accuracy of the prediction results of the reference model interface module, and thus ensures high accuracy of the expected data.

[0030] Specifically, through the interaction between the aforementioned reference model module and the aforementioned reference model interface module, the prediction of the combinational logic part is placed in the aforementioned reference model interface module and implemented through the aforementioned assignment statement assign() or always@(*), while the prediction of the sequential logic part is placed in the aforementioned reference model module. This achieves the separation and interaction of sequential logic prediction and combinational logic prediction, which can effectively avoid signal race problems and improve the stability and reusability of the verification environment.

[0031] To further ensure the high stability and short cycle of the above verification system, according to another specific embodiment of this application, such as... Figure 1 As shown, the verification system 10 further includes a first proxy module 104. The first end of the first proxy module 104 is connected to the input end of the design-under-test (DUT) module 20, and the second end of the first proxy module 104 is connected to the second end of the reference model module 101. The first proxy module 104 is used to send the test data to the DUT module 20 and also to send the test data to the reference model module 101. Because the first end of the first proxy module is connected to the input end of the DUT module, it can send the test data to the DUT module, ensuring that the DUT module can calculate the actual data based on the test data. Because the second end of the first proxy module is connected to the second end of the reference model module, it can receive the test data, enabling subsequent prediction of the combinational logic and timing logic based on the test data. This ensures that both the actual data and the expected data can be obtained, further guaranteeing the high stability and debugging efficiency of the verification system.

[0032] According to another specific embodiment of this application, such as Figure 1As shown, the verification system 10 further includes a second proxy module 105. The input of the second proxy module 105 is connected to the output of the design under test (DUT) module 20, and the output of the second proxy module 105 is connected to the scoring board module 103. The second proxy module 105 is used to receive the actual data output by the DUT module 20 and to send the actual data to the scoring board module 103. Because the input of the second proxy module is connected to the output of the DUT module, it can receive the actual data sent by the DUT module. Because the output of the second proxy module is connected to the scoring board module, it can output the actual data to the scoring board module, ensuring that the scoring board module can receive the actual data. This allows the scoring board module to compare the actual data with the expected data, thereby verifying the DUT module.

[0033] According to a specific embodiment of this application, such as Figure 1 As shown, the second proxy module 105 includes a first monitoring module 106. The input terminal of the first monitoring module 106 is the input terminal of the second proxy module 105, and the output terminal of the first monitoring module 106 is the output terminal of the second proxy module 105. The second proxy module includes the first monitoring module, ensuring that the actual data received by the scoreboard module meets the requirements of the scoreboard module.

[0034] According to another specific embodiment of this application, such as Figure 1 As shown, the first proxy module 104 sends out the test data, enabling the design-under-test (DUT) module 20 to receive the test data via the bus 201. The bus 201 is also used to transmit the actual data sent by the DUT module 20 to the second proxy module 105. The DUT module receives the test data via the bus, and also sends out the actual data via the bus, ensuring a high level of ease of operation for the verification system.

[0035] In one specific embodiment, the detector detects transactions from the bus and hands them over to the aforementioned reference model module for prediction processing.

[0036] According to another specific embodiment of this application, such as Figure 1As shown, the first proxy module 104 includes an stimulus generation module 107 and a driving module 108. The stimulus generation module 107 is used to send the test data. The input terminal of the driving module 108 is connected to the stimulus generation module 107, and the output terminal of the driving module 108 is connected to the input terminal of the design under test (DUT) module 20. The driving module 108 is used to receive the test data sent by the stimulus generation module 107 and also to send the test data to the DUT module 20. By sending the test data through the stimulus generation module in the first proxy module, receiving the test data sent by the stimulus generation module through the driving module in the first proxy module, and sending the test data to the DUT module through the driving module, the DUT module can receive the test data relatively easily, realize the actual calculation of the test data, and obtain the actual data. This ensures that subsequent predictions of the DUT module can be made based on the actual data and the expected data.

[0037] Specifically, the aforementioned driver module sends the test data to the aforementioned design-under-test module via the aforementioned bus.

[0038] To further ensure the high accuracy of the above verification system, according to a specific embodiment of this application, such as... Figure 1 As shown, the first proxy module 104 further includes a second monitoring module 109. The input terminal of the second monitoring module 109 is connected to the input terminal of the design under test module 20, and the output terminal of the second monitoring module 109 is the output terminal of the first proxy module 104. The second monitoring module 109 is used to send the test data to the reference model module 101. Since the input terminal of the second monitoring module in the first proxy module is connected to the input terminal of the design under test module, and the output terminal of the second monitoring module is connected to the reference model module, the test data can reach the reference model module through the second monitoring module. This ensures that the reference model module receives the test data, and that the expected data can be obtained relatively easily. This enables subsequent data interaction between the reference model module and the reference model interface module, ensuring high accuracy of the obtained actual data and further guaranteeing high accuracy of the verification system.

[0039] In one specific embodiment, the sequencer in the first agent module (Active Agent) sends the test data to the driver module (Driver), the driver module drives the test data to the design under test (DUT), the second monitoring module in the first agent module sends the transactions on the bus to the reference model module, and the second agent module (Passive Agent) monitors the output transactions of the design under test module through the built-in module, namely the first monitoring module (Monitor), that is, monitors the actual data, and sends the monitored actual data to the scoreboard module (Scoreboard).

[0040] According to another specific embodiment of this application, the reference model module and the reference model interface module transmit the first prediction data and the second prediction data through a predetermined mechanism, which includes uvm_config_db. This predetermined mechanism ensures that the reference model module and the reference model interface module can interact with each other, guaranteeing that the actual data can be obtained quickly and accurately, further ensuring the high accuracy of the verification system.

[0041] Specifically, by declaring the reference model interface module in the reference model module and obtaining the handle of the reference model interface module through the predetermined mechanism uvm_config_db, the signals output by the combinational logic in the reference model interface module can be used in the reference model module. At the same time, the output obtained by the timing logic inside the reference model can also be assigned to the reference model interface module to realize data interaction between the reference model module and the reference model interface module. The handle is an identifier used to represent the object.

[0042] According to another specific embodiment of this application, when the expected data and the actual data are consistent, the scoring board module is further configured to issue verification success data; when the expected data and the actual data are inconsistent, the scoring board module is further configured to issue verification failure data. By issuing verification success information when the expected data and the actual data are consistent, and issuing verification failure information when the expected data and the actual data are inconsistent, the scoring board module can accurately verify the design module under test, further ensuring high stability and high debugging efficiency of the verification system.

[0043] In one specific embodiment, by sending the final output obtained by the reference model module to the scoring board module, that is, by sending the expected data to the scoring board module, the scoring board module can compare whether the expected data of each clock cycle is consistent with the actual data output by the design under test module, thereby achieving the purpose of cycle-level (each rising edge of the clock) verification.

[0044] Specifically, the following code uses a counter as an example for illustration.

[0045] First, define the reference model interface module (Reference Interface) mentioned above to construct the logic of the combinational logic part. A code example is shown below:

[0046]

[0047] Then, the top-level verification environment is constructed, and the aforementioned reference model interface module is passed to the aforementioned reference model module (Reference Model) through UVN_Config_db.

[0048] Finally, the aforementioned reference model module is constructed to obtain data from the reference model interface at the top level of the verification environment. Furthermore, the reference model module and the reference model interface module jointly predict the output of the design under test module. A code example is shown below (using upward counting as an example):

[0049]

[0050] In the above embodiments of the present invention, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0051] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A verification system, characterized in that, The verification system includes: A reference model module is used to predict the timing logic based on the test data to obtain the first prediction data, wherein the test data is the initial data to be calculated. A reference model interface module is connected to the first end of the reference model module. The reference model interface module is used to perform combinational logic prediction on the first prediction data to obtain second prediction data. The reference model interface module is also used to send the second prediction data to the reference model module so that the reference model module adjusts the first prediction data according to the second prediction data to obtain the desired data. A scoring board module is connected to the second end of the reference model module. The scoring board module is used to connect to the output end of the design under test module. The scoring board module is used to receive actual data and expected data, and to verify the design under test module based on the expected data and the actual data. The design under test module is used to receive the test data and is also used to calculate the actual data from the test data. The reference model interface module implements the prediction of the combinational logic through the assignment statement assign() or always@(*); The reference model module and the reference model interface module transmit the first prediction data and the second prediction data through a predetermined mechanism, which includes uvm_config_db.

2. The verification system according to claim 1, characterized in that, The verification system also includes: A first proxy module has a first end connected to the input end of the design under test module, a second end connected to the second end of the reference model module, and is used to send the test data to the design under test module and the reference model module.

3. The verification system according to claim 2, characterized in that, The verification system also includes: The second proxy module has an input terminal connected to the output terminal of the design under test module and an output terminal connected to the scoreboard module. The second proxy module is also used to receive the actual data output by the design under test module and to send the actual data to the scoreboard module.

4. The verification system according to claim 3, characterized in that, The second agent module includes: The first monitoring module has its input terminal serving as the input terminal of the second agent module, and its output terminal serving as the output terminal of the second agent module.

5. The verification system according to claim 3, characterized in that, The first proxy module sends out the test data, enabling the design under test module to receive the test data via a bus. The bus is also used to transmit the actual data sent by the design under test module to the second proxy module.

6. The verification system according to claim 3, characterized in that, The first agent module includes: The stimulus generation module is used to generate the test data; The driving module has its input terminal connected to the excitation generation module and its output terminal connected to the input terminal of the design under test module. The driving module is used to receive the test data sent by the excitation generation module and also to send the test data to the design under test module.

7. The verification system according to claim 6, characterized in that, The first agent module also includes: The second monitoring module has an input terminal that is connected to the input terminal of the design module under test, and an output terminal that is the output terminal of the first proxy module. The second monitoring module is used to send the test data to the reference model module.

8. The verification system according to claim 1, characterized in that, If the expected data matches the actual data, the scoreboard module is also used to issue verification success data; if the expected data does not match the actual data, the scoreboard module is also used to issue verification failure data.

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