A data communication system, method, apparatus and readable storage medium

Abstract

This application discloses a data communication system, method, apparatus, and readable storage medium, relating to the field of electronic information. The data communication system provided in this application includes: a BMC, a PCH, an SMBus Slave, and a CPLD. The CPLD reads the communication signals between the BMC and the PCH, thereby switching control of the SMBus Slave to ensure that the entire board will not shut down due to a BMC malfunction. Compared with previous solutions, this application's data communication system utilizes a CPLD to detect and analyze the communication data between the PCH and the BMC, and determines whether the BMC is malfunctioning based on the communication signals between the BMC and the PCH to switch control of the SMBus Slave, thus ensuring the stability of machine functions and enhancing machine availability.

Description

Technical Field

[0001] This application relates to the field of electronic information, and in particular to a data communication system, method, apparatus and readable storage medium. Background Technology

[0002] In recent years, with the advancement of information technology, computers have been used more and more widely in daily life and industrial production. Under the server operating system, in order to maintain and manage the machine, it is necessary to obtain data such as the temperature of each board in the machine, the power supply voltage value, alarms, and asset information, and to perform actions such as controlling the fan and updating the board.

[0003] In existing solutions, temperature sensors, power chips, asset information storage chips, fan boards, etc. on the board are all connected to the Baseboard Manager Controller (BMC) via the System Management Bus (SMBus). Commands to obtain relevant information under the server operating system are sent from the PCH to the BMC through the channel in the Enhanced Serial Peripheral Interface (ESPI) bus. The BMC then converts the commands into corresponding SMBus operations. After completing the corresponding read / write operations, the commands are returned to the Paging Indicator Channel (PCH) via the ESPI bus. If the BMC malfunctions and hangs, it cannot respond to maintenance and management actions of the machine under the operating system, affecting the usability and stability of the machine.

[0004] Given the above-mentioned technologies, finding a data communication system with higher stability is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] The purpose of this application is to provide a data communication system, method, apparatus, and readable storage medium to address the problem that in the current server operating system, commands for obtaining relevant information are sent from the PCH to the BMC via the OOB channel in the ESPI bus, and then the BMC converts them into corresponding SMBus operations. After completing the corresponding read / write operations, the commands are returned to the PCH via the ESPI bus. However, if the BMC hangs abnormally, it cannot respond to maintenance and management actions of the machine under the operating system, affecting the usability and stability of the machine.

[0006] To address the aforementioned technical problems, this application provides a data communication system, comprising: BMC, PCH, SMBusSlave, and CPLD.

[0007] The BMC is connected to the PCH and is used for data communication with the PCH;

[0008] The CPLD includes an SMBus Master and an SMBus Switch. The SMBus Switch is used to control the connection between the BMC and the SMBus Slave when the BMC is working normally, and to control the connection between the SMBus Master and the SMBus Slave when the BMC is malfunctioning.

[0009] The SMBus Master is connected to the PCH and is used to communicate with the PCH for data when the BMC fails.

[0010] Preferably, the BMC communicates with the PCH, the CPLD communicates with the PCH via an eSPI bus, and the CPLD communicates with the SMBus Slave and the BMC via an SMBus bus.

[0011] Preferably, the CPLD further includes a bypass, which is used to connect the BMC and the SMBusSwitch, and to determine whether the BMC is abnormal based on the WDT signal of the BMC.

[0012] To address the aforementioned problems, this application provides a data communication method applied to a data communication system comprising: BMC, PCH, SMBusSlave, and CPLD, wherein the BMC is connected to the PCH, the CPLD includes an SMBus Master and an SMBus Switch, and the SMBus Master is connected to the PCH. The method includes:

[0013] The SMBus Switch is controlled to acquire communication information between the PCH and the BMC;

[0014] Determine whether the BMC has malfunctioned based on the communication information;

[0015] If so, control the SMBus switch to switch the BMC to the SMBus Master;

[0016] The SMBus Master is controlled to communicate with the PCH, and read / write operations are performed on the SMBus Slave according to the information sent by the PCH.

[0017] Preferably, the CPLD further includes a bypass, and the step of determining whether the BMC has malfunctioned based on the communication information includes:

[0018] The bypass detection is used to check whether the WDT signal of the BMC is flipped. If the WDT signal flips, it indicates that the BMC is not abnormal. If the WDT signal does not flip, it indicates that the BMC is abnormal.

[0019] Preferably, after controlling the SMBus switch to switch the BMC to the SMBus Master, the method further includes:

[0020] Determine whether the data in the CPLD's buffer is valid;

[0021] If so, the SMBus Master will communicate with the PCH based on the data in the buffer.

[0022] If not, then take over and execute the information sent by the PCH, and perform read and write operations on the SMBus Slave.

[0023] Preferably, controlling the SMBus Master to communicate with the PCH and performing read / write operations on the SMBus Slave according to the information sent by the PCH includes:

[0024] Receive the preset address of the SMBus Slave sent by the PCH, and the length of the communication data;

[0025] The communication command of the PCH is confirmed based on the length of the communication data;

[0026] If it is a read command, then according to the preset address, a read operation is performed on the SMBus slave, and the result obtained is sent to the PCH;

[0027] If it is a write command, the write data in the communication data is written to the corresponding SMBus Slave according to the preset address of the SMBus Slave.

[0028] To address the aforementioned problems, this application provides a data communication device applied to a data communication system comprising: a BMC, a PCH, an SMBusSlave, and a CPLD, wherein the BMC is connected to the PCH, the CPLD includes an SMBus Master and an SMBus Switch, and the SMBus Master is connected to the PCH. The device includes:

[0029] The acquisition module is used to control the SMBus Switch to acquire communication information between the PCH and the BMC;

[0030] The judgment module is used to determine whether the BMC is malfunctioning based on the communication information; if so, it enters the switching module.

[0031] The switching module is used to control the SMBus switch to switch the BMC to the SMBus Master;

[0032] The communication module is used to control the SMBus Master to communicate with the PCH and to perform read and write operations on the SMBus Slave according to the information sent by the PCH.

[0033] Preferably, the device further includes:

[0034] A buffer module is used to determine whether the data in the buffer of the CPLD is valid;

[0035] If so, the SMBus Master will communicate with the PCH based on the data in the buffer.

[0036] If not, then take over and execute the information sent by the PCH, and perform read and write operations on the SMBus Slave.

[0037] To address the aforementioned problems, this application also provides a data communication device, including a memory for storing computer programs;

[0038] A processor for executing the computer program to implement the steps of the data communication method described above.

[0039] To address the aforementioned problems, this application also provides a computer-readable storage medium, characterized in that a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, it implements the steps of the data communication method described above.

[0040] The data communication system provided in this application includes: BMC, PCH, SMBus Slave, and CPLD. The CPLD includes an SMBus Master and an SMBus Switch. The SMBus Switch controls the communication between the BMC and SMBus Slave when the BMC is working normally, and controls the communication between the SMBus Master and SMBus Slave when the BMC malfunctions, thereby ensuring that the entire board will not shut down due to a BMC malfunction. Compared with previous solutions, this application's data communication system utilizes the CPLD to detect and parse the communication data between the PCH and BMC, and determines whether the BMC is malfunctioning based on the communication signals between the BMC and PCH to switch control of the SMBus Slave. This ensures that the system's maintenance and management operations are uninterrupted and unaffected by BMC malfunctions, guaranteeing the stability of machine functions and enhancing machine availability.

[0041] The data communication method, apparatus, and computer-readable storage medium provided in this application correspond to the data communication method described above and have the same beneficial effects. Attached Figure Description

[0042] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0043] Figure 1 A structural diagram of a data communication system provided in an embodiment of this application;

[0044] Figure 2 A flowchart illustrating a data communication method provided in an embodiment of this application;

[0045] Figure 3 A schematic diagram of a data communication device provided in an embodiment of this application;

[0046] Figure 4 This is a schematic diagram of a data communication device provided for another embodiment of this application. Detailed Implementation

[0047] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0048] The core of this application is to provide a data communication system, method, apparatus, and readable storage medium to solve the problem that commands for obtaining relevant information under the current server operating system are sent from the PCH to the BMC via the OOB channel in the ESPI bus, and then the BMC converts them into corresponding SMBus operations. After completing the corresponding read and write operations, the commands are returned to the PCH via the ESPI bus. If the BMC hangs abnormally, it cannot respond to the maintenance and management actions of the machine under the operating system, which affects the usability and stability of the machine.

[0049] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0050] Figure 1 A structural diagram of a data communication system provided in this application embodiment includes: BMC1, PCH2, SMBusSlave3, CPLD4.

[0051] BMC1 is connected to PCH2 for data communication with PCH2;

[0052] CPLD4 includes an SMBus Master and an SMBus Switch. The SMBus Switch is used to control the connection between BMC1 and SMBus Slave3 when BMC1 is working normally, and to control the connection between SMBus Master and SMBus Slave3 when BMC1 is malfunctioning.

[0053] The SMBus Master connects to PCH2 for data communication with PCH2 in the event of a BMC1 failure.

[0054] It should be noted that SMBus provides a control bus for tasks such as system and power management. In systems using SMBus, devices send and receive messages through the SMBus instead of using separate control lines, thus saving pin count. Using SMBus, devices can also provide their production information, such as model number and part number, save their status for pending events, report different types of errors, receive control parameters, and return their status. SMBus devices exist in the first three layers of the existing 7-layer OSI network model: the physical layer, data link layer, and network layer. SMBus is also used to connect various devices, including power-related devices, system sensors, EEPROM communication devices, etc. This embodiment does not specifically limit the type of SMBus; it varies depending on the specific situation.

[0055] SPI stands for Serial Peripheral Interface, a high-speed, full-duplex, synchronous communication bus that uses only four pins on a chip, saving pins and PCB layout space. Due to its ease of use, more and more chips are integrating this communication protocol. In contrast, eSPI is an extended serial peripheral interface, which has a wider range of applications than SPI.

[0056] PCH2 is an abbreviation for Paging Indicator Channel. It refers to the integration of the memory controller and PCIe controller from the Northbridge into the CPU, essentially making the entire Northbridge chip integrated into the CPU, leaving only the Southbridge on the motherboard. Therefore, PCH2 can be understood as the Southbridge. Some Intel SoCs even integrate PCH2 into the CPU. The paging channel is a downlink transmission channel used to transmit data related to the paging process, used during network and terminal initialization. A simple example is initiating a voice call to a terminal; the network will use the paging channel of the terminal's cell to send a paging message. Different PCH2 channels can be used for different paging groups. Combined channels reduce the number of paging groups, while non-combined channels increase them. The more paging groups, the longer the user's waiting time.

[0057] The Baseboard Management Controller (BMC1) provides the intelligent features within the IPMI architecture. It is a dedicated microcontroller embedded on the motherboard of a computer (typically a server). The BMC1 manages the interface between the system management software and the platform hardware. The BMC1 is an independent processor embedded on the server motherboard that communicates with other hardware and software components within the host computer via various interfaces such as IPMB, LPC (low-pin-count-interface), and SMBus. It also transmits data to the local host / remote server via network, serial / Modem, and PCI interfaces to provide query and control functions. This embodiment does not specifically limit the particular structural type of the BMC1.

[0058] It should be noted that the control mode is switched through SMBus Switch in this solution, changing the read and write control of SMBus Slave3 from BMC1 to CPLD4. The core is to determine whether BMC1 has failed. In this embodiment, the method for determining the failure of BMC1 is not specifically limited.

[0059] The data communication system provided in this application includes: BMC1, PCH2, SMBus Slave3, and CPLD4. CPLD4 includes an SMBus Master and an SMBus Switch. The SMBus Switch controls the connection between BMC1 and SMBus Slave3 when BMC1 is working normally, and controls the connection between SMBus Master and SMBus Slave3 when BMC1 malfunctions, thereby ensuring that the entire board will not shut down due to a BMC1 malfunction. Compared with previous solutions, this application's data communication system utilizes CPLD4 to detect and parse the communication data between PCH2 and BMC1, and determines whether BMC1 is malfunctioning based on the communication signals between BMC1 and PCH2 to switch control of the SMBus slave. This ensures that the system's maintenance and management operations are uninterrupted and unaffected by BMC1 malfunctions, guaranteeing the stability of machine functions and enhancing machine availability.

[0060] The above embodiments do not limit the specific communication method. Here, a preferred solution is provided: BMC1 communicates with PCH2 and CPLD4 communicates with PCH2 via the eSPI bus. CPLD4 communicates with SMBus Slave3 and BMC1 via the SMBus bus.

[0061] It should be noted that the above communication method is adopted to improve the efficiency of signal transmission.

[0062] The above embodiments do not limit how to determine whether BMC1 is abnormal. Here, a preferred solution is provided: CPLD4 also includes a bypass, which is used to connect BMC1 and SMBus Switch, and to determine whether BMC1 is abnormal based on the WDT signal of BMC1.

[0063] It should be noted that bypasses include bypasses in UPS systems, burglar alarm systems, chemical processes, electrical and electronic systems, and security alarm systems. A bypass, distinct from the main circuit, refers to the ability to switch to another circuit without affecting the normal operation of the load when necessary for functionality. In practical systems, the bypass concept includes bypass buses, bypass switches, etc. A watchdog timer (WDT) is a timer circuit, typically with one input (feed the watchdog) and one output to the RST pin of the MCU. When the MCU is working normally, it outputs a signal to the feed the watchdog at regular intervals to reset the WDT. If the watchdog is not fed within a specified time (usually when the program crashes), the WDT timeout will send a reset signal to the MCU, resetting it and preventing MCU crashes. The watchdog's function is to prevent the program from entering an infinite loop or crashing; therefore, the WDT makes it easy to obtain the abnormal status of the BMC1 (Block Controller Unit).

[0064] Figure 2 A flowchart of a data communication method provided in an embodiment of this application is shown below. Figure 2 As shown, the method includes:

[0065] This application provides a data communication method applied to a data communication system including: BMC, PCH, SMBus Slave, and CPLD, wherein the BMC is connected to the PCH, the CPLD includes an SMBus Master and an SMBus Switch, and the SMBus Master is connected to the PCH. The method includes:

[0066] S10: Control the SMBus Switch to obtain communication information between the PCH and BMC;

[0067] S11: Determine whether the BMC is malfunctioning based on the communication information. If so, proceed to S12.

[0068] S12: Control the SMBus switch to switch the BMC to the SMBus Master;

[0069] S13: Controls the SMBus Master to communicate with the PCH and performs read and write operations on the SMBus Slave according to the information sent by the PCH.

[0070] It should be noted that the control mode is switched through SMBus Switch in this solution, changing the read and write control of SMBus Slave from BMC to CPLD. The core is to determine whether BMC has failed. In this embodiment, the method for determining BMC failure is not specifically limited.

[0071] Since the method provided in this application corresponds to the system described above, specific embodiments can be found in the system section above, and will not be repeated here.

[0072] The data communication method provided in this application is applied to a data communication system including a BMC, PCH, SMBus Slave, and CPLD. The CPLD includes an SMBus Master and an SMBus Switch. The SMBus Switch controls the connection between the BMC and the SMBus Slave when the BMC is working normally, and controls the connection between the SMBus Master and the SMBus Slave when the BMC malfunctions, thereby ensuring that the entire board will not shut down due to a BMC malfunction. Compared with previous solutions, because the data communication system of this application uses the CPLD to detect and parse the communication data between the PCH and the BMC, and determines whether the BMC is malfunctioning based on the communication signals between the BMC and the PCH to switch control of the SMBus slave, it ensures that the system's maintenance and management actions are uninterrupted and unaffected by BMC malfunctions, thus ensuring the stability of machine functions and enhancing machine availability.

[0073] The above embodiments do not limit how to determine whether the BMC has malfunctioned. A preferred solution is provided here: the CPLD also includes a bypass, and determining whether the BMC has malfunctioned based on communication information includes:

[0074] By bypassing the detection, it is determined whether the WDT signal of the BMC flips. If the WDT signal flips, it indicates that the BMC is not abnormal; if the WDT signal does not flip, it indicates that the BMC is abnormal.

[0075] It should be noted that a normal WDT signal toggle indicates that the BMC is performing timing operations normally. Therefore, when the WDT signal toggles normally, it means that the BMC is working properly, making detection relatively simple and easy to obtain.

[0076] After controlling the SMBus switch to switch the BMC to the SMBus Master, the following steps are also included:

[0077] Determine if the data in the CPLD's buffer is valid;

[0078] If so, then the SMBus Master communicates with the PCH based on the data in the buffer;

[0079] If not, it takes over and executes the information sent by the PCH, and performs read and write operations on the SMBus Slave.

[0080] It should be noted that a buffer is memory that temporarily stores output or input data. Data in the buffer comes from storage devices (such as hard drives), is placed in the buffer, and must be sent to the CPU or other computing devices later. The Chinese translation of "buffer" originates from the fact that when high-speed and low-speed components of a computer communicate, the output of the high-speed component must be temporarily stored somewhere to ensure compatibility between the two. Later, this meaning was expanded to mean "temporary storage area."

[0081] In summary, the preferred solution is as follows: when the CPLD detects a normal toggle of the BMC's WDT signal, it considers the BMC to be working normally and controls the internal SMBus switch to the Bypass section. That is, the CPLD directly transmits the BMC's SMBus operations to the subsequent SMBus slave. In this case, the CPLD is transparent to the system as a whole and does not affect existing functions.

[0082] When the CPLD detects that the WDT signal of the BMC is not toggling, it considers the BMC to be stuck and controls the internal SMBus switch to switch the internal SMBus Master of the CPLD.

[0083] If the BMC malfunctions but the data in the Mass Buffer is valid, the SMBus Master will control the read and write operations of the subsequent SMBus slaves based on the data in the Mass Buffer, and return the corresponding results to the PCH to ensure that the eSPI interaction is not interrupted.

[0084] If the BMC malfunctions and the Mass Buffer is empty, the CPLD will take over and execute any subsequent OOB channel operations on the eSPI bus.

[0085] The CPLD modifies the OOB_FREE and OOB_AVAIL flags in the internal eSPI slave status register according to the current actual state:

[0086] If there is an SMBus read / write operation in progress, clear OOB_FREE; otherwise, set OOB_FREE.

[0087] If the current SMBbus data reading is complete, then set OOB_AVAIL.

[0088] In a server operating system, in order to maintain and manage the machine and access the SMBus slave device on the machine, the PCH should first use the GET_STATUS command to check whether the OOB_FREE flag in the current status register is valid.

[0089] If the OOB_FREE flag is valid, and a read operation is performed on the SMBus slave, the address of the SMBus slave and the data length are sent via the PUT_OOB command in the OOB channel. After the CPLD parses the PUT_OOB command, if it detects that there is no other game data after the data length, it determines that a read operation has been performed on the SMBus slave; and controls the SMBus Master to read the SMBus slave data, while simultaneously clearing the OOB_FREE flag.

[0090] After the read is complete, OOB_AVAIL is set, and an alert signal is triggered to PCH. When PCH receives the alert signal, it will use the GET_STATUS command. After detecting that OOB_AVAIL is set, it will use the GET_OOB command to retrieve the data. After CPLD parses the GET_OOB command, it will return the read SMBus slave data to PCH.

[0091] If the OOB_FREE flag is valid, a write operation to the SMBus slave is performed via the PUT_OOB command in the OOB channel, which sends the SMBus slave's address, the length of the data to be written, and the specific data to be written. After the CPLD parses the PUT_OOB command, it controls the SMBus Master to perform the write operation on the SMBus slave and clears the OOB_FREE flag. The OOB_FREE flag is then set after the write operation is complete.

[0092] In the above embodiments, the data communication method has been described in detail. This application also provides embodiments corresponding to the data communication device. It should be noted that this application describes the embodiments of the device part from two perspectives: one is based on the functional module, and the other is based on the hardware.

[0093] Figure 3 This application provides a schematic diagram of a data communication device, applied to a data communication system including: BMC, PCH, SMBus Slave, and CPLD, such as... Figure 3 As shown, the device includes:

[0094] Module 10 is used to control the SMBus Switch to acquire communication information between the PCH and the BMC;

[0095] Judgment module 11 is used to determine whether the BMC has malfunctioned based on communication information. If so, it enters the switching module.

[0096] Switching module 12 is used to control the SMBus switch to switch the BMC to the SMBus Master;

[0097] The communication module 13 is used to control the communication between the SMBus Master and the PCH, and to perform read and write operations on the SMBus Slave according to the information sent by the PCH.

[0098] Since the embodiments of the apparatus and the embodiments of the method correspond to each other, please refer to the description of the embodiments of the method for the embodiments of the apparatus and their corresponding beneficial effects, which will not be repeated here.

[0099] The data communication device provided in this application is applied to a data communication system including a BMC, PCH, SMBus Slave, and CPLD. The CPLD includes an SMBus Master and an SMBus Switch. The SMBus Switch controls the connection between the BMC and the SMBus Slave when the BMC is working normally, and controls the connection between the SMBus Master and the SMBus Slave when the BMC malfunctions, thereby ensuring that the entire board will not shut down due to a BMC malfunction. Compared with previous solutions, because the data communication system of this application uses the CPLD to detect and parse the communication data between the PCH and the BMC, and determines whether the BMC is malfunctioning based on the communication signals between the BMC and the PCH to switch control of the SMBus slave, it ensures that the system's maintenance and management operations are uninterrupted and unaffected by BMC malfunctions, thus ensuring the stability of machine functions and enhancing machine availability.

[0100] Figure 4 A schematic diagram of a data communication device provided in another embodiment of this application is shown below. Figure 4 As shown, the data communication device includes: a memory 20 for storing computer programs;

[0101] The processor 21 is used to implement the steps of the data communication method mentioned in the above embodiments when executing a computer program.

[0102] The data communication device provided in this embodiment may include, but is not limited to, smartphones, tablets, laptops, or desktop computers.

[0103] The processor 21 may include one or more processing cores, such as a quad-core processor or an octa-core processor. The processor 21 may be implemented using at least one hardware form selected from Digital Signal Processor (DSP), Field-Programmable Gate Array (FPGA), and Programmable Logic Array (PLA). The processor 21 may also include a main processor and a coprocessor. The main processor, also known as the Central Processing Unit (CPU), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor 21 may integrate a Graphics Processing Unit (GPU), which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, the processor 21 may also include an Artificial Intelligence (AI) processor, which handles computational operations related to machine learning.

[0104] The memory 20 may include one or more computer-readable storage media, which may be non-transitory. The memory 20 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In this embodiment, the memory 20 is used to store at least the following computer program 201, which, after being loaded and executed by the processor 21, is capable of implementing the relevant steps of the data communication method disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory 20 may also include an operating system 202 and data 203, and the storage method may be temporary storage or permanent storage. The operating system 202 may include Windows, Unix, Linux, etc. The data 203 may include, but is not limited to, the data involved in the data communication method.

[0105] In some embodiments, the data communication device may further include a display screen 22, an input / output interface 23, a communication interface 24, a power supply 25, and a communication bus 26.

[0106] Those skilled in the art will understand that Figure 4 The structure shown does not constitute a limitation on the data communication device and may include more or fewer components than illustrated.

[0107] The data communication device provided in this application includes a memory and a processor. When the processor executes a program stored in the memory, it can implement the following method: the data communication method involved in the above embodiments.

[0108] The data communication device provided in this application is applied to a data communication system including a BMC, PCH, SMBus Slave, and CPLD. The CPLD includes an SMBus Master and an SMBus Switch. The SMBus Switch controls the connection between the BMC and the SMBus Slave when the BMC is working normally, and controls the connection between the SMBus Master and the SMBus Slave when the BMC malfunctions, thereby ensuring that the entire board will not shut down due to a BMC malfunction. Compared with previous solutions, because the data communication system of this application uses the CPLD to detect and parse the communication data between the PCH and the BMC, and determines whether the BMC is malfunctioning based on the communication signals between the BMC and the PCH to switch control of the SMBus slave, it ensures that the system's maintenance and management operations are uninterrupted and unaffected by BMC malfunctions, thus ensuring the stability of machine functions and enhancing machine availability.

[0109] Since the embodiments of the apparatus and the embodiments of the method correspond to each other, please refer to the description of the embodiments of the method for the embodiments of the apparatus and their corresponding beneficial effects, which will not be repeated here.

[0110] Finally, this application also provides an embodiment corresponding to a computer-readable storage medium. The computer-readable storage medium stores a computer program, which, when executed by a processor, implements the steps described in the above method embodiments.

[0111] It is understood that if the methods in the above embodiments are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and executes all or part of the steps of the methods in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0112] Since the embodiments of the readable storage medium portion correspond to the embodiments of the method portion, the embodiments of the apparatus portion and their corresponding beneficial effects are described in the description of the embodiments of the method portion, and will not be repeated here.

[0113] The data communication device provided in this application is applied to a data communication system including a BMC, PCH, SMBus Slave, and CPLD. The CPLD includes an SMBus Master and an SMBus Switch. The SMBus Switch controls the connection between the BMC and the SMBus Slave when the BMC is working normally, and controls the connection between the SMBus Master and the SMBus Slave when the BMC malfunctions, thereby ensuring that the entire board will not shut down due to a BMC malfunction. Compared with previous solutions, because the data communication system of this application uses the CPLD to detect and parse the communication data between the PCH and the BMC, and determines whether the BMC is malfunctioning based on the communication signals between the BMC and the PCH to switch control of the SMBus slave, it ensures that the system's maintenance and management operations are uninterrupted and unaffected by BMC malfunctions, thus ensuring the stability of machine functions and enhancing machine availability.

[0114] The foregoing provides a detailed description of a data communication system, method, apparatus, and computer-readable storage medium provided in this application. The various embodiments are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

[0115] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

Claims

1. A data communication system, characterized by include: BMC, PCH, SMBus Slave, CPLD: The BMC is connected to the PCH and is used for data communication with the PCH; The CPLD includes an SMBus Master and an SMBus Switch. The SMBus Switch is used to control the connection between the BMC and the SMBus Slave when the BMC is working normally, and to control the connection between the SMBus Master and the SMBus Slave when the BMC is malfunctioning. The SMBus Master is connected to the PCH and is used to communicate with the PCH for data when the BMC fails. The SMBus Master is also used to determine whether the data in the buffer of the CPLD is valid; if so, it controls the SMBus Master to communicate with the PCH according to the data in the buffer; if not, it takes over and executes the information sent by the PCH, and performs read and write operations on the SMBus Slave. The SMBus Master is also used to receive the preset address of the SMBus Slave and the length of the communication data sent by the PCH; to determine the communication instruction of the PCH according to the length of the communication data; if it is a read instruction, to perform a read operation on the SMBus Slave according to the preset address and send the read result to the PCH; if it is a write instruction, to write the write data in the communication data into the corresponding SMBus Slave according to the preset address of the SMBus Slave. The PCH is also used to check whether the OOB_FREE flag in the current status register is valid based on the GET_STATUS command. If the OOB_FREE flag is valid, a read operation is performed on the SMBus Slave, and the preset address of the SMBus Slave and the length of the communication data are sent through the PUT_OOB command in the OOB channel. The SMBus Master is also used to determine that if there is no other game data after detecting the data length, it is to perform a read operation on the SMBus Slave; after performing a read operation on the SMBus Slave, it clears the OOB_FREE flag and sets the OOB_AVAIL flag, and triggers an alert signal to the PCH. The PCH is also used to obtain SMBus Slave data by using the GET_STATUS command after receiving an alert signal and by using the GET_OOB command after detecting that the OOB_AVAIL flag is set. The CPLD is also used to parse the GET_OOB command and return the read SMBus Slave data to the PCH; The SMBus Master is also used to send the address of the SMBus Slave, the length of the data to be written, and the data to be written through the PUT_OOB command in the OOB channel if the OOB_FREE flag is valid and a write operation is performed on the SMBus Slave. The CPLD is also used to parse the PUT_OOB command and then control the SMBus Master to write the write data in the communication data into the corresponding SMBus Slave. The SMBus Master is also used to clear the OOB_FREE flag and set the OOB_FREE flag after writing is complete.

2. The data communication system of claim 1, wherein, The BMC communicates with the PCH, and the CPLD communicates with the PCH via the eSPI bus. The CPLD communicates with the SMBus Slave and the BMC via the SMBus bus.

3. The data communication system of claim 2, wherein, The CPLD also includes a bypass, which is used to connect the BMC and the SMBus Switch, and to determine whether the BMC is abnormal based on the WDT signal of the BMC.

4. A data communication method characterized by, The method is applied to a data communication system including a BMC, PCH, SMBus Slave, and CPLD, wherein the BMC is connected to the PCH, the CPLD includes an SMBus Master and an SMBus Switch, and the SMBus Master is connected to the PCH. The SMBus Switch is controlled to acquire communication information between the PCH and the BMC; Determine whether the BMC has malfunctioned based on the communication information; If so, control the SMBus Switch to switch the BMC to the SMBus Master; The SMBus Master is controlled to communicate with the PCH, and read / write operations are performed on the SMBusSlave according to the information sent by the PCH. After controlling the SMBus Switch to switch the BMC to the SMBus Master, the method further includes: determining whether the data in the buffer of the CPLD is valid; if so, controlling the SMBus Master to communicate with the PCH according to the data in the buffer; if not, taking over and executing the information sent by the PCH, and performing read and write operations on the SMBusSlave. The process of controlling the SMBus Master to communicate with the PCH and performing read / write operations on the SMBus Slave according to the information sent by the PCH includes: receiving the preset address of the SMBus Slave and the length of the communication data sent by the PCH; confirming the communication command of the PCH according to the length of the communication data; if it is a read command, performing a read operation on the SMBus Slave according to the preset address and sending the read result to the PCH; if it is a write command, writing the write data in the communication data into the corresponding SMBus Slave according to the preset address of the SMBus Slave. The method further includes: checking whether the OOB_FREE flag in the current status register is valid through PCH and based on the GET_STATUS command; if the OOB_FREE flag is valid, performing a read operation on the SMBus Slave, and then sending the preset address of the SMBus Slave and the length of the communication data through the PUT_OOB command in the OOB channel. The step of confirming the PCH communication instruction based on the length of the communication data includes: after detecting the data length, if there is no other game data, it is determined that a read operation is performed on the SMBus Slave; After performing a read operation on the SMBus Slave, the process further includes: clearing the OOB_FREE flag and setting the OOB_AVAIL flag, while simultaneously triggering an alert signal to the PCH. Upon receiving the alert signal, the PCH uses the GET_STATUS command. After detecting that the OOB_AVAIL flag is set, it uses the GET_OOB command to retrieve the SMBus Slave data. After the CPLD parses the GET_OOB command, it returns the read SMBus Slave data to the PCH. The method further includes: if the OOB_FREE flag is valid and a write operation is performed on the SMBus Slave, then the address of the SMBus Slave, the length of the data to be written, and the data to be written are sent through the PUT_OOB command in the OOB channel; The step of writing the write data in the communication data into the corresponding SMBus Slave includes: after parsing the PUT_OOB command through CPLD, controlling the SMBus Master to write the write data in the communication data into the corresponding SMBus Slave; After writing the write data from the communication data to the corresponding SMBus Slave, the process also includes: clearing the OOB_FREE flag and setting the OOB_FREE flag after the write is completed.

5. The data communication method according to claim 4, characterized by, The CPLD also includes a bypass, and the step of determining whether the BMC has malfunctioned based on the communication information includes: The bypass detection is used to check whether the WDT signal of the BMC is flipped. If the WDT signal flips, it indicates that the BMC is not abnormal. If the WDT signal does not flip, it indicates that the BMC is abnormal.

6. A data communication device, characterized by The device is applied to a data communication system including a BMC, PCH, SMBus Slave, and CPLD, wherein the BMC is connected to the PCH, the CPLD includes an SMBus Master and an SMBus Switch, the SMBus Master is connected to the PCH, and the device includes: The acquisition module is used to control the SMBus Switch to acquire communication information between the PCH and the BMC; The judgment module is used to determine whether the BMC is malfunctioning based on the communication information; if so, it enters the switching module. The switching module is used to control the SMBus Switch to switch the BMC to the SMBus Master; The communication module is used to control the SMBus Master to communicate with the PCH, and to perform read and write operations on the SMBus Slave according to the information sent by the PCH; The device is also used to determine whether the data in the buffer of the CPLD is valid; if so, it controls the SMBus Master to communicate with the PCH according to the data in the buffer; if not, it takes over and executes the information sent by the PCH, and performs read and write operations on the SMBus Slave. The communication module is specifically used to receive the preset address of the SMBus Slave and the length of the communication data sent by the PCH; to determine the communication instruction of the PCH according to the length of the communication data; if it is a read instruction, to perform a read operation on the SMBus Slave according to the preset address and send the read result to the PCH; if it is a write instruction, to write the write data in the communication data into the corresponding SMBus Slave according to the preset address of the SMBus Slave. The device is also used to check whether the OOB_FREE flag in the current status register is valid through PCH and based on the GET_STATUS command. If the OOB_FREE flag is valid, a read operation is performed on the SMBus Slave, and the preset address of the SMBus Slave and the length of the communication data are sent through the PUT_OOB command in the OOB channel. The device is further configured to, after detecting the data length, determine that a read operation is to be performed on the SMBusSlave if no other game data is available; after the read operation on the SMBusSlave, the OOB_FREE flag is cleared and the OOB_AVAIL flag is set, and an alert signal is triggered to the PCH. Upon receiving the alert signal, the PCH uses the GET_STATUS command. After detecting that the OOB_AVAIL flag is set, it uses the GET_OOB command to obtain the SMBusSlave data; after the CPLD parses the GET_OOB command, it returns the read SMBusSlave data to the PCH. The device is also used to, if the OOB_FREE flag is valid and a write operation is performed on the SMBus Slave, send the address of the SMBus Slave, the length of the data to be written, and the data to be written via the PUT_OOB command in the OOB channel; The communication module is also used to control the SMBus Master to write the write data in the communication data into the corresponding SMBus Slave after parsing the PUT_OOB command through the CPLD; after writing the write data in the communication data into the corresponding SMBus Slave, clear the OOB_FREE flag bit, and set the OOB_FREE flag bit after the writing is completed.

7. A data communication device, characterized by Includes memory used to store computer programs; A processor, configured to implement the steps of the data communication method as described in any one of claims 4 to 5 when executing the computer program.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the data communication method as described in any one of claims 4 to 5.

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