Display panel, display device including the same, and method for manufacturing the display device

Abstract

Disclosed are a display panel, a display device including the same, and a method for manufacturing the display device, in which a unit pixel is divided into a wide-angle region and a narrow-angle region in which at least a sub-pixel is arranged and light emission is performed individually and selectively. A semi-cylindrical lens is arranged in the wide-angle region to cover a plurality of sub-pixels. A hemispherical lens is arranged in the narrow-angle region to cover the sub-pixels respectively. Therefore, the direction of light emitted from the light-emitting layer is controlled by adjusting the refractive index of each lens in the wide-angle region and the narrow-angle region. Therefore, the viewing angle is controlled.

Description

Technical Field

[0001] The present disclosure relates to a display panel in which a unit pixel is divided into a wide-angle region and a narrow-angle region that output colors separately, a display device including the display panel, and a method of manufacturing the display device. Background Art

[0002] Flat panel displays (FPDs) include organic light emitting diode (OLED) display devices having high luminance and low operating voltage characteristics.

[0003] Since the OLED display device is self-luminous, its contrast is large, and the OLED display device is made into an ultra-thin display. In addition, the OLED display device has a response time of several microseconds, which makes it easy to realize moving images. The OLED display device has no viewing angle limitation, is stable even at low temperatures, and operates at a low voltage of DC 5V to 15V, which makes it easy to manufacture and design a driving circuit.

[0004] Furthermore, since the manufacturing process of the OLED display device mainly consists of deposition and packaging, the manufacturing process is very simple.

[0005] A plurality of thin film transistors, such as a switching thin film transistor, a driving thin film transistor, and a sensing thin film transistor, are formed in each pixel region of the OLED display device. Summary of the invention

[0006] However, in an OLED display device, most of the light emitted from its organic light emitting layer may be lost when passing through various components of the display device and emitted to the outside. Therefore, the light emitted to the outside of the OLED display device is only about 50% or less of the light emitted from the organic light emitting layer.

[0007] In this regard, the amount of light emitted from the organic light-emitting layer increases as the amount of current applied to the OLED display device increases. Therefore, the illumination of the OLED display device can be enhanced by applying a larger amount of current to the organic light-emitting layer. However, this may increase power consumption. In addition, the life of the OLED display device is also reduced.

[0008] Recently, in order to control a light path of an OLED display device, a light control film (LCF) is attached to an outer surface of a substrate of the OLED display device.

[0009] The light control film (LCF) can control the amount of light that penetrates the polarizing plate (POL) using a louver structure disposed on the top surface thereof based on the pitch and vertical dimension of the louver structure. In addition, the light control film (LCF) can block light at a certain angle or greater using the louver structure. For example, the light control film (LCF) can block light incident on the panel at an angle of 60 degrees or greater.

[0010] Another solution for controlling the light path may include an SPM film that can apply an electrical signal to a liquid crystal injection layer disposed on the top surface of a polarizing plate (POL) to block light. A liquid phase-related solution should be used to ensure the dispersion stability of the injection liquid of the SPM film. In addition, the liquid is very susceptible to temperature, and therefore, the SPM film may not operate at low or high temperatures.

[0011] The above-mentioned light control film (LCF) or SPM film causes a decrease in illuminance when a blocking layer is added as described above.

[0012] Therefore, in order to solve the above-mentioned problems of the OLED display device, the inventors of the present disclosure invented the following display panel: in the display panel, the unit pixel is divided into a wide-angle area and a narrow-angle area in which sub-pixels are arranged, and the sub-pixels in the wide-angle area and the sub-pixels in the narrow-angle area are selectively activated.

[0013] In addition, the inventors of the present disclosure invented the following display panel based on the user's choice when viewing the display device: in the display panel, a unit pixel is divided into a wide-angle area and a narrow-angle area in which sub-pixels of the unit pixel are arranged, and the color of the sub-pixel in the wide-angle area is output through a semi-cylindrical lens, or the color of the sub-pixel in the narrow-angle area is output through a hemispherical lens.

[0014] The purpose according to the present disclosure is not limited to the above-mentioned purpose. Other purposes and advantages not mentioned according to the present disclosure can be understood based on the following description, and can be more clearly understood based on the embodiments according to the present disclosure. In addition, it will be easily understood that the purposes and advantages according to the present disclosure can be achieved using the means and combinations thereof shown in the claims.

[0015] A display panel according to an embodiment of the present disclosure may be provided. In the display panel, a unit pixel may be divided into a wide-angle region and a narrow-angle region in which at least one sub-pixel is arranged. A semi-cylindrical first lens may be disposed in the wide-angle region. A hemispherical second lens may be disposed in the narrow-angle region.

[0016] In addition, a display device according to an embodiment of the present disclosure may be displayed. A unit pixel may be divided into a wide-angle region and a narrow-angle region in which at least one sub-pixel is arranged. A gate driver of the display device applies a gate signal to at least one sub-pixel through at least one gate line under the control of a timing controller. A data driver of the display device applies a data signal to at least one sub-pixel through at least one data line under the control of a timing controller.

[0017] According to an embodiment of the present disclosure, a unit pixel may be divided into a wide-angle region and a narrow-angle region. A plurality of pixels arranged in a light-emitting region may be arranged in the wide-angle region and the narrow-angle region and may be activated in the wide-angle region and the narrow-angle region in a separate manner. Therefore, the light-emitting angle of the pixel in the unit pixel may be selected to control the viewing angle.

[0018] In addition, according to an embodiment of the present disclosure, the refractive indices of the layers are similar to each other, and the refractive indices of the lens and the outermost layer may be different from each other by a certain amount to control the direction of light.

[0019] In addition, according to an embodiment of the present disclosure, the direction of light emitted from the light emitting layer can be controlled by adjusting the refractive index of each lens in the wide angle region and the narrow angle region. Therefore, the viewing angle can be adjusted based on the direction of the controlled light.

[0020] Furthermore, according to the present disclosure, the viewing angle may be controlled based on the refractive index of each layer in each pixel within a unit pixel.A physical light control layer may be associated with pixel operations within a panel to control the viewing angle.

[0021] Furthermore, according to the present disclosure, the display mode of a display device may be selectively implemented as a privacy mode required by the display device (a mobile device, an IT device, and an automatic directional display).

[0022] Furthermore, since there are no additional layers, the present disclosure can improve light efficiency without sacrificing light loss.

[0023] Furthermore, the present disclosure may increase lifespan and achieve high illuminance of a display device by improving light efficiency.

[0024] Furthermore, according to the present disclosure, one compensation pixel in a wide-angle area may be divided into two light-emitting units using a lens.

[0025] Furthermore, the present disclosure can achieve the prevention of upward light leakage required for privacy or LCF (Light Control Film) during operation of pixels in narrow angle areas.

[0026] In addition, according to the embodiments of the present disclosure, the film existing in the conventional film display device can be removed, thereby increasing the brightness and improving the light collection efficiency using the lens. Therefore, it can be expected that the life of the display device product will be improved.

[0027] The effects of the present disclosure are not limited to the above effects, and those skilled in the art will clearly understand the other effects not mentioned from the following description. In addition to the above effects, the specific effects of the present disclosure will be described below while describing the specific details for executing the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a configuration diagram schematically showing a configuration of a display device according to an embodiment of the present disclosure.

[0029] Figure 2A and Figure 2B is a structural diagram schematically showing a unit pixel structure of a display panel according to an embodiment of the present disclosure.

[0030] Figure 3 is a view illustrating a shape and a cutoff direction of each of a first lens and a second lens provided in a unit pixel of a display panel according to an embodiment of the present disclosure.

[0031] Figures 4 to 8 is a view illustrating an example in which at least two or more first lenses are arranged in a first lens array in a wide angle region of a display panel according to an embodiment of the present disclosure.

[0032] Fig. 9 In a display device according to an embodiment of the present disclosure, Figure 1 A cross-sectional view taken along line Ι-Ι'.

[0033] Fig.10 is a diagram illustrating a size and illuminance efficiency of each of a first lens in a wide angle region and a second lens in a narrow angle region in a display panel according to an embodiment of the present disclosure.

[0034] Fig.11 is a view showing an example in which each of the first lens and the second lens according to an embodiment of the present disclosure outputs an image while cutting off light in each of a wide-angle region and a narrow-angle region in a display panel.

[0035] Fig.12 is a diagram showing an example of a pixel circuit configuration of a unit pixel of a display panel according to an embodiment of the present disclosure.

[0036] Fig.13 is shown for driving Fig.12 FIG. 5 is a diagram showing the timing of control signals of a pixel circuit.

[0037] Fig.14 A layout diagram of a first light emission control signal applying line and a second light emission control signal applying line according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0038] For the sake of brevity and clarity of explanation, the elements in the figures are not necessarily drawn to scale. The same reference numerals in different figures represent the same or similar elements, and therefore perform similar functions. In addition, for the sake of simplicity of description, the description and details of known steps and elements are omitted. In addition, in the following detailed description of the present disclosure, many specific details are set forth to provide a thorough understanding of the present disclosure. However, it should be understood that the present disclosure can be practiced without these specific details. In other cases, known methods, processes, components and circuits are not described in detail to avoid unnecessary obscurity of various aspects of the present disclosure.

[0039] Examples of various embodiments are further illustrated and described below. It will be understood that the description herein is not intended to limit the claims to the specific embodiments described. On the contrary, it is intended to cover the alternatives, modifications and equivalents that may be included within the spirit and scope of the present disclosure defined by the appended claims.

[0040] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for describing the embodiments of the present disclosure are exemplary, and the present disclosure is not limited thereto. The same reference numerals refer to the same elements herein. In addition, for the sake of brevity of description, the description and details of known steps and elements are omitted. In addition, in the following detailed description of the present disclosure, many specific details are set forth to provide a thorough understanding of the present disclosure. However, it will be understood that the present disclosure can also be practiced without these specific details. In other cases, known methods, processes, components and circuits are not described in detail to avoid unnecessary obscurity of various aspects of the present disclosure.

[0041] The terms used herein are only used for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "one" and "an" are also intended to include plural forms unless the context clearly indicates otherwise. It will also be understood that the terms "include", "comprise", "include ... "and "included" when used in this specification specify the presence of stated features, integers, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, operations, elements, parts and / or parts thereof. As used herein, the term "and / or" includes any and all combinations of one or more associated listed items. Expressions such as "at least one" can modify the entire list of elements when preceding a list of elements, but not a single element of the list. When "C to D" is mentioned, this means C inclusive to D inclusive, unless otherwise specified.

[0042] It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the spirit and scope of the present disclosure, the first element, component, region, layer or part described below may be referred to as a second element, component, region, layer or part.

[0043] In addition, it will be understood that when a first element or layer is referred to as being “on” or “under” a second element or layer, the first element can be directly disposed on or under the second element, or can be indirectly disposed on or under the second element with a third element or layer disposed between the first element or layer and the second element or layer.

[0044] It will be understood that when an element or layer is referred to as being “connected to” or “coupled to” another element or layer, it can be directly on, directly connected to, or directly coupled to the other element or layer, or one or more intervening elements or layers may be present. Additionally, it will be understood that when an element or layer is referred to as being “between” two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present.

[0045] In addition, as used herein, when a layer, film, region, plate, etc. is disposed "on" or "on top" of another layer, film, region, plate, etc., the former may directly contact the latter or another layer, film, region, plate, etc. may be disposed between the former and the latter. As used herein, when a layer, film, region, plate, etc. is disposed "on" or "on top" of another layer, film, region, plate, etc., the former may directly contact the latter and no other layer, film, region, plate, etc. may be disposed between the former and the latter. In addition, as used herein, when a layer, film, region, plate, etc. is disposed "under" or "below" another layer, film, region, plate, etc., the former may directly contact the latter or another layer, film, region, plate, etc. may be disposed between the former and the latter. As used herein, when a layer, film, region, plate, etc. is disposed "under" or "below" another layer, film, region, plate, etc., the former may directly contact the latter and no other layer, film, region, plate, etc. may be disposed between the former and the latter.

[0046] Unless otherwise defined, all terms used herein, including technical and scientific terms, have the same meaning as commonly understood by those of ordinary skill in the art to which the inventive concept belongs. It will also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0047] In one example, when a certain embodiment can be implemented differently, the functions or operations specified in a particular block may occur in an order different from the order specified in the flow chart. For example, two consecutive blocks may actually be executed at the same time. Depending on the related functions or operations, these blocks may be executed in reverse order.

[0048] In a description of a temporal relationship, for example, a temporal precedence relationship between two events such as "after", "subsequently", "before", etc., unless "directly after", "directly subsequent", or "directly before" is not indicated, another event may occur between the two events.

[0049] The features of various embodiments of the present disclosure may be combined with each other in part or in whole, and may be technically associated with each other or operate with each other. The various embodiments may be implemented independently of each other, and may be implemented together in an associated relationship.

[0050] For ease of description, spatially relative terms such as "below", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of an element or feature to another element or feature as shown in the figure. It will be understood that spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation depicted in the drawings. For example, if the device in the drawings is turned over, the elements described as "below" or "below" or "below" other elements or features will be oriented to be "above" other elements or features. Therefore, the example terms "below" and "below" can include both the orientation of above and below. The device can be oriented in other ways (e.g., rotated 90 degrees or other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0051] Hereinafter, an organic light emitting display device and a method of manufacturing the same according to an embodiment of the present disclosure will be described.

[0052] Figure 1 is a configuration diagram schematically showing a configuration of a display device according to an embodiment of the present disclosure.

[0053] Reference Figure 1, a display device 100 according to an embodiment of the present disclosure includes a display panel 10 , a gate driver 20 , a data driver 30 , a timing controller 40 , and the like.

[0054] A plurality of data lines DL1 to DLm and a plurality of gate lines GL1 to GLn may be arranged in the display panel 10. A pixel may be disposed at a cross region between one gate line and one data line. One pixel P may include at least one sub-pixel SP. Hereinafter, in an embodiment of the present disclosure, one pixel P may be referred to as a "unit pixel".

[0055] The display panel 10 may include a unit pixel 110 composed of at least one sub-pixel SP. In addition, the unit pixel 110 may include one pixel P or at least one pixel P. In this regard, Figure 2A and Figure 2B The structure of one unit pixel 110 is described in more detail in FIG.

[0056] The gate driver 20 may drive a plurality of gate lines GL1 to GLn.

[0057] The data driver 30 may drive a plurality of data lines DL1 to DLm.

[0058] The timing controller 40 may control the gate driver 20 and the data driver 30 .

[0059] The gate driver 20 may sequentially supply a scan (gate) signal to the plurality of gate lines GL1 to GLn to sequentially drive the plurality of gate lines GL1 to GLn.

[0060] The data driver 30 may supply data voltages to the plurality of data lines DL1 to DLm to drive the plurality of data lines DL1 to DLm.

[0061] The timing controller 140 may provide control signals to the gate driver 20 and the data driver 30 to control the gate driver 20 and the data driver 30. The timing controller 40 may start scanning according to the timing implemented in each frame, may convert input image data input from an external component according to a data signal format used by the data driver 30, may output the converted image data, and may control data driving at an appropriate timing based on scanning.

[0062] The gate driver 20 sequentially provides a scanning signal of a turn-on voltage or a turn-off voltage to the plurality of gate lines GL1 to GLn under the control of the timing controller 40 to sequentially drive the plurality of gate lines GL1 to GLn. In addition, according to a driving scheme or a display panel design scheme, the gate driver 20 may be configured as follows: Figure 1 The display panel 10 is shown as being located only on one side of the display panel 10 , or may be located on two opposite sides of the display panel 10 .

[0063] In addition, the gate driver 20 may include at least one gate driver integrated circuit. Each gate driver integrated circuit may be connected to a bonding pad of the display panel 10 in a TAB (Tape Automated Bonding) scheme or in a COG (Chip on Glass) scheme. Alternatively, the gate driver integrated circuit may be directly disposed in the display panel 10 in a GIP (Gate in Panel) scheme. In some cases, the gate driver integrated circuit may be integrated into the display panel 10.

[0064] In addition, each gate driver integrated circuit may be implemented in a COF (Chip on Film) scheme. In this case, a gate driver chip corresponding to each gate driver integrated circuit may be mounted on a flexible film. One end of the flexible film may be bonded to the display panel 10.

[0065] When a specific gate line is turned on, the data driver 30 converts the image data received from the timing controller 40 into an analog data voltage and supplies the analog data voltage to the plurality of data lines DL1 to DLm to drive the plurality of data lines DL1 to DLm. In addition, the data driver 30 may include at least one source driver integrated circuit to drive the plurality of data lines DL1 to DLm.

[0066] Each source driver integrated circuit may be connected to a bonding pad of the display panel 10 in a TAB (Tape Automated Bonding) scheme or in a COG (Chip on Glass) scheme. Alternatively, the source driver integrated circuit may be directly provided in the display panel 10. In some cases, the source driver integrated circuit may be integrated into the display panel 10.

[0067] In addition, each source driver integrated circuit can be implemented in a chip on film (COF) solution. In this case, the source driver chip corresponding to each source driver integrated circuit can be mounted on a flexible film. One end of the flexible film can be bonded to at least one source printed circuit board. The other end of the flexible film can be bonded to the display panel 10.

[0068] The source printed circuit board may be connected to the control printed circuit board through a connection medium such as a flexible flat cable (FFC) or a flexible printed circuit (FPC). The timing controller 40 is disposed on the control printed circuit board.

[0069] In addition, a power controller (not shown) that supplies voltage or current to the display panel 10, the gate driver 20 and the data driver 30 or controls the voltage or current to be supplied may be further provided in the control printed circuit board. The source printed circuit board and the control printed circuit board as described above may be integrated in a single printed circuit board.

[0070] In addition, although not shown in the drawings, a switching thin film transistor T1, a driving thin film transistor Tdr, a storage capacitor Cst, and a light emitting diode OLED1 may be provided in each pixel P.

[0071] Each of the switching thin film transistor T1 and the driving thin film transistor Tdr may include an active layer ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE. The light emitting diode OLED1 may include an anode electrode AE, an organic light emitting layer OLE, and a cathode electrode CE.

[0072] The gate electrode GE, source electrode SE and drain electrode DE of the switching thin film transistor T1 may be connected to the gate line GL, data line DL and gate electrode GE of the driving thin film transistor Tdr, respectively. The gate electrode GE, source electrode SE and drain electrode DE of the driving thin film transistor Tdr may be connected to the drain electrode of the switching thin film transistor T1, the anode of the light emitting diode OLED1 and the power line PL, respectively. The anode and cathode of the light emitting diode OLED1 may be connected to the source electrode of the driving thin film transistor Tdr and the low potential voltage Vss, respectively.

[0073] In one example, a pixel P according to the present disclosure includes at least one sub-pixel SP. The sub-pixel SP may mean a unit in which a specific type of color filter is formed or no color filter is formed and the organic light emitting element emits a special color. The colors presented in the sub-pixel may include red (R), green (G), blue (B), and optional white (W), but may not be limited thereto.

[0074] In addition, the electrode connected to the thin film transistor that controls the light emission of each sub-pixel SP of the display panel 10 is referred to as a first electrode. An electrode disposed on the front surface of the display panel 10 or disposed to include two or more pixels is referred to as a second electrode. When the first electrode is an anode electrode AE, the second electrode is used as a cathode electrode CE, or when the second electrode is an anode electrode AE, the first electrode is used as a cathode electrode CE. Hereinafter, a case in which an anode electrode is used as an example of a first electrode and a cathode electrode is used as an example of a second electrode will be described. The present disclosure is not limited thereto.

[0075] A pixel P according to the present disclosure includes at least one sub-pixel SP. For example, one pixel may include 2 to 4 sub-pixels. A sub-pixel SP may mean a unit in which a specific type of color filter is formed or no color filter is formed and an organic light emitting element emits a special color. The colors presented in the sub-pixel may include red (R), green (G), blue (B), and optional white (W). The present disclosure is not limited thereto.

[0076] The present disclosure may be applied to an organic light-emitting display device having a bottom emission scheme. The present disclosure is not limited thereto. In some cases, the present disclosure may also be applied to an organic light-emitting display device having a top emission scheme or a dual emission scheme.

[0077] Figure 2A and Figure 2B is a structural diagram schematically showing a unit pixel structure of a display panel according to an embodiment of the present disclosure.

[0078] Reference Figure 2A and Figure 2B , the display panel 10 according to an embodiment of the present disclosure may include a unit pixel 110 , a first lens array 120 , and a second lens array 130 .

[0079] The unit pixel 110 may be divided into a wide angle area WAA and a narrow angle area NAA. At least one sub-pixel SP may be disposed in each of the wide angle area WAA and the narrow angle area NAA.

[0080] The first lens array 120 may include at least one first lens Lz1 disposed in the wide angle area WAA.

[0081] The second lens array 130 may include at least one second lens Lz2 disposed in the narrow angle area NAA.

[0082] The unit pixel 110 may include a first unit pixel 112 disposed in the wide angle area WAA and a second unit pixel 114 disposed in the narrow angle area NAA.

[0083] The first unit pixel 112 may be composed of at least one sub-pixel 1SP1 , 1SP2 , and 1SP3 , and the second unit pixel 114 may be composed of at least one sub-pixel 2SP1 , 2SP2 , and 2SP3 .

[0084] For example, the first unit pixel 112 may include a first subpixel 1SP1 of red (R), a second subpixel 1SP2 of green (G), and a third subpixel 1SP3 of blue (B), and may optionally include white (W). However, the present disclosure is not limited thereto.

[0085] In addition, the second unit pixel 114 may include a first subpixel 2SP1 of red (R), a second subpixel 2SP2 of green (G), and a third subpixel 2SP3 of blue (B), and may optionally include white (W). However, the present disclosure is not limited thereto.

[0086] In this regard, the wide angle region may be referred to as a “wide viewing region” or a “wide viewing angle region”, and the narrow angle region may be referred to as a “narrow viewing region” or a “narrow viewing angle region.” Considering visibility and lens efficiency, at least two subpixels SP may be continuously arranged.

[0087] The at least one sub-pixel may include a plurality of sub-sub-pixels.

[0088] The unit pixel 110 includes at least three sub-pixels SP. In the wide angle area WAA, the first lens Lz1 may be formed to extend over at least two sub-pixels.

[0089] In the first unit pixel 112 as the wide-angle area WAA, the first sub-pixel 1SP1 may include at least one red (R) sub-sub-pixel 1SP1-1. For example, the first sub-pixel 1SP1 may be composed of three red (R) sub-sub-pixels 1SP1-1. The three sub-sub-pixels 1SP1-1 may be arranged continuously in the vertical direction.

[0090] In this regard, the three sub-pixels 1SP1-1 may receive data power from the first-first anode electrode AE1-1 via the first-first contact hole CH1-1. The first-first anode electrode AE1-1 may be implemented as a metal film having a rectangular shape surrounding the three sub-pixels 1SP1-1. The three sub-pixels 1SP1-1 may be connected to the first-first contact hole CH1-1. Figure 2B Three first-first openings OP1-1 of the same size and shape defined in the first-first bank BK1-1 shown in FIG. 1 are exposed. The first-first bank BK1-1 may have the same shape and size as those of the first-first anode electrode AE1-1.

[0091] In the first unit pixel 112, the second sub-pixel 1SP2 may include at least one green (G) sub-sub-pixel 1SP2-1. For example, the second sub-pixel 1SP2 may be composed of 6 green (G) sub-sub-pixels 1SP2-1. The 6 sub-sub-pixels 1SP2-1 may be arranged in two rows extending horizontally and arranged vertically, wherein each row has 3 sub-sub-pixels.

[0092] In this regard, the six sub-sub-pixels 1SP2-1 may receive data power from the first to second anode electrodes AE1-2 via the first to second contact holes CH1-2. The first to second anode electrodes AE1-2 may be implemented as a metal film having a rectangular shape surrounding the three sub-sub-pixels 1SP2-1 in the lower row and the three sub-sub-pixels 1SP2-1 in the upper row. The six sub-sub-pixels 1SP2-1 may be connected to the first and second anode electrodes AE1-2 through the first and second contact holes CH1-2. Figure 2BSix first-second openings OP1-2 of the same size and shape defined in the first-second bank BK1-2 shown in FIG. 1 are exposed. The first-second bank BK1-2 may have the same shape and size as those of the first-second anode electrodes AE1-2.

[0093] In the first unit pixel 112, the third sub-pixel 1SP3 may include at least one blue (B) sub-sub-pixel 1SP3-1. For example, the third sub-pixel 1SP3 may be composed of three blue (B) sub-sub-pixels 1SP3-1. The three sub-sub-pixels 1SP3-1 may be sequentially arranged in the vertical direction.

[0094] In this regard, the three sub-pixels 1SP3-1 may receive data power from the first to third anode electrodes AE1-3 via the first to third contact holes CH1-3. The first to third anode electrodes AE1-3 may be implemented as a rectangular metal film surrounding the three sub-pixels 1SP3-1. The three sub-pixels 1SP3-1 may be connected to the first to third anode electrodes AE1-3 through the first to third contact holes CH1-3. Figure 2B The three first to third openings OP1-3 of the same size and shape defined in the first to third banks BK1-3 shown in FIG. 1 are exposed. The first to third banks BK1-3 may have the same shape and size as those of the first to third anode electrodes AE1-3.

[0095] In the second unit pixel 114 as the narrow angle area NAA, the first sub-pixel 2SP1 may include at least one red (R) sub-sub-pixel 2SP1-1. For example, the first sub-pixel 2SP1 may be composed of three red (R) sub-sub-pixels 2SP1-1. The three sub-sub-pixels 2SP1-1 may be arranged sequentially in the vertical direction.

[0096] In this regard, the three sub-pixels 2SP1-1 may receive data power from the second-first anode electrode AE2-1 via the second-first contact hole CH2-1. The second-first anode electrode AE2-1 may be implemented as a metal film having a rectangular shape surrounding the three sub-pixels 2SP1-1. The three sub-pixels 2SP1-1 may be connected to the second-first anode electrode AE2-1 through the second-first contact hole CH2-1. Figure 2B Three second-first openings OP2-1 of the same size and shape defined in the second-first bank BK2-1 shown in FIG. 1 are exposed. The second-first bank BK2-1 may have the same shape and size as those of the second-first anode electrode AE2-1.

[0097] In the second unit pixel 114 as the narrow angle area NAA, the second sub-pixel 2SP2 may include at least one green (G) sub-sub-pixel 2SP2-1. For example, the second sub-pixel 2SP2 may be composed of 6 green (G) sub-sub-pixels 2SP2-1. The 6 sub-sub-pixels 2SP2-1 may be composed of 3 sub-sub-pixels 2SP2-1 arranged in an upper triangle shape and 3 sub-sub-pixels 2SP2-1 arranged in a lower triangle shape.

[0098] In this regard, the six sub-pixels 2SP2-1 may receive data power from the second-second anode electrode AE2-2 via the second-second contact hole CH2-2. The second-second anode electrode AE2-2 may be implemented as a metal film surrounding the three sub-pixels 2SP2-1 arranged in the upper triangle shape and the three sub-pixels 2SP2-1 arranged in the lower triangle shape. The six sub-pixels 2SP2-1 may be respectively connected to the second-second anode electrode AE2-2 as shown in FIG. Figure 2B Six second-second openings OP2-2 of the same size and shape defined in the second-second bank BK2-2 shown in FIG. 1 are exposed. The second-second bank BK2-2 may have the same shape and size as those of the second-second anode electrode AE2-2.

[0099] In the second unit pixel 114 as the narrow angle area NAA, the third sub-pixel 2SP3 may include at least one blue (B) color sub-sub-pixel 2SP3-1. For example, the third sub-pixel 2SP3 may be composed of three blue (B) sub-sub-pixels 2SP3-1. The three sub-sub-pixels 2SP3-1 may be arranged continuously in the vertical direction.

[0100] In this regard, the three sub-pixels 2SP3-1 may receive data power from the second to third anode electrodes AE2-3 via the second to third contact holes CH2-3. The second to third anode electrodes AE2-3 may be implemented as a rectangular metal film surrounding the three sub-pixels 2SP3-1. The three sub-pixels 2SP3-1 may be connected to the second to third anode electrodes AE2-3 through the second to third contact holes CH2-3. Figure 2B The three second to third openings OP2-3 of the same size and shape defined in the second to third banks BK2-3 shown in FIG. 2 are exposed. The second to third banks BK2-3 may have the same shape and size as those of the second to third anode electrodes AE2-3.

[0101] One first lens Lzl of the first lens array 120 may be disposed in the wide angle area WAA, or at least two first lenses Lzl of the first lens array 120 may be disposed in the wide angle area WAA.

[0102] The first lens Lz1 may be a semi-cylindrical lens having a rectangular bottom.

[0103] When the first lens array 120 includes one first lens Lz1, one first lens Lz1 may be disposed to cover one unit pixel 112 or at least one sub-pixel SP. In this regard, one sub-pixel 1SP1 may include at least one sub-sub-pixel 1SP1-1.

[0104] When the first lens array 120 includes at least two first lenses Lz1, the at least two first lenses Lz1 may have the same shape and the same size as each other and be disposed in the wide angle area WAA.

[0105] At least two first lenses Lz1 may have the same shape and different sizes and be disposed in the wide angle area WAA.

[0106] One first lens Lz1 may be disposed on a top surface of at least one sub-pixel SP to cover at least one sub-pixel SP in the wide-angle area WAA.

[0107] For example, Figure 2A As shown in FIG. 1 , in the first unit pixel 112 as the wide-angle area WAA, the first lens Lz1 may be disposed to cover the first subpixel 1SP1 of red (R), the second subpixel 1SP2 of green (G), and the third subpixel 1SP3 of blue (B).

[0108] Each of the at least three sub-pixels may include a plurality of sub-sub-pixels. The at least three sub-pixels may include a first sub-pixel 1SP1, a second sub-pixel 1SP2, and a third sub-pixel 1SP3 that emit different colors. The third sub-pixel may have a larger number of sub-sub-pixels than each of the first sub-pixel and the second sub-pixel may have.

[0109] In addition, if Figure 2A As shown in the figure, in the first unit pixel 112, a first lens Lzl can be set on the top surface of and cover the following items: a sub-sub-pixel 1SP1-1 of the first sub-pixel 1SP1, three sub-sub-pixels 1SP2-1 of the second sub-pixel 1SP2, and a sub-sub-pixel 1SP3-1 of the third sub-pixel 1SP3.

[0110] In addition, if Figure 2A As shown in the figure, in the first unit pixel 112, a first lens Lz1 can be disposed on the top surface of and cover the following items: a sub-subpixel 1SP1-1 of the first subpixel 1SP1 of red (R), a sub-subpixel 1SP3-1 of the third subpixel 1SP3 of blue (B).

[0111] At least one second lens Lz2 of the second lens array 120 may be disposed in the narrow angle area NAA.

[0112] The second lens Lz2 may be a hemispherical lens having a circular bottom.

[0113] One second lens Lz2 of the at least one second lens Lz2 may be disposed to cover one sub-pixel SP.

[0114] When one sub-pixel SP is composed of at least one sub-pixel 2SP1 - 1 , 2SP2 - 1 , 2SP3 - 1 , one second lens Lz2 may cover only one sub-pixel 2SP1 - 1 .

[0115] Therefore, the three second lenses Lz2 may cover the three sub-sub-pixels 2SP1-1, 2SP2-1, and 2SP3-1, respectively. That is, each second lens Lz2 may cover each of the sub-sub-pixels 2SP1-1, 2SP2-1, and 2SP3-1 constituting one sub-pixel 2SP1.

[0116] At least one second lens Lz2 in the narrow angle area NAA may have the same shape, the same size, and the same thickness (vertical dimension).

[0117] Each second lens Lz2 may be individually formed on each of the plurality of sub-sub-pixels in the narrow angle area NAA.

[0118] Each second lens Lz2 may be individually disposed on the top surface of each sub-pixel SP to cover only each sub-pixel SP in the narrow angle area NAA.

[0119] The second lens Lz2 may have a bottom surface having an area greater than a light emitting area of ​​each sub-subpixel.

[0120] At least one of the first subpixel 2SP1 of the first color (R), the second subpixel 2SP2 of the second color (G), the third subpixel 2SP3 of the third color (B), and the fourth subpixel 2SP4 of the fourth color (W) may be disposed in the narrow angle area NAA. Alternatively, at least one subpixel SP of the first subpixel 2SP1 of the first color (R), the second subpixel 2SP2 of the second color (G), the third subpixel 2SP3 of the third color (B), and the fourth subpixel 2SP4 of the fourth color (W) may be arranged according to a combination thereof.

[0121] Each of the at least one second lens Lz2 may individually cover each of the sub-pixels SP of the first color (R), the sub-pixels SP of the second color (G), the sub-pixels SP of the third color (B), and the sub-pixels SP of the fourth color (W). Alternatively, each of the at least one second lens Lz2 may individually cover each sub-pixel.

[0122] The first lens Lz1 and the second lens Lz2 may have different shapes and different sizes.

[0123] Each of the first lens Lz1 and the second lens Lz2 may be implemented as a concave lens or a convex lens according to a refractive index.

[0124] The refractive index of each of the first lens Lz1 and the second lens Lz2 may be determined according to the shape and thickness (vertical size) thereof.

[0125] Figure 3 is a view illustrating a shape and a cutoff direction of each of a first lens and a second lens disposed on a unit pixel of a display panel according to an embodiment of the present disclosure.

[0126] Reference Figure 3 , in the unit pixel 110 according to an embodiment of the present disclosure, the first lens Lz1 may be a semi-cylindrical lens, and the second lens Lz2 may be a hemispherical lens.

[0127] The first lens Lz1 and the second lens Lz2 may have different shapes and different sizes.

[0128] The first lens Lz1 and the second lens Lz2 may have different shapes and different sizes, but may have the same thickness (vertical dimension).

[0129] The first lens Lz1 and the second lens Lz2 may have different shapes, different sizes, and different thicknesses or vertical dimensions.

[0130] The first lens Lz1 may have a semi-cylindrical shape having a rectangular bottom surface. Therefore, the light emission direction of the first lens Lz1 may be cut off in the yy' direction (vertical direction) and may not be cut off in the xx' direction (horizontal direction).

[0131] That is, since the first lens Lz1 has a length exceeding the width of one sub-pixel SP in the x-axis direction, the first lens is not cut in the x-x' direction (horizontal direction). The first lens has a curvature, and its width in the x-x' direction decreases as it extends upward along the z-axis. Therefore, the first lens is cut in the y-y' direction (vertical direction).

[0132] The second lens Lz2 is a hemispherical type having a circular bottom surface. The second lens has a curvature, and its width in each of the x-x' direction (horizontal direction) and the y-y' direction (vertical direction) becomes smaller as it extends upward along the z-axis.

[0133] Therefore, the light emission direction may be cut off by the width of one sub-pixel SP from the circular bottom surface in all x-x' directions (horizontal direction) and y-y' directions (vertical direction). In this regard, one sub-pixel SP covered with one second lens Lz2 may mean one sub-sub-pixel 2SP1-1 covered with one second lens Lz2 having a hemispherical shape, or may mean one sub-pixel 2SP1 consisting of only one sub-sub-pixel 2SP1-1. The same applies to the following description.

[0134] As described above, the size of each of one sub-pixel SP, the first lens Lz1, and the second lens Lz2 may vary according to the optical output cut-off angle.

[0135] In addition, the size of each of one sub-pixel SP, the first lens Lz1, and the second lens Lz2 may vary according to light efficiency and light concentration of one sub-pixel SP.

[0136] Figures 4 to 8 is a view showing an example in which a first lens array consists of at least two first lenses in a wide-angle region of a display panel according to an embodiment of the present disclosure.

[0137] Reference Figure 4 According to an embodiment of the present disclosure, the first lens array 120 may be disposed in the wide-angle area WAA in the unit pixel 110 of the display panel 10, and may include a first lens Lz1a covering a sub-pixel SP of a first color (R), a first lens Lz1b covering at least one sub-pixel SP of a second color (G), and a first lens Lz1c covering a sub-pixel SP of a third color (B).

[0138] That is, the first lens array 120 according to an embodiment of the present disclosure may include a plurality of first lenses Lz1, wherein one first lens Lz1 may cover one sub-pixel SP or cover at least one sub-pixel SP.

[0139] In this regard, at least one of the sub-pixel SP of the first color (R), the sub-pixel SP of the second color (G), the sub-pixel SP of the third color (B), and the sub-pixel SP of the fourth color (W) may be disposed in the wide-angle area WAA. Alternatively, at least one of the sub-pixel SP of the first color (R), the sub-pixel SP of the second color (G), the sub-pixel SP of the third color (B), and the sub-pixel SP of the fourth color (W) may be arranged in the wide-angle area WAA according to a combination thereof.

[0140] One first lens Lz1 or two or more first lenses Lz1 may cover at least one of the sub-pixel SP of the first color (R), the sub-pixel SP of the second color (G), the sub-pixel SP of the third color (B), and the sub-pixel SP of the fourth color (W) that may be disposed in the wide-angle area WAA. Alternatively, one first lens Lz1 or two or more first lenses Lz1 may cover at least one sub-pixel SP of the sub-pixel SP of the first color (R), the sub-pixel SP of the second color (G), the sub-pixel SP of the third color (B), and the sub-pixel SP of the fourth color (W) that are arranged in the wide-angle area WAA according to a combination thereof.

[0141] Reference Figure 5 According to an embodiment of the present disclosure, the first lens array 120 may include a first lens Lz1d covering one sub-pixel SP of a first color (R) and at least one (e.g., three) sub-pixel SP of a second color (G), and a first lens Lz1c covering a sub-pixel SP of a third color (B).

[0142] That is, the first lens Lz1 may be disposed to cover sub-pixels SP of different colors (R and G) among the sub-pixels SP of the first color (R), the sub-pixels SP of the second color (G), and the sub-pixels SP of the third color (B), or may be disposed to cover only one sub-pixel SP of the third color (B).

[0143] Reference Figure 6 According to an embodiment of the present disclosure, the first lens array 120 may include a first lens Lz1a covering one sub-pixel SP of a first color (R) and a first lens Lz1e covering at least one (e.g., three) sub-pixels SP of a second color (G) and one sub-pixel SP of a third color (B).

[0144] That is, the first lens Lz1 may be disposed to cover only the sub-pixel SP of one color (R) or to cover the sub-pixels SP of different colors (G and B). In this regard, a plurality of sub-pixels SP of one color (G) may exist in the sub-pixels SP of different colors (G and B).

[0145] Reference Figure 7 , the first lens array 120 according to an embodiment of the present disclosure may include a first lens Lz1f covering one sub-pixel SP of a first color (R) and one sub-pixel SP of a third color (B).

[0146] That is, the first lens Lz1 may be disposed to cover sub-pixels SP of different colors (G and B) that are spaced apart from each other.

[0147] Reference Figure 8According to an embodiment of the present disclosure, the first lens array 120 may include a first lens Lz1g covering a sub-pixel SP of a first color (R) and a sub-pixel SP of a second color (G), and a first lens Lz1h covering a sub-pixel SP of a second color (G) and a sub-pixel SP of a third color (B).

[0148] That is, the first lens Lz1 may include two lenses that may respectively cover two combinations of sub-pixels SP of two different colors. In this regard, the two combinations of two different colors may be different from each other.

[0149] Fig. 9 is an edge display device according to an embodiment of the present disclosure Figure 1 A cross-sectional view of a unit pixel cut along the I-I' line.

[0150] Reference Fig. 9 , the unit pixel 110 of the display panel 10 according to the embodiment of the present disclosure may include a wide-angle area WAA and a narrow-angle area NAA.

[0151] The unit pixel 110 may include at least one sub-pixel SP.

[0152] At least one sub-pixel SP may include: a first anode electrode layer AE1 in the wide-angle area WAA; a second anode electrode layer AE2 in the narrow-angle area NAA; a first light-emitting layer OLED1 and a second light-emitting layer OLED2 on the first anode electrode layer AE1 and the second anode electrode layer AE2, respectively; and a cathode electrode layer CE on both the first light-emitting layer OLED1 and the second light-emitting layer OLED2. In addition, at least one sub-pixel SP may include: a first barrier layer BM1 on the cathode electrode layer CE; a first insulating layer Encap on the first barrier layer; a second barrier layer BM2 on the first insulating layer; a first gap-filling layer GF1 on the second barrier layer; a first lens Lz1 on the first gap-filling layer and in the wide-angle area; a second lens Lz2 on the first gap-filling layer and in the narrow-angle area; and a second gap-filling layer GF2 on both the first lens and the second lens. In this regard, each of the first barrier layer and the second barrier layer may be open in each of a region overlapping with the first anode electrode layer and a region overlapping with the second anode electrode layer.

[0153] The wide-angle area WAA may include: a first anode electrode layer AE1; a first light-emitting layer OLED1 on the first anode electrode layer; a cathode electrode layer CE on the first light-emitting layer; a first barrier layer BM1 having an opening defined therein and disposed on the cathode electrode layer; a first insulating layer Encap on the first barrier layer; a second barrier layer BM2 having an opening defined therein and disposed on the first insulating layer; a first gap-filling layer GF1 on the second barrier layer; a first lens Lz1 on the first gap-filling layer; and a second gap-filling layer GF2 on the first lens.

[0154] In this regard, the opening OP of the first barrier layer BM1 and the opening OP of the second barrier layer BM2 may have the same size and the same thickness.

[0155] The first and second barrier layers BM1 and BM2 may, for example, prevent light from being incident on the active layer ACT of the driving thin film transistor Tdr to prevent leakage current from being generated.

[0156] The narrow angle area NAA may include: a second anode electrode layer AE2; a second light-emitting layer OLED2 on the second anode electrode layer; a cathode electrode layer CE on the second light-emitting layer; a first barrier layer BM1 having an opening defined therein and disposed on the cathode electrode layer; a first insulating layer Encap on the first barrier layer; a second barrier layer BM2 having an opening defined therein and disposed on the first insulating layer; a first gap filling layer GF1 on the second barrier layer; a second lens Lz2 on the first gap filling layer; and a second gap filling layer GF2 on the second lens.

[0157] In this regard, the opening OP of the first barrier layer BM1 and the opening OP of the second barrier layer BM2 may have the same size and the same thickness.

[0158] The first anode electrode layer AE1 of the wide angle area WAA and the second anode electrode layer AE2 of the narrow angle area NAA may constitute the same layer, may be made of the same material, may have the same thickness, and may be formed using the same process. The first anode electrode layer AE1 and the second anode electrode layer AE2 may be formed by a mask process using a photoresist (PR).

[0159] The first light-emitting layer OLED1 of the wide-angle area WAA and the second light-emitting layer OLED2 of the narrow-angle area NAA may constitute the same layer, may be made of the same material, may have the same thickness, may be formed using the same process, and may present the same color.

[0160] Each of the first and second light emitting layers OLED1 and OLED2 may include a hole injection layer HIL, a hole transport layer HTL, a light emitting material layer EML, an electron transport layer ETL, and an electron injection layer EIL.

[0161] The first gap-filling layer GF1 of the wide-angle area WAA and the first gap-filling layer GF1 of the narrow-angle area NAA may constitute the same layer, may be made of the same material, may have the same thickness, and may be formed using the same process.

[0162] The distance between the first light emitting layer OLED1 and the first lens Lz1 can be adjusted based on the thickness (vertical dimension) of the first gap filling layer GF1. In addition, the distance between the second light emitting layer OLED2 and the second lens Lz2 can be adjusted based on the thickness (vertical dimension) of the first gap filling layer GF1.

[0163] The first gap-filling layer GF1 may be made of one or a combination of acrylic, epoxy, and silicon. In addition, the first gap-filling layer GF1 may be made of an organic material.

[0164] The particle size in the first gap-filling layer GF1 may be equal to the wavelength of light, or may be larger or smaller than the wavelength of light by a certain range. The first gap-filling layer GF1 may have a forward diffusion characteristic based on one of particle density, particle size, and particle shape.

[0165] In this regard, the first gap filling layer GF1 may have a refractive index smaller than that of the first insulating layer Encap. That is, the first gap filling layer GF1 may have a refractive index smaller than that of the first insulating layer Encap due to one of particle density, particle size, and particle shape.

[0166] The material of the first insulating layer Encap may be one of TiO 2 , Al 2 O 3 and SiO 2 .

[0167] In this regard, when the material of the first insulating layer Encap is TiO2, the first insulating layer Encap may have a refractive index in the range of 2.6 to 2.9. When the material of the first insulating layer Encap is Al2O3, the first insulating layer Encap may have a refractive index in the range of 1.75 to 1.76. When the material of the first insulating layer Encap is SiO2, the first insulating layer Encap may have a refractive index in the range of 1.40 to 1.55.

[0168] The first lens Lz1 of the wide angle area WAA and the second lens Lz2 of the narrow angle area NAA may constitute the same layer, may be made of the same material, may have the same thickness, and may be formed using the same process. However, the first lens Lz1 of the wide angle area WAA and the second lens Lz2 of the narrow angle area NAA may be formed to have different shapes and different sizes.

[0169] The refractive indices of the layers of the wide angle area WAA and the narrow angle area NAA may be similar to each other.

[0170] In the wide angle area WAA and the narrow angle area NAA, the cathode electrode CE may be disposed on the second gap filling layer GF2. The cathode electrode CE may be made of at least one selected from a group of conductive metals including an opaque metal material, for example, aluminum (Al), tungsten (W), copper (Cu), molybdenum (Mo), chromium (Cr), tantalum (Ta), titanium (Ti), alloys thereof, and combinations thereof. However, the present disclosure is not limited thereto.

[0171] Each refractive index of the first lens Lz1 and the second lens Lz2 may be determined according to the shape of each of the first lens and the second lens and the thickness (vertical size) of the first gap-filling layer GF1.

[0172] Fig.10 is a diagram illustrating a size and illuminance efficiency of each of a first lens in a wide angle region and a second lens in a narrow angle region in a display panel according to an embodiment of the present disclosure.

[0173] Reference Fig.10 , the first lens Lz1 provided in the wide angle area WAA in the unit pixel 110 according to an embodiment of the present disclosure may be a semi-cylindrical lens, the width of the bottom of the semi-cylindrical lens may be 14 μm and the thickness (vertical dimension) thereof may be 4 μm. The curvature of the lens may be optimized by adjusting the shape of the lens according to the shape of the pixel.

[0174] In this regard, along the rectangular bottom shape of the first lens Lzl, the pixel size may be 8.5 μm in the x-axis direction and may be 95.1 μm in the y-axis direction.

[0175] In the wide-angle area WAA of the unit pixel 110 , for example, the thickness (vertical dimension) of each of the layers may be 10 μm, and the refractive index n thereof may be 1.5.

[0176] The first light emitting layer OLED1 may have a bottom width of 8.5 μm, a vertical dimension of 10 μm or less, and a refractive index n of 1.5.

[0177] The first barrier layer BM1 disposed on the first light emitting layer OLED1 may have an opening OP defined therein. The size of the opening OP may be 10 μm, which is greater than the minimum bottom width of the first light emitting layer OLED1 of 8.5 μm.

[0178] The first gap-filling layer GF1 disposed on the first barrier layer BM1 may have a thickness (vertical dimension) of 10 μm and a refractive index n of 1.5.

[0179] The first lens Lz1 disposed on the first gap-filling layer GF1 may have a vertical size of 4 μm. The layer in which the first lens Lz1 is disposed may have a refractive index n of 1.44 to 1.64.

[0180] The first lens Lz1 disposed in the wide angle area WAA in the unit pixel 110 may operate in an LCF (Light Control Film) mode.

[0181] Therefore, it can be found that, in the wide-angle area WAA of the unit pixel 110, the illuminance efficiency in the case where the first lens Lz1 exists can be 165% of the illuminance efficiency in the case where the lens does not exist.

[0182] In this regard, when the light amount L of the pixel disposed under the first lens Lz1 is 10%, the cutoff angle of the first lens Lz1 may be set to ±30°.

[0183] In one example, the size of the pixel set in the narrow angle area NAA in the unit pixel 110 according to an embodiment of the present disclosure may be 8.5 μm in diameter, and the thickness (vertical dimension) of the second light emitting layer OLED2 may be 10 μm. The refractive index n of the second light emitting layer OLED2 may be set to 1.5.

[0184] The second barrier layer BM2 on the second light emitting layer OLED2 may have an opening OP defined therein. The size of the opening OP may be 10 μm, which is larger than the minimum bottom width of the second light emitting layer OLED2 of 8.5 μm.

[0185] The first gap-filling layer GF1 disposed on the second barrier layer BM2 may have a thickness (vertical dimension) of 10 μm and a refractive index n of 1.5.

[0186] The second lens Lz2 disposed on the first gap-filling layer GF1 may be a hemispherical lens, a diameter of a circular bottom of the hemispherical lens may be 16.5 μm, which is larger than a pixel diameter of 8.5 μm, and a vertical size of the hemispherical lens may be 6.5 μm.

[0187] The layer in which second lens Lz2 is disposed may have a thickness (vertical dimension) of 10 μm, which is greater than the thickness (vertical dimension) of second lens Lz2 of 6.5 μm.

[0188] In the narrow angle area NAA of the unit pixel 110 , for example, the thickness (vertical dimension) of each layer may be 10 μm, and the refractive index n of each layer may be 1.5.

[0189] The second lens Lz2 disposed in the narrow angle area NAA of the unit pixel 110 may operate in the SPM mode.

[0190] Therefore, it can be determined that, in the wide-angle area WAA of the unit pixel 110 , the illuminance efficiency in the case where the second lens Lz2 exists may be 327% of the illuminance efficiency in the case where the lens does not exist.

[0191] In this regard, when the light amount L of the pixel disposed under the second lens is 10%, the cutoff angle of the second lens Lz2 may be set to ±30°.

[0192] Fig.11 is a view showing an example in which each of the first lens and the second lens according to an embodiment of the present disclosure outputs an image while cutting off light in each of a wide-angle region and a narrow-angle region in a display panel.

[0193] Reference Fig.11 , the first lens Lz1 disposed in the wide angle area WAA in the unit pixel 110 according to an embodiment of the present disclosure may be a semi-cylindrical lens, and thus may cut off light emitted from the sub-pixel SP in the yy′ direction.

[0194] Therefore, the first lens Lzl can cut off the light output from the sub-pixels SP of the first color (R), the sub-pixels SP of the second color (G), the sub-pixels SP of the third color (B), and the sub-pixels SP of the fourth color (W) arranged in the wide-angle area WAA, and thus can be used as a light control film (LCF) in the normal mode.

[0195] In addition, since the second lens Lz2 disposed in the narrow angle area NAA in the unit pixel 110 according to an embodiment of the present disclosure is a hemispherical lens, the second lens may cut off light emitted from the sub-pixel SP in the xx′ and yy′ directions.

[0196] Therefore, the second lens Lz2 may cut off light output from the sub-pixels SP of the first color (R), the sub-pixels SP of the second color (G), the sub-pixels SP of the third color (B), and the sub-pixels SP of the fourth color (W) arranged in the narrow angle area NAA, and thus may operate in the SPM mode.

[0197] Fig.12 An example of a pixel circuit configuration of a unit pixel of a display panel according to an embodiment of the present disclosure is shown. Fig.13 Shown is the drive Fig.12 The timing of the control signal of the pixel circuit.

[0198] Reference Fig.12 and Fig.13 , the pixel PXL in the unit pixel 110 according to an embodiment of the present disclosure may include a first light emitting diode OLED1 , a second light emitting diode OLED2 , a driving transistor Tdr, and an internal compensation circuit.

[0199] In this regard, the first light emitting diode OLED1 may be disposed in the wide angle area WAA. The second light emitting diode OLED2 may be disposed in the narrow angle area NAA. The first lens Lz1 may be disposed on the first light emitting diode OLED1. The second lens Lz2 may be disposed on the second light emitting diode OLED2.

[0200] Each of the transistors T1 to T7 and Tdr included in the pixel PXL can be implemented as a PMOS type LTPS (low temperature polysilicon) TFT, and thus the required response characteristics can be ensured. For example, at least one of the switching transistors T1 to T7 can be implemented as an NMOS type or PMOS type oxide TFT having good leakage current characteristics when turned off, and each of the remaining transistors can be implemented as a PMOS type LTPS TFT having good response characteristics.

[0201] The unit pixel 110 may include at least one sub-pixel SP. The at least one sub-pixel SP may further include: a first transistor T1 connected to the data line Data; a driving transistor Tdr connected to the driving power ELVDD; a fourth transistor T4, which is disposed between the driving transistor and the first anode electrode layer AE1-1 and connected to the driving transistor and the first anode electrode layer AE1-1, and can be switched based on the first light emission control signal EM2; and a sixth transistor T6, which is disposed between the driving transistor and the second anode electrode layer AE2-1 and connected to the driving transistor and the second anode electrode layer AE2-1, and can be switched based on the second light emission control signal EM3. At least one sub-pixel SP may share the same data line Data and the same driving transistor Tdr.

[0202] In this regard, the first transistor T1 is referred to as a “first switching transistor T1 ”, the fourth transistor T4 is referred to as a “first light emission control thin film transistor T4 ”, and the sixth transistor T6 is referred to as a “second light emission control thin film transistor T6 ”.

[0203] In addition, the first to seventh transistors T1 to T7 may be referred to as first to seventh switching transistors T1 to T7, respectively.

[0204] Each of the first and second light emitting diodes OLED1 and OLED2 may emit light based on an amount of current adjusted according to a voltage Vgs between the gate and source of the driving transistor Tdr.

[0205] The first light emitting diode OLED1 may be connected to the driving transistor Tdr through the first light emission control thin film transistor T4, and the second light emitting diode OLED2 may be connected to the driving transistor Tdr through the second light emission control thin film transistor T6.

[0206] A gate electrode of the first emission control thin film transistor T4 may be connected to the first emission control signal applying line EM2. One of the first and second electrodes of the first emission control thin film transistor T4 may be connected to the driving transistor Tdr, and the other electrode of the first emission control thin film transistor T4 may be connected to the first light emitting diode OLED1.

[0207] A gate electrode of the second emission control thin film transistor T6 may be connected to the second emission control signal applying line EM3, one of the first and second electrodes of the second emission control thin film transistor T6 may be connected to the driving transistor Tdr, and the other electrode of the second emission control thin film transistor T6 may be connected to the second light emitting diode OLED2.

[0208] The first anode electrode AE1-1 of the first light emitting diode OLED1 may be connected to the first electrode or the second electrode of the first light emitting control thin film transistor T4. The cathode electrode of the first light emitting diode OLED1 may be connected to the low potential power voltage VSS. For example, the first light emitting diode OLED1 may receive power through the first anode electrode AE1-1. The organic compound layer as the first light emitting layer OLED1 may be disposed between the anode electrode and the cathode electrode.

[0209] The second anode electrode AE2-1 of the second light emitting diode OLED2 may be connected to the first electrode or the second electrode of the second light emitting control thin film transistor T6. The cathode electrode of the second light emitting diode OLED2 may be connected to the low potential power voltage VSS. For example, the second light emitting diode OLED2 may receive power through the second anode electrode AE2-1. The organic compound layer as the second light emitting layer OLED2 may be disposed between the anode electrode and the cathode electrode.

[0210] The organic compound layer may include a hole injection layer HIL, a hole transport layer HTL, a light emitting material layer EML, an electron transport layer ETL, and an electron injection layer EIL. However, the present disclosure is not limited thereto. For example, two or more organic compound layers emitting different colors may be stacked according to a series structure. When current flows in the first light emitting layer OLED1 or the second light emitting layer OLED2, holes passing through the hole transport layer HTL and electrons passing through the electron transport layer ETL move to the first light emitting layer OLED1 or the second light emitting layer OLED2 where excitons may be generated. As a result, the first light emitting layer OLED1 or the second light emitting layer OLED2 may emit visible light.

[0211] The driving transistor Tdr controls the current flowing through the first light-emitting layer OLED1 or the second light-emitting layer OLED2 according to the voltage Vgs between its gate and source. The gate electrode of the driving transistor Tdr can be connected to the node P2, one of its first electrode and the second electrode can be connected to the first power line for providing the high potential power voltage ELVDD, and the other electrode can be connected to the node P3. The source electrode of the driving transistor Tdr can be connected to the first power line and the drain electrode can be connected to the node P3. In addition, the drain electrode of the driving transistor Tdr can be connected to the first power line and the source electrode can be connected to the node P3. The voltage Vgs between the gate and the source of the driving transistor Tdr can be the voltage applied to the nodes P2 and P3.

[0212] The compensation circuit is configured to sample the voltage Vgs between the gate and the source of the driving transistor Tdr so as to compensate for the threshold voltage variation of the driving transistor Tdr, and may include first to seventh switching transistors T1 to T7 and a storage capacitor Cst. The remaining elements of the first to seventh switching transistors T1 to T7 and the storage capacitor Cst except the first switching transistor T1 for applying the data voltage Vdata of the data line 14 may constitute the compensation circuit.

[0213] The first switching transistor T1 may be connected to and disposed between the data line Data and the node P1, and may be switched based on the first scan signal SCAN1. A gate electrode of the first switching transistor T1 may be connected to the first gate line 15a to which the first scan signal SCAN1 is applied. One of the first electrode and the second electrode of the first switching transistor T1 may be connected to the data line 14, and the other electrode thereof may be connected to the node P1.

[0214] The second switching transistor T2 can be connected to the node P2 and the node P3 and arranged between the node P2 and the node P3, and can be switched based on the second scan signal SCAN2. The gate electrode of the second switching transistor T2 can be connected to the second gate line 15b to which the second scan signal SCAN2 is applied. One of the first electrode and the second electrode of the second switching transistor T2 can be connected to the node P3 and the other electrode thereof can be connected to the node P2.

[0215] Since one electrode of the second switch transistor T2 can be connected to the gate electrode of the driving transistor Tdr, the off-current characteristic of the second switch transistor T2 should be good. Therefore, the second switch transistor T2 can be designed to have a double gate structure to suppress leakage current when turned off.

[0216] In the dual-gate structure, the first gate electrode and the second gate electrode are connected to each other to have the same potential, and the channel length is greater than the channel length of the single-gate structure. As the channel length increases, the resistance during the cut-off period increases and the leakage current decreases, thereby ensuring the stability of the operation. However, the second switch transistor T2 can be implemented as a single-gate structure. In this case, the second switch transistor T2 can be implemented as an oxide TFT.

[0217] The third switch transistor T3 can be connected to the node P1 and a reference line to which a reference voltage Vref is applied and is disposed between the node P1 and the reference line, and can be switched based on the light emitting signal EM1. The gate electrode of the third switch transistor T3 can be connected to the third gate line 15c to which the light emitting signal EM1 is applied. One of the first electrode and the second electrode of the third switch transistor T3 can be connected to the node P1 and the other of the first electrode and the second electrode of the third switch transistor T3 can be connected to the reference line.

[0218] The fourth switching transistor T4 may be used as a first light emission control thin film transistor T4 which switches the light emission operation of the first light emitting diode OLED1 disposed in the wide angle area WAA.

[0219] The fourth switch transistor T4 may be connected to the node P6 connected to the driving transistor Tdr and the anode electrode of the first light emitting diode OLED1 and disposed between the node P6 and the anode electrode of the first light emitting diode OLED1, and may be switched based on the first light emitting control signal EM2. The gate electrode of the fourth switch transistor T4 may be connected to the first light emitting control signal applying line EM2 to which the first light emitting control signal EM2 is applied. One of the first electrode and the second electrode of the fourth switch transistor T4 may be connected to the node P6, and the other of the first electrode and the second electrode of the fourth switch transistor T4 may be connected to the anode electrode of the first light emitting diode OLED1.

[0220] The fifth switch transistor T5 can be connected to the reference line and the node P8 as the connection point between the fourth switch transistor T4 and the first light emitting diode OLED1 and is disposed between the reference line and the node P8, and can be switched based on the second scan signal SCAN2. The gate electrode of the fifth switch transistor T5 can be connected to the second gate line 15b to which the second scan signal SCAN2 is applied. One of the first electrode and the second electrode of the fifth switch transistor T5 can be connected to the node P8, and the other of the first electrode and the second electrode of the fifth switch transistor T5 can be connected to the reference line.

[0221] The sixth switching transistor T6 functions as a second light emission control thin film transistor T6 which switches the light emission operation of the second light emitting diode OLED2 disposed in the narrow angle area NAA.

[0222] The sixth switch transistor T6 may be connected to the node P6 connected to the driving transistor Tdr and the anode electrode of the second light emitting diode OLED2 and disposed between the node P6 and the anode electrode of the second light emitting diode OLED2, and may be switched based on the second light emitting control signal EM3. The gate electrode of the sixth switch transistor T6 may be connected to the second light emitting control signal applying line EM3 to which the second light emitting control signal EM3 is applied. One of the first electrode and the second electrode of the sixth switch transistor T6 may be connected to the node P6, and the other of the first electrode and the second electrode of the sixth switch transistor T6 may be connected to the anode electrode of the second light emitting diode OLED2.

[0223] The seventh switching transistor T7 may be connected to a node P9 as a connection point between the sixth switching transistor T6 and the second light emitting diode OLED2 and a reference line and disposed between the node P9 and the reference line, and may be switched based on the second scan signal SCAN2. A gate electrode of the seventh switching transistor T7 may be connected to a second gate line 15b to which the second scan signal SCAN2 is applied. One of the first electrode and the second electrode of the seventh switching transistor T7 may be connected to the node P9, and the other of the first electrode and the second electrode of the seventh switching transistor T7 may be connected to the reference line.

[0224] The storage capacitor Cst may be connected to the node P1 and the node P2 and disposed between the node P1 and the node P2 .

[0225] Reference Fig.13 Each pixel PXL may operate in an initialization period Initial, a sensing and initialization period Sensing&Initial, a holding period th, and an emission period Emission. In this regard, the sensing and initialization period may be referred to as a "programming period".

[0226] In the initialization period Initial, the second scan signal SCAN2 and the light emitting signal EM1 may be input as the gate low voltage VGL as a turn-on level. The first scan signal SCAN1 may be input as the gate high voltage VGH as a turn-off level.

[0227] In addition, in the initialization period Initial, the first light emitting control signal EM2 may be input as a gate low voltage VGL as a turn-on level, and the second light emitting control signal EM3 may be input as a gate high voltage VGH as a turn-off level.

[0228] In the sensing and initialization period Sensing&Initial, each of the first scan signal SCAN1 and the second scan signal SCAN2 may be input as a gate low voltage VGL as a turn-on level, and the emission signal EM1 may be input as a gate high voltage VGH as a turn-off level.

[0229] In addition, in the sensing and initialization period Sensing&Initial, each of the first and second light emitting control signals EM2 and EM3 may be input as a gate high voltage VGH as a turn-off level.

[0230] In the holding period th, each of the first and second scan signals SCAN1 and SCAN2 and the light emitting signal EM1 may be input as the gate high voltage VGH as a turn-off level. Each of the first and second light emitting control signals EM2 and EM3 may maintain a gate high voltage VGH state.

[0231] In the emission period Emission, each of the first scan signal SCAN1 and the second scan signal SCAN2 may be input as a gate high voltage VGH as a turn-off level. The emission signal EM1 may be input as a gate low voltage VGL as a turn-on level.

[0232] In addition, in the light emission period Emission, the first light emission control signal EM2 may be input as a gate low voltage VGL as a turn-on level, and the second light emission control signal EM3 may be input as a gate high voltage VGH as a turn-off level.

[0233] Therefore, the first emission control thin film transistor T4 can be turned on, and the second emission control thin film transistor T6 can be turned off. That is, when the first emission control thin film transistor T4 disposed in the wide angle area WAA is turned on, the second emission control thin film transistor T6 disposed in the narrow angle area NAA can be turned off.

[0234] The initialization period Initial, the sensing and initialization period Sensing&Initial, and the holding period th may be completed within 1 horizontal period 1H. 1 horizontal period 1H may be a duration allocated to initialization, programming, and holding operations of the display lines.

[0235] exist Fig.13 In the example, the initialization period Initial may be set to be equal to or shorter than 1 horizontal period 1H. The sensing and initialization period Sensing&Initial may be set to be equal to or shorter than 1 horizontal period 1H. In this case, the first scan signal SCAN1 may be set to be equal to or shorter than 2 horizontal periods. Fig.13 In the embodiment, the holding period th can be set to be equal to or shorter than 1 horizontal period.

[0236] In the initialization period Initial, the second switching transistor T2 and the fifth switching transistor T5 may be turned on in response to the second scan signal SCAN2 of the turn-on level ON. In response to the light emitting signal EM1 of the turn-on level ON, the third switching transistor T3 may be turned on. The fourth switching transistor T4 may be turned on in response to the first light emitting control signal EM2 of the turn-on level ON. As a result, all nodes P1, P2, P3, and P6 may be initialized to the reference voltage Vref. The initialization operation is intended to reset the potentials of the nodes P1, P2, P3, and P6 to a constant value before the programming operation to increase the reliability of the internal compensation.

[0237] The reference voltage Vref is set closer to the low potential power voltage VSS, so that the reference voltage Vref is lower than the high potential power voltage EVDD and lower than the operating point voltage Voled of each of the first light emitting diode OLED1 and the second light emitting diode OLED2. Therefore, in the initialization period Initial, the first light emitting diode OLED1 and the second light emitting diode OLED2 do not emit light.

[0238] In the programming period, that is, in the sensing and initialization period Sensing&Initial, the second scan signal SCAN2 maintains the on level, and the first scan signal SCANl also becomes the on level, so that the first switch transistor T1, the second switch transistor T2 and the fifth switch transistor T5 are turned on, and the light-emitting signal EM1 and the first light-emitting control signal EM2 are inverted to the off level, so that the third switch transistor T3 and the fourth switch transistor T4 are turned off.

[0239] Because the voltage ELVDD-Vref as the gate-source voltage Vgs of the driving transistor Tdr set in the initialization period Initial is greater than the threshold voltage Vth of the driving transistor Tdr, the driving current flows through the driving transistor Tdr in the programming period (that is, the sensing and initialization period Sensing & Initial). In this regard, the gate electrode and the drain electrode of the driving transistor Tdr may be connected to each other due to the on-state of the second switching transistor T2, so that the driving transistor Tdr may be diode-disconnected, and the driving current flows along the diode-disconnected path due to the off-state of the fourth switching transistor T4. The threshold voltage Vth of the driving transistor Tdr may be sampled based on the driving current flowing along the diode-disconnected path and may be stored in nodes P2 and P3.

[0240] In the programming period (ie, the sensing and initialization period), the current flow between the node P1 and the reference line can be prohibited due to the off state of the third switching transistor T3. Then, due to the on state of the first switching transistor T1, the data voltage Vdata output to the data line 14 is applied to the node P1.

[0241] In the programming period (ie, the sensing and initialization period Sensing&Initial), due to the turn-on state of the fifth switching transistor T5 , the reference voltage Vref may be continuously applied to the node P8 , and the OLED does not emit light.

[0242] In the programming period Sensing & Initial, the potential of the node P1 may be set to the data voltage Vdata, the potentials of the nodes P2 and P3 may be set to ELVDD-1Vth1, and the potential of the node P8 may be set to the reference voltage Vref.

[0243] In the holding period th, the first scan signal SCAN1 and the second scan signal SCAN2 may be inverted from the on level to the off level, so that the first switch transistor T1, the second switch transistor T2, and the fifth switch transistor T5 are turned off. In addition, each of the light emitting signal EM1 and the first light emitting control signal EM2 maintains the off level, so that the third switch transistor T3 and the fourth switch transistor T4 maintain the off state. In the holding period th, due to the off state of the first switch transistor T1 to the fifth switch transistor T5, all nodes from the first node to the third node P1, P2 and P3 and the eighth node P8 are in a floating state.

[0244] The holding period th is intended to allow the inversion timing when the first scan signal SCAN1 and the second scan signal SCAN2 change from the on level to the off level to be before the inversion timing when the light emitting signal EM1 changes from the off level to the on level, thereby increasing the stability of the operation. When the inversion timing associated with the first scan signal SCAN1 and the second scan signal SCAN2 coincides with the inversion timing associated with the light emitting signal EM1, or when the inversion timing associated with the first scan signal SCAN1 and the second scan signal SCAN2 is later than the inversion timing associated with the light emitting signal EM1, the sampling operation of the threshold voltage becomes unstable. Therefore, the holding period th is prepared to prevent this problem. However, the holding period th may be omitted.

[0245] In the emission period Emission, the first scan signal SCAN1 and the second scan signal SCAN2 maintain the off level, so that the first switch transistor T1, the second switch transistor T2 and the fifth switch transistor T5 can be continuously turned off. The emission signal EM1 and the first emission control signal EM2 are inverted to the on level, so that the third switch transistor T3 and the fourth switch transistor T4 are turned on.

[0246] In the light emission period Emission, due to the on-state of the third switching transistor T3 , the reference voltage Vref is applied to the node P1 , so that the potential of the node P1 decreases from the data voltage Vdata to the reference voltage Vref.

[0247] In the light emission period Emission, the node P2 floats and is coupled to the node P1 through the storage capacitor Cst. Therefore, the potential change Vdata-Vref of the node P1 during the light emission period Emission can be applied to the node P2. As a result, during the light emission period Emission, the potential of the node P2 is reduced by Vdata-Vref compared to its EVDD-1Vth1 in the previous holding period th. In other words, during the light emission period Emission, the potential of the node P2 becomes (EVDD-1Vth1-Vdata+Vref).

[0248] Therefore, the gate-source voltage Vgs of the driving transistor Tdr capable of compensating for the variation of the threshold voltage Vth of the driving transistor Tdr can be set. A driving current Ioled corresponding to the gate-source voltage Vgs as expressed by the following Equation 1 flows through the driving transistor Tdr.

[0249] The driving current Ioled may allow the potential of each of the node P3 and the node P8 to increase to the operating point voltage Voled of the first light emitting diode OLED1, thereby turning on the first light emitting diode OLED1. As a result, the first light emitting diode OLED1 emits light based on the driving current Ioled.

[0250] Equation 1

[0251] Ioled=K(Vgs-|Vth|) 2

[0252] =K(EVDD-{EVDD-|Vth|-Vdata+Vref}-|Vth|) 2

[0253] =K(Vdata-Vref) 2

[0254] Here, K represents a constant value determined based on the mobility, channel ratio, and parasitic capacitance of the driving transistor Tdr, and Vth represents the threshold voltage of the driving transistor Tdr.

[0255] As can be seen from the above Equation 1, the driving current Ioled of the first light emitting diode OLED1 is not affected by the high potential power voltage ELVDD and the threshold voltage Vth of the driving transistor Tdr.

[0256] In the present disclosure, scanning signals for pixel initialization and threshold voltage sensing are provided to adjacent display lines for a specific period in an overlapping manner. To this end, a gate driver circuit that can create overlapping scanning signals using a small number of clocks and a simple circuit configuration can be proposed.

[0257] Fig.14 A layout diagram of a first light emission control signal applying line and a second light emission control signal applying line according to an embodiment of the present disclosure is shown.

[0258] Reference Fig.14 In the unit pixel 110 of the display panel 10 according to an embodiment of the present disclosure, the first light emitting control signal applying line EM2 connected to the first light emitting diode OLED1 set in the wide-angle area WAA can be separated from the second light emitting control signal applying line EM3 connected to the second light emitting diode OLED2 set in the narrow-angle area NAA.

[0259] exist Fig.14 In the embodiment, the high potential power voltage applying line VDD, the reference voltage applying line Vref, and the data voltage applying line Vdata may extend in a vertical direction in a plan view, and may be spaced apart from each other at a constant interval in a horizontal direction in a plan view.

[0260] The first light emitting control signal applying line EM2 and the second light emitting control signal applying line EM3 may intersect the high potential power voltage applying line VDD, the reference voltage applying line Vref and the data voltage applying line Vdata, and may extend in the horizontal (left-right) direction, and may be spaced apart from each other at a constant interval in the vertical direction.

[0261] In a plan view, the reference voltage applying line Vref may be disposed on one side (left side) of the driving transistor Tdr, and the data voltage applying line Vdata may be disposed on the opposite side (right side) of the driving transistor Tdr.

[0262] The light emitting signal applying line EM1 may intersect the reference voltage applying line Vref and the data voltage applying line Vdata, and may extend in a horizontal (left-right) direction.

[0263] The light emitting signal applying line EM1 is usually connected to the gate electrodes of the third switching transistor T3 and the fourth switching transistor T4 at the same time. However, in an embodiment of the present disclosure, the light emitting signal applying line EM1 may be connected only to the gate electrode of the third switching transistor T3. A separate first light emitting control signal applying line EM2 may be connected to the gate electrode of the fourth switching transistor T4.

[0264] The first light emission control signal applying line EM2 may be connected to a gate electrode of a first light emission control thin film transistor T4 connected to a first light emitting diode OLED1 disposed in the wide angle area WAA. In this regard, a first anode electrode AE1-1 of the first light emitting diode OLED1 may be electrically connected to a gate electrode of the first light emission control thin film transistor T4 via a first-first contact hole CH1-1.

[0265] The second light emission control signal applying line EM3 may be connected to the gate electrode of the second light emission control thin film transistor T6, which is connected to the second light emitting diode OLED2 disposed in the narrow angle area NAA. In this regard, the second anode electrode AE2-1 of the second light emitting diode OLED2 may be electrically connected to the gate electrode of the second light emission control thin film transistor T6 via the second-first contact hole CH2-1.

[0266] Therefore, the first light emitting diode OLED1 disposed in the wide angle area WAA and the second light emitting diode OLED2 disposed in the narrow angle area NAA perform light emitting operations at different times. Therefore, in order to control these different switching operations, the first light emitting control signal applying line EM2 and the second light emitting control signal applying line EM3 are spaced apart from each other.

[0267] As described above, the first light emission control thin film transistor T4 may be connected to the first light emission control signal applying line EM2. The first light emitting diode OLED1 may be electrically connected to the first light emission control thin film transistor T4 via the first-first contact hole CH1-1. The second light emission control thin film transistor T6 may be connected to the second light emission control signal applying line EM3. The second light emitting diode OLED2 may be electrically connected to the second light emission control thin film transistor T6 via the second-first contact hole CH2-1.

[0268] Therefore, the timing controller 40 may apply the first emission control signal to the first emission control signal applying line EM2 to turn on the first emission control thin film transistor T4, and may not apply the second emission control signal to the second emission control signal applying line EM3 while the first emission control thin film transistor T4 is turned on.

[0269] In addition, the timing controller 40 may apply the second emission control signal to the second emission control signal applying line EM3 to turn on the second emission control thin film transistor T6 , and may not apply the first emission control signal to the first emission control signal applying line EM2 while the second emission control thin film transistor T6 is turned on.

[0270] As described above, according to the present disclosure, a plurality of pixels arranged in the light-emitting area can be arranged in each of the wide-angle area and the narrow-angle area of ​​the unit pixel, and can be activated separately in the wide-angle area and the narrow-angle area. Therefore, the light-emitting angle of the pixel in the unit pixel can be selected to control the viewing angle of the display panel.

[0271] In addition, according to the present disclosure, the refractive index of each of the lenses divided in the wide-angle area and the lenses arranged in the narrow-angle area can be adjusted to control the direction of light emitted from each light-emitting layer in each of the wide-angle area and the narrow-angle area. Therefore, the viewing angle can be adjusted using the controlled direction of light.

[0272] As described above, the present disclosure has been described with reference to the accompanying drawings and embodiments. The present disclosure is not limited to the embodiments and drawings disclosed in the present disclosure. It is obvious that those skilled in the art can make various modifications within the scope of the technical idea of ​​the present disclosure. In addition, even if the effect according to the configuration of the present disclosure is not explicitly described when describing the embodiments of the present disclosure above, the effect predicted according to the configuration should naturally be considered as the effect of the present disclosure.

Claims

1. A display panel, comprising: a unit pixel divided into a wide-angle region and a narrow-angle region, wherein at least one sub-pixel is disposed in each of the wide-angle region and the narrow-angle region; A first lens disposed in the wide-angle region; and a second lens disposed in the narrow angle region, wherein the at least one sub-pixel comprises a first light-emitting layer in the wide-angle region and a second light-emitting layer in the narrow-angle region, wherein a first shielding layer has an opening defined therein and is disposed on the first light emitting layer and the second light emitting layer, a first insulating layer is disposed on the first shielding layer, a second shielding layer has an opening defined therein and is disposed on the first insulating layer, and The opening of the first shielding layer and the opening of the second shielding layer overlap with the first lens and the second lens respectively.

2. The display panel according to claim 1, wherein: The first lens is a semi-cylindrical lens, and the second lens is a hemispherical lens.

3. The display panel according to claim 1, wherein: The at least one sub-pixel includes a plurality of sub-sub-pixels.

4. The display panel according to claim 1, wherein: The first lens includes at least two or more first lenses that are arranged in the wide angle region and have the same shape and the same size as each other.

5. The display panel according to claim 1, wherein: The unit pixel includes at least three sub-pixels, wherein in the wide-angle area, the first lens covers at least two sub-pixels.

6. The display panel according to claim 1, wherein: The second lens includes at least two or more second lenses that are arranged in the narrow angle region and have the same shape, the same size, and the same thickness as each other.

7. The display panel according to claim 3, wherein: The second lens includes a plurality of second lenses arranged in the narrow angle region and respectively formed on the plurality of sub-sub-pixels.

8. The display panel according to claim 1, wherein: The first lens and the second lens have different shapes and different sizes.

9. The display panel according to claim 7, wherein: Each second lens has a bottom surface having an area larger than a light emitting area of ​​each sub-sub-pixel.

10. The display panel according to claim 5, wherein: Each of the at least three sub-pixels includes a plurality of sub-sub-pixels, The at least three sub-pixels include a first sub-pixel, a second sub-pixel and a third sub-pixel that emit different colors. The number of the plurality of sub-sub-pixels of the third sub-pixel is greater than each of the number of the plurality of sub-sub-pixels of the first sub-pixel and the number of the plurality of sub-sub-pixels of the second sub-pixel.

11. The display panel according to claim 1, wherein: A size of each of the at least one sub-pixel, the first lens, and the second lens varies based on a light output cutoff angle.

12. The display panel according to claim 1, wherein: A size of each of the at least one sub-pixel, the first lens, and the second lens varies based on light efficiency and light concentration of the at least one sub-pixel.

13. The display panel according to claim 1, wherein: The at least one sub-pixel comprises: a first anode electrode layer in the wide angle region and a second anode electrode layer in the narrow angle region; The first light-emitting layer and the second light-emitting layer are respectively disposed on the first anode electrode layer and the second anode electrode layer; a cathode electrode layer disposed on both the first light-emitting layer and the second light-emitting layer; The first shielding layer is disposed on the cathode electrode layer; The first insulating layer is disposed on the first shielding layer; The second shielding layer is disposed on the first insulating layer; a first gap-filling layer disposed on the second shielding layer; The first lens is disposed on the first gap-filling layer in the wide-angle region; the second lens being disposed on the first gap-filling layer in the narrow angle region; and a second gap-filling layer disposed on both the first lens and the second lens, The opening of the first shielding layer and the opening of the second shielding layer are respectively defined in a region overlapping with the first anode electrode layer and a region overlapping with the second anode electrode layer.

14. The display panel according to claim 13, wherein: The opening of the first shielding layer and the opening of the second shielding layer have the same size and the same thickness.

15. The display panel according to claim 13, wherein: The at least one sub-pixel comprises: a first transistor connected to the data line; a drive transistor connected to a drive power source; a fourth transistor which is provided between and connected to the driving transistor and the first anode electrode layer and is capable of switching based on a first light emission control signal; and A sixth transistor is provided between and connected to the driving transistor and the second anode electrode layer, and is capable of switching based on a second light emission control signal.

16. The display panel according to claim 13, wherein: The distance between the first light emitting layer and the first lens is adjusted based on the thickness of the first gap filling layer, Wherein, a distance between the second light emitting layer and the second lens is adjusted based on a thickness of the first gap filling layer.

17. The display panel according to claim 13, wherein: The first gap filling layer is made of one selected from acrylic acid, epoxy resin, silicon, or a combination thereof.

18. The display panel according to claim 13, wherein: The first gap-filling layer is made of an organic material.

19. A display device comprising: A display panel, the display panel comprising: a unit pixel divided into a wide-angle region and a narrow-angle region, wherein at least one sub-pixel is disposed in each of the wide-angle region and the narrow-angle region; A first lens disposed in the wide-angle region; and a second lens disposed in the narrow angle region; a gate driver for applying a gate signal to the at least one sub-pixel in each of the wide-angle area and the narrow-angle area through at least one gate line; a data driver for applying a data signal to the at least one sub-pixel in each of the wide-angle area and the narrow-angle area through at least one data line; and a timing controller, which is used to control the gate driver and the data driver, wherein the at least one sub-pixel comprises a first light-emitting layer in the wide-angle region and a second light-emitting layer in the narrow-angle region, wherein a first shielding layer has an opening defined therein and is disposed on the first light emitting layer and the second light emitting layer, a first insulating layer is disposed on the first shielding layer, a second shielding layer has an opening defined therein and is disposed on the first insulating layer, and The opening of the first shielding layer and the opening of the second shielding layer overlap with the first lens and the second lens respectively.

20. The display device according to claim 19, wherein: The display device further includes: a first light emission control signal applying line connected to the at least one sub-pixel provided in the wide-angle region; and a second light emission control signal applying line connected to the at least one sub-pixel provided in the narrow angle region, Wherein, the first light emission control signal applying line and the second light emission control signal applying line are spaced apart from each other.

21. The display device according to claim 20, wherein: The first light emission control thin film transistor is connected to the first light emission control signal applying line, The first light emitting diode is electrically connected to the first light emitting control thin film transistor via the first contact hole. The second light emission control thin film transistor is connected to the second light emission control signal applying line. The second light emitting diode is electrically connected to the second light emitting control thin film transistor via the second contact hole.

22. The display device according to claim 21, wherein: The timing controller is configured to: applying a first light emission control signal to the first light emission control signal application line to turn on the first light emission control thin film transistor; and The second light emission control signal is not applied to the second light emission control signal application line when the first light emission control thin film transistor is turned on.

23. The display device according to claim 21, wherein: The timing controller is configured to: applying a second light emission control signal to the second light emission control signal application line to turn on the second light emission control thin film transistor; and The first light emission control signal is not applied to the first light emission control signal application line when the second light emission control thin film transistor is turned on.

Images