Dynamic power control

Abstract

This application is directed to dynamic power control. In some examples, a memory device can be configured to adjust a first duration for transitioning power modes. For example, the memory device can be configured to operate in a first power mode, a second power mode, and a third power mode. While operating in the second power mode, the memory device can be configured to increase or decrease the first duration for transitioning to the third power mode based on a second duration between received commands. If no command is received during the first duration, the memory device can transition from the second power mode to the third power mode.

Description

[0001] Cross-reference of related applications

[0002] This patent application claims priority to U.S. Patent Application No. 17 / 736,886, entitled "Dynamic Power Control," filed May 4, 2022, by Wang et al., and claims the benefit of U.S. Provisional Patent Application No. 63 / 208,875, entitled "Dynamic Power Control," filed June 9, 2021, by Wang et al., each of which is assigned to the assignee and each of which is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field involves dynamic power control. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices such as computers, user devices, wireless communication devices, cameras, and digital displays. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed to one of two supported states, often corresponding to logic 1 or logic 0. In some instances, a single memory cell can support more than two possible states, and the memory cell can store any one of the two possible states. To access the information stored by the memory device, a component can read or sense the state of one or more memory cells within the memory device. To store information, a component can write or program one or more memory cells within the memory device into corresponding states.

[0005] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), 3D crosspoint memory, NOR (Non-OR), and NAND (NAND) memory devices. Memory devices can be volatile or non-volatile. Volatile memory cells (e.g., DRAM cells) may lose their programmed state over time unless periodically refreshed by an external power supply. Non-volatile memory cells (e.g., NAND memory cells) can maintain their programmed state for a long time even in the absence of an external power supply. Summary of the Invention

[0006] A device is described. The device may include a plurality of memory cells and a controller coupled to the plurality of memory cells. The controller is operable to: set a first duration for operating the device in a second power mode different from a first power mode; receive a first command and a second command from a host device after setting the first duration for operating the device in the second power mode, wherein at least the second command is received after the device transitions from the first power mode to the second power mode; adjust the first duration for operating the device in the second power mode based at least in part on a second duration between receiving the first command and the second command; and continue operating the device in the second power mode for the adjusted first duration based at least in part on the adjusted first duration after receiving a third command while operating in the first power mode.

[0007] A non-transitory computer-readable medium is described. The non-transitory computer-readable medium may store code containing instructions that, when executed by a processor of a memory device, cause the memory device to: set a first duration for operating the memory device in a second power mode, different from a first power mode, at the memory device comprising a plurality of memory cells; receive a first command and a second command from a host device after setting the first duration for operating the memory device in the second power mode, wherein at least the second command is received after the memory device transitions from the first power mode to the second power mode; adjust the first duration for operating the memory device in the second power mode, at least in part, based on a second duration between receiving the first command and the second command; and, after receiving a third command while operating in the first power mode, continue operating in the second power mode for an adjusted first duration, at least in part, based on the adjustment of the first duration.

[0008] A method is described. The method may include: setting a first duration at a memory device comprising a plurality of memory cells for operating the memory device in a second power mode different from a first power mode; receiving a first command and a second command from a host device after setting the first duration for operating the memory device in the second power mode, wherein at least the second command is received after the memory device transitions from the first power mode to the second power mode; adjusting the first duration for operating the memory device in the second power mode based at least in part on a second duration between receiving the first command and the second command; and continuing the adjusted first duration for operating the memory device in the second power mode based at least in part on the adjusted first duration after receiving a third command while operating in the first power mode. Attached Figure Description

[0009] Figure 1 Examples of systems supporting dynamic power control based on the examples disclosed herein are shown.

[0010] Figure 2 Examples of systems supporting dynamic power control based on the examples disclosed herein are shown.

[0011] Figure 3 An example of a timing diagram supporting dynamic power control is shown, based on the examples disclosed herein.

[0012] Figure 4 An example of a block diagram supporting dynamic power control is shown, based on the examples disclosed herein.

[0013] Figure 5A An example of a process flow diagram supporting dynamic power control based on the examples disclosed herein is shown.

[0014] Figure 5B An example of a block diagram supporting dynamic power control is shown, based on the examples disclosed herein.

[0015] Figure 6 A block diagram illustrating a memory device supporting dynamic power control based on the examples disclosed herein.

[0016] Figure 7 The flowchart illustrates one or more methods for supporting dynamic power control based on the examples disclosed herein. Detailed Implementation

[0017] Some memory devices can be configured to operate in various power modes. For example, a memory device can be configured to operate in a sleep mode (e.g., hibernation mode), where power to the array and various circuitry can be cut off. Furthermore, a memory device can be configured to operate in a "power-saving mode," where power to some portions of the memory device, but not others, can be maintained (e.g., other portions can be powered off). In some examples, a memory device can transition from a normal mode (e.g., active mode) to a power-saving mode if no command is received for a first duration, and can transition from a power-saving mode to a sleep mode if no command is received for a second duration longer than the first duration. However, because the memory device may take a longer time to transition from sleep mode to normal mode compared to transitioning from power-saving mode, increasing the second duration when the memory device is receiving relatively few commands may result in poorer performance (e.g., longer latency), while decreasing the second duration may increase power consumption. Accordingly, a memory device configured to dynamically adjust the first and second durations may be desirable.

[0018] This document describes a memory device configured to dynamically adjust the duration between entering a power-saving mode and transitioning to a sleep mode (e.g., hibernation mode). In some instances, the memory device can be configured to determine the duration between received commands while operating in a power-saving mode, which can allow the memory device to extend or shorten the duration of transitioning to sleep mode. For example, the memory device can determine one or more of the durations between commands after entering a power-saving mode. If the duration exceeds a first threshold, the memory device can shorten the duration of transitioning to sleep mode (e.g., shorten it to a minimum duration). Furthermore, if the duration does not exceed a second threshold, the memory device can extend the duration of transitioning to sleep mode (e.g., extend it to a maximum duration). By dynamically adjusting the duration of transition from power-saving mode to sleep mode, the memory device can remain in power-saving mode when receiving commands at relatively short intervals, which can reduce latency that would otherwise be attributed to the memory device transitioning to sleep mode. Furthermore, the memory device can transition to sleep mode when receiving commands at relatively long intervals, which can reduce the overall power consumption of the memory device.

[0019] First, as referenced Figure 1 and 2 The features of this disclosure are described in the context of the memory system described. References Figure 3-5B The features of this disclosure are described in the context of timing diagrams, block diagrams, and process flowcharts. Further references Figure 6 and 7These and other features of this disclosure are illustrated and described in the context of device diagrams and flowcharts involving dynamic power control.

[0020] Figure 1 An example of a system 100 supporting dynamic power control according to the examples disclosed herein is shown. System 100 includes a host system 105 coupled to a memory system 110.

[0021] The memory system 110 may be or include any device or collection of devices, wherein the device or collection of devices includes at least one memory array. For example, the memory system 110 may be or include a universal flash memory (UFS) device, an embedded multimedia controller (eMMC) device, a flash device, a universal serial bus (USB) flash device, a secure digital card (SD card), a solid-state drive (SSD), a hard disk drive (HDD), a dual in-line memory module (DIMM), a small form factor DIMM (SO-DIMM), or a non-volatile DIMM (NVDIMM), and other possibilities.

[0022] System 100 may be included in a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transportation), device with Internet of Things (IoT) capabilities, embedded computer (e.g., embedded computer included in a vehicle, industrial equipment or networked business device), or any other computing device that includes memory and processing devices.

[0023] System 100 may include a host system 105 that can be coupled to memory system 110. In some instances, this coupling may include an interface to a host system controller 106, which may be an instance of a controller or control component configured to cause host system 105 to perform various operations as described herein. Host system 105 may include one or more devices, and in some cases, may include a processor chipset and a software stack executed via the processor chipset. For example, host system 105 may include an application configured to communicate with memory system 110 or devices therein. The processor chipset may include one or more cores, one or more caches (e.g., memory native to host system 105 or included in host system 105), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a Peripheral Component Interconnect High Speed ​​(PCIe) controller, a Serial Advanced Technology Attachment (SATA) controller). Host system 105 may use memory system 110, for example, to write data to and read data from memory system 110. Although Figure 1The diagram shows a memory system 110, but the host system 105 can be coupled to any number of memory systems 110.

[0024] Host system 105 may be coupled to memory system 110 via at least one physical host interface. In some cases, host system 105 and memory system 110 may be configured to communicate via the physical host interface using associated protocols (e.g., exchanging or otherwise transmitting control, address, data, and other signals between memory system 110 and host system 105). Examples of physical host interfaces may include, but are not limited to, SATA interfaces, UFS interfaces, eMMC interfaces, PCIe interfaces, USB interfaces, Fibre Channel interfaces, Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Dual Data Rate (DDR) interfaces, DIMM interfaces (e.g., DDR-enabled DIMM sockets), Open NAND Flash Interface (ONFI), and Low Power Dual Data Rate (LPDDR) interfaces. In some instances, one or more such interfaces may be contained in or otherwise supported between host system controller 106 of host system 105 and memory system controller 115 of memory system 110. In some instances, host system 105 may be coupled to memory system 110 via a corresponding physical host interface for each memory device 130 included in memory system 110, or via a corresponding physical host interface for each type of memory device 130 included in memory system 110 (e.g., host system controller 106 may be coupled to memory system controller 115).

[0025] Memory system 110 may include memory system controller 115 and one or more memory devices 130. Memory device 130 may include one or more memory arrays of any type of memory cells (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). Although in Figure 1 The example shows two memory devices 130-a and 130-b, but the memory system 110 may contain any number of memory devices 130. Furthermore, if the memory system 110 contains more than one memory device 130, the different memory devices 130 within the memory system 110 may contain the same or different types of memory cells.

[0026] The memory system controller 115 may be coupled to and communicate with the host system 105 (e.g., via a physical host interface) and may be an example of a controller or control component configured to cause the memory system 110 to perform various operations as described herein. The memory system controller 115 may also be coupled to and communicate with the memory device 130 to perform operations generally referred to as access operations at the memory device 130, such as reading data, writing data, erasing data, or refreshing data, and other such operations. In some cases, the memory system controller 115 may receive commands from the host system 105 and communicate with one or more memory devices 130 to execute such commands (e.g., at a memory array within the one or more memory devices 130). For example, the memory system controller 115 may receive commands or operations from the host system 105 and may translate these commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. In some cases, the memory system controller 115 may exchange data with the host system 105 and one or more memory devices 130 (e.g., in response to or in combination with commands from the host system 105). For example, the memory system controller 115 may translate responses (e.g., data packets or other signals) associated with the memory device 130 into corresponding signals for the host system 105.

[0027] The memory system controller 115 can be configured for other operations associated with the memory device 130. For example, the memory system controller 115 may perform or manage operations such as wear leveling, garbage collection, error control operations such as error detection or error correction, encryption, caching, media management, background refresh, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 130.

[0028] The memory system controller 115 may include hardware, such as one or more integrated circuits or discrete components, buffer memories, or combinations thereof. The hardware may include circuitry with dedicated (e.g., hard-decoded) logic to perform the operations attributed herein to the memory system controller 115. The memory system controller 115 may be or include a microcontroller, a dedicated logic circuitry (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry.

[0029] The memory system controller 115 may also include local memory 120. In some cases, local memory 120 may include read-only memory (ROM) or other memory that stores operational code (e.g., executable instructions) that can be executed by the memory system controller 115 to perform the functions attributed to the memory system controller 115 herein. In some cases, local memory 120 may additionally or alternatively include static random access memory (SRAM) or other memory that can be used by the memory system controller 115 for, for example, internal storage or operations related to the functions attributed to the memory system controller 115 herein.

[0030] although Figure 1 The memory system 110 described herein has been illustrated as including a memory system controller 115, but in some cases, the memory system 110 may not include a memory system controller 115. For example, the memory system 110 may additionally or alternatively rely on an external controller (e.g., implemented by the host system 105) or one or more local controllers 135 within the memory device 130 to perform the functions attributed herein to the memory system controller 115. Generally, one or more functions attributed herein to the memory system controller 115 may, in some cases, be performed by the host system 105, the local controller 135, or any combination thereof. In some cases, the memory device 130, at least partially managed by the memory system controller 115, may be referred to as a managed memory device. An example of a managed memory device is a managed NAND (MNAND) device.

[0031] Memory device 130 may include one or more arrays of non-volatile memory cells. For example, memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase-change memory (PCM), auto-select memory, other chalcogenide-based memories, ferroelectric random access memory (RAM) (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), electrically erasable programmable ROM (EEPROM), or any combination thereof. Alternatively or additionally, memory device 130 may include one or more arrays of volatile memory cells. For example, memory device 130 may include RAM memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0032] In some instances, memory device 130 may include (e.g., on the same die or within the same package) a local controller 135 that can operate on one or more memory cells of the respective memory device 130. The local controller 135 may operate in conjunction with memory system controller 115, or may perform one or more functions attributed herein to memory system controller 115. For example, such as Figure 1 As shown, memory device 130-a may include local controller 135-a, and memory device 130-b may include local controller 135-b.

[0033] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include a memory die 160. For example, in some cases, memory device 130 may be a package including one or more dies 160. In some instances, die 160 may be a block of electronic-grade semiconductor diced from a wafer (e.g., a silicon die diced from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a corresponding set of blocks 170, wherein each block 170 may include a corresponding set of pages 175, and each page 175 may include a set of memory cells.

[0034] In some cases, the NAND memory device 130 may include memory cells configured to each store one bit of information, which may be referred to as a single-level cell (SLC). Alternatively, the NAND memory device 130 may include memory cells configured to each store multiple bits of information; if configured to store two bits of information, it may be referred to as a multi-level cell (MLC); if configured to store three bits of information, it may be referred to as a three-level cell (TLC); if configured to store four bits of information, it may be referred to as a four-level cell (QLC), or more generally, a multi-level memory cell. Multi-level memory cells can provide greater storage density compared to SLC memory cells, but in some cases, this may involve narrower read or write margins or greater complexity for supporting circuitry.

[0035] In some cases, plane 165 may refer to a group of blocks 170, and in some cases, parallel operations may occur within different planes 165. For example, parallel operations may be performed on memory cells within different blocks 170, provided that the different blocks 170 are in different planes 165. In some cases, individual blocks 170 may be referred to as physical blocks, and virtual blocks 180 may refer to a group of blocks 170 within which parallel operations may occur. For example, parallel operations may be performed on blocks 170-a, 170-b, 170-c, and 170-d respectively within planes 165-a, 170-b, 170-c, and 170-d, and blocks 170-a, 170-b, 170-c, and 170-d may be collectively referred to as virtual blocks 180. In some cases, a virtual block may contain blocks 170 from different memory devices 130 (e.g., blocks contained in one or more planes of memory devices 130-a and 130-b). In some cases, blocks 170 within a virtual block may have the same block address within their respective planes 165 (e.g., block 170-a may be “block 0” of plane 165-a, block 170-b may be “block 0” of plane 165-b, etc.). In some cases, performing parallel operations in different planes 165 may be subject to one or more restrictions, such as performing parallel operations on memory cells within different pages 175 that have the same page address within their respective planes 165 (e.g., regarding command decoding, page address decoding circuitry, and other circuitry shared across planes 165).

[0036] In some cases, block 170 may contain memory cells organized in rows (page 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 may share a common word line (e.g., coupled to a common word line), and memory cells in the same string may share a common digital line (which may alternatively be called a bit line) (e.g., coupled to a common digital line).

[0037] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first granularity level (e.g., at the page granularity level), but can be erased at a second granularity level (e.g., at the block granularity level). That is, page 175 can be the smallest unit of memory (e.g., a collection of memory cells) that can be independently programmed or read (simultaneously programmed or read as part of a single programming or reading operation), and block 170 can be the smallest unit of memory (e.g., a collection of memory cells) that can be independently erased (e.g., simultaneously erased as part of a single erase operation). Furthermore, in some cases, NAND memory cells can be erased before they can be rewritten with new data. Therefore, for example, in some cases, used page 175 may not be updated until the entire block 170 containing page 175 has been erased.

[0038] System 100 may include any number of non-transitory computer-readable media supporting dynamic power control. For example, host system 105, memory system controller 115, or memory device 130 may include or otherwise access one or more non-transitory computer-readable media storing instructions (e.g., firmware) to perform the functions attributed herein to host system 105, memory system controller 115, or memory device 130. For example, if executed by host system 105 (e.g., by host system controller 106), memory system controller 115, or memory device 130 (e.g., by local controller 135), such instructions may cause host system 105, memory system controller 115, or memory device 130 to perform one or more associated functions as described herein.

[0039] In some cases, memory system 110 may utilize memory system controller 115 to provide a managed memory system, which may include, for example, one or more memory arrays and associated circuitry combined with a local (e.g., on-die or in-package) controller (e.g., local controller 135). An example of a managed memory system is a managed NAND (MNAND) system.

[0040] In some instances, memory system 110 may be configured to operate in a power-saving mode or a sleep mode (e.g., hibernation mode). As described herein, a power-saving mode may utilize more power than a sleep mode, but memory system 110 may be able to transition from a power-saving mode to a normal mode (e.g., active mode) faster than transitioning from a sleep mode to an active mode. Memory system 110 may set an initial duration (e.g., a first duration, Tpsm) for operation in power-saving mode. Accordingly, memory system 110 may enter power-saving mode when memory system controller 115 receives a command (e.g., a hibernation command) from host system 105, or when memory system controller 115 fails to receive a command for the duration (e.g., when host system 105 is idle).

[0041] After entering the power saving mode, the memory system controller 115 may determine the duration between received commands (e.g., a second duration, Tperiod). For example, the memory system controller 115 may receive a first command, transition to the power saving mode, and then receive a second command. The memory system controller 115 may determine the duration between the first command and the second command, which may be referred to as Tperiod. In some examples, the memory system controller 115 may compare Tperiod with a first threshold (e.g., a low threshold, TH_low), and if Tperiod does not satisfy the threshold (e.g., if Tperiod<TH_low), Tpsm may be increased. Furthermore, the memory system controller 115 may compare Tperiod with a second threshold (e.g., a high threshold, TH_high), and if Tperiod satisfies the threshold (e.g., if Tperiod>TH_high), Tpsm may be decreased.

[0042] Accordingly, if no command is received within Tpsm, the memory system 110 may transition from the power saving mode to the sleep mode. By increasing Tpsm when the memory system controller 115 is receiving commands from the host system 105 at relatively short intervals, the latency incurred by the memory system 110 when transitioning power modes can be improved. That is, because the memory system 110 can transition from the power saving mode to the active mode faster than transitioning from the sleep mode to the active mode, latency can be improved by increasing Tpsm under heavy load conditions. Additionally or alternatively, by decreasing Tpsm when the memory system controller 115 is receiving commands from the host system 105 at relatively long intervals, the memory system 110 can achieve additional power savings by transitioning to the sleep mode faster.

[0043] Figure 2 An example of a system 200 that supports dynamic power control according to the examples disclosed herein is shown. System 200 may be an example of Figure 1 the system 100 described with reference to or aspects thereof. The system 200 may include a memory system 210 configured to store data received from the host system 205 and transmit data to the host system 205 if requested by the host system 205 using an access command (e.g., a read command or a write command). The system 200 may implement aspects of the system 100 described with reference to Figure 1 For example, the memory system 210 and the host system 205 may be examples of the memory system 110 and the host system 105, respectively.

[0044] As described herein, memory system 210 may include memory device 240 for storing, for example, data transferred between memory system 210 and host system 205 in response to receiving an access command from host system 205. Memory device 240 may include, as referenced... Figure 1 The memory device 240 may include one or more memory devices as described. For example, memory device 240 may include NAND memory, PCM, self-select memory, 3D cross-point, other chalcogenide-based memory, FERAM, MRAM, NOR (e.g., NOR flash) memory, STT-MRAM, CBRAM, RRAM, or OxRAM.

[0045] Memory system 210 may include a memory controller 230 for controlling the transfer of data directly to and from memory device 240, such as for storing data, retrieving data, and determining memory locations where data is to be stored and retrieved. The memory controller 230 may communicate with memory device 240 directly or via a bus (not shown) using protocols specific to each type of memory device 240. In some cases, a single memory controller 230 may be used to control multiple memory devices 240 of the same or different types. In some cases, memory system 210 may include multiple memory controllers 230, for example, different memory controllers 230 for each type of memory device 240. In some cases, the memory controller 230 may be implemented as described in the reference. Figure 1 The aspects of the local controller 135 described.

[0046] The memory system 210 may additionally include an interface 220 for communicating with the host system 205, and a buffer 225 for temporarily storing data transferred between the host system 205 and the memory device 240. The interface 220, buffer 225, and memory controller 230 can be used, for example, to translate data between the host system 205 and the memory device 240 via data path 250, and can be collectively referred to as the data path components.

[0047] Using buffer 225 to temporarily store data during transmission allows data to be buffered while commands are being processed, thereby reducing latency between commands and allowing for arbitrary data sizes associated with commands. This also allows for handling command bursts, and once the burst stops, the buffered data can be stored or emitted (or both). Buffer 225 may contain relatively fast memory (e.g., some type of volatile memory such as SRAM or DRAM), or hardware accelerators or both, to allow for rapid storage of data into and from buffer 225. Buffer 225 may include data path switching components for bidirectional data transfer between buffer 225 and other components.

[0048] Temporary storage of data within buffer 225 refers to the storage of data in buffer 225 during the execution of an access command. That is, after the access command is completed, the associated data may no longer be maintained in buffer 225 (e.g., it may be overwritten by data used for additional access commands). Additionally, buffer 225 may be a non-cached buffer. That is, the host system 205 may not read data directly from buffer 225. For example, a read command may be added to a queue without performing an operation to match the address with an address already existing in buffer 225 (e.g., no cached address matching or lookup operation).

[0049] The memory system 210 may additionally include a memory system controller 215 for executing commands received from the host system 205 and controlling data path components when moving data. The memory system controller 215 may be as described in the reference... Figure 1 An example of the described memory system controller 115. Bus 235 can be used for communication between system components.

[0050] In some cases, one or more queues (e.g., command queue 260, buffer queue 265, and storage queue 270) may be used to control the processing of access commands and the movement of corresponding data. This may be advantageous, for example, if the memory system 210 processes more than one access command from the host system 205 in parallel. As examples of possible implementations, command queue 260, buffer queue 265, and storage queue 270 are depicted at interface 220, memory system controller 215, and storage controller 230, respectively. However, queues (if used) may be located anywhere within the memory system 210.

[0051] Data transferred between host system 205 and memory device 240 may take a different path within memory system 210 than non-data information (e.g., commands, status information). For example, system components in memory system 210 may communicate with each other using bus 235, while data may use data path 250 via data path components instead of bus 235. Memory system controller 215 may control how and whether data is transferred between host system 205 and memory device 240 by communicating with data path components on bus 235 (e.g., using a protocol specific to memory system 210).

[0052] If host system 205 issues an access command to memory system 210, interface 220 may receive the command, for example, according to a protocol (e.g., UFS protocol or eMMC protocol). Therefore, interface 220 can be considered as the front end of memory system 210. Upon receiving each access command, interface 220 may transmit the command to memory system controller 215, for example, via bus 235. In some cases, each command may be added to command queue 260 via interface 220 to transmit the command to memory system controller 215.

[0053] The memory system controller 215 may determine that an access command has been received based on communication from interface 220. In some cases, the memory system controller 215 may determine that an access command has been received by retrieving a command from command queue 260. After, for example, the command has been retrieved from command queue 260 by memory system controller 215, the command may be removed from command queue 260. In some cases, the memory system controller 215 may cause interface 220 to remove the command from command queue 260, for example, via bus 235.

[0054] After confirming that an access command has been received, the memory system controller 215 can execute the access command. For a read command, this may mean obtaining data from the memory device 240 and transmitting the data to the host system 205. For a write command, this may mean receiving data from the host system 205 and moving the data to the memory device 240.

[0055] In either case, the memory system controller 215 may use the buffer 225, particularly for temporary storage of data received from or sent to the host system 205. The buffer 225 may be considered as an intermediate end of the memory system 210. In some cases, buffer address management (e.g., pointers to address locations in the buffer 225) may be performed by hardware (e.g., dedicated circuitry) in the interface 220, the buffer 225, or the memory controller 230.

[0056] In order to process a write command received from host system 205, memory system controller 215 may first determine whether buffer 225 has sufficient available space to store the data associated with the command. For example, memory system controller 215 may determine the amount of space available in buffer 225 to store the data associated with the write command, for example via firmware (e.g., controller firmware).

[0057] In some cases, buffer queue 265 can be used to control a stream of commands associated with data stored in buffer 225, the stream of commands including write commands. Buffer queue 265 may contain access commands associated with data currently stored in buffer 225. In some cases, commands in command queue 260 can be moved to buffer queue 265 via memory system controller 215 and can remain in buffer queue 265 while the associated data is stored in buffer 225. In some cases, each command in buffer queue 265 may be associated with an address at buffer 225. That is, a pointer indicating the location in buffer 225 that stores data associated with each command can be maintained. Using buffer queue 265, multiple access commands can be received sequentially from host system 205 and at least a portion of the access commands can be processed in parallel.

[0058] If buffer 225 has sufficient space to store the write data, memory system controller 215 may cause interface 220 to transmit an availability indication (e.g., a "ready to deliver" indication) to host system 205, for example, according to a protocol (e.g., UFS protocol or eMMC protocol). When interface 220 subsequently receives data associated with the write command from host system 205, interface 220 may use data path 250 to deliver the data to buffer 225 for temporary storage. In some cases, interface 220 may obtain the location within buffer 225 from buffer 225 or buffer queue 265 where the data to be stored. Interface 220 may indicate to memory system controller 215, for example, via bus 235 whether the data delivery to buffer 225 has been completed.

[0059] Once written data has been stored in buffer 225 via interface 220, the data can be transferred from buffer 225 and stored in memory device 240. This can be accomplished using memory controller 230. For example, memory system controller 215 can cause memory controller 230 to retrieve data from buffer 225 using data path 250 and transfer the data to memory device 240. Memory controller 230 can be considered as the back-end of memory system 210. Memory controller 230 can, for example, indicate to memory system controller 215 via bus 235 that data transfer to memory device 240 has been completed.

[0060] In some cases, memory queue 270 can be used to assist in the transfer of write data. For example, memory system controller 215 can push write commands from buffer queue 265 (e.g., via bus 235) to memory queue 270 for processing. Memory queue 270 may contain entries for each access command. In some instances, memory queue 270 may additionally contain: a buffer pointer (e.g., an address) indicating the location in buffer 225 where data associated with the command is stored; and a memory pointer (e.g., an address) indicating the location in memory device 240 associated with the data. In some cases, memory controller 230 can obtain the location within buffer 225 from which data is to be obtained, either from buffer 225, buffer queue 265, or memory queue 270. Memory controller 230 can manage the locations within memory device 240 used for storing data (e.g., performing wear leveling, garbage collection, etc.). Entries can be added to memory queue 270, for example, via memory system controller 215. After the data transfer is complete, the entry can be removed from the storage queue 270, for example, via the storage controller 230 or the memory system controller 215.

[0061] In order to process a read command received from host system 205, memory system controller 215 may again first determine whether buffer 225 has sufficient available space to store the data associated with the command. For example, memory system controller 215 may determine the amount of space available in buffer 225 to store the data associated with the read command, for example via firmware (e.g., controller firmware).

[0062] In some cases, buffer queue 265 can be used to supplement buffer storage of data associated with read commands in a manner similar to that discussed above with respect to write commands. For example, if buffer 225 has sufficient space to store read data, memory system controller 215 can cause memory controller 230 to retrieve the data associated with the read command from memory device 240 and store the data in buffer 225 for temporary storage using data path 250. Memory controller 230 can indicate to memory system controller 215, for example, via bus 235, when data transfer to buffer 225 has been completed.

[0063] In some cases, the storage queue 270 can be used to assist in the transfer of read data. For example, the memory system controller 215 can push a read command to the storage queue 270 for processing. In some cases, the storage controller 230 can obtain the location within the memory device 240 from which data is to be retrieved from, either from the buffer 225 or the storage queue 270. In some cases, the storage controller 230 can obtain the location within the buffer 225 from the buffer queue 265 from which data is to be stored. In some cases, the storage controller 230 can obtain the location within the buffer 225 from the storage queue 270 from which data is to be stored. In some cases, the memory system controller 215 can move a command processed by the storage queue 270 back to the command queue 260.

[0064] Once data has been stored in buffer 225 by storage controller 230, it can be transferred from buffer 225 and sent to host system 205. For example, storage system controller 215 can cause interface 220 to retrieve data from buffer 225 using data path 250 and, for example, transmit the data to host system 205 according to a protocol (e.g., UFS protocol or eMMC protocol). For example, interface 220 can process commands from command queue 260 and can, for example, indicate to storage system controller 215 via bus 235 that data transmission to host system 205 has been completed.

[0065] The memory system controller 215 can execute received commands in a sequence (e.g., according to the first-in, first-out order of the command queue 260). For each command, the memory system controller 215 can cause the data corresponding to the command to move in and out of buffer 225, as discussed above. While the data is moving into and stored in buffer 225, the command can remain in buffer queue 265. If the processing of the command has been completed (e.g., if the data corresponding to the access command has been passed from buffer 225), the command can be removed from buffer queue 265, for example, by the memory system controller 215. If the command is removed from buffer queue 265, the address where the data associated with the command was previously stored can be used to store the data associated with the new command.

[0066] The memory system controller 215 may be additionally configured for operations associated with the memory device 240. For example, the memory system controller 215 may perform or manage operations such as wear leveling, garbage collection, error control operations (e.g., error detection or error correction), encryption, caching, media management, background refresh, health monitoring, and address translation between logical addresses (e.g., LBAs) associated with commands from the host system 205 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 240. That is, the host system 205 may issue commands indicating one or more LBAs, and the memory system controller 215 may recognize one or more physical block addresses indicated by the LBAs. In some cases, one or more consecutive LBAs may correspond to non-consecutive physical block addresses. In some cases, the memory controller 230 may be configured to perform one or more of the above operations in conjunction with or in place of the memory system controller 215. In some cases, the memory system controller 215 may perform the functions of the memory controller 230, and the memory controller 230 may be omitted.

[0067] In some instances, memory system 210 may be configured to operate in a power-saving mode or a sleep mode (e.g., hibernation mode). As described herein, a power-saving mode may utilize more power than a sleep mode, but memory system 210 may be able to transition from a power-saving mode to a normal mode (e.g., active mode) faster than transitioning from a sleep mode to an active mode. Memory system 210 may set an initial duration (e.g., a first duration, Tpsm) for operation in power-saving mode. Accordingly, memory system 210 may enter power-saving mode when memory system controller 215 receives a command (e.g., a hibernation command) from host system 205, or when memory system controller 215 fails to receive a command for the duration (e.g., when host system 205 is idle).

[0068] After entering the power saving mode, the memory system controller 215 may determine the duration between received commands (e.g., a second duration, Tperiod). For example, the memory system controller 215 may receive a first command, transition to the power saving mode, and then receive a second command. The memory system controller 215 may determine the duration between the first command and the second command, which may be referred to as Tperiod. In some examples, the memory system controller 215 may compare Tperiod with a first threshold (e.g., TH_low), and may increase Tpsm if Tperiod does not satisfy the threshold (e.g., if Tperiod<TH_low). Additionally, the memory system controller 215 may compare Tperiod with a second threshold (e.g., TH_high), and may decrease Tpsm if Tperiod satisfies the threshold (e.g., if Tperiod>TH_high).

[0069] Accordingly, if no command is received within Tpsm, the memory system 210 may transition from the power saving mode to the sleep mode. By increasing Tpsm when the memory system controller 215 receives commands from the host system 205 at relatively short intervals, the latency incurred by the memory system 210 when transitioning power modes can be improved. That is, since the memory system 210 can transition from the power saving mode to the active mode faster than transitioning from the sleep mode to the active mode, latency can be improved by increasing Tpsm under heavy load conditions. Additionally or alternatively, by decreasing Tpsm when the memory system controller 215 receives commands from the host system 205 at relatively long intervals, the memory system 210 can achieve additional power savings by transitioning to the sleep mode more quickly.

[0070] Figure 3 An example of a timing diagram 300 supporting dynamic power control according to examples disclosed herein is shown. The timing diagram 300 may illustrate a power consumption signal 305, a mode signal 310, and a command signal 315. The power consumption signal 305 may illustrate the power consumption of a memory device (e.g., as referenced in Figure 2 the memory system 210 described herein), and the mode signal 310 may illustrate signals being transmitted from a memory controller (e.g., as referenced in Figure 2 the memory system controller 215 described herein) for the memory system to transition power modes. Additionally, the command signal 315 may illustrate commands being transmitted from a host device (e.g., as referenced in Figure 2 the host system 205 described herein) to the memory device.

[0071] As described herein, a memory device can be configured to dynamically adjust the duration (e.g., Tpsm) for transitioning to a power-saving mode. By dynamically adjusting the duration of the transition from a power-saving mode to a sleep mode, the memory device can remain in a power-saving mode while receiving commands at relatively short intervals, which reduces latency that would otherwise be attributed to the memory device transitioning to a sleep mode. Furthermore, the memory device can be configured to transition to a sleep mode while receiving commands at relatively long intervals, which reduces the overall power consumption of the memory device.

[0072] During t1, the memory device may operate in a first power mode (e.g., normal mode, active mode). When operating in the first power mode, the memory device cannot initiate any power saving relative to a second power mode (e.g., power saving mode) or a third power mode (e.g., sleep mode, hibernation mode). That is, all or most of the components of the memory device may be powered in the first power mode, and the power consumption of the memory device may be at or near the first power level 320. Furthermore, the memory device may receive commands from the host device at intervals that would not cause the memory device to enter a second power mode. For example, the duration between at least some commands received during t1 may not meet the threshold duration that would otherwise cause the memory device to transition from the first power mode to the second power mode. In some instances, the memory device may receive a first command 325 during t1, which may be indicated by a command signal 315 going high.

[0073] During t2, the memory device may receive a second command 330, which may be indicated by the command signal 315 going high. In some examples, the duration 335 between the first command 325 and the second command 330 may satisfy a threshold duration for transitioning the memory device from a first power mode to a second power mode. The duration 335 may be referred to as Tperiod and may represent the duration between the currently received command and the previously received command. For example, the first command 325 may be received at a first time (e.g., T_old), and the second command 330 may be received at a second time (e.g., T_new). Tperiod may be calculated based on the difference between T_new and T_old (e.g., T_new - T_old).

[0074] In some examples, duration 335 may satisfy a threshold duration for the memory device to transition to a second power mode (e.g., a power-saving mode). The memory device may transition to the second power mode based on signal 337 (e.g., signal 337 corresponding to command 330), represented by mode signal 310 going high. Signal 337 may be emitted from the memory controller (e.g., as referenced). Figure 2The memory system controller 215 described herein transmits data to various components of the memory device. When operating in the second power mode, the memory device can achieve some power savings compared to the first power mode. That is, fewer components can be powered when the memory system operates in the second power mode, so the power consumption of the memory device can be at or near the second power level 340.

[0075] When operating in the second power mode, the memory device can set an initial duration (e.g., a first duration Tpsm) for transitioning to the third power mode. For example, if a command is received within Tpsm, the memory device can adjust Tpsm based on Tperiod. That is, if Tperiod is less than a first threshold or greater than a second threshold, Tpsm can be adjusted accordingly. However, if no command is received within Tpsm, the memory device can transition to the third power mode. Figure 3 As shown, during t2, the memory device can receive a third command 345, indicated by the command signal 315 going high, and can receive the third command within Tpsm.

[0076] In some instances, the duration 350 (e.g., Tperiod) between the second command 330 and the third command 345 can be compared with a first threshold and a second threshold to determine whether Tpsm should be adjusted. Regardless of whether Tpsm is adjusted, the memory device can exit the second power mode and enter (e.g., re-enter) the first power mode to process the third command 345. Accordingly, a signal 355 (e.g., corresponding to command 345) can be issued, which can be represented by the mode signal 310 going high, and the power consumption of the memory device can be at or near the first power level 320. The delay associated with the memory device transitioning from the second power state to the first power state can be relatively low. After processing the third command 345, the device can enter (e.g., re-enter) the second power mode based on a signal 360 that can be represented by the mode signal 310 going high. The power consumption of the memory device can return to the second power level 340 for duration t2.

[0077] During t3, the memory device cannot receive commands. That is, after receiving the third command 345, the memory device may not receive commands for at least one duration 365 (e.g., Tperiod) exceeding Tpsm. In some examples, the absence of a command for duration 365 may cause the memory device to transition from a second power mode (e.g., power-saving mode) to a third power mode (e.g., sleep mode, hibernation mode). The memory device may transition to the third power mode based on signal 370, indicated by mode signal 310 going high. Signal 370 may be emitted from the memory controller (e.g., as referenced). Figure 2The memory system controller 215 described herein transmits data to various components of the memory device. When operating in the third power mode, the memory device can achieve power savings compared to the first and second power modes. That is, when operating in the third power mode, very few or no components of the memory device can be powered, so the power consumption of the memory device can be at or near the third power level 375.

[0078] although Figure 3 Not shown, but the memory device can receive a fourth command after entering the third power mode. To process the fourth command, the memory device can exit the third power mode and enter (e.g., re-enter) the first power mode to process the fourth command. As described herein, the latency associated with the memory device transitioning from the third power mode to the first power mode can be higher than that when the memory device transitions from the second power mode to the first power mode. However, the power savings achieved by the memory device when operating in the third power mode can be greater than those when operating in the second power mode. Accordingly, dynamically adjusting Tpsm allows the memory device to optimize both latency and power savings.

[0079] Figure 4 An example of a block diagram 400 supporting dynamic power control according to the embodiments disclosed herein is shown. The block diagram may show a first power mode 405, a second power mode 410, and a third power mode 415 of a memory device. As described herein, the memory device can be configured to dynamically adjust the duration (e.g., Tpsm) for transitioning between power modes. By dynamically adjusting the duration of the transition from the second power mode 410 to the third power mode 415, the memory device can remain in the second power mode 410 when receiving commands at relatively short intervals, which reduces the latency that would otherwise be attributed to the memory device transitioning to the third power mode 415. Furthermore, the memory device can be configured to transition to the third power mode 415 when receiving commands at relatively long intervals, which reduces the overall power consumption of the memory device.

[0080] In some instances, the memory device may operate in a first power mode 405. As described herein, the first power mode 405 may also be referred to as an active mode or a normal power mode. When operating in the first power mode 405, the memory device may process data from a host device (e.g., as described in reference...). Figure 2 The host system 205 described receives commands (e.g., access commands). Furthermore, the memory device can consume more power compared to the second power mode 410 and the third power mode 415. That is, when operating in the first power mode, most or all of the components of the memory device can be powered.

[0081] In some examples, the memory device may operate in a second power mode 410. As described herein, the second power mode 410 may also be referred to as a power-saving mode. When operating in the second power mode 410, at least some components may be powered off. For example, in the second power mode 410, the controller (e.g., as described in reference...) Figure 2 At least a portion of the described memory system controller 215, the CPU, the bus (e.g., the ONFI bus), or at least a portion of the memory array can be de-energized. For example, some aspects of the memory device, such as a portion of the controller or a portion of the memory array, can remain powered, allowing the memory device to transition relatively quickly from the second power mode 410 to the first power mode. Accordingly, when operating in the second power mode 410, the memory device may consume less power than when operating in the first power mode 405, but more power than when operating in the third power mode 415.

[0082] The memory device can also operate in a third power mode 415. As described herein, the third power mode 415 may also be referred to as a sleep mode or hibernation mode. When operating in the third power mode 415, all or most of the components of the memory device can be powered off. For example, the memory array cannot be accessed while bias voltages or other voltages can still be applied to the memory device. That is, at least the controller (e.g., as referenced) Figure 2 The described memory system controller 215 and memory array can be powered off, making the memory array inaccessible. Accordingly, when operating in the third power mode 415, the memory device can consume less power than when operating in the first power mode 405 or the second power mode 410.

[0083] As described herein, the memory device can transition between power modes. For example, transition 420 may indicate that the memory device transitions from a first power mode 405 to a second power mode 410. Transition 420 may occur based on the host device becoming idle (e.g., based on the absence of commands received from the host device for a certain duration) or based on receiving a command instructing the memory device to transition to a power state. Furthermore, transition 425 may indicate that the memory device transitions from the second power mode 410 to a third power mode 415. Transition 425 may occur based on the memory device not receiving any commands for a duration longer than Tpsm (e.g., Tperiod). That is, if the host is idle for a duration longer than Tpsm, the memory device may transition from the second power mode 410 to the third power mode 415.

[0084] Alternatively, transition 430 may represent a transition of the memory device from a second power mode 410 to a first power mode 405. Transition 430 may occur based on the memory device receiving a command (e.g., an access command) while operating in the second power mode 410. In some examples, the memory device may transition to the first power mode 405 to process the command and may then transition back to the second power mode. In other examples, after receiving a command, the memory device may transition from the second power mode 410 to the first power mode 405 until the host becomes idle.

[0085] Furthermore, transition 435 may represent a transition of the memory device from a third power mode 415 to operation in a first power mode 405. Transition 435 may occur based on the memory device receiving a command (e.g., an access command) while operating in the third power mode 415. As described herein, transition 430 may occur faster than transition 435; however, the memory device may achieve additional power savings while operating in the third power mode 415. Accordingly, dynamically adjusting Tpsm allows the memory device to optimize performance and power savings based on the frequency at which commands are received from the host device.

[0086] Figure 5A An example of a process flow diagram 500-a supporting dynamic power control according to the examples disclosed herein is shown. In some instances, process flow diagram 500-a may illustrate various operations performed by a memory device to adjust the duration (e.g., Tpsm) of the transition from a second power state to a third power state. Aspects of process flow diagram 500-a may be controlled by a controller (e.g., as referenced). Figure 2 The described memory system controller 215), comparator (or multiple comparators), or state machine executes. Dynamically adjusting Tpsm allows the memory device to be based on the host device (e.g., as referenced). Figure 2 The described host system 205 receives commands at a frequency that optimizes performance and power savings.

[0087] At 505, the memory device can receive commands (e.g., a new command, a second command). In some instances, commands can be received from the host device and may be received at a certain time (e.g., T_new). In some instances, another command (e.g., a first command) may have been received at a time (e.g., T_old) before the second command was received.

[0088] At 510, the memory device can determine the duration (e.g., Tperiod) between receiving the first command and the second command. In some examples, Tperiod can be calculated using T_new - T_old. As described herein, Tperiod can be used to determine whether to adjust Tpsm.

[0089] At 515, the memory device can determine whether Tperiod satisfies one or more thresholds. For example, a first threshold (e.g., TH_low) and a second threshold (e.g., TH_high) are used to determine whether to adjust Tpsm. For example, if Tperiod does not satisfy TH_low (e.g., if Tperiod<TH_low), Tpsm can be increased. Additionally or alternatively, if Tperiod satisfies TH_high (e.g., if Tperiod>TH_high), Tpsm can be decreased. By way of example, TH_low may be 20 ms and TH_high may be 200 ms, however both TH_low and TH_high are configurable thresholds. In some examples, TH_low and TH_high may be programmed by a host device (e.g., based on commands received from the host device).

[0090] In some examples, at 515, Tperiod may satisfy the first threshold and may not satisfy the second threshold. That is, Tperiod may be between TH_low and TH_high (e.g., TH_low<Tperiod<TH_high), and therefore Tpsm may not be adjusted (e.g., Tpsm may be maintained at its current duration). In such examples, the memory device may not adjust Tpsm, and may restart the process described herein (e.g., the memory device may wait at 505 to receive a new command).

[0091] If Tperiod does not satisfy TH_low or if Tperiod satisfies TH_high, Tpsm may be adjusted at 520. In some examples, at 520, Tperiod may be transmitted to a state machine, and the state machine may update Tpsm based on Tperiod. As described herein, dynamically adjusting Tpsm may enable the memory device to optimize performance and power saving based on the frequency of receiving commands from the host device.

[0092] Figure 5B An example of a block diagram 500-b supporting dynamic power control according to examples disclosed herein is illustrated. In some examples, block diagram 500-b may represent different states managed by a state machine corresponding to different durations of Tpsm. For example, block diagram 500-b may show state 0 525, state 1 530, state 2 535, state 3 540, and state 4 545. In some examples, each state may be associated with a different Tpsm, and the state may be selected based on comparing Tperiod with the first threshold (e.g., TH_low) and the second threshold (e.g., TH_high). Although five states are illustrated and described herein, the memory device may include any number of states, and each state may be associated with a corresponding configurable Tpsm value.

[0093] In some examples, the memory device may initially be configured to operate in state 2 535. For example, state 2 535 may be associated with an intermediate Tpsm value (e.g., a Tpsm value between PSM_high and PSM_low). PSM_high may be associated with a maximum Tpsm duration corresponding to state 4 545, and PSM_low may be associated with a minimum Tpsm duration corresponding to state 0 525. For illustrative purposes only, PSM_high may be 110 ms, and PSM_low may be 10 ms. Additionally or alternatively, state 1 530, state 2 535, and state 3 540 may be associated with Tpsm values between PSM_high and PSM_low.

[0094] As referenced above Figure 5A described herein, when a command is received from a host device, the memory device may calculate Tperiod. The memory device may then compare Tperiod with TH_low and TH_high. If Tperiod does not satisfy a first threshold (e.g., if Tperiod<TH_low), the state machine or other components of the memory device may increase Tpsm. For example, transition 550 from state 0 525 to state 1 530 may occur when state 0 525 is enabled and the memory device receives a command with Tperiod<TH_low. Similarly, transitions 555, 560, and 565 may occur when the respective states are enabled and the memory device receives a command with Tperiod<TH_low. In some examples, Tpsm may not be increased beyond the value associated with state 4 545 (e.g., Tpsm may not be increased beyond PSM_high).

[0095] Additionally or alternatively, when a command is received from a host device, the memory device may calculate Tperiod and compare Tperiod with TH_high. If Tperiod satisfies a second threshold (e.g., if Tperiod>TH_high), the state machine or other components of the memory device may decrease Tpsm. For example, transition 585 from state 4 545 to state 3 540 may occur when state 4 545 is enabled and the memory device receives a command with Tperiod>TH_high. Similarly, transitions 580, 575, and 570 may occur when the respective states are enabled and the memory device receives a command with Tperiod>TH_high. In some examples, Tpsm may not be decreased beyond the value associated with state 0 525 (e.g., Tpsm may not be decreased below PSM_low).

[0096] In some examples, the memory device may use more than one duration (e.g., more than one Tperiod) before transitioning to a state. That is, the memory device may transition to a state based on a finite number of Tperiods failing to meet a first threshold or meeting a second threshold. The number of Tperiods used for state transitions can be programmable and can be set in relation to design choices. For example, the number of Tperiods used for state transitions can be three (3), such that three consecutive Tperiods (or three Tperiods within a fixed duration) must fail to meet either the first or the second threshold before a state transition occurs. Regardless of whether a finite number of Tperiods is required before a state transition occurs, dynamically adjusting Tpsm allows the memory device to optimize performance and power savings based on the frequency of commands received from the host device.

[0097] Figure 6 A block diagram 600 illustrates a memory device 620 supporting dynamic power control according to an example disclosed herein. The memory device 620 may be as described in the reference... Figure 1 Examples of aspects of the memory device described in section 5. The memory device 620 or its various components may be examples of means for performing various aspects of the dynamic power control as described herein. For example, the memory device 620 may include a duration component 625, a receiving component 630, a power management component 635, a determining component 640, a comparing component 645, or any combination thereof. Each of these components may communicate directly or indirectly with each other (e.g., via one or more buses).

[0098] Duration component 625 may be configured or otherwise supported for setting a first duration for operating the memory device in a second power mode different from the first power mode at a memory device comprising multiple memory cells. In some instances, duration component 625 may be configured or otherwise supported for adjusting the first duration for operating the memory device in the second power mode based at least in part on a second duration between receiving a first command and a second command.

[0099] In some instances, the duration component 625 may be configured or otherwise supported to include means for increasing the first duration at least partially based on determining that the second duration does not meet the first threshold. In some instances, the duration component 625 may be configured or otherwise supported to include means for decreasing the first duration at least partially based on determining that the second duration meets the second threshold. In some instances, the duration component 625 may be configured or otherwise supported to include means for maintaining the first duration at least partially based on determining that the second duration meets the first threshold but does not meet the second threshold.

[0100] The receiving component 630 may be configured or otherwise supported to receive a first command and a second command from the host device after a first duration for operating the memory device in a second power mode is set, wherein at least the second command is received after the memory device transitions from the first power mode to the second power mode. In some instances, the receiving component 630 may be configured or otherwise supported to receive a sixth command from the host device, wherein the sixth command is configured to adjust a first threshold, a second threshold, or both.

[0101] The power management component 635 may be configured or otherwise supported for operating the memory device in a second power mode for an adjusted first duration, at least in part based on an adjusted first duration, after receiving a third command while operating in a first power mode. In some instances, the power management component 635 may be configured or otherwise supported for operating the memory device in a third power mode for an adjusted first duration, at least in part based on a command received after the absence of a third command and within the adjusted first duration, while operating the memory device in a second power mode.

[0102] In some instances, to support adjusting the first duration for operating the memory device in a second power mode, the determining component 640 may be configured or otherwise supported to support means for determining the second duration corresponding to the time between receiving the first and second commands. In some instances, the determining component 640 may be configured or otherwise supported to support means for determining a third duration corresponding to the time between receiving a fourth and a fifth command, wherein the memory device transitions to the second power mode after receiving the fourth command, and wherein the memory device receives the fifth command after transitioning from the first power mode to the second power mode following the reception of the fourth command.

[0103] In some instances, the determining component 640 may be configured or otherwise supported for determining whether a second duration satisfies a first threshold, at least in part, based on comparing a second duration with a first threshold. In some instances, the determining component 640 may be configured or otherwise supported for determining whether a second duration satisfies a second threshold, at least in part, based on comparing a second duration with a first threshold and a second threshold. In some instances, the determining component 640 may be configured or otherwise supported for determining whether a second duration satisfies a first threshold and a second threshold, at least in part, based on comparing a second duration with a first threshold and a second threshold.

[0104] In some instances, to support adjustments to the first duration for operating the memory device in a second power mode, the comparison component 645 may be configured or otherwise supported to support means for comparing a second duration with a first threshold and a second threshold, wherein adjusting the first duration for operating the memory device in the second power mode is at least partially based on comparing the second duration with the first and second thresholds. In some instances, the comparison component 645 may be configured or otherwise supported to support means for comparing a third duration with the first and second thresholds, wherein adjusting the first duration for operating the memory device in the second power mode is at least partially based on comparing the third duration with the first and second thresholds.

[0105] In some instances, the second power mode comprises a power mode with a lower power level than the first power mode. In some instances, the third power mode comprises a power mode with a lower power level than the second power mode. In some instances, when operating in the second power mode, the controller remains powered while at least a subset of the plurality of memory cells is not powered.

[0106] Figure 7 A flowchart illustrating a method 700 supporting dynamic power control according to an example disclosed herein is provided. Operation of method 700 may be implemented by a memory device or its components as described herein. For example, operation of method 700 may be provided by a reference... Figures 1 to 6 The described memory device performs the functions described. In some instances, the memory device may execute a set of instructions to control the functional elements of the device to perform the described functions. Alternatively, the memory device may use dedicated hardware to perform aspects of the described functions.

[0107] At 705, the method may include setting a first duration for operating the memory device in a second power mode different from the first power mode at a memory device comprising a plurality of memory cells. The operation of 705 may be performed according to examples as disclosed herein. In some examples, aspects of the operation of 705 may be referenced... Figure 6 The duration component 625 described is executed.

[0108] At 710, the method may include receiving a first command and a second command from a host device after setting a first duration for operating the memory device in a second power mode, wherein at least the second command is received after the memory device transitions from the first power mode to the second power mode. Operation of 710 may be performed according to examples as disclosed herein. In some examples, aspects of the operation of 710 may be described by reference to... Figure 6 The described receiving component 630 is executed.

[0109] At 715, the method may include adjusting, at least in part, the first duration for operating the memory device in a second power mode based on a second duration between receiving the first and second commands. The operation of 715 may be performed according to examples disclosed herein. In some instances, aspects of the operation of 715 may be determined by reference to... Figure 6 The duration component 625 described is executed.

[0110] At 720, the method may include, after receiving a third command while operating in a first power mode, operating the memory device in a second power mode for an adjusted first duration, at least in part based on an adjusted first duration. The operation of 720 may be performed according to examples disclosed herein. In some examples, aspects of the operation of 720 may be referenced... Figure 6 The power management component 635 described is implemented.

[0111] In some instances, the device as described herein may perform one or more methods, such as method 700. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: setting a first duration at a memory device comprising a plurality of memory cells for operating the memory device in a second power mode different from a first power mode; receiving a first command and a second command from a host device after setting the first duration for operating the memory device in the second power mode, wherein at least the second command is received after the memory device transitions from the first power mode to the second power mode; adjusting the first duration for operating the memory device in the second power mode at least in part based on a second duration between receiving the first and second commands; and continuing the adjusted first duration for operating the memory device in the second power mode at least in part based on the adjusted first duration after receiving a third command while operating in the first power mode.

[0112] Some examples of the method 700 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for operating the memory device in a second power mode for an adjusted first duration, at least in part based on a command received after the absence of a third command and during the adjusted first duration.

[0113] In some instances of the method 700 and device described herein, the second power mode includes a power mode lower than the first power mode, and the third power mode includes a power mode lower than the second power mode.

[0114] In some instances of the method 700 and apparatus described herein, adjusting the first duration for operating the memory device in a second power mode may include operations, features, circuitry, logic, components, or instructions for: determining the second duration as corresponding to the time between receiving a first command and a second command; and comparing the second duration with a first threshold and a second threshold, wherein adjusting the first duration for operating the memory device in the second power mode may be based at least in part on comparing the second duration with the first threshold and the second threshold.

[0115] Some examples of the method 700 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for: determining a third duration as corresponding to the time between receiving a fourth command and a fifth command, wherein the memory device transitions to a second power mode after receiving the fourth command, and wherein the fifth command may be received after the memory device transitions from a first power mode to a second power mode following the receipt of the fourth command; and comparing the third duration with a first threshold and a second threshold, wherein adjusting the first duration for operating the memory device in the second power mode may be based at least in part on comparing the third duration with the first threshold and the second threshold.

[0116] Some examples of the method 700 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for: determining whether a second duration satisfies a first threshold based at least in part on comparing a second duration with a first threshold; and increasing a first duration based at least in part on determining that the second duration does not satisfy the first threshold.

[0117] Some examples of the method 700 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for: determining whether a second duration satisfies a second threshold based at least in part on comparing a second duration with a first threshold and a second threshold; and reducing a first duration based at least in part on determining that the second duration satisfies the second threshold.

[0118] Some examples of the method 700 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for: determining whether a second duration satisfies the first and second thresholds, at least in part, based on comparing a second duration with a first threshold and a second threshold; and maintaining a first duration, at least in part, based on determining that the second duration satisfies the first threshold and does not satisfy the second threshold.

[0119] Some examples of the method 700 and device described herein may further include operations, features, circuit systems, logic, components, or instructions for receiving a sixth command from a host device, wherein the sixth command may be configured to adjust a first threshold, a second threshold, or both.

[0120] In some instances of the method 700 and device described herein, when operating in a second power mode, the controller remains powered while at least a subset of the plurality of memory cells may not be powered.

[0121] It should be noted that the methods described above describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts of the methods can be combined.

[0122] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof. Some diagrams may show a signal as a single signal; however, the signal may represent a signal bus, which may have various bit widths.

[0123] The terms "electronic communication," "conductive contact," "connection," and "coupling" can refer to a relationship between components that supports the flow of electrons between them. Components are considered to be in electronic communication with each other (or in conductive contact, connected, or coupled) if any conductive path exists between them that can support the flow of signals between them at any given time. At any given time, the conductive path between components that are in electronic communication (or in conductive contact, connected, or coupled) can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path between the components, or it can be an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some instances, one or more intermediate components, such as switches or transistors, can be used to interrupt the signal flow between connected components for a period of time.

[0124] The term "coupling" refers to the condition that shifts from an open-circuit relationship between components to a closed-circuit relationship. In an open-circuit relationship, signals cannot currently travel between components via a conductive path, while in a closed-circuit relationship, signals can travel between components via a conductive path. If a component, such as a controller, couples other components together, this change initially allows signals to flow between other components via conductive paths that were previously not permitted.

[0125] The term "isolation" refers to a relationship between components where signals cannot currently flow between them. Components are isolated from each other if there is an open circuit between them. For example, components separated by a switch located between two components are isolated from each other when the switch is open. If a controller isolates two components, it prevents signals from flowing between the components using previously permitted conductive paths.

[0126] The terms “if,” “when,” “based on,” or “at least partially based on” are used interchangeably. In some instances, these terms are used interchangeably when describing a conditional action, a conditional process, or a connection between parts of a process.

[0127] The term "in response to" can refer to a condition or action that occurs at least partially (if not completely) as a result of a preceding condition or action. For example, a first condition or action may be performed, and a second condition or action may occur at least partially as a result of the preceding condition or action (whether directly after or following one or more other intermediate conditions or actions).

[0128] Additionally, the term "directly in response to" can refer to a condition or action occurring as a direct result of a previous condition or action. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of the occurrence of a previous condition or action, regardless of whether other conditions or actions occur. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of the occurrence of a previous condition or action, such that no other intermediate conditions or actions occur between the earlier condition or action and the second condition or action, or a limited number of one or more intermediate steps or actions occur between the earlier condition or action and the second condition or action. Unless otherwise specified, any condition or action described herein as being performed "based on," "at least in part based on," or "in response to" a certain other step, action, event, or condition may additionally or alternatively (e.g., in alternative instances) be performed "directly in response to" this other condition or action.

[0129] The devices discussed herein, including memory arrays, can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, and gallium nitride. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemicals including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, either by ion implantation or by any other doping method.

[0130] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include a three-terminal device comprising a source, a drain, and a gate. The terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may comprise heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or a channel. If the channel is n-type (i.e., the majority carriers are electrons), the FET may be called an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), the FET may be called a p-type FET. The channel may be capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. If a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "on" or "activated." If a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "off" or "deactivated."

[0131] The description herein, illustrated with reference to the accompanying drawings, describes exemplary configurations and does not represent all instances that can be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description" and is not "preferred" or "superior" to other instances. The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some cases, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0132] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by a hyphen following the reference numeral and a second numeral used to differentiate among similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, regardless of the second reference numeral.

[0133] The functionality described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functionality can be stored as one or more instructions or code on or transmitted through a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functionality described above can be implemented in software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functionality can also be physically located in various locations, including distributed implementations such that portions of the functionality are implemented in different physical locations.

[0134] For example, the various illustrative blocks and components described in connection with the disclosure herein may be implemented or executed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device designed to perform the functions described herein, discrete gate or transistor logic, discrete hardware components, or any combination thereof. A general-purpose processor may be a microprocessor; however, alternatively, the processor may be any processor, controller, microcontroller, or state machine. The processor may be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a combination of multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0135] As used herein, the word "or" in a list of items contained in the claims (e.g., a list of items beginning with phrases such as "at least one of" or "one or more of") indicates an inclusive list, such that a list of at least one of A, B, or C means A or B or C, or AB or AC or BC, or ABC (i.e., A and B and C). Additionally, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "at least partially based on".

[0136] Computer-readable media includes both non-transitory computer storage media and communication media, with communication media encompassing any medium that facilitates the transfer of a computer program from one place to another. Non-transitory storage media can be any available medium accessible by a general-purpose or special-purpose computer. By way of example, and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory medium that can be used to carry or store desired program code components in the form of instructions or data structures and is accessible by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of media. As used in this article, disks and optical discs include CDs, laser discs, optical discs, digital multifunction discs (DVDs), floppy disks, and Blu-ray discs. Disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of these are also included within the scope of computer-readable media.

[0137] The description provided herein enables those skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but should be given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A memory device comprising: Multiple memory units; as well as A controller, coupled to and operable to: A first duration is set for operating the memory device in a second power mode different from the first power mode; After setting a first duration for operating the memory device in the second power mode, a first command and a second command are received from the host device, wherein at least the second command is received after the memory device transitions from the first power mode to the second power mode; The second duration is determined to correspond to the time between receiving the first command and the second command; The second duration is compared with the first threshold and the second threshold; The first duration for operating the memory device in the second power mode is adjusted at least in part based on comparing the second duration with the first threshold and the second threshold; as well as After receiving a third command while operating in the first power mode, the memory device continues to operate in the second power mode for the adjusted first duration, at least in part based on the adjustment of the first duration.

2. The memory device of claim 1, wherein the controller is operable to: After operating the memory device in the second power mode for the adjusted first duration, the memory device is then operated in the third power mode, at least in part based on the absence of the third command and the command received during the adjusted first duration.

3. The memory device of claim 2, wherein the second power mode includes a power mode lower than the first power mode, and wherein the third power mode includes a power mode lower than the second power mode.

4. The memory device of claim 1, wherein the controller is operable to: The third duration is defined as the time between receiving the fourth command and the fifth command, wherein the memory device transitions to the second power mode after receiving the fourth command, and wherein the memory device receives the fifth command after transitioning from the first power mode to the second power mode following the receipt of the fourth command; and The third duration is compared with the first threshold and the second threshold, wherein the adjustment of the first duration for operating the memory device in the second power mode is at least in part based on comparing the third duration with the first threshold and the second threshold.

5. The memory device of claim 1, wherein the controller is operable to: Determining whether the second duration satisfies the first threshold is based at least in part on comparing the second duration with the first threshold; and The first duration is increased at least in part based on the determination that the second duration does not meet the first threshold.

6. The memory device of claim 1, wherein the controller is operable to: The determination of whether the second duration satisfies the second threshold is based at least in part on comparing the second duration with the first threshold and the second threshold; and The first duration is reduced, at least in part, based on the determination that the second duration satisfies the second threshold.

7. The memory device of claim 1, wherein the controller is operable to: The determination of whether the second duration satisfies the first and second thresholds is based at least in part on comparing the second duration with the first and second thresholds; and The first duration is maintained at least in part based on determining that the second duration satisfies the first threshold and does not satisfy the second threshold.

8. The memory device of claim 1, wherein the controller is operable to: A sixth command is received from the host device, wherein the sixth command is configured to adjust the first threshold, the second threshold, or both.

9. The memory device of claim 1, wherein when operating in the second power mode, the controller remains powered while at least a subset of the plurality of memory cells is not powered.

10. A non-transitory computer-readable medium storing code comprising instructions that, when executed by a processor of a memory device, cause the memory device to: A first duration is set at the memory device comprising multiple memory cells for operating the memory device in a second power mode different from the first power mode; After setting a first duration for operating the memory device in the second power mode, a first command and a second command are received from the host device, wherein at least the second command is received after the memory device transitions from the first power mode to the second power mode; The second duration is defined as the time between receiving the first command and the second command; The second duration is compared with the first threshold and the second threshold; The first duration for operating the memory device in the second power mode is adjusted at least in part based on comparing the second duration with the first threshold and the second threshold; as well as After receiving a third command while operating in the first power mode, the operation in the second power mode continues for the adjusted first duration, at least in part based on the adjustment of the first duration.

11. The non-transitory computer-readable medium of claim 10, wherein the instructions, when executed by the processor of the memory device, further cause the memory device to: The operation in the second power mode continues for the adjusted first duration and then operates in the third power mode, based at least in part on the absence of the third command and the command received during the adjusted first duration.

12. The non-transitory computer-readable medium of claim 11, wherein the second power mode includes a power mode lower than the first power mode, and wherein the third power mode includes a power mode lower than the second power mode.

13. The non-transitory computer-readable medium of claim 10, wherein the instructions, when executed by the processor of the memory device, further cause the memory device to: The third duration is defined as the time between receiving the fourth command and the fifth command, wherein the memory device transitions to the second power mode after receiving the fourth command, and wherein the memory device receives the fifth command after transitioning from the first power mode to the second power mode following the receipt of the fourth command; and The third duration is compared with the first threshold and the second threshold, wherein the adjustment of the first duration for operating the memory device in the second power mode is at least in part based on comparing the third duration with the first threshold and the second threshold.

14. The non-transitory computer-readable medium of claim 10, wherein the instructions, when executed by the processor of the memory device, further cause the memory device to: Determining whether the second duration satisfies the first threshold is based at least in part on comparing the second duration with the first threshold; and The first duration is increased at least in part based on the determination that the second duration does not meet the first threshold.

15. The non-transitory computer-readable medium of claim 10, wherein the instructions, when executed by the processor of the memory device, further cause the memory device to: The determination of whether the second duration satisfies the second threshold is based at least in part on comparing the second duration with the first threshold and the second threshold; and The first duration is reduced, at least in part, based on the determination that the second duration satisfies the second threshold.

16. The non-transitory computer-readable medium of claim 10, wherein the instructions, when executed by the processor of the memory device, further cause the memory device to: The determination of whether the second duration satisfies the first and second thresholds is based at least in part on comparing the second duration with the first and second thresholds; and The first duration is maintained at least in part based on determining that the second duration satisfies the first threshold and does not satisfy the second threshold.

17. The non-transitory computer-readable medium of claim 10, wherein the instructions, when executed by the processor of the memory device, further cause the memory device to: A sixth command is received from the host device, wherein the sixth command is configured to adjust the first threshold, the second threshold, or both.

18. A method performed at a memory device, comprising: A first duration is set at the memory device comprising multiple memory cells for operating the memory device in a second power mode different from the first power mode; After setting a first duration for operating the memory device in the second power mode, a first command and a second command are received from the host device, wherein at least the second command is received after the memory device transitions from the first power mode to the second power mode; The second duration is defined as the time between receiving the first command and the second command; The second duration is compared with the first threshold and the second threshold; The first duration for operating the memory device in the second power mode is adjusted at least in part based on comparing the second duration with the first threshold and the second threshold; as well as After receiving a third command while operating in the first power mode, the memory device continues to operate in the second power mode for the adjusted first duration, at least in part based on the adjustment of the first duration.

19. The method of claim 18, further comprising: After operating the memory device in the second power mode for the adjusted first duration, the memory device is then operated in the third power mode, at least in part based on the absence of the third command and commands received during the adjusted first duration.

20. The method of claim 19, wherein the second power mode includes a power mode lower than the first power mode, and wherein the third power mode includes a power mode lower than the second power mode.

21. The method of claim 18, further comprising: The third duration is defined as the time between receiving the fourth command and the fifth command, wherein the memory device transitions to the second power mode after receiving the fourth command, and wherein the memory device receives the fifth command after transitioning from the first power mode to the second power mode following the receipt of the fourth command. as well as The third duration is compared with the first threshold and the second threshold, wherein the adjustment of the first duration for operating the memory device in the second power mode is at least in part based on comparing the third duration with the first threshold and the second threshold.

22. The method of claim 18, further comprising: Whether the second duration satisfies the first threshold is determined at least in part based on comparing the second duration with the first threshold; as well as The first duration is increased at least in part based on the determination that the second duration does not meet the first threshold.

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