Sensitive amplifier circuit

Abstract

This invention discloses a power-compensated sensitive amplifier, in which the source terminals of the fourth and fifth PMOS transistors and the drain terminals of the first and second NMOS transistors are connected to the same power supply voltage; the gate terminals of the second and third PMOS transistors are short-circuited; the source terminal of the second PMOS transistor is connected to the source terminal of the first NMOS transistor, and its drain terminal is connected to the drain terminals of the fourth and third NMOS transistors; the source terminal of the third PMOS transistor is connected to the drain terminal of the second NMOS transistor, and its drain terminal is connected to the drain terminals of the fifth and fourth NMOS transistors; the gate terminals of the fourth and fifth PMOS transistors are short-circuited; the gate terminals of the third and fourth NMOS transistors are short-circuited; the source terminal of the third NMOS transistor (N3) is connected to a reference current source; the source terminal of the fourth NMOS transistor is used to receive the amplified current; a compensation circuit is used to generate a compensation voltage; the gate terminals of the first and second NMOS transistors are connected to the same compensation voltage; the compensation voltage is higher than the power supply voltage. This power-compensated sensitive amplifier improves voltage dependence characteristics, making it suitable for wide-voltage applications.

Description

Technical Field

[0001] The present invention relates to semiconductor integrated circuit memory technology, and particularly to a power supply compensated sense amplifier circuit. Background Art

[0002] A sense amplifier (SA) in a memory circuit is used to read data stored in the memory. Its principle is to compare the current (Icell) of the selected memory cell with a reference current (IREF). If Icell > IREF, "1" is read, and if Icell < IREF, "0" is read. It can also be the other way around.

[0003] A traditional sense amplifier circuit is as Figure 1 shown. It includes a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, a fourth NMOS transistor N4, a second PMOS transistor P2, a third PMOS transistor P3, a fourth PMOS transistor P4, a fifth PMOS transistor P5, and a reference current source IREF; the source terminals of the second PMOS transistor P2, the third PMOS transistor P3, the fourth PMOS transistor P4, and the fifth PMOS transistor P5 and the gate terminals of the first NMOS transistor N1 and the second NMOS transistor N2 are connected to the power supply voltage VDD; the gate terminals of the second PMOS transistor P2 and the third PMOS transistor P3 are shorted and used to connect to the read enable terminal SAENB; the gate terminals of the fourth PMOS transistor P4 and the fifth PMOS transistor P5 are shorted and used to connect to the precharge terminal PCHB; for the first NMOS transistor N1, its drain terminal is connected to the drain terminal of the second PMOS transistor P2, and its source terminal is connected to the drain terminal of the fourth PMOS transistor P4 and the drain terminal of the third NMOS transistor N3; for the second NMOS transistor N2, its drain terminal is connected to the drain terminal of the third PMOS transistor P3, and its source terminal is connected to the drain terminal of the fifth PMOS transistor P5 and the drain terminal of the fourth NMOS transistor N4; the gate terminals of the third NMOS transistor N3 and the fourth NMOS transistor N4 are shorted; the source terminal of the third NMOS transistor N3 is connected to the reference current source IREF; the source terminal of the fourth NMOS transistor N4 is connected to the bit line of the memory array.

[0004] In traditional sensitive amplifier circuits, the first NMOS transistor N1 and the second NMOS transistor N2 typically use power dissipators with threshold voltages close to 0. These power dissipators have their gates connected to the power supply voltage VDD and operate in the linear region, essentially functioning as resistors. During read operation, the precharge terminal PCHB and the read enable terminal SAENB are simultaneously set low, turning on the precharge transistors (fourth PMOS transistor P4 and fifth PMOS transistor P5) in the diagram. This precharges the sources of the third NMOS transistor N3 and the fourth NMOS transistor N4 to the VLIM-Vth voltage, where VLIM is the clamping voltage used to clamp the memory array BL (bit line) voltage, and Vth is the threshold voltage of N3 and N4. Then, the precharge terminal PCHB is set high, turning off the fourth PMOS transistor P4 and the fifth PMOS transistor P5, thus entering the detection phase. Since the first NMOS transistor N1 and the second NMOS transistor N2 operate in the linear region, they can be considered as a resistor (with a resistance value of R). In this case, the voltage at the first amplifier output terminal OUTA = VDD - IREF * R; the voltage at the second amplifier output terminal OUTB = VDD - Icell * R. The sensitive amplifier circuit converts the current signal into a voltage signal and outputs it to the next stage latch.

[0005] In traditional sensitive amplifier circuits, the resistance values ​​of the first NMOS transistor N1 and the second NMOS transistor N2 are greatly affected by the power supply voltage VDD and the process angle of the power dissipation, which limits the characteristics and operating voltage range of the sensitive amplifier. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide a power-compensated sensitive amplifier that can improve voltage dependence characteristics and make it suitable for wide voltage applications.

[0007] To solve the above-mentioned technical problems, the present invention provides a power compensation sensitive amplifier, which includes a compensation circuit and a sensitive amplifier circuit.

[0008] The sensitive amplifier circuit includes a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, a fourth NMOS transistor N4, a second PMOS transistor P2, a third PMOS transistor P3, a fourth PMOS transistor P4, a fifth PMOS transistor P5, and a reference current source IREF.

[0009] The source terminals of the fourth PMOS transistor P4 and the fifth PMOS transistor P5, and the drain terminals of the first NMOS transistor N1 and the second NMOS transistor N2 are connected to the power supply voltage VDD.

[0010] The gate terminals of the second PMOS transistor P2 and the third PMOS transistor P3 are shorted to connect to the read enable terminal SAENB.

[0011] The second PMOS transistor P2 has its source terminal connected to the source terminal of the first NMOS transistor N1, and its drain terminal connected to the drain terminal of the fourth PMOS transistor P4 and the drain terminal of the third NMOS transistor N3.

[0012] The source of the third PMOS transistor P3 is connected to the drain of the second NMOS transistor N2, and its drain is connected to the drain of the fifth PMOS transistor P5 and the drain of the fourth NMOS transistor N4.

[0013] The gate terminals of the fourth PMOS transistor P4 and the fifth PMOS transistor P5 are shorted to connect to the pre-charge terminal PCHB;

[0014] The gate terminals of the third NMOS transistor N3 and the fourth NMOS transistor N4 are shorted;

[0015] The source terminal of the third NMOS transistor N3 is connected to the reference current source IREF;

[0016] The source terminal of the fourth NMOS transistor N4 is used to receive the amplified current;

[0017] The compensation circuit is used to generate the compensation voltage VCOMP;

[0018] The gate terminals of the first NMOS transistor N1 and the second NMOS transistor N2 are connected to the same compensation voltage VCOMP;

[0019] The compensation voltage VCOMP is higher than the power supply voltage VDD.

[0020] Preferably, VCOMP = VDD + Vds, where Vds is the source-drain voltage drop of the first NMOS transistor N1 or the second NMOS transistor N2 operating in the linear region.

[0021] Preferably, the current to be amplified is the read current of the storage unit.

[0022] Preferably, the source terminal of the fourth NMOS transistor N4 is used to connect to the memory cell bit line;

[0023] The gate terminals of the third NMOS transistor N3 and the fourth NMOS transistor N4 are connected to the clamping voltage VLIM.

[0024] VLIM≥VBL+Vth; VBL is the bit line voltage of the memory cell, and Vth is the threshold voltage of the fourth NMOS transistor N4.

[0025] Preferably, the compensation circuit includes a zeroth NMOS transistor N0, a zeroth PMOS transistor P0, a first PMOS transistor P1, and a comparison current source ICOMP;

[0026] The source terminals of the zeroth PMOS transistor P0 and the first PMOS transistor P1 are connected to the charge pump output voltage VPP, where VPP > VDD;

[0027] The gate and drain terminals of the zeroth PMOS transistor P0 and the gate terminal of the first PMOS transistor P1 are shorted and then connected to the comparator current source ICOMMP.

[0028] The drain of the first PMOS transistor P1 is connected to the gate and drain of the zeroth NMOS transistor N0, and serves as the output terminal of the compensation voltage VCOMP.

[0029] The source terminal of the zeroth NMOS transistor N0 is connected to the power supply voltage VDD.

[0030] Preferably, the zeroth NMOS transistor N0 is of the same type as the first NMOS transistor N1 and the second NMOS transistor N2.

[0031] Preferably, the zeroth NMOS transistor N0, the first NMOS transistor N1, and the second NMOS transistor N2 are all enhancement-mode NMOS transistors.

[0032] The power-compensated sensitive amplifier of the present invention incorporates a compensation circuit, which improves the voltage dependence characteristics of traditional sensitive amplifier circuits, making them suitable for wide voltage applications. Attached Figure Description

[0033] To more clearly illustrate the technical solution of the present invention, the accompanying drawings used in the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1 It is a traditional sensitive amplifier circuit;

[0035] Figure 2 This is a circuit diagram of an embodiment of the power compensation sensitive amplifier of the present invention. Detailed Implementation

[0036] The technical solutions of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0037] Example 1

[0038] like Figure 2 As shown, the power supply compensation sensitive amplifier includes a compensation circuit and a sensitive amplifier circuit.

[0039] The sensitive amplifier circuit includes a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, a fourth NMOS transistor N4, a second PMOS transistor P2, a third PMOS transistor P3, a fourth PMOS transistor P4, a fifth PMOS transistor P5, and a reference current source IREF.

[0040] The source terminals of the fourth PMOS transistor P4 and the fifth PMOS transistor P5, and the drain terminals of the first NMOS transistor N1 and the second NMOS transistor N2 are connected to the power supply voltage VDD.

[0041] The gate terminals of the second PMOS transistor P2 and the third PMOS transistor P3 are shorted to connect to the read enable terminal SAENB.

[0042] The second PMOS transistor P2 has its source terminal connected to the source terminal of the first NMOS transistor N1, and its drain terminal connected to the drain terminal of the fourth PMOS transistor P4 and the drain terminal of the third NMOS transistor N3.

[0043] The source of the third PMOS transistor P3 is connected to the drain of the second NMOS transistor N2, and its drain is connected to the drain of the fifth PMOS transistor P5 and the drain of the fourth NMOS transistor N4.

[0044] The gate terminals of the fourth PMOS transistor P4 and the fifth PMOS transistor P5 are shorted to connect to the pre-charge terminal PCHB;

[0045] The gate terminals of the third NMOS transistor N3 and the fourth NMOS transistor N4 are shorted;

[0046] The source terminal of the third NMOS transistor N3 is connected to the reference current source IREF;

[0047] The source terminal of the fourth NMOS transistor N4 is used to receive the amplified current;

[0048] The compensation circuit is used to generate the compensation voltage VCOMP;

[0049] The gate terminals of the first NMOS transistor N1 and the second NMOS transistor N2 are connected to the same compensation voltage VCOMP;

[0050] The compensation voltage VCOMP is higher than the power supply voltage VDD.

[0051] The power-compensated sensitive amplifier in Example 1 incorporates a compensation circuit, which improves the voltage dependence characteristics of traditional sensitive amplifier circuits, making it suitable for wide voltage applications.

[0052] Example 2

[0053] Based on the power-compensated sensitive amplifier of Embodiment 1, VCOMP = VDD + Vds, where Vds is the source-drain voltage drop of the first NMOS transistor N1 or the second NMOS transistor N2 operating in the linear region.

[0054] Preferably, the current to be amplified is the read current (Icell) of the storage cell.

[0055] Preferably, the source terminal of the fourth NMOS transistor N4 is used to connect to the memory cell bit line;

[0056] The gate terminals of the third NMOS transistor N3 and the fourth NMOS transistor N4 are connected to the clamping voltage VLIM.

[0057] VLIM≥VBL+Vth; VBL is the bit line voltage of the memory cell, and Vth is the threshold voltage of the fourth NMOS transistor N4.

[0058] Example 3

[0059] Based on the power compensation sensitive amplifier of Embodiment 1, the compensation circuit includes a zeroth NMOS transistor N0, a zeroth PMOS transistor P0, a first PMOS transistor P1, and a comparison current source ICOMP.

[0060] The source terminals of the zeroth PMOS transistor P0 and the first PMOS transistor P1 are connected to the charge pump output voltage VPP, where VPP > VDD;

[0061] The gate and drain terminals of the zeroth PMOS transistor P0 and the gate terminal of the first PMOS transistor P1 are shorted and then connected to the comparator current source ICOMMP.

[0062] The drain of the first PMOS transistor P1 is connected to the gate and drain of the zeroth NMOS transistor N0, and serves as the output terminal of the compensation voltage VCOMP.

[0063] The source terminal of the zeroth NMOS transistor N0 is connected to the power supply voltage VDD.

[0064] Example 3: Power supply compensation sensitive amplifier. The operating voltage of its compensation circuit is the charge pump output voltage VPP, which generates the compensation voltage VCOMP through a mirror current source circuit.

[0065] Example 4

[0066] Based on the power compensation sensitive amplifier in Embodiment 3, the zeroth NMOS transistor N0 is of the same type as the first NMOS transistor N1 and the second NMOS transistor N2 (both are depletion-type NMOS transistors or both are enhancement-type NMOS transistors).

[0067] Example 4: Power-compensated sensitive amplifier. The NMOS transistor that generates the compensation voltage VCOMP is the same type as the NMOS transistors (N1 and N2) in the sensitive amplifier circuit. Therefore, it can not only improve the voltage characteristics of the sensitive amplifier, but also compensate for the influence of the NMOS process corner, thus playing a compensation role.

[0068] Example 5

[0069] Based on the power compensation sensitive amplifier of Embodiment 3, the zeroth NMOS transistor N0, the first NMOS transistor N1, the second NMOS transistor N2, the third NMOS transistor N3, and the fourth NMOS transistor N4 are all enhancement-type NMOS transistors.

[0070] The power-compensated sensitive amplifier in Example 5 replaces the first NMOS transistor N1 and the second NMOS transistor N2, which operate in the linear region of the sensitive amplifier circuit, with enhancement-type NMOS transistors and adds a compensation circuit. Since the compensation voltage VCOMP generated by this compensation circuit is higher than the power supply voltage VDD and is related to the source-drain voltage drop of the enhancement-type zeroth NMOS transistor N0, the compensation voltage VCOMP varies with the power supply voltage VDD and the process angle of the NMOS transistors. When the threshold voltage of the zeroth NMOS transistor N0 is low, the compensation voltage VCOMP is also low; conversely, the compensation voltage VCOMP is also high. Therefore, the equivalent resistance of the first NMOS transistor N1 and the second NMOS transistor N2 operating in the linear region remains essentially unchanged, effectively improving the voltage dependence characteristics of the sensitive amplifier and making it suitable for wide-voltage applications.

[0071] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A power-compensated sensitive amplifier, characterized in that, It includes a compensation circuit and a sensitive amplifier circuit; The sensitive amplifier circuit includes a first NMOS transistor (N1), a second NMOS transistor (N2), a third NMOS transistor (N3), a fourth NMOS transistor (N4), a second PMOS transistor (P2), a third PMOS transistor (P3), a fourth PMOS transistor (P4), a fifth PMOS transistor (P5), and a reference current source (IREF). The source terminals of the fourth PMOS transistor (P4) and the fifth PMOS transistor (P5), and the drain terminals of the first NMOS transistor (N1) and the second NMOS transistor (N2) are connected to the power supply voltage VDD. The gate terminals of the second PMOS transistor (P2) and the third PMOS transistor (P3) are shorted to connect to the read enable terminal (SAENB); The second PMOS transistor (P2) has its source terminal connected to the source terminal of the first NMOS transistor (N1), and its drain terminal connected to the drain terminal of the fourth PMOS transistor (P4) and the drain terminal of the third NMOS transistor (N3). The source terminal of the third PMOS transistor (P3) is connected to the drain terminal of the second NMOS transistor (N2), and its drain terminal is connected to the drain terminal of the fifth PMOS transistor (P5) and the drain terminal of the fourth NMOS transistor (N4). The gate terminals of the fourth PMOS transistor (P4) and the fifth PMOS transistor (P5) are shorted to connect to the precharge terminal (PCHB); The gate terminals of the third NMOS transistor (N3) and the fourth NMOS transistor (N4) are shorted; The source terminal of the third NMOS transistor (N3) is connected to the reference current source (IREF); The source terminal of the fourth NMOS transistor (N4) is used to receive the amplified current; The compensation circuit is used to generate the compensation voltage VCOMP; The gate terminals of the first NMOS transistor (N1) and the second NMOS transistor (N2) are connected to the same compensation voltage VCOMP; The compensation voltage VCOMP is higher than the power supply voltage VDD; The compensation circuit includes a zeroth NMOS transistor (N0), a zeroth PMOS transistor (P0), a first PMOS transistor (P1), and a comparison current source ICOMMP; The source terminals of the zeroth PMOS transistor (P0) and the first PMOS transistor (P1) are connected to the charge pump output voltage VPP, where VPP > VDD; The gate and drain terminals of the zeroth PMOS transistor (P0) and the gate terminal of the first PMOS transistor (P1) are shorted and then connected to the comparator current source ICOMMP. The drain of the first PMOS transistor (P1) is connected to the gate and drain of the zeroth NMOS transistor (N0) and serves as the output terminal of the compensation voltage VCOMP. The source terminal of the zeroth NMOS transistor (N0) is connected to the power supply voltage VDD.

2. The power supply compensation sensitive amplifier according to claim 1, characterized in that, VCOMP = VDD + Vds, where Vds is the source-drain voltage drop of the first NMOS transistor (N1) or the second NMOS transistor (N2) operating in the linear region.

3. The power supply compensation sensitive amplifier according to claim 1, characterized in that, The current to be amplified is the read current of the storage unit.

4. The power supply compensation sensitive amplifier according to claim 3, characterized in that, The source terminal of the fourth NMOS transistor (N4) is used to connect to the memory cell bit line; The gate terminals of the third NMOS transistor (N3) and the fourth NMOS transistor (N4) are connected to the clamping voltage VLIM. VLIM≥VBL+Vth; VBL is the bit line voltage of the memory cell, and Vth is the threshold voltage of the fourth NMOS transistor (N4).

5. The power-compensated sensitive amplifier according to claim 1, characterized in that, The zeroth NMOS transistor (N0) is of the same type as the first NMOS transistor (N1) and the second NMOS transistor (N2).

6. The power supply compensation sensitive amplifier according to claim 1, characterized in that, The zeroth NMOS transistor (N0), along with the first NMOS transistor (N1) and the second NMOS transistor (N2), are all enhancement-mode NMOS transistors.

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