Reference level calibration using soft bits of decoded data

Abstract

Calibration of soft bit reference levels in a non-volatile memory system is disclosed. When the soft bit reference levels are to be calibrated, encoded data is read from a group of memory cells. The encoded data is decoded and error corrected. Thus, the original data programmed into the memory cells is recovered. The group of memory cells is sensed at candidate soft bit reference levels and possibly other reference levels. For each candidate soft bit reference level, the mutual information between the original programmed data and the data for the candidate soft bit reference level is determined. The mutual information serves as a good measure of how well the candidate soft bit reference level will aid in decoding the data. In one aspect, the soft bit reference level of the number of candidates having the highest mutual information is selected as the calibrated soft bit reference level.

Description

Background Technology

[0001] The robust growth in demand for portable consumer electronics devices has driven the need for high-capacity storage devices. Non-volatile semiconductor memory devices (also referred to herein as "non-volatile memory systems"), such as flash memory cards, are widely used to meet the increasing demands for digital information storage and exchange. Their portability, versatility, and rugged design, along with their high reliability and large capacity, make these memory devices ideal for use in a variety of host electronic devices, including, for example, digital cameras, digital music players, video game controllers, PDAs, cellular phones, desktop computers, laptops, and notebook computers. Typically, host electronic devices provide power to non-volatile memory systems.

[0002] Storing multiple bits of information in a single nonvolatile memory cell typically involves mapping a sequence of bits to states of the nonvolatile memory cell. For example, a first sequence of bits "110" could correspond to a first state of the nonvolatile memory cell, and a second sequence of bits "010" could correspond to a second state of the nonvolatile memory cell. After determining that a sequence of bits is to be stored in a particular nonvolatile memory cell, the nonvolatile memory cell can be programmed with states corresponding to that sequence of bits.

[0003] Once a memory cell in a memory device has been programmed, data can be read from the memory cell by sensing its programming state. In one technique, the memory cell is sensed at one or more "hard bit reference voltages." The hard bit reference voltage is used to distinguish between the two states. However, due to one or more factors, the sensed state can sometimes differ from the written programming state. Error detection and correction decoding can be used to detect and correct data errors caused by a sensed state that does not match the written programming state. Some error correction decoding uses only "hard bits," which are derived from the sensing of the hard bit reference voltage.

[0004] Improved error correction capabilities can be achieved by using soft-bit decoding data. Soft bits are derived by sensing memory cells using a set of "soft-bit reference voltages." The soft bits indicate the reliability of the hard bits for each memory cell. For illustration, soft bits can be used in conjunction with ECC (Error Correction Code) decoding to enhance error correction capabilities in non-volatile memory systems that may experience memory cell errors and internal transmission errors. For example, improved error correction capabilities can be achieved by using low-density parity-check (LDPC) codes and including soft-bit values ​​as input to the decoder, compared to decoding schemes based solely on hard bits.

[0005] In some techniques, one or more soft reference voltages exist on each side of each hard reference voltage. For example, a soft reference voltage may exist at a voltage slightly below the hard reference voltage, and a soft reference voltage may exist at a voltage slightly above the hard reference voltage. In some cases, two soft reference voltages exist on each side of the hard reference voltage. In some cases, three soft reference voltages exist on each side of the hard reference voltage.

[0006] However, error correction capability depends on the quality of soft reliability information. Using soft bits that are not sensed at the correct location (e.g., the correct voltage level) can degrade the quality of soft reliability information and reduce its informativeness. Setting the soft bit threshold is a trade-off. If the soft bit reference voltage is too close to the hard bit reference voltage, many errors will not be flagged as low reliability. On the other hand, if the soft bit reference voltage is too far from the hard bit reference voltage, too many correct bits will be flagged as unreliable. Attached Figure Description

[0007] Elements with similar numbers refer to common components in different attached drawings.

[0008] Figure 1A It is a block diagram of one implementation of a memory system connected to a host computer.

[0009] Figure 1B This is a block diagram of one implementation scheme of the front-end processor circuit.

[0010] Figure 2A This is a block diagram of one implementation scheme for the back-end processor circuit.

[0011] Figure 2B This is a block diagram of one implementation scheme of a memory package.

[0012] Figure 3A This is a functional block diagram of one implementation scheme for a memory die.

[0013] Figure 3B This is a functional block diagram of one implementation of an integrated memory component.

[0014] Figure 3C This is a block diagram of an implementation scheme for the read / write circuitry and ECC of the integrated memory component.

[0015] Figure 4A A side view depicts one embodiment of an integrated memory assembly stacked on a substrate.

[0016] Figure 4B A side view depicts one embodiment of an integrated memory assembly stacked on a substrate.

[0017] Figure 5This is a flowchart describing one implementation of the process for programming a NAND string of memory cells organized into an array.

[0018] Figure 6A An exemplary threshold voltage distribution for a memory array is shown when each memory cell stores three bits of data.

[0019] Figure 6B The threshold voltage distribution for each memory cell storing four bits of data is depicted.

[0020] Figure 7A An example is depicted in which the soft bit threshold might be set too close to the hard bit threshold.

[0021] Figure 7B An example is depicted in which the soft threshold might be set too far from the hard threshold.

[0022] Figure 8A The curves depicting bit error rate (BER) versus block error rate (BLER) are shown.

[0023] Figure 8B The BER vs. BLER curves are plotted for different positions of the soft-bit reference level.

[0024] Figure 9 A flowchart depicts one implementation of the process for calibrating the soft-bit reference level.

[0025] Figure 10 The threshold distribution of candidate soft reference levels associated with hard reference levels is depicted.

[0026] Figure 11 This is a flowchart of one implementation scheme for calculating mutual information based on the channel transition matrix.

[0027] Figures 12A to 12E An example of bin counting for five different candidate soft bit reference levels is shown.

[0028] Figure 13 This is a flowchart of one implementation scheme for the process of calculating mutual information based on LLR.

[0029] Figure 14 This is a flowchart of one implementation of a process for sensing a set of reduced candidate soft-bit reference voltages and determining mutual information.

[0030] Figure 15 The threshold distribution with mutual information for candidate soft reference levels associated with hard reference levels is depicted.

[0031] Figure 16 The threshold distribution with associated soft and hard reference voltages is depicted.

[0032] Figure 17 This is a flowchart of an implementation scheme for simulating soft bit reading.

[0033] Figure 18 Two threshold distributions and information from pages sent to the memory controller are shown to illustrate an implementation scheme for digital simulation of soft bit reads.

[0034] Figure 19 This is a flowchart depicting one implementation of the process of transmitting data during the calibration of the soft-bit reference level. Detailed Implementation

[0035] The technology of the present invention will now be described with reference to the accompanying drawings, which, in various embodiments, relate to calibrating a soft-bit reference level in a non-volatile memory system. Calibrating the soft-bit reference level means calibrating the spacing between the hard-bit reference level and the associated soft-bit reference level. The spacing between the hard-bit reference level and the soft-bit reference level may be referred to herein as the "soft-bit Δ". Numerous embodiments will be provided herein in which the hard-bit and soft-bit reference levels are reference voltage levels, but the reference level may be other physical parameters, such as current levels. Calibrating the soft-bit reference level improves the quality of reliability information (e.g., soft bits) derived from sensing non-volatile memory cells at the soft-bit reference level. Therefore, soft-bit-based error correction is improved.

[0036] In one implementation, a soft-bit reference level (or soft-bit Δ) is calibrated based on data programmed into a non-volatile memory cell. While calibrating the soft-bit reference level, encoded data is read from a group of memory cells. This encoded data is decoded and error-corrected. Thus, the original data programmed into the memory cell is restored. A group of memory cells is sensed at candidate soft-bit reference levels and possibly other levels, generating array data. The candidate soft-bit reference level is on one side of and close to the associated hard-bit reference level. Note that sensing can also occur at other reference levels, such as hard-bit reference levels and other soft-bit reference levels, to generate data. The result includes data for each candidate soft-bit reference level. For each candidate soft-bit reference level, mutual information between the original programmed data and the data for that candidate soft-bit reference level is determined. The term mutual information, as used herein, is common in probability and information theory, where the mutual information of two variables is a measure of the interdependence between the two variables. Mutual information serves as a good measure of the extent to which soft information read from a candidate soft-bit reference level will aid in decoding the data. In one implementation, a new soft-bit reference level with the highest mutual information among several candidates is selected as one side of the hard-bit reference level. Similarly, a new soft-bit reference level can be determined for the other side of the hard-bit reference level. Furthermore, new soft-bit reference levels can be determined for other hard-bit reference levels. Therefore, calibrating the soft-bit reference level based on error correction data improves the quality of reliability information (e.g., soft bits). These new soft-bit reference levels can be used when reading the group of tested memory cells and other memory cells.

[0037] It should be understood that the invention can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the invention to those skilled in the art. In fact, the invention is intended to cover alternatives, modifications, and equivalents of these embodiments, all of which are included within the scope and spirit of the invention as defined by the appended claims. Furthermore, numerous specific details are set forth in the following detailed description of the invention in order to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without such specific details.

[0038] Figures 1A to 4B An example memory system is described that can be used to implement the soft bit reference level calibration disclosed herein. Figure 1AThis is a block diagram of one embodiment of a memory system 100 connected to a host system 120. The memory system 100 can implement the techniques disclosed herein. Many different types of memory systems can be used with the techniques disclosed herein. An exemplary memory system is a solid-state drive (“SSD”); however, other types of memory systems may also be used. The memory system 100 includes a memory controller 102, a memory package 104 for storing data, and local memory (e.g., DRAM / ReRAM) 106. The memory controller 102 includes a front-end processor circuit (FEP) 110 and one or more back-end processor circuits (BEP) 112. In one embodiment, the FEP circuit 110 is implemented on an ASIC. In one embodiment, each BEP circuit 112 is implemented on a separate ASIC. The ASICs for each of the BEP circuits 112 and FEP circuits 110 are implemented on the same semiconductor, such that the memory controller 102 is fabricated as a system-on-a-chip (“SoC”). Both FEP 110 and BEP 112 include their own processors. In one implementation, FEP 110 and BEP 112 operate in a master-slave configuration, where FEP 110 is the master and each BEP 112 is a slave. For example, FEP circuit 110 implements a flash translation layer that performs memory management (e.g., garbage collection, wear leveling, etc.), logic-to-physical address translation, communication with the host, DRAM (local volatile memory) management, and overall operation management of the SSD (or other non-volatile memory system). BEP circuit 112 manages memory operations within the integrated memory assembly / die according to requests from FEP circuit 110. In some implementations, the integrated memory assembly is referred to as a memory package. For example, BEP circuit 112 can perform read, erase, and program processes. Additionally, BEP circuit 112 can perform buffer management, set specific voltage levels required by FEP circuit 110, perform error correction (ECC), control the switching mode interface to the memory package, etc. In one implementation, each BEP circuit 112 is responsible for its own set of memory packages. The memory controller 102 may perform soft bit reference calibration as part of an implementation based on decoded data stored in memory cells within the memory package 104. In some implementations, the memory controller decodes the data to correct any errors in the encoded data read from the memory cells, thereby restoring the original data programmed into the memory cells.

[0039] In one embodiment, there are multiple memory packages 104. Each memory package 104 may include one or more memory dies. In one embodiment, each memory die in the memory package 104 utilizes NAND flash memory (including two-dimensional NAND flash memory and / or three-dimensional NAND flash memory). In other embodiments, the memory package 104 may include other types of memory; for example, the memory package may include phase-change memory (PCM) memory.

[0040] In one embodiment, memory controller 102 communicates with host system 120 using interface 130, which implements NVM Express (NVMe) via PCI Express (PCIe). To work with memory system 100, host system 120 includes a host processor 122, host memory 124, and PCIe interface 126 communicating on bus 128. Host memory 124 is the host's physical memory and can be DRAM, SRAM, non-volatile memory, or another type of storage device. Host system 120 is external to and separate from memory system 100. In one embodiment, memory system 100 is embedded within host system 120.

[0041] Figure 1B This is a block diagram of one implementation scheme of FEP circuit 110. Figure 1BA PCIe interface 150 communicating with a host system 120 and a host processor 152 communicating with the PCIe interface are shown. The host processor 152 can be any type of processor known in the art suitable for implementation. The host processor 152 communicates with a network on-chip (NOC) 154. An NOC is a communication subsystem on an integrated circuit, typically between cores in a SoC. NOCs can span synchronous and asynchronous clock domains or use non-clocked asynchronous logic. NOC technology applies network theory and methods to on-chip communication and brings significant improvements compared to conventional bus and cross-switch interconnects. Compared to other designs, NOCs improve the scalability of SoCs and the power efficiency of complex SoCs. The wires and links of a NOC are shared by many signals. Because all links in a NOC can operate simultaneously on different data packets, a high degree of parallelism is achieved. Therefore, as the complexity of integrated subsystems increases, NOCs offer enhanced performance (such as throughput) and scalability compared to previous communication architectures (e.g., dedicated point-to-point signal lines, shared buses, or segmented buses with bridges). Connected to and communicating with the NOC 154 are the memory processor 156, SRAM 160, and DRAM controller 162. The DRAM controller 162 operates and communicates with the DRAM (e.g., DRAM 106). SRAM 160 is the local RAM used by the memory processor 156. The memory processor 156 runs the FEP circuitry and performs various memory operations. Two PCIe interfaces, 164 and 166, also communicate with the NOC. Figure 1B In one embodiment, the memory controller 102 includes two BEP circuits 112; therefore, there are two PCIe interfaces 164 / 166. Each PCIe interface communicates with one of the BEP circuits 112. In other embodiments, there may be more or fewer than two BEP circuits 112; therefore, there may be more than two PCIe interfaces.

[0042] Figure 2A This is a block diagram of one implementation scheme of BEP circuit 112. Figure 2A A diagram is shown for communicating with FEP circuit 110 (e.g., with...). Figure 1BThe PCIe interface 200 communicates with one of the PCIe interfaces 164 and 166. The PCIe interface 200 communicates with two NOCs 202 and 204. In one embodiment, the two NOCs may be combined into a single large NOC. Each NOC (202 / 204) is connected to the SRAM (230 / 260), buffer (232 / 262), processor (220 / 250), and data path controller (222 / 252) via an XOR engine (224 / 254), an ECC engine (226 / 256), and a read reference voltage calibration engine (225 / 255). In one embodiment, the read reference voltage calibration engine (225 / 255) is configured to calibrate a soft-bit reference voltage. The read reference voltage calibration engine can also calibrate a hard-bit reference voltage. It is not necessary to calibrate reference voltages, such as soft-bit reference voltages, within the memory controller 102. In some embodiments, the soft-bit reference voltage is calibrated within the memory package 104.

[0043] ECC engines 226 / 256 are used to perform error correction, as is known in the art. Herein, ECC engines 226 / 256 may be referred to as controller ECC engines. In some embodiments, ECC engines 226 / 256 are used to decode encoded data read from memory cells in memory package 104 during soft-bit reference voltage calibration. ECC engines 226 / 256 correct any errors in the encoded data, thereby restoring the original data programmed into the memory cells. In some embodiments, memory controller 102 sends this restored data to memory package 104, which uses the restored data when calibrating the soft-bit reference level.

[0044] XOR engines 224 / 254 are used to perform XOR on data, enabling data to be combined and stored in a recoverable manner in the event of programming errors. A data path controller 222 is connected to memory interface 228 for communication with the integrated memory component via four channels. Therefore, the top NOC 202 is associated with memory interface 228 for the four channels used to communicate with the integrated memory component, and the bottom NOC 204 is associated with memory interface 258 for the four additional channels used to communicate with the integrated memory component. In one embodiment, each memory interface 228 / 258 includes four switching mode interfaces (TM interfaces), four buffers, and four schedulers. One scheduler, buffer, and TM interface exist for each of the channels. The processor can be any standard processor known in the art. The data path controllers 222 / 252 can be a processor, FPGA, microprocessor, or other type of controller. XOR engines 224 / 254, ECC engines 226 / 256, and read reference voltage calibration engines (225 / 255) are dedicated hardware circuitry referred to as hardware accelerators. In other implementations, the XOR engine 224 / 254 and ECC engine 226 / 256 can be implemented in software. The scheduler, buffer, and TM interface are hardware circuits. In other implementations, the memory interface (circuit for communicating with the memory die) can be... Figure 2A The different structures are depicted. Additionally, they have the same... Figure 1B and Figure 2A Controllers with different architectures can also be used with the techniques described in this article.

[0045] Figure 2B This is a block diagram of one embodiment of a memory package 104 including multiple memory dies 300 connected to a memory bus (data lines and chip enable lines) 322. The memory bus 322 is connected to a switching mode interface 228 for communication with the TM interface of the BEP circuit 112 (see, for example...). Figure 2A In some implementations, the memory package may include a small controller connected to the memory bus and the TM interface. The memory package may have one or more memory dies. In one implementation, each memory package includes eight or 16 memory dies; however, other numbers of memory dies may also be implemented. The techniques described herein are not limited to any particular number of memory dies.

[0046] Figure 3A This is a functional block diagram of one implementation scheme of the memory die 300. Figure 2B Each of one or more memory dies 300 can be implemented as Figure 3A The memory die 300. Figure 3AThe components depicted are circuits. In one embodiment, each memory die 300 includes a memory structure 326, control circuitry 310, read / write circuitry 328, and decoders 324 / 332, all of which are circuits. The memory structure 326 is addressable via word lines through row decoder 324 and via bit lines through column decoder 332. The read / write circuitry 328 includes a plurality of sense blocks 350 (which include SB1, SB2, ..., SBp (sensor circuitry)) and allows data from one (or more) pages of a plurality of memory cells to be read or programmed in parallel. In one embodiment, each sense block includes a sense amplifier and a set of latches connected to the bit lines. The latches store data to be written and / or data already read. The sense block includes a bit line driver.

[0047] Commands and data are transmitted between memory controller 102 and memory die 300 via memory controller interface 315. Memory controller interface 315 is an electrical interface for communicating with memory controller 102. Examples of memory controller interface 315 include a switching mode interface and an Open NAND Flash Interface (ONFI). Other I / O interfaces may also be used. For example, memory controller interface 315 may implement a switching mode interface connected to the switching mode interface of memory interface 228 / 258 of memory controller 102. In one embodiment, memory controller interface 315 includes a set of input and / or output (I / O) pins connected to communication channel 322 (also referred to herein as memory bus). In one embodiment, communication channel 322 is connected to memory controller 102 as part of the switching mode interface.

[0048] Control circuitry 310 cooperates with read / write circuitry 328 to perform memory operations (e.g., write, read, erase, etc.) on memory structure 326. In one embodiment, control circuitry 310 includes state machine 312, on-chip address decoder 314, power control module 316, memory controller interface 315, memory area 318, ECC engine 330, and soft bit reference voltage calibration 334.

[0049] The soft-bit reference voltage calibration 334 performs some or all of the functions to calibrate the soft-bit reference voltage 334. In some embodiments, some or all of the soft-bit reference voltage calibration 334 is integrated into the state machine 312. In one embodiment, the soft-bit reference voltage calibration 334 is capable of calculating the mutual information between data programmed into the memory structure and data sensed at a candidate soft-bit reference level. In one embodiment, a final soft-bit reference level is selected to maximize the mutual information. Maximizing the mutual information results in a final soft-bit reference level that provides the most useful information for decoding the data stored in the memory structure 326.

[0050] ECC engine 330 is optional and can be used to decode data programmed into memory structure 326. In this way, any errors in the data can be corrected to restore the original data programmed into the memory structure. The restored original data can be used when calibrating the soft-bit reference level. As mentioned above, ECC engine 330 is optional. In some embodiments of soft-bit reference voltage calibration, memory die 300 sends encoded data to memory controller 102 for decoding. Memory controller 102 can then calibrate the soft-bit reference level based on error correction data, or it can send restored data to memory die 300 so that the memory die (e.g., soft-bit reference voltage calibration 334) can use the error correction data to calibrate the soft-bit reference level.

[0051] State machine 312 provides die-level control of memory operations. In one embodiment, state machine 312 may be software-programmable. In other embodiments, state machine 312 is implemented entirely in hardware (e.g., electronic circuitry) without using software. In some embodiments, state machine 312 may be replaced by a microcontroller or microprocessor. In one embodiment, control circuitry 310 includes buffers such as registers, ROM fuses, and other storage devices for storing default values ​​(such as base voltage and other parameters). Default values ​​and other parameters may be stored in areas of memory structure 326 (e.g., structure parameter storage device 326a).

[0052] The on-chip address decoder 314 provides an address interface between the address used by the controller 102 and the hardware address used by the decoders 324 and 332. The power control module 316 controls the power and voltage supplied to the word lines and bit lines during memory operations. The power control module 316 may include a charge pump for generating voltage.

[0053] Storage area 318 can be used to store parameters for operating memory structure 326. Storage area 318 may include volatile or non-volatile memory. In some embodiments, parameters include a soft bit reference level. Parameters may also include a hard bit reference level. Memory structure 326 has storage area 326a, which may also contain a copy of the parameters for operating memory structure 326. In some embodiments, when memory die 300 is powered on, parameters are copied from storage area 326a to storage area 318.

[0054] In one embodiment, control circuitry 310 is configured, either alone or in combination with read / write circuitry 328 and decoders 324 / 332, to be connected to memory structure 326. Control circuitry 310, either alone or in combination with read / write circuitry 328 and decoders 324 / 332, is an example of one or more control circuits performing the functions described below in the flowcharts. In one embodiment, one or more control circuits including memory controller 102 and control circuitry 310 perform the functions described below in the flowcharts. In another embodiment, one or more control circuits, either alone or in combination with memory controller 102, include state machine 312 (and / or microcontroller and / or microprocessor). In yet another alternative, one or more control circuits include memory controller 102, control circuitry 310, read / write circuitry 328, and decoders 324 / 332, which perform the functions described below in the flowcharts. As used herein, the term "appendix" may include, but is not limited to, memory die 300, memory package 104, memory system 100, or host system 120 including memory system 100.

[0055] In one embodiment, memory structure 326 includes a monolithic three-dimensional memory array of non-volatile memory cells, wherein multiple memory stages are formed over a single substrate such as a wafer. The memory structure can include any type of non-volatile memory monolithically formed in one or more physical layers of the memory cell array, having an active region disposed over a silicon (or other type) substrate. In one example, the non-volatile memory cells of memory structure 326 include vertical NAND strings with charge-trapping material, such as those described, for example, in U.S. Patent 9,721,662, the entire contents of which are incorporated herein by reference. In another embodiment, memory structure 326 includes a two-dimensional memory array of non-volatile memory cells. In one example, the non-volatile memory cells are NAND flash memory cells utilizing floating gates, such as those described, for example, in U.S. Patent 9,082,502, the entire contents of which are incorporated herein by reference. Other types of memory cells (e.g., NOR flash memory) may also be used.

[0056] The exact type of memory array architecture or memory cell included in memory structure 326 is not limited to the examples described above. Many different types of memory array architecture or memory cell technologies can be used to form memory structure 326. Implementing the new embodiments claimed herein does not require a specific non-volatile memory technology. Other examples of technologies suitable for memory cells in memory structure 326 include ReRAM memory, magnetoresistive memory (e.g., MRAM, spin-transfer torque MRAM, spin-orbit torque MRAM), phase-change memory (e.g., PCM), etc. Examples of suitable technologies for the architecture of memory structure 326 include two-dimensional arrays, three-dimensional arrays, cross-point arrays, stacked two-dimensional arrays, vertical bitline arrays, etc.

[0057] An example of ReRAM, or PCMRAM, or crosspoint memory includes reversible resistive switching elements arranged in a crosspoint array accessed by X-rays and Y-rays (e.g., word lines and bit lines). In another embodiment, the memory cell may include a conductive bridge memory element. A conductive bridge memory element may also be referred to as a programmable metallized cell. Based on the physical repositioning of ions within a solid electrolyte, the conductive bridge memory element can be used as a state-changing element. In some cases, the conductive bridge memory element may include two solid metal electrodes, one relatively inert (e.g., tungsten) and the other electrochemically active (e.g., silver or copper), with a thin film of solid electrolyte between the two electrodes. As temperature increases, ion mobility also increases, leading to a decrease in the programming threshold of the conductive bridge memory cell. Therefore, the conductive bridge memory element can have a wide range of programming thresholds across the entire temperature range.

[0058] Magnetoresistive RAM (MRAM) stores data using magnetic storage elements. Each element consists of two ferromagnetic plates, each of which remains magnetized, separated by a thin insulating layer. One of the plates is a permanent magnet set to a specific polarity; the magnetization of the other plate can be changed to match the magnetization of an external magnetic field to store memory. The storage device is constructed from a grid of such memory cells. In one embodiment for programming, each memory cell is located between a pair of write lines arranged perpendicular to each other, parallel to the cell, one above and one below. When current passes through them, an induced magnetic field is generated.

[0059] Phase change memory (PCM) utilizes the unique properties of chalcogenide glasses. One implementation uses a Ge2Sb2Te5 alloy to achieve a phase change by electrically heating the phase change material. The programming dose is an electrical pulse of varying amplitude and / or length, resulting in different resistance values ​​in the phase change material.

[0060] Those skilled in the art will recognize that the techniques described herein are not limited to a single specific memory structure, but encompass many related memory structures within the technical essence and scope described herein and as understood by those skilled in the art.

[0061] Figure 3B A functional block diagram of one embodiment of an integrated memory assembly 306 is depicted. The integrated memory assembly 306 can be used in a memory package 104 within a memory system 100. In one embodiment, the integrated memory assembly 306 includes two types of semiconductor dies (or more simply, "dies"). A memory structure die 302 includes a memory structure 326. The memory structure 326 may contain non-volatile memory cells. A control die 304 includes control circuitry 310. In some embodiments, the control die 304 is configured to connect to the memory structure 326 within the memory structure die 302. For example, the control circuitry 310 is configured to connect to the non-volatile memory cells within the memory structure 326 within the memory structure die 302. In some embodiments, the memory structure die 302 and the control die 304 are coupled together. The control circuitry 310 includes a state machine 312, an address decoder 314, power control circuitry 316, a memory controller interface 315, a memory area 318, a soft bit reference voltage calibration 334, and an ECC engine 330. The above has already been about Figure 3A The various components in the control circuit 310 are described.

[0062] The control circuit 310 also includes a read / write circuit 328. In another embodiment, a portion of the read / write circuit 328 is located on the control die 304, and a portion of the read / write circuit 328 is located on the memory structure die 302.

[0063] Any subgroup of components in the control circuitry 310 of the control die 304 can be considered as one or more control circuits that perform the functions described below in the flowchart. Alternatively, one or more control circuits may include controller 102 and control circuitry 310 of the control die 304, performing the functions described below in the flowchart. One or more control circuits may consist of hardware only or a combination of hardware and software (including firmware). For example, a firmware-programmed controller is an example of a control circuit. One or more control circuits may include a processor, PGA (Programmable Gate Array), FPGA (Field Programmable Gate Array), ASIC (Application-Specific Integrated Circuit), integrated circuit, or other types of circuitry. The term "means" as used herein may include, but is not limited to, control die 304 and integrated memory component 306.

[0064] Passage 352 is a pathway between one or more components in control circuitry 310 and a memory structure on memory structure die 302. The pathway can be used to provide or receive signals (e.g., voltage, current). The pathway includes conductive paths. The pathway may include, but is not limited to, one or more of bonding pads, metal interconnects, vias, transistors, conductive materials, and other materials capable of transmitting or carrying electrical signals.

[0065] In one embodiment, the integrated memory component 306 includes a set of input and / or output (I / O) pins connected to a communication channel 322 (also referred to herein as a memory bus). The communication channel 322 is depicted as being connected to a control die 304. The communication channel 322 may be connected to either or both of the memory structure die 302 and / or the control die 304. In one embodiment, the communication channel 322 directly connects the memory controller 102 to the control die 304.

[0066] Figure 3B This is a block diagram of one embodiment of the read / write circuit 328 and ECC engine 330 of the control die 304. The read / write circuit 328 includes a sense amplifier 350 and a latch 360. The latch 360 may include a data latch 360a and a parity latch 360b. In one embodiment, the data latch 360a stores the data bits of the codeword, while the parity latch stores the parity bit of the codeword. It is not necessary to have separate latches for the data bits and for the parity bit. Figure 3C Four sets of data latches 360(1), 360(2), 360(3), and 360(4) are depicted. Each set can be used to store codewords for different pages. In an embodiment where four bits are stored in each memory cell, four pages are stored in a set of memory cells. These four pages may be referred to as the lower page (LP), lower-middle page (LMP), upper-middle page (UMP), and upper page (UP). In another embodiment, the sense amplifier 350 is located on the memory structure die 302, but the latches 360 are located on the control die 304.

[0067] The on-die ECC engine 330 is capable of encoding data bits received from the memory controller 102. In one embodiment, the on-die ECC engine 330 forms codewords, each codeword containing data bits and parity bits. In one embodiment, the memory controller 102 provides the codewords to the control die 304. The control circuitry 310 stores these codewords in non-volatile memory cells within the memory structure 326. The on-die ECC engine 330 decodes and performs error correction on the codewords read from the memory structure 326. In some embodiments, the on-die ECC engine 330 is used during soft-bit reference voltage calibration to recover data programmed into the memory structure 326.

[0068] In some implementations, the on-die ECC engine 330 calculates a parity bit for each stored data unit (e.g., a page). The parity bit (also called an error-correcting code) may be stored along with the data unit (e.g., a page). The combination of a data unit and its associated parity bit is called a codeword. In one implementation, the parity bit is stored away from the data unit (e.g., a page).

[0069] The on-die ECC engine 330 includes an encoder 380 and a decoder 390. The encoder 380 is configured to encode data using an ECC scheme such as a Reed Solomon encoder, a Bose-Chaudhuri-Hocquenghem (BCH) encoder, a low-density parity (LDPC) encoder, a turbocode encoder, an encoder configured to encode one or more other ECC encoding schemes, or any combination thereof. The encoder 380 can form a codeword containing data bits 382 and parity bits 384. The data bits may be provided by a memory controller 102.

[0070] In one embodiment, data bit 382 is stored in data latch 360a, and parity bit 384 is stored in parity latch 360b. Based on the bits in latch 360, the sense amplifier 350 can control the bit line voltage in memory structure 326 when a non-volatile memory cell is being programmed. Thus, codewords can be programmed into the non-volatile memory cells in memory structure 326. It should be understood that other voltages can also be applied to memory structure 326, such as applying a programming voltage to a memory cell selected for programming.

[0071] Decoder 390 is configured to decode codewords stored in memory structure die 302. In one embodiment, sense amplifier 350 senses bit lines in memory structure 326 to read codewords. The sense amplifier 350 may store the read codewords in latch 360. Decoder 390 is capable of detecting and correcting errors in the codewords.

[0072] In some embodiments, the integrated memory component 306 contains more than one control die 304 and more than one memory structure die 302. In some embodiments, the integrated memory component 306 includes a stack of multiple control dies 304 and multiple memory structure dies 302. Figure 4AA side view of one embodiment of an integrated memory assembly 306 (e.g., a stack including control dies 304 and memory structure dies 302) stacked on a substrate 402 is depicted. The integrated memory assembly 306 has three control dies 304 and three memory structure dies 302. In some embodiments, there are more than three memory structure dies 302 and more than three control dies 304.

[0073] Each control die 304 is attached (e.g., bonded) to at least one memory structure die in the memory structure die 302. Some of the bonding pads 470, 474 are depicted. There may be more bonding pads. The space between the two bondsed dies 302, 304 is filled with a solid layer 448, which may be formed of epoxy resin or other resins or polymers. The solid layer 448 protects the electrical connection between the dies 302, 304 and further secures the dies together. Various materials may be used as the solid layer 448.

[0074] The integrated memory component 306 may be stacked, for example, in a stepped offset manner, such that the bonding pads at each stage are not covered and can be reached from above. Wire connections 406, attached to the bonding pads, connect the control die 304 to the substrate 402. Multiple such wire connections may be formed over the width of each control die 304 (i.e., formed to...). Figure 4A (on the page).

[0075] A through-silicon via (TSV) 412 for memory structure die 302 can be used to route signals through memory structure die 302. A through-silicon via (TSV) 414 for control die 304 can be used to route signals through control die 304. TSVs 412 and 414 can be formed before, during, or after the formation of integrated circuits in semiconductor dies 302 and 304. TSVs can be formed by etching through holes in the wafer. These holes can then be lined with a barrier to prevent metal diffusion. The barrier layer can in turn be lined with a seed layer, and the seed layer can be plated with an electrical conductor, such as copper, although other suitable materials such as aluminum, tin, nickel, gold, doped polysilicon, and alloys or combinations thereof can be used.

[0076] Solder balls 408 may optionally be attached to contact pads 410 on the lower surface of substrate 402. Solder balls 408 may be used to electrically and mechanically couple integrated memory assembly 306 to host devices such as printed circuit boards. Solder balls 408 may be omitted if integrated memory assembly 306 will be used as an LGA package. Solder balls 408 may form part of the interface between integrated memory assembly 306 and memory controller 102.

[0077] Figure 4BA side view of one embodiment of an integrated memory assembly 306 stacked on a substrate 402 is depicted. The integrated memory assembly 306 has three control dies 304 and three memory structure dies 302. In some embodiments, there are more than three memory structure dies 302 and more than three control dies 304. In this example, each control die 304 is bonded to at least one memory structure die 302. Optionally, a control die 304 may be bonded to two memory structure dies 302.

[0078] Some of the bonding pads 470 and 474 are depicted. There may be more bonding pads. The space between the two joined dies 302 and 304 is filled with a solid layer 448, which may be formed of epoxy resin or other resins or polymers. Figure 4A Compared to the examples in, Figure 4B The integrated memory component 306 in the memory structure has no stepped offset. A through-silicon via (TSV) 412 for memory structure die 302 can be used to route signals through the memory structure die 302. A through-silicon via (TSV) 414 for control die 304 can be used to route signals through the control die 304.

[0079] Solder balls 408 may optionally be attached to contact pads 410 on the lower surface of substrate 402. Solder balls 408 may be used to electrically and mechanically couple integrated memory assembly 306 to host devices such as printed circuit boards. Solder balls 408 may be omitted if integrated memory assembly 306 will be used as an LGA package.

[0080] As briefly discussed above, the control die 304 and the memory structure die 302 can be bonded together. Bonding pads on each die 302, 304 can be used to bond the two dies together. In some embodiments, in a so-called Cu-Cu bonding process, the bonding pads are bonded directly to each other without solder or other additional material. In the Cu-Cu bonding process, the bonding pads are controlled to be highly flat and formed in a highly controlled environment that is essentially free of environmental particles that would otherwise deposit on the bonding pads and prevent a tight bond. Under these properly controlled conditions, the bonding pads are aligned and pressed against each other to form a bond based on surface tension. This bond can be formed at room temperature, although heat can also be applied. In embodiments using Cu-Cu bonding, the bonding pads can be approximately 5 μm square and spaced apart from each other at a pitch of 5 μm to 5 μm. Although this process is referred to herein as Cu-Cu bonding, the term can also be applied when the bonding pads are formed from materials other than copper.

[0081] When the area of ​​the bonding pads is small, it can be difficult to bond semiconductor dies together. The size and spacing of the bonding pads can be further reduced by providing a film layer on the surface of the semiconductor die, including the bonding pads. The film layer is disposed around the bonding pads. When the dies are placed together, the bonding pads can bond to each other, and the film layers on the individual dies can bond to each other. This bonding technique can be called hybrid bonding. In embodiments using hybrid bonding, the bonding pads can be approximately 5 μm square and spaced apart from each other with a pitch of 1 μm to 5 μm. Bonding techniques can be used to provide bonding pads with even smaller sizes and pitches.

[0082] Some embodiments may include a membrane on the surfaces of dies 302 and 304. If such a membrane is not initially provided, the space between the dies can be underfilled with epoxy resin or other resins or polymers. The underfill material can be applied as a liquid and then allowed to harden into a solid layer. This underfilling step protects the electrical connection between dies 302 and 304 and further secures the dies together. Various materials are available as underfill materials.

[0083] Figure 5 This is a flowchart describing one embodiment of a process 500 for programming a NAND string of memory cells organized into an array. Figure 5 The process can be executed in the direction of state machine 312. In an exemplary embodiment, the above-described control circuitry 310 (and read / write circuitry 328 and decoders 332 / 324) are used on memory die 300 for execution. Figure 5 The process. In one exemplary embodiment, the control circuit 310 described above is used to execute via the integrated memory component 306. Figure 5 The process comprises multiple cycles, each cycle including a programming phase (e.g., steps 504 to 508) and a verification phase (e.g., steps 510 to 518).

[0084] In many implementations, the amplitude of the programmed pulse increases by a predetermined step size with each successive pulse. Figure 5 In step 502, the programming voltage (Vpgm) is initialized to the initial amplitude (e.g., about 12V to 16V, or another suitable level), and the programming counter PC maintained by state machine 312 is initialized to 1.

[0085] In one implementation, a set of memory cells selected for programming (referred to herein as selected memory cells) are programmed simultaneously and all connected to the same word line (selected word line). Other memory cells not selected for programming (unselected memory cells) may also be connected to the selected word line. That is, the selected word line will also be connected to memory cells that should be disabled for programming. Furthermore, when the memory cells reach their intended target data state, they will be disabled for further programming. These NAND strings (e.g., unselected NAND strings) boost their channels to disable programming; these strings include the memory cells to be disabled for programming connected to the selected word line. When the channel has a boosted voltage, the voltage difference between the channel and the word line is insufficient to induce programming. To aid the boost, in step 504, the memory system precharges the channels of the NAND strings that include the memory cells connected to the selected word lines to be disabled for programming.

[0086] In one implementation, step 504 marks the start of a programming operation. In some implementations, different groups of memory cells are programmed simultaneously. For example, programming of memory cells in different memory structures 326 can be performed concurrently. In some implementations, the start of concurrent programming operations (e.g., step 504) is interleaved, such that step 504 occurs at different times for different memory structures 326.

[0087] In step 506, a NAND string including a memory cell connected to the selected word line to be disabled for programming is boosted to disable programming. Such a NAND string is referred to herein as an "unselected NAND string". In one embodiment, the unselected word line receives one or more boost voltages (e.g., about 7 to 11 volts) to perform a boost scheme. A programming disable voltage is applied to the bit line coupled to the unselected NAND string.

[0088] In step 508, a programming pulse of the programming signal Vpgm is applied to the selected word line (the word line selected for programming). In one embodiment, if a memory cell on the NAND string is to be programmed, the corresponding bit line is biased at the programming enable voltage. In this document, such a NAND string is referred to as the "selected NAND string".

[0089] In step 508, programming pulses are simultaneously applied to all memory cells connected to the selected word line, such that all memory cells connected to the selected word line are programmed simultaneously (unless they are disabled for programming). That is, they are programmed at the same time or during an overlap period (both are considered simultaneous). In this way, all memory cells connected to the selected word line will have their threshold voltage changes simultaneously, unless they are disabled for programming.

[0090] In step 510, the memory cell that has reached its target state is locked and cannot be further programmed. Step 510 may include performing verification at one or more verification reference levels. In one embodiment, the verification process is performed by testing whether the threshold voltage of the memory cell selected for programming has reached the appropriate verification reference voltage.

[0091] In step 510, after the memory cell has been verified (by the test of Vt) that the memory cell has reached its target state, the memory cell can be locked.

[0092] If, in step 512, it is determined that all memory cells have reached their target threshold voltage (pass), the programming process is complete and successful because all selected memory cells have been programmed and verified to their target state. In step 514, a "pass" status is reported. Otherwise, if, in 512, it is determined that not all memory cells have reached their target threshold voltage (failure), the programming process continues to step 516.

[0093] In step 516, the memory system counts the number of memory cells that have not yet reached their corresponding target threshold voltage distribution. That is, the system counts the number of memory cells that have not yet reached their target state. This counting can be performed by state machine 312, memory controller 102, or other logic. In one implementation, each sensing block in the sensing block stores the state (pass / fail) of its corresponding cell. In one implementation, there is a total count that reflects the total number of currently programmed memory cells for which the last verification step has failed. In another implementation, a separate count is maintained for each data state.

[0094] In step 518, it is determined whether the count from step 516 is less than or equal to a predetermined limit. In one embodiment, the predetermined limit is the number of bits that can be corrected by error correction codes (ECC) during the page read process of a memory cell. If the number of failed cells is less than or equal to the predetermined limit, the programming process can stop and a "pass" status is reported in step 514. In this case, enough memory cells have been correctly programmed so that ECC can be used during the read process to correct any remaining memory cells that have not yet been fully programmed. In some embodiments, the predetermined limit used in step 518 is lower than the number of bits that can be corrected by error correction codes (ECC) during the read process to allow for future / additional errors. The predetermined limit can be a fraction (proportional or non-proportional) of the number of bits that can be corrected by ECC during the page read process of a memory cell when programming fewer than all memory cells of a page, or when comparing counts of only one data state (or fewer than all states). In some embodiments, the limit is not predetermined. Instead, it varies based on the number of errors already counted for the page, the number of program erase cycles performed, or other criteria.

[0095] If the number of failed memory cells is not less than a predetermined limit, the programming process continues at step 520 and the programming counter PC is checked against the programming limit value (PL). Examples of programming limit values ​​include 1, 12, 16, 19, and 30; however, other values ​​can be used. If the programming counter PC is not less than the programming limit value PL, the programming process is considered to have failed and a "failure" status is reported in step 524. If the programming counter PC is less than the programming limit value PL, the process continues at step 522, during which the programming counter PC is incremented by 1, and the programming voltage Vpgm is stepped to the next amplitude. For example, the next pulse will have an amplitude one step larger than the previous pulse (e.g., a step size of 0.1 volts to 1.0 volts). After step 522, the process loops back to step 504, and another programming pulse is applied to the selected word line, causing execution to... Figure 5 Another iteration of the programming process (steps 504 to 522).

[0096] At the end of a successful programming process, the threshold voltage of the memory cell should, where appropriate, be within one or more distributions of the threshold voltages of the memory cells used for programming or within the distribution of the threshold voltages of the erased memory cells. Figure 6A An exemplary threshold voltage distribution for a memory array is shown when each memory cell stores three bits of data. However, other implementations may use different data capacities per memory cell (e.g., one, two, four, or five bits of data per memory cell). Figure 6AEight threshold voltage distributions are shown, corresponding to eight data states. The first threshold voltage distribution (data state) Er represents an erased memory cell. The other seven threshold voltage distributions (data states) AG represent programmed memory cells and are therefore also referred to as programmed states. Each threshold voltage distribution (data state) corresponds to a predetermined set of data bits. The specific relationship between the data programmed into a memory cell and the threshold voltage level of that cell depends on the data encoding scheme adopted by that cell. In one implementation, Gray code allocation is used to assign data values ​​to a range of threshold voltages such that if the memory's threshold voltage is erroneously shifted to its adjacent physical state, only one bit will be affected.

[0097] Figure 6A Seven read reference voltages, VrA, VrB, VrC, VrD, VrE, VrF, and VrG, are shown for reading data from memory cells. By testing (e.g., performing a sensing operation) whether the threshold voltage of a given memory cell is higher or lower than the seven read reference voltages, the system can determine the data state (i.e., A, B, C, D, ...) of the memory cell.

[0098] Figure 6A Seven verification reference voltages, VvA, VvB, VvC, VvD, VvE, VvF, and VvG, are also shown. In some embodiments, when memory cells are programmed to data state A, the system tests whether these memory cells have a threshold voltage greater than or equal to VvA. When memory cells are programmed to data state B, the system tests whether these memory cells have a threshold voltage greater than or equal to VvB. When memory cells are programmed to data state C, the system determines whether these memory cells have a threshold voltage greater than or equal to VvC. When memory cells are programmed to data state D, the system tests whether these memory cells have a threshold voltage greater than or equal to VvD. When memory cells are programmed to data state E, the system tests whether these memory cells have a threshold voltage greater than or equal to VvE. When memory cells are programmed to data state F, the system tests whether these memory cells have a threshold voltage greater than or equal to VvF. When memory cells are programmed to data state G, the system tests whether these memory cells have a threshold voltage greater than or equal to VvG. Figure 6A It also shows Vev, which is the voltage level used to test whether a memory cell has been correctly erased.

[0099] In one implementation known as full-sequence programming, memory cells can be directly programmed from an erased data state Er to any of the programmed data states A through G. For example, a group of memory cells to be programmed can be erased first, leaving all memory cells in the group in an erased data state Er. Then, a programming process is used to directly program the memory cells to data states A, B, C, D, E, F, and / or G. For example, while some memory cells are being programmed from data state Er to data state A, other memory cells are being programmed from data state Er to data state B and / or from data state Er to data state C, and so on. Figure 6A The arrow indicates full-sequence programming. In some implementations, the data states AG may overlap, where the control die 304 and / or memory controller 102 rely on error correction to identify the correct data being stored.

[0100] In addition to full-sequence programming, the techniques described herein can also be used with other types of programming, including but not limited to multi-level programming / multi-phase programming. In one implementation of multi-level programming / multi-phase programming, in the first stage, all memory cells ending at any of the data states D through G are programmed to an intermediate state no higher than D. In the first stage, memory cells ending at any of the data states Er through C are not programmed. In the second stage, memory cells ending at any of the data states B or C are programmed to a state no higher than B; memory cells ending at data states F or G are programmed to a state no higher than F. In the third stage, the memory cells are programmed to their final state. In one implementation, the first page is programmed in the first stage, the second page in the second stage, and the third page in the third stage. As described herein, once a page has been programmed into a set of memory cells, the memory cells can be retrieved by reading the memory cells. Therefore, the intermediate states associated with multi-phase programming are considered programming states herein.

[0101] Generally, during verification and read operations, the selected word line is connected to a voltage (an example of a reference signal), the level of which is specific to each read operation (see, for example, [reference]). Figure 6A The read comparison levels VrA, VrB, VrC, VrD, VrE, VrF, and VrG) or verification operations (e.g., see [link to relevant documentation]). Figure 6AThe verification target levels (VvA, VvB, VvC, VvD, VvE, VvF, and VvG) are specified to determine whether the threshold voltage of the relevant memory cell has been reached. After the word line voltage is applied, the conduction current of the memory cell is measured to determine whether the memory cell is turned on (conducted current) in response to the voltage applied to the word line. If the conduction current is measured to be greater than a certain value, then it is assumed that the memory cell is turned on and the voltage applied to the word line is greater than the threshold voltage of the memory cell. If the conduction current is not measured to be greater than a certain value, then it is assumed that the memory cell is not turned on and the voltage applied to the word line is not greater than the threshold voltage of the memory cell. During the read or verification process, unselected memory cells are provided with one or more read pass voltages (also known as bypass voltages) at their control gate, causing these memory cells to conduct current as if they were being operated through the gate (e.g., conducting current regardless of whether these memory cells are being programmed or erased).

[0102] There are many methods to measure the conduction current of a memory cell during a read or verification operation. In one example, the conduction current of the memory cell is measured as the rate at which the memory cell discharges or charges a dedicated capacitor in a sense amplifier. In another example, the conduction current of a selected memory cell allows (or does not allow) the NAND string of the memory cell to discharge to the corresponding bit line. The voltage on the bit line is measured after a certain period of time to see if it has discharged. It should be noted that the techniques described herein can be used in conjunction with various methods known in the art for verification / reading. Other read and verification techniques known in the art can also be used.

[0103] Figure 6B The threshold voltage distribution and a page mapping scheme are depicted when each memory cell stores four bits of data. Figure 6B The text describes the potential overlap between data states S0 and S15. This overlap can occur due to factors such as memory cell charge loss (and thus a drop in threshold voltage). Programming interference can unintentionally increase the threshold voltage of memory cells. Similarly, read interference can unintentionally increase the threshold voltage of memory cells. Over time, the location of the threshold voltage distribution can change. Such changes can increase the bit error rate, thereby increasing decoding time or even making decoding impossible. However, by recalibrating the soft bit reference level, as disclosed herein, decoding time and success rate are improved.

[0104] As mentioned above, Figure 6BAn example is depicted where each memory cell stores four bits. Therefore, four pages can be stored in a set of memory cells. Fifteen hard-bit (HB) read reference levels (Vr1 to Vr15) are depicted. This set of memory cells can be connected to the same word line. Each HB read reference level is used to distinguish between two adjacent threshold voltage distributions. In other words, each HB read reference level is used to distinguish between two adjacent data states. For example, HB read reference level Vr4 is used to distinguish between data states S3 and S4.

[0105] Figure 6B The soft bit (SB) reference levels associated with the four HB reference levels are also described. These four HB reference levels can be those used to sense data for a page. A set of SB reference levels is grouped around each of Vr1, Vr4, Vr6, and Vr11. For example, a set of SB reference levels Vr1_s1, Vr1_s2, Vr1_s3, and Vr1_s4 is grouped around the HB reference level Vr1; a set of SB reference levels Vr4_s1, Vr4_s2, Vr4_s3, and Vr4_s4 is grouped around the HB reference level Vr4; a set of SB reference levels Vr6_s1, Vr6_s2, Vr6_s3, and Vr6_s4 is grouped around the HB reference level Vr6; and a set of SB reference levels Vr11_s1, Vr11_s2, Vr11_s3, and Vr11_s4 is grouped around the HB reference level Vr11. There can be an SB reference level associated with other HB reference levels, but it is not in Figure 6B Depicted in [the text]. Figure 6B In this model, there are four SB reference levels associated with each corresponding HB reference level, but there may be more or fewer SB reference levels associated with the HB reference levels. Figure 6B In this system, an equal number of SB reference levels exist on each side of the corresponding HB reference level, but this is not necessary. For example, sensing the SB reference level on only one side of the corresponding HB reference level can provide useful reliability information.

[0106] It should be noted that although some embodiments disclosed herein involve memory cells whose state is represented by the threshold voltage (Vt) of the memory cell, the state of a memory cell can be represented by another physical parameter, including but not limited to resistance or conductance. For example, in Figure 6A and Figure 6B In this context, the data state is represented by a Vt distribution. However, for other types of memory cells, the data state can be represented by a resistance distribution or a conductance distribution.

[0107] In some implementations, when the ECC engine is unable to decode codewords stored in memory cells using data sensed using the HB reference voltage, the SB reference voltage is used to read data from the memory cells. Typically, a set of SB reference voltages exists for each HB reference voltage. The SB reference voltages are at voltages slightly higher or slightly lower than the corresponding HB reference voltage. Hereinafter, the SB reference voltage at a voltage slightly higher than the corresponding HB reference voltage is referred to as the "upper SB reference voltage." Hereinafter, the SB reference voltage at a voltage slightly lower than the corresponding HB reference voltage is referred to as the "lower SB reference voltage." In some implementations, one or more upper SB reference voltages and one or more lower SB reference voltages exist for each HB reference voltage. One implementation is a single-sided SB read, where only the upper SB reference voltage or only the lower SB reference voltage is used. For example, sensing can be performed on one or more lower SB reference voltages for each HB reference voltage. Alternatively, sensing can be performed on one or more upper SB reference voltages for each HB reference voltage.

[0108] This set of SB reference voltages is used to generate "soft" reliability information, which increases the decoder's error correction capability. Sensing the SB reference voltages generates one or more "soft bits" for each memory cell. These "soft bits" indicate whether the memory cell's physical parameters (e.g., Vt, resistance) are close to the HB reference level, making the memory cell's HB less reliable, or whether they are far from the HB reference level, making the HB more reliable. In other words, if the soft reliability information indicates that a memory cell has physical parameters whose values ​​are close to the HB reference level, it is considered less reliable compared to if the soft reliability information indicates that a memory cell has physical parameters whose values ​​are far from the HB reference level.

[0109] However, this correction capability depends on the quality of the soft reliability information. Using soft bits that are not sensed at the correct location (e.g., the correct voltage level) can degrade the quality of the soft reliability information and reduce its informativeness. Setting the SB threshold is a trade-off. If the SB threshold is too close to the HB threshold, many errors will not be flagged as low reliability. Figure 7A An example is depicted in which the SB reference level may be set too close to the HB threshold. Figure 7ATwo adjacent memory cell distributions 702 and 704 are depicted. These two adjacent memory cell distributions 702 and 704 correspond to two adjacent data states. In one embodiment, each memory cell distribution 702 and 704 is a Vt distribution. In another embodiment, each memory cell distribution 702 and 704 is a resistance distribution. The horizontal axis is labeled "Sensed Voltage" to indicate that in some embodiments, voltage is used to sense the memory cell. The sensed voltage can be used to test physical parameters of the memory cell, such as Vt, resistance, or conductance. Sensing the physical parameters of the memory cell is not limited to using voltage.

[0110] Hard reference level 706 is used to distinguish two adjacent memory cell distributions 702, 704. In other words, HB reference level 706 is used to distinguish two adjacent data states. Two SB reference levels 708a, 708b are depicted. In one embodiment, HB reference level 706 is a voltage used to distinguish two Vt distributions. In another embodiment, HB reference level 706 is a voltage used to distinguish two resistance distributions. Therefore, depending on the physical parameters of the memory cell being tested, HB reference level 706 may correspond to the Vt of the memory cell, the resistance of the memory cell, or some other physical parameter of the memory cell. Similar reasoning applies to SB reference level 708.

[0111] Zone 710 corresponds to a portion of memory cells in memory cell distribution 704 that is incorrect because they have physical parameter (e.g., Vt, resistance) values ​​lower than HB reference level 706. In other words, zone 710 corresponds to a portion of memory cells intended to be programmed to the data state associated with memory cell distribution 704, but now has physical parameter values ​​lower than HB reference level 706. However, since the memory cells in zone 710 also have physical parameter values ​​lower than SB reference level 708a, they fall into the high reliability category. However, it is expected that such memory cells would be labeled as low reliability. Note that phrases such as "memory cells have resistance lower than HB reference level 706" mean that the resistance of the memory cell is lower than the resistance tested by HB reference level 706. Note that phrases such as "memory cells have Vt lower than HB reference level 706" mean that the Vt of the memory cell is lower than the Vt tested by HB reference level 706.

[0112] Zone 712 corresponds to a portion of the memory cells in memory cell distribution 702 that is incorrect because they have physical parameter values ​​higher than HB reference level 706. In other words, zone 712 corresponds to some memory cells intended to be programmed to the data state associated with memory cell distribution 702, but now have physical parameter values ​​higher than HB reference level 706. However, since the memory cells in zone 712 also have physical parameter values ​​higher than SB reference level 708b, they fall into the high reliability category. However, it is expected that such memory cells would be labeled as low reliability.

[0113] On the other hand, if the SB threshold is too far from the HB reference voltage, too many correct bits are marked as unreliable. Figure 7B An example is depicted in which the SB threshold might be set too far from the HB threshold. Figure 7B Two adjacent memory cell distributions 702 and 704 are depicted. A hard bit (HB) reference level 706 is used to distinguish the two adjacent memory cell distributions 702 and 704. Two SB reference levels 714a and 714b are depicted. Zone 716 corresponds to a portion of the memory cells in memory cell distribution 702, which is correct because they have physical parameter values ​​lower than the HB reference level 706. However, since the memory cells in zone 716 also have physical parameter values ​​higher than the SB reference level 714a, they fall into the low reliability category. However, fewer expected non-faulty memory cells are marked as low reliability. In other words, the SB reference level 714a is set too far below the HB reference level 706. Zone 718 corresponds to a portion of the memory cells in memory cell distribution 704, which is correct because they have physical parameter values ​​higher than the HB reference level 706. However, since the memory cells in zone 718 also have physical parameter values ​​lower than the SB reference level 714b, they fall into the low reliability category. However, fewer non-error-prone memory cells are expected to be flagged as low reliability. In other words, the SB reference level 714b is set too far above the HB reference level 706.

[0114] As mentioned above, SB can indicate the reliability of HB for each memory cell. Figure 8AThe curves depict the block error rate (BLER) versus bit error rate (BER). The vertical axis represents the BLER, which is the probability that the decoder fails to decode a codeword. Error correction is expected to result in a low BLER. The horizontal axis represents the BER, which is the amount of error in a codeword. Error correction is expected to be able to correct data with a high BER. In other words, a low BLER is expected for a high BER. Curve 802 corresponds to using only HB during error correction. Curve 804 corresponds to using both HB and SB during error correction. For curve 804, it is assumed that the SB reference level is established at an appropriate level for good error correction. Curves 802 and 804 illustrate that using both HB and SB significantly enhances error correction capability. For example, for two points on curves 802 and 804 with the same BLER, curve 804 corresponds to a higher BER. Therefore, curve 804 shows that using both HB and SB can correct data with a higher BER while achieving the same BLER as using only HB.

[0115] However, the position of the SB reference level has a significant impact on the SB's ability to improve error correction. Figure 8B The graphs depict BER versus BLER at different positions relative to the SB reference level. The vertical axis represents the block error rate (BLER), and the horizontal axis represents the bit error rate (BER). However, it should be noted that... Figure 8B The proportion (value) of BER in the middle does not necessarily correspond to Figure 8A The curves 812, 814, 816, and 818 represent the worst-case positions of the SB reference levels. Curves 812 through 818 indicate that if the SB reference level is not correctly selected, the error correction capability is reduced.

[0116] Figure 9 A flowchart depicts one embodiment of a process 900 for calibrating the SB reference level based on raw data programmed into a non-volatile memory cell. The raw data can be obtained by decoding encoded data stored in the memory cell. Decoding the encoded data corrects any errors in the data, thereby generating the raw data programmed into the memory cell. Calibrating the SB reference level based on the raw data improves the quality of reliability information (e.g., soft bits) derived from the non-volatile memory cell sensing the calibrated soft-bit reference level.

[0117] Process 900 can be used to store memory cells with one bit per cell (e.g., SLC) or multiple bits per cell (e.g., two, three, four, or more bits per cell). Typically, one or more SB reference levels are associated with an HB reference level (e.g., grouped around it). Any number of SB reference levels can exist within this group. In one embodiment, the final calibrated SB reference level has one SB reference level on each side of the corresponding HB reference level. In one embodiment, the final calibrated SB reference level has two SB reference levels on each side of the corresponding HB reference level. In one embodiment, the final calibrated SB reference level has three SB reference levels on each side of the corresponding HB reference level. Single-sided SB reference levels are also possible. In one embodiment, the final calibrated SB reference level has one or more lower SB reference levels (no upper SB reference level required) for each corresponding HB reference level. In one embodiment, the final calibrated SB reference level has one or more upper SB reference levels (no lower SB reference level required) for each corresponding HB reference level. Process 900 can be used to calibrate the SB reference levels associated with the HB reference level used to read data from a page. For example, regarding... Figure 6B In the example, process 900 can be used to calibrate the SB reference levels associated with Vr1, Vr4, Vr6, and Vr11. However, for ease of explanation, the calibration of the SB reference level associated with one of the HB reference levels can be discussed. In some embodiments, the discussion will focus on the SB reference voltage calibrated on one side of the HB reference voltage.

[0118] In one implementation, process 900 is triggered in response to the inability to decode data read from a set of memory cells. For example, a decoding failure may occur within a block of memory cells. For instance, decoding using both HB and SB may fail. After calibrating the SB reference level in process 900, another attempt can be made to decode the data using both HB and SB. Calibrating the SB reference level helps recover from the initial failure to decode using both HB and SB. However, process 900 can be performed without decoding failure.

[0119] Step 902 includes sensing data from a set of non-volatile memory cells. In one embodiment, at least one page of data is read. The data of this page may be stored in the memory cell as an ECC codeword. Note that in one embodiment of the decoding failure triggering process 900, this decoding failure is for a codeword different from the codeword sensed in step 902. For example, the set sensed in step 902 may be a different set of memory cells than the set where decoding failure exists. If the set of memory cells stores multiple codewords, the codeword sensed in step 902 may be a codeword different from the codeword in the set where decoding failure occurred. Memory cells may be sensed at one or more HB reference levels. For example, regarding Figure 6B The memory cells Vr1, Vr4, Vr6, and Vr11 can be sensed to sense the data of a page. Therefore, an ECC codeword is read. Process 900 can be repeated for data in other pages stored in the memory cells. For example, sensing can occur at the HB reference level for one page, then at the HB reference level for another page, and so on. After sensing for a page, an HB can be determined for each memory cell. The HB can be determined by the sensing block 350. The HB is provided to the ECC decoder. The ECC decoder can be located in the memory controller 102, on the control die 304, or on the memory die 300.

[0120] Optionally, in step 902, the memory cell can be sensed at the current level of the SB reference level. If the SB reference level is used, the sensing block 350 can determine one or more SBs for each memory cell. The SBs are then provided to the ECC decoder.

[0121] Step 904 includes decoding the encoded data to restore the original data programmed into the group of memory cells. Step 904 may include decoding the ECC codewords stored in the memory cells. The ECC decoder will correct any errors in the encoded data. If the ECC decoder cannot correct all errors using only HB, the current value of SB can be used. Optionally, if decoding the codewords is difficult, a different group of memory cells can be selected. For example, a different group within the same block can be selected, where steps 902 through 904 are repeated. Step 904 results in the restoration of the original programmed data.

[0122] Step 906 includes a group of candidate SB reference level sensing non-volatile memory cells. Figure 10An example of candidate SB reference levels associated with an HB reference level is depicted. Note that in this example, there is a lower candidate SB reference voltage 1018a and an upper candidate SB reference voltage 1018b. A set of candidate SB reference levels may exist for each HB reference level. In the lower-side SB implementation, the lower candidate SB reference voltage 1018a exists (the upper candidate 1018b is not required). In the upper-side SB implementation, the upper candidate SB reference voltage 1018b exists (the lower candidate 1018a is not required). In some cases, process 900 is used to calibrate the SB reference level used when reading data from a page. When there is more than one bit per cell, reading a page may involve reading at more than one HB reference level, each reference level having its own SB reference level. In this case, step 906 may include sensing each of the HB reference levels required for reading the page within a set of candidate SB reference levels. In one embodiment, step 906 is performed by control circuitry 310 on memory die 300. In one embodiment, step 906 is performed by control circuitry 310 on control die 304.

[0123] Step 906 results in data for each candidate SB reference level. The data for each candidate SB reference level is based on sensing at the corresponding candidate SB reference level, but may also be based on sensing at other reference levels. For example, reference... Figure 10 Data for candidate SB reference level 1026 can be based on sensing at SB reference level 1026, HB reference level 1020 and SB reference level 1028.

[0124] Step 908 includes calculating the mutual information (MI) between the restored programmed data and the data sensed against the candidate SB reference levels. This MI serves as a good measure of the extent to which the set of candidate SB reference levels will aid in decoding the data. Therefore, calibrating the SB reference level based on the MI improves the quality of reliability information (e.g., soft bits). In one embodiment, the MI is based on the channel transition matrix. Regarding... Figure 11 and Figures 12A to 12E Further details of an implementation scheme for calculating MI based on the channel transition matrix are shown and described. In one implementation, MI is based on the log-likelihood ratio. Regarding... Figure 13 Further details of the implementation of calculating MI based on log-likelihood ratio are shown and described.

[0125] Step 910 includes selecting a new SB reference level based on MI. In one embodiment, the candidate SB reference level with the highest MI is selected from a set of candidate SB reference levels. This selection can be performed individually for the lower candidate SB reference voltage 1018a and the upper candidate SB reference voltage 1018b for each HB reference level. For example, in Figure 10 In this embodiment, SB reference level 1026 can be selected from the following candidate SB reference level 1018a. Similarly, SB reference level 1028 can be selected from the above candidate SB reference level 1018b. The new SB reference level does not need to be one of the candidate SB reference levels. For example, the new SB reference level can be located between two candidate SB reference levels. In one embodiment, step 910 is performed by control circuitry 310 on memory die 300. In one embodiment, step 910 is performed by control circuitry 310 on control die 304. In one embodiment, step 910 is performed by memory controller 102.

[0126] Now let's discuss this in more detail. Figure 10 . Figure 10 The distribution of two memory cells, 1012 and 1014, is depicted. Figure 10 A diagram of MI 1016 versus the SB reference voltage is also depicted. The two memory cell distributions 1012 and 1014 can be either two memory cell distributions where each memory cell stores one bit (SLC), or two memory cell distributions where each memory cell stores multiple bits per cell (e.g., two bits, three bits, or four bits per cell). In one embodiment, the two memory cell distributions 1012 and 1014 are... Figure 6B Two adjacent distributions in the equation. For example, distribution 1012 can correspond to S3 and distribution 1014 can correspond to S4.

[0127] A reference voltage HB of 1020 and ten candidate reference voltages SB of 1018 are depicted. Figure 9 In one embodiment of step 906, memory cells are sensed across ten SB reference voltages 1018. There may be more or fewer than ten candidate SB voltages 1018. Five lower candidate SB reference voltages 1018a exist, each having a voltage lower than the HB reference voltage 1020. Five upper candidate SB reference voltages 1018b exist, each having a voltage higher than the HB reference voltage 1020. One embodiment is discussed where one candidate on each side of the HB reference voltage 1020 is selected as the new SB reference voltage. However, the new SB reference voltage can be a weighted average of two candidates with the two highest MI values. The weights can be based on the MI of the two candidates. For example, if the MI of one of the two candidates is slightly higher, the new SB reference voltage can be closer to that candidate. The new SB reference voltage can be, for example... Figure 6B Vr4_s2 and Vr4_s3 in the example. However, in some implementations, more than two SB reference voltages can be used for a given HB reference voltage. For example, in Figure 6BIn addition, there are Vr4s1 and Vr4S4 associated with Vr4. In some implementations, these additional SB reference voltages are calibrated separately from the calibrations Vr4_s2 and Vr4_s3.

[0128] Mutual Information (MI) 1016 has an MI for each SB reference level 1018. The MI for a particular SB reference voltage 1018 is a statistical measure of how useful the reliability information (e.g., soft bits) associated with that SB reference voltage is. In other words, the MI indicates how the SB reference voltage will help decode the data. The higher the MI, the more useful the reliability information from the corresponding SB reference voltage will be.

[0129] Mutual information 1022 is highest for any candidate SB reference level 1018a. Mutual information 1022 corresponds to SB reference level 1026. Therefore, this is the MI between the data sensed using HB reference level 1020 and SB reference level 1026 and the original data programmed into the memory cell. Therefore, SB reference level 1026 can be selected as the new SB reference level.

[0130] Mutual information 1024 is highest for any candidate SB reference level 1018b. Mutual information 1024 corresponds to SB reference level 1028. Therefore, this is the MI between the data sensed using HB reference level 1020 and SB reference level 1028 and the original data programmed into the memory cell. Therefore, SB reference level 1028 can be selected as the new SB reference level.

[0131] Therefore, returning to the Figure 9 In the discussion of step 910, a new lower SB reference level 1026 can be selected. Similarly, a new upper SB reference level 1028 can be selected. Note that the lower SB reference level 1026 can be selected independently of the upper SB reference level 1028, allowing them to be in different voltage gaps (or soft bits Δ) relative to the HB reference voltage 1020. Furthermore, the lower and upper SB reference levels can be selected for each HB reference voltage associated with the data of the page read from the memory cell in step 902.

[0132] In some implementations, MI is calculated based on the channel transition matrix. Figure 11 This is a flowchart of one implementation of process 1100, which calculates MI based on the channel transition matrix. Process 1100 provides further details of one implementation of step 908. Step 1102 includes fixing the SB reference voltage on one side of the currently uncalibrated HB reference voltage. Fixing the SB reference voltage means that the SB reference voltage remains unchanged during process 1100. Figures 12A to 12EIn this embodiment, the lower SB reference voltage is calibrated (relative to candidate 1018a). The upper SB reference voltage is fixed at the upper SB reference voltage 1206.

[0133] Step 1104 involves selecting a candidate SB reference voltage on one side of the HB reference voltage being calibrated. Figures 12A to 12E In each case, a different candidate was selected from the next candidate SB reference voltage 1018a.

[0134] Step 1106 includes accessing data from sensing the candidate SB reference voltage. This data may be based on sensing data beyond just the candidate SB reference voltage. For example, for Figure 12A The candidate is the next candidate SB reference voltage 1204. However, the data can also be based on sensing at HB reference voltage 1020 and fixed at SB reference voltage 1206.

[0135] Step 1110 includes calculating the number of bits programmed to 0 in each SB cell. Step 1112 includes calculating the number of bits programmed to 1 in each SB cell. For the purposes of discussion, it will be assumed that memory cells programmed to 1 should have a Vt lower than the HB reference voltage 1020, and memory cells programmed to 0 should have a Vt higher than the HB reference voltage 1020. For example, Figure 12A Distribution 1012 is shown, representing memory cells programmed to "1". Most of those memory cells do indeed have a Vt below the HB reference voltage 1020, but a few have a Vt above the HB reference voltage 1020. Similarly, Figure 12A Distribution 1014 is shown, representing memory cells programmed to "0". Most of those memory cells have a Vt higher than the HB reference voltage 1020, but a few have a Vt lower than the HB reference voltage 1020.

[0136] Figures 12A to 12E An example of bin counting for five different candidate SB reference levels is shown. Figure 12AEight bins are shown for analysis of SB reference voltage 1204. In this example, SB reference voltage 1206 is fixed. Four bins 1202a represent memory cell counts initially programmed to "1". Four bins 1202b represent memory cell counts initially programmed to "0". Each bin 1202 is defined based on the reference voltage. Bin 0 is used to count memory cells with a Vt lower than SB reference voltage 1204. Note that for illustrative purposes, an example of testing the threshold voltage of the memory cells is shown, but different parameters such as resistance can be tested for different types of memory cells. Bin 1 is used to count memory cells with a threshold voltage between SB reference voltage 1204 and HB reference voltage 1020. Bin 2 is used to count memory cells with a threshold voltage between HB reference voltage 1020 and SB reference voltage 1206. Bin 3 is used to count memory cells with a threshold voltage higher than SB reference voltage 1206.

[0137] Figure 12B The bins 1202a and 1202b are shown for analysis of the SB reference voltage 1208. Figure 12C The bins 1202a and 1202b are shown for analysis of the SB reference voltage 1210. Figure 12D The bins 1202a and 1202b are shown for analysis of the SB reference voltage 1212. Figure 12E The diagram shows bins 1202a and 1202b for analyzing SB reference voltage 1214. Note that SB reference voltage 1206 is used in each case. Therefore, when testing the lower candidate SB reference voltage 1018a, the upper SB reference voltage 1018b is fixed. Note that fixing SB reference voltage 1206 is an example. The upper SB reference voltage 1018b can be fixed at different levels.

[0138] Steps 1110 and 1112 can be performed using the following formula. The formula sums all bits (or codewords) in the page.

[0139] N[warehouse = i, programming bit = x]

[0140]

[0141] Where i = 1:#warehouse, and x = 0,1

[0142]

[0143] In the above formula, 1 [condition] This refers to the indicator function. N[I,x] is the number of bits (e.g., memory cells) in a given SB that are programmed to a certain value (i.e., 1 or 0). Figures 12A to 12EThe bins 1202a and 1202b in the middle provide a visual representation of N[I,x].

[0144] Step 1114 involves calculating the channel transition matrix. The channel transition matrix N[I,x] can be calculated using the following formula.

[0145]

[0146] in

[0147] Step 1116 involves calculating MI. MI can be calculated using the following formula.

[0148] MI = H(p) y|x ·p x )-H(p y|x )

[0149] In the above formula, H is the Shannon entropy function, and p x This represents the probability that the programmed data is 0 or 1. The probability can be calculated using the following formula.

[0150]

[0151] When the data is scrambled, the probability can be simplified to p0 = p1 = 0.5.

[0152] Step 1118 is to determine if another candidate SB reference voltage exists to be analyzed. If so, steps 1104 through 1116 are repeated for the next candidate SB reference voltage. For example, after calculating MI for SB reference voltage 1204 (see... Figure 12A ), can calculate MI for SB reference voltage 1208 (see Figure 12B After analyzing the MI for all lower candidate SB reference voltages 1018a, step 1120 is performed. Step 1120 includes selecting the SB reference voltage level that maximizes the MI. Therefore, the MI in step 1116 can be selected for the highest SB reference voltage. Thus, step 1120 can be used, for example, to select the SB reference voltage 1026 from the lower candidate SB reference voltage 1018a (see...). Figure 10 In one implementation, the new SB reference voltage is based on the two candidate SB reference voltage levels with the highest MI. For example, a weighted average of the two candidate SB reference voltage levels can be used, where the weights are based on the corresponding values ​​for MI.

[0153] Then process 1100 can be repeated for the upper SB reference voltage 1018b. The process is similar for the lower SB reference voltage 1018a. However, chamber 1202 will be different. Figures 12A to 12EThe compartment is depicted in the diagram. For all cases, the lower SB reference voltage 1018a is fixed, while the upper SB reference voltage 1018b differs in each case. In this way, MI is determined for each upper SB reference voltage in upper SB reference voltage 1018b. (Refer to...) Figure 10 The execution process 1100 is a technique used to determine MI1016.

[0154] In some implementations, MI is calculated based on the log-likelihood ratio (LLR). Figure 13 This is a flowchart of one embodiment of process 1300, which calculates MI based on LLR. Process 1300 provides further details of one embodiment of step 908 of process 900. Step 1302 includes fixing the SB reference voltage on one side of the currently uncalibrated HB reference voltage. Fixing the SB reference voltage means that the SB reference voltage remains unchanged during process 1300. Step 1304 includes selecting a candidate SB reference voltage on one side of the HB reference voltage being calibrated.

[0155] Step 1306 includes accessing data based on sensing at a candidate SB reference voltage. This data can be based on sensing at more than just the candidate SB reference voltage. For example, the data can also be based on sensing at the HB reference voltage and one or more other SB reference voltages. This is similar to the discussion in step 1106, where data for the candidate SB reference voltage 1204 can also be based on sensing at the HB reference voltage 1020 and the fixed SB reference voltage 1206. Data can also be based on sensing at other SB reference voltages associated with reading a page (or ECC codeword). In one embodiment, data is sent from memory die 300 or control die 304 to memory controller 102.

[0156] Step 1308 includes determining the LLR for the data based on sensing at the candidate SB reference voltage. The LLR is the probability of a decoded bit with a given value. The sign of the LLR typically provides a bit estimate (i.e., a positive LLR corresponds to a bit of 0, and a negative LLR corresponds to a bit of 1). The magnitude of the LLR provides the reliability of the estimate (i.e., |LLR| = 0 means the estimate is completely unreliable, and |LLR| = ∞ means the estimate is completely reliable and the bit value is known). The LLR can be determined by an ECC decoder. In some embodiments, the LLR is determined by a low-density parity-check (LDCP) decoder. In some embodiments, the LLR is determined by the memory controller 102. However, the LLR can be determined by, for example, the ECC engine 330 on the control die 304 or the memory die 300.

[0157] Step 1310 includes estimating the MI based on LLR and programmed data. In one implementation, the MI is calculated using the following formula.

[0158]

[0159] In the above formula, E[] is the expectation function. PB is the programming data that is converted from 0 / 1 to + / -1. For example, PB = 1 - 2x, where x is the programming bit. In other words, 0 can be represented as 1, and 1 can be represented as -1. In the above formula, all bits in the codeword are summed. Therefore, in this example, there are N bits in the codeword. In the above summation, if LLR matches the programming bit (PB), it will be highly helpful for MI.

[0160] Step 1312 is to determine whether there are multiple candidate SB reference voltages to consider. If so, steps 1304 to 1310 are repeated to determine the MI for the next candidate SB reference voltage. After determining the MI for all candidate SB reference voltages, one candidate SB reference voltage is selected in step 1314. Step 1314 involves selecting the candidate SB reference voltage that maximizes the MI. Therefore, step 1314 can be used, for example, to select SB reference voltage 1026 from the next candidate SB reference voltage 1018a (see...). Figure 10 Similarly, step 1314 can be used, for example, to select SB reference voltage 1028 from the above candidate SB reference voltage 1018b (see...). Figure 10 In one implementation, the new SB reference voltage is based on the two candidate SB reference voltages with the highest MI. For example, a weighted average of the two candidate SB reference voltages can be used, where the weights are based on the corresponding values ​​for MI.

[0161] In some implementations, sensing is performed on a predetermined set of candidate SB reference voltages. For example, the reference... Figure 10 Sensing can occur at each of the ten candidate SB reference voltages 1018 to calibrate both the lower and upper SB reference voltages. In another embodiment, time and / or power are saved by avoiding sensing at one or more candidate SB reference voltages. Sensing can be avoided by assuming that the MI for a set of candidate SB reference voltages is a unimodal function with a single peak. This method may be referred to herein as the gradient method.

[0162] Figure 14 This is a flowchart of one implementation of the gradient method process 1400 when sensing and determining MI. Process 1400 is an implementation of steps 906 and 908 of process 900. Step 1402 includes setting the MI tracker to 0. This is the variable used to track MI. As will be seen, if MI cannot increase from one candidate SB reference level to the next candidate SB reference level, the process stops checking for new candidate SB reference levels.

[0163] Step 1404 includes setting the initial SB reference level. The reference level will be set... Figure 15 Discussion procedure 1400. An example of calculating MI for the next candidate SB reference level 1018a will be discussed. The initial SB reference level could be candidate SB reference level 1502.

[0164] Step 1406 includes sensing at an initial candidate SB reference level. The first sensing may occur at candidate SB reference level 1502. Note that sensing may be performed at HB reference level 1020 prior to process 1400. In some embodiments, sensing is also performed at one of the upper SB reference levels 1018b. Additional sensing may be performed to generate data at least in part based on sensing at the lower candidate reference level 1018a.

[0165] Step 1408 includes determining the MI for the candidate SB reference level. In one embodiment, the MI is determined based on the channel transition matrix, as described above in conjunction with procedure 1100. In one embodiment, the MI is determined as described in steps 1104 through 1116 of procedure 1100. In one embodiment, the MI is determined based on the LLR, as described above in conjunction with procedure 1300. In one embodiment, the MI is determined as described in steps 1304 through 1310 of procedure 1300.

[0166] Step 1410 determines whether MI has increased. MI will increase in the first iteration of process 1400. In step 1412, the candidate SB reference level is changed. In one implementation, the voltage of the SB reference level is decreased. For example, the SB reference level is changed to SB reference level 1504. The MI tracker is updated to the current MI, which refers to the MI calculated in step 1408. Then, steps 1406 and 1408 are executed again. Reference Figure 15 In the example, MI 1216 is increased relative to SB reference level 1504, so step 1412 is executed again. This time, the SB reference level is set to SB reference level 1026. The MI tracker is updated to the current MI, which refers to the MI calculated in step 1408. Then, steps 1406 and 1408 are executed again. (Reference) Figure 15 In the example above, MI is increased relative to SB reference level 1026, so step 1412 is executed again. This time, the SB reference level is set to SB reference level 1506. The MI tracker is updated to the current MI, which refers to the MI calculated in step 1408. Then, steps 1406 and 1408 are executed again. (Reference) Figure 15In the example above, the MI does not increase relative to the SB reference level 1026 for SB reference level 1506. Therefore, no further sensing is performed for the next candidate SB reference level 1018a.

[0167] In step 1414, the SB reference level that maximizes MI is selected. Figure 15 In the example, SB reference level 1026 has the highest MI for the next candidate SB reference level 1018a, and is therefore selected. In one implementation, the new SB reference level is based on the two candidate SB reference levels with the highest MI. For example, a weighted average of the two candidate SB reference levels can be used, where the weights are based on the corresponding values ​​for MI.

[0168] The process can be repeated 1400 times for the candidate SB reference level 1018b. Note that... Figure 15 The white arrow for MI 1216 indicates an increase in MI 1216, and the block arrow indicates a decrease in MI 1216. For the upper candidate SB reference level 1018b, sensing can be performed only at the three candidate SB reference levels, where the SB reference level 1028 is selected based on having the maximum MI.

[0169] One implementation includes simulating SB reads. Simulated SB reads can be used to generate additional SBs from a relatively small number of candidate SB reads. Figure 16 The threshold distribution with associated SB and HB reference voltages is depicted. Figure 16 Eight memory cells, 1601 to 1608, are depicted, corresponding to eight data states. Each memory cell stores three bits, or three pages for a group. In one embodiment, each page is stored as an ECC codeword. HB reference voltages 1630, 1632, and 1634 are used to read one of the pages containing data. In one embodiment, if a memory cell is read as having a Vt lower than HB reference voltage 1630, the bit is reported as 1. If a memory cell is read as having a Vt between HB reference voltages 1630 and 1632, the bit is reported as 0. If a memory cell is read as having a Vt between HB reference voltages 1632 and 1634, the bit is reported as 1. If a memory cell is read as having a Vt higher than HB reference voltage 1634, the bit is reported as 0. Figure 16 The HB reference voltage used to read other pages is not shown.

[0170] Consistent with other embodiments herein, ten candidate SB reference voltages are depicted for each HB reference voltage. Lower candidate SB voltage 1620a and upper candidate SB voltage 1620b are depicted by HB reference voltage 1630. Lower candidate SB voltage 1622a and upper candidate SB voltage 1622b are depicted by HB reference voltage 1632. Lower candidate SB voltage 1624a and upper candidate SB voltage 1624b are depicted by HB reference voltage 1634.

[0171] Figure 17 This is a flowchart of one implementation of the digital analog SB reading process 1700. Step 1702 includes setting an initial set of candidate SB reference voltages for the page data. Figure 16 The initial group may include the leftmost candidate SB reference voltage associated with each HB reference voltage. Therefore, in one embodiment of step 1702, a total of three candidate SB reference voltages are selected.

[0172] Step 1704 includes sensing that the group of memory cells is the group of candidate SB reference voltages.

[0173] Step 1706 includes determining the SB for each memory cell. In one embodiment, step 1706 determines the SB in a manner similar to determining the HB. However, instead of using HB reference levels 1630, 1632, and 1634, three candidate SB reference levels are used.

[0174] Step 1708 includes sending SB for each memory cell to memory controller 102. Therefore, bits for a page can be sent to memory controller 102.

[0175] Step 1710 is to determine whether to sense multiple candidate SB reference voltages. Figure 16 In this example, a total of 10 groups of candidate SB reference voltages will be sensed. Each group will have one candidate SB reference voltage for each HB reference voltage. Step 1712 includes changing each candidate SB reference voltage. For example, the next candidate SB reference voltage to the right of each previous candidate SB reference voltage (i.e., a higher voltage) can be selected. Figure 16 In the example, process 1700 will loop ten times, causing ten SBs for each memory cell to be sent to memory controller 102. In other words, SBs for ten pages are sent to memory controller 102.

[0176] Step 1714 involves the memory controller 102 simulating many possible combinations of the SB reference voltage. (Reference) Figure 16It should be noted that there are many possible combinations of the SB reference voltage, assuming one SB reference voltage is used for each HB reference voltage. In one embodiment, a digital simulation was performed to calculate all possible combinations of one SB reference voltage for each HB reference voltage. The digital simulation was based on information contained in ten pages sent to the memory controller 102.

[0177] Figure 18 Two threshold distributions and information from pages sent to memory controller 102 are shown to illustrate an implementation of a digital analog SB read. The diagram depicts... Figure 16 Distributions 1602 and 1603, and lower candidate SB reference voltages 1620a and upper candidate SB reference voltages 1620b. Ten reads refer to the SBs of reading tens of pages in process 1700. If a memory cell is in a "bin" between two SB reference voltages, the numbers 1 and 0 indicate whether the memory cell should be read as 0 or 1. For example, if a memory cell is in bin 1802, it will be read as 0 for reads 1 through 7 and as 1 for reads 8 through 10. Similar reasoning applies to... Figure 18 Other warehouses within.

[0178] This technology can also be used with Figure 16 Other SB bins associated with HB reference voltages. However, memory cells that are read as 0 for reads 1 through 7 and as 1 for reads 8 through 10 can also be in the SB bin associated with HB reference voltage 1634. For example, a read at HB reference voltage 1632 can resolve any ambiguity between these two cases.

[0179] Therefore, digital simulation can determine which SB compartment each memory cell is in. From this SB compartment information, the memory controller 102 can "simulate" SB reads at any combination of SB reference voltages (with one SB reference voltage for each HB reference voltage). Therefore, it is not necessary to read memory cells logically at all these combinations of SB reference voltages. Furthermore, it is not necessary to send SB pages to the memory controller 102 for each combination of SB reference voltages.

[0180] Figure 19 This is a flowchart depicting one embodiment of the process 1900 for transmitting data during calibration of the soft-bit reference level. Step 1902 includes providing undecoded (or raw) data for a codeword from a semiconductor die to a memory controller 102. In one embodiment, undecoded data is provided from a control die 304 to the memory controller 102. In another embodiment, undecoded data is provided from a memory die 300 to the memory controller 102. This is possible... Figure 9 The data read in step 902.

[0181] Step 1904 includes decoding the data using the memory controller 102. Therefore, the memory controller 102 corrects any errors in the data to recover the original data. Step 1904 is... Figure 9 One implementation of step 904.

[0182] Step 1906 includes the memory controller 102 transmitting decoded (and error-correcting) data to the semiconductor die. In one embodiment, decoded data is provided to the control die 304. In one embodiment, decoded data is provided to the memory die 300.

[0183] Step 1908 includes control circuitry on the semiconductor die using the error correction data when calibrating the SB reference voltage. The control circuitry can perform... Figure 9 Steps 906 to 910, process 1100, process 1300 and / or process 1400, but not limited thereto. The control circuit may include, for example, a soft-bit reference voltage calibration 334. The control circuit may include one or more of other elements, such as a state machine 312, a decoder 314, a power control 316 and / or a read / write circuit 328.

[0184] Based on the foregoing, it can be seen that the first aspect includes an apparatus comprising: a memory controller interface; and one or more control circuits configured to connect to a memory structure including non-volatile memory cells. The one or more control circuits are configured to read encoded data from a group of non-volatile memory cells. Reading codewords may include sensing the group at one or more hard bit reference levels. The one or more control circuits are configured to provide the encoded data to a data decoder. The one or more control circuits are configured to receive error correction data from the data decoder to recover the original data programmed into the group. The one or more control circuits are configured to sense the group at candidate soft bit reference levels associated with one or more hard bit reference levels, thereby generating data for each corresponding candidate soft bit reference level. The one or more control circuits are configured to calculate mutual information between the error correction data and the data for each candidate soft bit reference level for each candidate soft bit reference level. The one or more control circuits are configured to establish a soft bit reference level for sensing non-volatile memory cells in the memory structure based on the mutual information.

[0185] In a second aspect, and to facilitate the first aspect, establishing a soft bit reference level for sensing non-volatile memory cells in a memory structure includes one or more control circuits selecting a candidate soft bit reference level having maximum mutual information between error correction data and data for the corresponding candidate soft bit reference level.

[0186] In the third aspect, and in order to facilitate the first or second aspect, for each candidate soft-bit reference level, calculating the mutual information between the error correction data and the data for the corresponding candidate soft-bit reference level includes one or more control circuits: calculating the channel transition matrix for each corresponding candidate soft-bit reference level based on the data sensed at the corresponding candidate soft-bit reference level; and calculating the mutual information between each channel transition matrix and the error correction data.

[0187] In the fourth aspect, and in order to facilitate the first or second aspect, for each candidate soft-bit reference level, calculating the mutual information between the error correction data and the data for the corresponding candidate soft-bit reference level includes one or more control circuits: determining the log-likelihood ratio for each corresponding candidate soft-bit reference level based on the data sensed at the corresponding candidate soft-bit reference level; and calculating the mutual information between the error correction data and the log-likelihood ratio for each corresponding candidate soft-bit reference level.

[0188] In the fifth aspect, and in order to facilitate any of the first to fourth aspects, the candidate soft bit reference level control sensing group includes one or more control circuits sensing a group of non-volatile memory cells for each candidate soft bit reference level in a predetermined set of candidate soft bit reference levels.

[0189] In the sixth aspect, and in order to facilitate any of the first to fifth aspects, the sensing of the candidate soft-bit reference level group and the calculation of mutual information include one or more control circuits: a) sensing the group of non-volatile memory cells at the candidate soft-bit reference level; b) calculating the mutual information between error correction data and data sensed at the candidate soft-bit reference level; and c) repeating a) and b) for different candidate soft-bit reference levels until the mutual information no longer increases.

[0190] In the seventh aspect, and to facilitate any of the first to sixth aspects, the candidate soft bit reference level sensing group includes one or more control circuits: sensing data for multiple groups of candidate soft bit reference levels, wherein each group includes a candidate soft bit level for each hard bit associated with data in the page; instructing the memory controller interface to send a soft bit for each memory cell in the group of candidate soft bit reference levels to the memory controller via a communication channel; and having the memory controller simulate a combination of candidate soft bit reference levels for the page based on the soft bit for each memory cell in the group of candidate soft bit reference levels.

[0191] In the eighth aspect, and in order to facilitate any of the first to seventh aspects, the apparatus includes: a semiconductor die containing a data decoder, the semiconductor die including one or more control circuits configured to: calculate mutual information between error correction data and data for each candidate soft bit reference level; and based on the mutual information, establish a soft bit reference level for sensing non-volatile memory cells in a memory structure.

[0192] In a ninth aspect, and to facilitate any of the first to eighth aspects, the apparatus includes: a semiconductor die including a memory controller interface and one or more control circuits configured to be connected to a memory structure; and a memory controller communicating with the semiconductor die via a communication channel, wherein the memory controller includes a data decoder; wherein the memory controller interface is configured to provide the encoded data to the data decoder via the communication channel.

[0193] In the tenth aspect, and in order to facilitate the ninth aspect, one or more control circuits of the semiconductor die are configured to: receive error correction data from a memory controller to restore the original data programmed into the group; calculate the mutual information between the error correction data and the data for the corresponding candidate soft bit reference level; and based on the mutual information, establish a soft bit reference level for sensing non-volatile memory cells in the memory structure.

[0194] In the eleventh aspect, and in order to facilitate the ninth aspect, the memory controller: receives error correction data from the data decoder to restore the original data programmed into the group; calculates the mutual information between the error correction data and the data for the corresponding candidate soft bit reference level; and establishes a soft bit reference level for sensing non-volatile memory cells in the memory structure based on the mutual information.

[0195] In the twelfth aspect, and in order to facilitate any of the first to eleventh aspects, one or more hard bit reference levels are one or more hard bit reference voltages; sensing the group at the candidate soft bit reference level includes the one or more control circuits sensing the group for each of the one or more hard bit reference voltages as a lower candidate soft bit reference voltage and an upper candidate soft bit reference voltage; calculating the mutual information includes the one or more control circuits calculating the mutual information between the error correction data and the data sensed based on the candidate soft bit reference voltage for each lower candidate soft bit reference voltage and for each upper candidate soft bit reference voltage; establishing the soft bit reference level includes one or more control circuits: i) for each hard bit reference voltage, selecting the lower candidate soft bit reference voltage with the highest mutual information as the calibrated lower soft bit reference voltage; and ii) for each hard bit reference voltage, selecting the upper candidate soft bit reference voltage with the highest mutual information as the calibrated upper soft bit reference voltage.

[0196] One embodiment includes a method of operating a non-volatile memory device. The method includes sensing a group of non-volatile memory cells using one or more HB reference voltages to generate encoded data. The method includes decoding and error-correcting the encoded data to restore data programmed into the group. The method includes sensing a group of lower candidate soft reference voltages and upper candidate soft reference voltages for each of the one or more hard reference voltages. The method includes calculating mutual information between error-corrected data and data sensed based on the candidate soft reference voltages for each lower candidate soft reference voltage and for each upper candidate soft reference voltage. The method includes selecting, for each hard reference voltage, a lower candidate soft reference voltage with the highest mutual information as a calibrated lower soft reference voltage. The method includes selecting, for each hard reference voltage, an upper candidate soft reference voltage with the highest mutual information as a calibrated upper soft reference voltage.

[0197] One embodiment includes a non-volatile memory system comprising a memory structure including non-volatile memory cells. The memory system includes a sensing device for reading codewords from a group of non-volatile memory cells based on one or more hard bit reference levels. The sensing device is further configured to sense the group of candidate soft bit reference voltages, thereby generating data for each respective candidate soft bit reference voltage based on sensing at the respective candidate soft bit reference voltage and the hard bit reference voltage associated with the respective candidate soft bit reference voltage. The memory system includes a decoding device for decoding and error-correcting codewords to recover the original data programmed into the group. The memory system includes a soft bit calibration device for selecting a calibrated soft bit reference voltage based on the highest mutual information between the original data and the data for each candidate soft bit reference voltage.

[0198] In one embodiment, the sensing device includes one or more of a state machine 312, an address decoder 314, a power control 316, a read / write circuit 328, and / or a sensing block 350. In one embodiment, the sensing device performs steps 1102 to 1106 of process 1100. In one embodiment, the sensing device performs steps 1302 to 1306 of process 1300. In one embodiment, the sensing device performs steps 1702 to 1708 of process 1700.

[0199] In one embodiment, the decoding device includes one or more of ECC 226 / 256, ECC engine 330 and / or decoder 390.

[0200] In one embodiment, the soft-position calibration device includes one or more of a read reference voltage calibration engine (225 / 255) and a soft-position reference voltage calibration 334. In one embodiment, the soft-position calibration device performs steps 1110 to 1120 of process 1100. In one embodiment, the soft-position calibration device performs steps 1308 to 1314 of process 1300. In one embodiment, the soft-position calibration device performs steps 1406 to 1414 of process 1400.

[0201] The specific embodiments of the invention described above have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations are possible based on the teachings above. The described embodiments were chosen to best elucidate the principles of the invention and its practical application, thereby enabling others skilled in the art to best use the invention with various modifications suitable for the contemplated particular purpose in various embodiments. The scope of the invention is intended to be defined by the appended claims.

Claims

1. An apparatus comprising: Memory controller interface; as well as One or more control circuits, configured to be connected to a memory structure including non-volatile memory cells, wherein the one or more control circuits are configured to: Reading encoded data from the group of non-volatile memory cells includes sensing the group at one or more hard bit reference levels; The encoded data is provided to the data decoder; Receive error correction data from the data decoder to restore the original data programmed into the group; The group is sensed at candidate soft reference levels associated with the one or more hard reference levels, thereby generating data for each corresponding candidate soft reference level; For each candidate soft-bit reference level, calculate the mutual information between the error correction data and the data for the corresponding candidate soft-bit reference level; as well as Based on the mutual information, a soft bit reference level is established for sensing the non-volatile memory cells in the memory structure.

2. The apparatus of claim 1, wherein establishing the soft bit reference level for sensing non-volatile memory cells in the memory structure includes the one or more control circuits: A candidate soft-bit reference level is selected, the candidate soft-bit reference level having the maximum mutual information between the error correction data and the data for the corresponding candidate soft-bit reference level.

3. The apparatus of claim 1, wherein calculating the mutual information between the error correction data and the data for the corresponding candidate soft-bit reference level for each candidate soft-bit reference level includes the one or more control circuits: The channel transition matrix for each corresponding candidate soft-bit reference level is calculated based on the data sensed at the corresponding candidate soft-bit reference level; and Calculate the mutual information between each channel transition matrix and the error correction data.

4. The apparatus of claim 1, wherein calculating the mutual information between the error correction data and the data for the corresponding candidate soft bit reference level for each candidate soft bit reference level includes the one or more control circuits: The log-likelihood ratio for each corresponding candidate soft-bit reference level is determined based on the data sensed at the corresponding candidate soft-bit reference level; and Calculate the mutual information between the error correction data and the log-likelihood ratio for each corresponding candidate soft bit reference level.

5. The apparatus of claim 1, wherein sensing the group at the candidate soft bit reference level includes the one or more control circuits: The set of non-volatile memory cells is sensed at each of a predetermined set of candidate soft-bit reference levels.

6. The apparatus of claim 1, wherein sensing the group at the candidate soft bit reference level and calculating the mutual information includes the one or more control circuits: a) Sensing the group of non-volatile memory cells at a candidate soft bit reference level; b) Calculate the mutual information between the error correction data and the data sensed at the candidate soft bit reference level; and c) Repeat steps a) and b) for different candidate soft-bit reference levels until the mutual information no longer increases.

7. The apparatus of claim 1, wherein sensing the group at the candidate soft bit reference level to generate data for each candidate soft bit reference level includes the one or more control circuits: Sensing data against multiple sets of candidate soft bit reference levels, where each set includes a candidate soft bit level for each hard bit associated with the data of the page; The memory controller interface is instructed to send soft bits for each memory cell in each group of candidate soft bit reference levels to the memory controller via a communication channel. as well as The memory controller simulates a combination of candidate soft-bit reference levels for the page based on the soft bits for each memory cell in the group for each group of candidate soft-bit reference levels.

8. The apparatus of claim 1, wherein the apparatus comprises: A semiconductor die including the data decoder, the semiconductor die including one or more control circuits, the one or more control circuits being configured to: Calculate the mutual information between the error correction data and the data for each candidate soft bit reference level; as well as Based on the mutual information, a soft bit reference level is established for sensing non-volatile memory cells in the memory structure.

9. The apparatus of claim 1, wherein the apparatus comprises: A semiconductor die, the semiconductor die including the memory controller interface and the one or more control circuits configured to be connected to the memory structure; as well as A memory controller that communicates with the semiconductor die via a communication channel, wherein the memory controller includes the data decoder; The memory controller interface is configured to provide the encoded data to the data decoder via the communication channel.

10. The apparatus of claim 9, wherein one or more control circuits of the semiconductor die are configured to: Receive the error correction data from the memory controller to restore the original data programmed into the group; Calculate the mutual information between the error correction data and the data for the corresponding candidate soft bit reference level; as well as Based on the mutual information, a soft bit reference level is established for sensing non-volatile memory cells in the memory structure.

11. The apparatus of claim 9, wherein the memory controller: Receive the error correction data from the data decoder to restore the original data programmed into the group; Calculate the mutual information between the error correction data and the data for the corresponding candidate soft bit reference level; as well as Based on the mutual information, a soft bit reference level is established for sensing non-volatile memory cells in the memory structure.

12. The apparatus according to claim 1, wherein: The one or more hard bit reference levels are one or more hard bit reference voltages; Sensing the group at the candidate soft bit reference level includes the one or more control circuits sensing the group at the lower candidate soft bit reference voltage and the upper candidate soft bit reference voltage for each of the one or more hard bit reference voltages; Calculating the mutual information includes the one or more control circuits calculating the mutual information between the error correction data and the data sensed based on the candidate soft-bit reference voltage for each lower candidate soft-bit reference voltage and for each upper candidate soft-bit reference voltage; Establishing a soft-bit reference level includes one or more of the following control circuits: i) For each hard bit reference voltage, select the next candidate soft bit reference voltage with the highest mutual information as the next soft bit reference voltage for calibration; as well as ii) For each hard bit reference voltage, select the upper candidate soft bit reference voltage with the highest mutual information as the upper soft bit reference voltage for calibration.

13. A method of operating a non-volatile storage device, the method comprising: A group of non-volatile memory cells is sensed by one or more hard-bit reference voltages to generate coded data; Decode and error-correct the encoded data to restore the data programmed into the group; The group is sensed for the lower candidate soft reference voltage and the upper candidate soft reference voltage for each of the one or more hard reference voltages; For each lower candidate soft-bit reference voltage and for each upper candidate soft-bit reference voltage, calculate the mutual information between the error-corrected data and the data sensed based on the candidate soft-bit reference voltage; For each hard bit reference voltage, the next candidate soft bit reference voltage with the highest mutual information is selected as the next soft bit reference voltage for calibration. as well as For each hard bit reference voltage, the upper candidate soft bit reference voltage with the highest mutual information is selected as the upper soft bit reference voltage for calibration.

14. The method of claim 13, wherein calculating the mutual information between the error-corrected data and the data sensed based on the candidate soft-bit reference voltage comprises: Based on the data sensed at the corresponding candidate soft-bit reference voltage, calculate the channel transition matrix for each lower candidate soft-bit reference voltage and for each upper candidate soft-bit reference voltage. as well as Calculate the mutual information between each channel transition matrix and the restored data programmed into the group.

15. The method of claim 13, wherein calculating the mutual information between the error-corrected data and the data sensed based on the candidate soft-bit reference voltage comprises: Based on the data sensed at the corresponding candidate soft-bit reference voltage, determine the log-likelihood ratio for each lower candidate soft-bit reference voltage and for each upper candidate soft-bit reference voltage; as well as The mutual information between the restored data programmed into the group and the log-likelihood ratio for each corresponding candidate soft bit reference voltage is calculated.

16. A non-volatile memory system, comprising: A memory structure, the memory structure including non-volatile memory cells; A sensing device for reading codewords from a group of non-volatile memory cells based on one or more hard bit reference levels, the sensing device being further configured to sense the group at a candidate soft bit reference voltage, thereby generating data for each corresponding candidate soft bit reference voltage based on the sensing at the corresponding candidate soft bit reference voltage and the hard bit reference voltage associated with the corresponding candidate soft bit reference voltage; A decoding device for decoding and error-correcting the codewords to restore the original data programmed into the group; as well as A soft-bit calibration device for selecting a calibrated soft-bit reference voltage based on the highest mutual information between the raw data and the data for each candidate soft-bit reference voltage.

17. The non-volatile memory system of claim 16, wherein the soft bit calibration device is further configured to: The channel transition matrix for each candidate soft-bit reference voltage is calculated based on the information sensed at the corresponding candidate soft-bit reference voltage; and Calculate the mutual information between each channel transition matrix and the error-corrected codeword.

18. The non-volatile memory system of claim 16, wherein the soft bit calibration device is further configured to: The log-likelihood ratio of each candidate soft-bit reference voltage is determined based on the information sensed at the corresponding candidate soft-bit reference voltage; and The mutual information between the error-corrected codeword and the log-likelihood ratio for each candidate soft-bit reference voltage is calculated.

19. The non-volatile memory system of claim 16, wherein the soft bit calibration device is further configured to: a) Instruct the sensing device to sense the group of non-volatile memory cells at a candidate soft bit reference voltage; b) Determine the mutual information between the error-corrected codeword and the data sensed for the candidate soft-bit reference voltage; and c) Repeat a) and b) for different candidate soft-bit reference voltages until the mutual information no longer increases.

20. The non-volatile memory system of claim 16, wherein the soft bit calibration device is further configured to: The sensing device is instructed to sense multiple sets of candidate soft-bit reference voltages, wherein each set includes a candidate soft-bit level for each hard bit associated with the codeword; and Based on the soft bits for each memory cell in the group for each group of candidate soft bit reference voltages, a combination of candidate soft bit reference voltages for the codeword is simulated.

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