Method for manufacturing a semiconductor structure and structure thereof

Abstract

The embodiment of the present disclosure relates to the semiconductor field, and provides a manufacturing method of a semiconductor structure and a structure thereof, wherein the manufacturing method of the semiconductor structure comprises the following steps: providing a substrate; forming, on a surface of the substrate, a stack structure and a first isolation layer between adjacent stack structures along a first direction, the stack structure comprising a first interlayer dielectric layer, an initial active layer and a second interlayer dielectric layer; etching part of the initial active layer to form a first trench; forming a first metal conductive layer in the first trench; etching part of the first interlayer dielectric layer and the second interlayer dielectric layer to form a second trench; forming a second metal conductive layer in the second trench, the second metal conductive layer covering a sidewall of the second trench and being in contact with the first metal conductive layer; and etching part of the first metal conductive layer and the second metal conductive layer to form a lower electrode structure arranged in an array along the first direction and a second direction. The performance of the semiconductor structure can be improved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductors, and in particular to a method for manufacturing a semiconductor and its structure. Background Technology

[0002] As semiconductor structures continue to evolve and their critical dimensions shrink, limitations in lithography machines restrict further reduction. Therefore, achieving higher storage density chips on a single wafer remains a key research focus for many researchers and semiconductor professionals. In two-dimensional or planar semiconductor devices, memory cells are arranged horizontally. Thus, the integration density of two-dimensional or planar semiconductor devices is determined by the area occupied by each memory cell. This integration density is significantly influenced by the technology used to form intricate patterns, limiting the potential for further increases in integration density. Consequently, the development of semiconductor devices is moving towards three-dimensional semiconductor devices.

[0003] However, in three-dimensional semiconductor devices, there is still a continuous pursuit of better performance. Summary of the Invention

[0004] This disclosure provides a method for fabricating a semiconductor structure and the structure thereof, which can at least improve the performance of the semiconductor structure.

[0005] According to some embodiments of this disclosure, one aspect of this disclosure provides a method for fabricating a semiconductor structure, comprising: providing a substrate; forming a stacked structure spaced apart along a first direction and a first isolation layer located between adjacent stacked structures on the surface of the substrate, the stacked structure including a first interlayer dielectric layer, an initial active layer and a second interlayer dielectric layer; etching a portion of the initial active layer to form a first trench; forming a first metal conductive layer in the first trench, the first metal conductive layer filling the first trench and contacting and connecting with a retained initial active layer; etching a portion of the first interlayer dielectric layer and the second interlayer dielectric layer to form a second trench; forming a second metal conductive layer in the second trench, the second metal conductive layer covering the sidewalls of the second trench and contacting and connecting with the first metal conductive layer; etching a portion of the first metal conductive layer and the second metal conductive layer to form a lower electrode structure arrayed along the first direction and a second direction; the first direction being perpendicular to the substrate surface and the second direction being parallel to the substrate surface.

[0006] In some embodiments, after forming the lower electrode structure, the method further includes: forming a capacitor dielectric layer, the capacitor dielectric layer covering the surfaces of the first metal conductive layer and the second metal conductive layer; forming an upper electrode structure, the upper electrode structure being located on the surface of the capacitor dielectric layer and filling the second trench, wherein the lower electrode structure, the capacitor dielectric layer and the upper electrode structure constitute the capacitor.

[0007] In some embodiments, before forming the capacitor dielectric layer, the method further includes: forming a fill layer that fills the second trench and exposes the sidewalls of the first metal conductive layer and the second metal conductive layer; etching the sidewalls of the first metal conductive layer and the second metal conductive layer to form the lower electrode structure; and removing the fill layer to expose the surface of the lower electrode structure.

[0008] In some embodiments, the step of forming the capacitor dielectric layer includes: forming the capacitor dielectric layer covering the sidewall of the first isolation layer to form a capacitor that shares the capacitor dielectric layer in the first direction.

[0009] In some embodiments, the method further includes: etching the remaining initial active layer to form a third trench; forming an oxide semiconductor layer located within the third trench, the oxide semiconductor layer being in contact with the first metal conductive layer.

[0010] In some embodiments, after forming the oxide semiconductor layer, the method for fabricating the semiconductor structure includes: etching the oxide semiconductor layer and the remaining first metal conductive layer to form a fourth trench and spaced oxide semiconductor layers and spaced first metal conductive layers, the fourth trench spacing the stacked structure along the second direction; the remaining oxide semiconductor layer constitutes an active structure.

[0011] In some embodiments, after etching a portion of the oxide semiconductor layer, the method for fabricating the semiconductor structure further includes: forming a second isolation layer, the second isolation layer being located between adjacent oxide semiconductor layers arranged along the second direction and the second isolation layer filling the fourth trench.

[0012] In some embodiments, the material of the oxide semiconductor layer includes indium gallium zinc oxide or zinc tin oxide.

[0013] In some embodiments, after forming the oxide semiconductor layer, the method further includes: forming word lines that surround the surface of the oxide semiconductor layer and extend along one of the first direction or the second direction; and forming bit lines that surround the surface of the oxide semiconductor layer, spaced from the word lines and extending along the other of the first direction or the second direction.

[0014] According to some embodiments of this disclosure, another aspect of this disclosure provides a semiconductor structure, including: a substrate; active structures located on the surface of the substrate and spaced apart along a first direction and a second direction; lower electrode structures electrically connected to each of the active structures in a one-to-one correspondence, the first direction being perpendicular to the substrate surface and the second direction being parallel to the substrate surface; a first isolation layer located between adjacent active structures in the first direction and between adjacent lower electrode structures in the first direction; the lower electrode structure includes: a first metal conductive layer and a second metal conductive layer, the second metal conductive layer including a first side surface, the first side surface being in contact with the first metal conductive layer, a second side surface, the second side surface being opposite to the first side surface and in contact with the first isolation layer, and a third side surface, the third side surface being connected to the first side surface and the second side surface.

[0015] In some embodiments, the device further includes: a capacitor dielectric layer covering the surface of the second metal conductive layer and the sidewall of the first metal layer; an upper electrode structure covering the surface of the capacitor dielectric layer, wherein the lower electrode structure, the capacitor dielectric layer, and the upper electrode structure constitute a capacitor.

[0016] In some embodiments, the capacitor dielectric layer further covers the sidewall of the first isolation layer to form a capacitor that shares the capacitor dielectric layer along the first direction.

[0017] In some embodiments, the projection of the upper electrode structure onto the substrate lies within the projection of the lower electrode structure onto the substrate.

[0018] In some embodiments, the active structure is made of oxide semiconductor.

[0019] In some embodiments, the method further includes: a word line that surrounds the surface of the active structure and extends along one of the first direction or the second direction; and a bit line that surrounds the surface of the oxide semiconductor layer, is spaced from the word line, and extends along the other of the first direction or the second direction.

[0020] The technical solution provided by the embodiments of this disclosure has at least the following advantages: by forming a stacked structure spaced apart along a first direction and a first isolation layer between adjacent stacked structures on the substrate surface, etching a portion of the initial active layer to form a first trench, forming a first metal conductive layer in the first trench, etching a portion of the first interlayer dielectric layer and the second interlayer dielectric layer to form a second trench, forming a second metal conductive layer in the second trench, and etching the first metal conductive layer and the second metal conductive layer to form an arrayed lower electrode structure, the capacitance can be increased by using the first metal conductive layer and the second metal conductive layer to form the lower electrode structure, thereby improving the performance of the semiconductor structure. Attached Figure Description

[0021] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figures 1 to 25 This is a schematic diagram of the structure corresponding to each step of a method for fabricating a semiconductor structure according to an embodiment of this disclosure. Detailed Implementation

[0023] As the background technology shows, with the continuous miniaturization of integration, three-dimensional semiconductor devices are still constantly pursuing higher storage density, faster speed and lower power consumption.

[0024] This disclosure provides a method for fabricating a semiconductor structure. The method involves forming a first isolation layer between adjacent stacked structures spaced along a first direction on the surface of a substrate, then etching an initial active layer to form a first trench, and forming a first metal conductive layer within the first trench. A portion of the first interlayer dielectric layer and the second interlayer dielectric layer are etched to form a second trench, and a second metal conductive layer is formed within the second trench. The first and second metal conductive layers are then etched to form an arrayed lower electrode structure. The lower electrode structure, composed of the first and second metal conductive layers, can increase the capacitance, thereby improving the performance of the semiconductor structure.

[0025] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0026] refer to Figures 1 to 25 , Figures 1 to 25 This is a schematic diagram of the structure corresponding to each step of a method for fabricating a semiconductor structure according to an embodiment of this disclosure.

[0027] For details, please refer to Figure 1 and Figure 2 ,in, Figure 1 This is a top view of the semiconductor structure. Figure 2 For along Figure 1 A cross-sectional view along the AA direction.

[0028] Specifically, a substrate 100 is provided, and stacked structures 110 arranged at intervals along a first direction X and a first isolation layer 120 located between adjacent stacked structures 110 are formed on the surface of the substrate 100. The stacked structure 110 includes a first interlayer dielectric layer 130, an initial active layer 140 and a second interlayer dielectric layer 150.

[0029] In some embodiments, the substrate 100 is a semiconductor material, including but not limited to any one of a silicon substrate, a germanium substrate, a germanium-silicon substrate, or a silicon carbide substrate. The substrate 100 may also be an ion-doped substrate, wherein the doping ions are N-type ions or P-type ions. Specifically, N-type ions may be phosphorus ions, arsenic ions, or antimony ions, and P-type ions may be boron ions, indium ions, or boron fluoride ions.

[0030] In some instances, the material of the first interlayer dielectric layer 130 can be the same as that of the second interlayer dielectric layer 150, such as silicon oxide or other insulating materials. The formation of the first interlayer dielectric layer 130 and the second interlayer dielectric layer 150 can provide a basis for the subsequent formation of bit lines, and the first interlayer dielectric layer 130 and the second interlayer dielectric layer 150 can also isolate the initial active layer 140 spaced apart in the first direction X.

[0031] The material of the initial active layer 140 can be silicon carbide or polycrystalline silicon semiconductor material. Forming the initial active layer 140 can provide a process basis for the subsequent formation of an array of active structures.

[0032] refer to Figure 3 The initial active layer 140 is etched to form a first trench 160, which provides a process basis for the subsequent formation of an oxide semiconductor layer.

[0033] In some embodiments, the method of etching the initial active layer 140 may be to use wet etching to etch the initial active layer 140 through the sidewalls of the stacked structure 110.

[0034] refer to Figure 4 A first conductive metal layer 170 is formed in the first trench 160, the first conductive metal layer 170 fills the first trench 160 and is in contact with the retained initial active layer 140. The first conductive metal layer 170 can serve as part of the lower electrode structure of the capacitor.

[0035] In some embodiments, the material of the first metal conductive layer 170 may be titanium, titanium nitride, cobalt, or nickel, etc.

[0036] In some embodiments, the material of the first metal conductive layer 170 can also be a metal semiconductor material, in which case a portion of the first metal conductive layer 170 can also serve as the drain of an active structure.

[0037] refer to Figure 5 The first interlayer dielectric layer 130 and the second interlayer dielectric layer 150 are etched to form a second trench 180. The formation of the second trench 180 can provide a process basis for the subsequent formation of the second metal conductive layer.

[0038] In some embodiments, when etching the first interlayer dielectric layer 130 and the second interlayer dielectric layer 150, only a portion of the surface of the first metal conductive layer 170 is exposed. That is, in the third direction Z, the length of the etched first interlayer dielectric layer 130 and the second interlayer dielectric layer 150 is less than the length of the first metal conductive layer 170. This allows control over the length of the subsequently formed second metal conductive layer, preventing contact between the second metal conductive layer and the gate or word line of the active structure, thereby improving the reliability of the semiconductor structure. In other embodiments, the lengths of the etched first and second interlayer dielectric layers may be equal to the length of the first metal conductive layer, thereby increasing the length of the second metal conductive layer, which in turn increases the length of the lower electrode structure of the semiconductor structure, thus improving the performance of the semiconductor structure.

[0039] refer to Figure 6 A second metal conductive layer 190 is formed in the second trench 180. The second metal conductive layer 190 covers the sidewall of the second trench 180 and is in contact with the first metal conductive layer 170. By forming the second metal conductive layer 190, the facing area between the lower electrode structure and the subsequently formed upper electrode structure can be increased, thereby increasing the capacitance of the capacitor and thus improving the performance of the semiconductor structure.

[0040] refer to Figures 7 to 10The first metal conductive layer 170 and the second metal conductive layer 190 are etched to form a lower electrode structure 200 arranged in an array along a first direction X and a second direction Y; the first direction X is perpendicular to the surface of the substrate 100, and the second direction Y is parallel to the surface of the substrate 100. By etching the first metal conductive layer 170 and the second metal conductive layer 190, the spaced lower electrode structure 200 can be formed, thereby providing a process basis for the subsequent formation of spaced capacitors.

[0041] In some embodiments, before forming the capacitor dielectric layer, the method further includes: forming a fill layer 210, the fill layer 210 filling the second trench 180 and exposing the sidewalls of the first metal conductive layer 170 and the second metal conductive layer 190; etching the sidewalls of the first metal conductive layer 170 and the second metal conductive layer 190 to form the lower electrode structure 200; and removing the fill layer 210 to expose the surface of the lower electrode structure 200. Understandably, during the formation of the second conductive metal layer 190, a portion of the second conductive metal layer 190 also covers a portion of the sidewalls of the first conductive metal layer 170 and the first isolation layer 120. By forming the fill layer 210, the first conductive metal layer 170 and the second conductive metal layer 190 located on the inner wall of the second trench 180 can be protected during subsequent etching. Etching the fill layer 210 exposes the sidewalls of the first conductive metal layer 170 and the second conductive metal layer 190 in the third direction Z, effectively separating the second conductive metal layers 190 connected in the first direction X into multiple discrete second conductive metal layers 190. This avoids the lower electrode structure 200 arranged in the first direction X being connected in series. By exposing the sidewalls of the first conductive metal layer 170 and the second conductive metal layer 190 through the fill layer 210, this unwanted portion of the second conductive metal layer 190 can be etched simultaneously during the etching process. (Reference) Figure 8 By etching a portion of the stacked structure to form trenches extending along the third direction Z and penetrating the stacked structure 110 in the first direction X, a lower electrode structure 200 spaced in the second direction is formed, and then reference is made to... Figure 10 Removing the filler layer provides a process basis for the subsequent formation of the dielectric layer and the upper electrode structure.

[0042] refer to Figure 11 and Figure 12After forming the lower electrode structure, the process further includes: forming a capacitor dielectric layer 220, which covers the surfaces of the first metal conductive layer 170 and the second metal conductive layer 190; forming an upper electrode structure 230, which is located on the surface of the capacitor dielectric layer 220 and fills the second trench 180. The lower electrode structure 200, the capacitor dielectric layer 220, and the upper electrode structure 230 constitute a capacitor 240. By forming the capacitor 240 and utilizing its different states, the '0' state or '1' state of the semiconductor structure can be characterized to achieve data storage, where the '0' state can represent a low level and the '1' state can represent a high level.

[0043] In some embodiments, the step of forming the capacitor dielectric layer 220 includes: forming a capacitor dielectric layer 220 covering the sidewalls of the first isolation layer 120 to form a capacitor 240 sharing the capacitor dielectric layer 220 in the first direction X. By forming a capacitor 240 sharing the capacitor dielectric layer 220 in the first direction X, the number of steps in forming the capacitor 240 can be reduced, thereby forming the capacitor dielectric layer 220 by directly depositing the material of the capacitor dielectric layer 220.

[0044] In some embodiments, such as Figure 9 As shown, after forming the arrayed lower electrode structure 200, the method further includes forming a third isolation layer 250, which can be used to isolate adjacent capacitors 240. The third isolation layer 250 is filled in a trench extending along the third direction Z and penetrating the stacked structure 110 in the first direction X to isolate adjacent lower electrode structures 200 in the second direction Y.

[0045] In some embodiments, the process of removing the filler layer 210 further includes: removing the third isolation layer 250 in the same process step, and then forming the capacitor dielectric layer 220 and the upper electrode structure 230 after removing the third isolation layer 250. In this way, the capacitors 240 arranged along the second direction Y also share the capacitor dielectric layer 220 and the upper electrode structure 230. That is, the capacitors 240 arranged along the first direction X and the second direction Y share the capacitor dielectric layer 220 and the upper electrode structure 230.

[0046] In some embodiments, the material of the third isolation layer 250 can be the same as that of the filler layer 210, which can be insulating materials such as silicon oxide or silicon nitride. In other embodiments, the material of the third isolation layer 250 can be different from that of the filler layer 210.

[0047] The material of the lower electrode structure 200 may include any one or any combination of metal materials such as titanium nitride, tantalum nitride, copper or tungsten; the material of the capacitor dielectric layer 220 may include any one or any combination of ZrO, AlO, ZrNbO, ZrHfO, ZrAlO; the material of the upper electrode structure 230 may include compounds formed by one or two of metal nitrides and metal silicides, such as titanium nitride, titanium silicide, nickel silicide, titanium silicon nitride or other conductive materials, or the material of the upper electrode structure 230 may also be a conductive semiconductor material, such as polycrystalline silicon, germanium silicon, etc.

[0048] It is understandable that the relative area between the lower electrode structure 200 and the upper electrode structure 230 of capacitor 260, the distance between the lower electrode structure 200 and the upper electrode structure 230, and the material of the capacitor dielectric layer 220 may all affect the capacitance of capacitor 260. Therefore, the relative area between the lower electrode structure 200 and the upper electrode structure 230, the distance between the lower electrode structure 200 and the upper electrode structure 230, and the material of the capacitor dielectric layer 220 of capacitor 260 can be set according to actual needs.

[0049] refer to Figure 13 and Figure 14 The method for fabricating the semiconductor structure further includes: etching the remaining initial active layer 140 to form a third trench 270; forming an oxide semiconductor layer 280, which is located within the third trench 270 and is in contact with the first metal conductive layer 170. Forming the oxide semiconductor layer 280 provides a technological basis for forming the active structure, and using the oxide semiconductor layer 280 as a subsequent active structure formation can improve the carrier transport rate of the active structure.

[0050] In some embodiments, the material of the oxide semiconductor layer 280 may include indium gallium zinc oxide or zinc tin oxide. Using indium gallium zinc oxide or zinc tin oxide as the material of the oxide semiconductor layer can improve the ion mobility of the oxide semiconductor layer 280, thereby improving the performance of the subsequent oxide semiconductor layer 280 as a channel region. The material of the oxide semiconductor layer 280 may also be one or more of other similar materials such as indium zinc oxide, indium gallium silicon oxide, indium tungsten oxide, indium oxide, tin oxide, titanium oxide, magnesium zinc oxide, zirconium indium zinc oxide, hafnium indium zinc oxide, tin indium zinc oxide, aluminum tin indium zinc oxide, silicon indium zinc oxide, aluminum zinc tin oxide, gallium zinc tin oxide, zirconium zinc tin oxide, etc.

[0051] refer to Figure 15In some embodiments, after forming the oxide semiconductor layer 280, the method for fabricating the semiconductor structure further includes: etching the oxide semiconductor layer 280 and the remaining first metal conductive layer 170 to form a fourth trench 290 and spaced oxide semiconductor layers 280 and spaced first metal conductive layers 170. The fourth trench 290 spaces the stacked structure 110 along the second direction Y, and the remaining oxide semiconductor layer 280 constitutes an active structure. By forming the fourth trench 290, the oxide semiconductor layer 280 and the first metal conductive layer 170 can be cut off, that is, an active structure spaced along the second direction Y and capacitors 260 can be formed. It can be understood that in the previous steps, only part of the first metal conductive layer 170 is etched, that is, the capacitors 260 arranged along the second direction Y are still connected through the first metal conductive layer 170. By forming the fourth trench 290, the capacitors 260 can be spaced along the second direction Y.

[0052] refer to Figure 16 In some embodiments, after etching a portion of the oxide semiconductor layer 280, the method for fabricating the semiconductor structure further includes: forming a second isolation layer 310, wherein the second isolation layer 310 is located between adjacent oxide semiconductor layers 280 arranged along the second direction Y and the second isolation layer 310 fills the fourth trench 290. By forming the second isolation layer 310, the insulation of adjacent active structures can be improved, thereby improving the reliability of the semiconductor structure.

[0053] refer to Figures 17 to 25 In some embodiments, after forming the oxide semiconductor layer 280, the method further includes: forming a word line 320, the word line 320 surrounding the surface of the oxide semiconductor layer 280 and extending along one of a first direction X or a second direction Y; forming a bit line 350, the bit line 350 surrounding the surface of the oxide semiconductor layer 280, the bit line 350 being spaced from the word line 320 and extending along the other of the first direction X or the second direction Y.

[0054] For details, please refer to Figure 17 In some embodiments, after forming the second isolation layer 310, the process further includes etching a portion of the first interlayer dielectric layer 130 and the second interlayer dielectric layer 150 to expose a portion of the surface of the active structure 300, thereby providing a process basis for the subsequent formation of word lines.

[0055] In some embodiments, before forming the word line 320, a gate dielectric layer 340 is formed, the gate dielectric layer 340 being located on the surface of the active structure 300. By forming the gate dielectric layer 340, direct contact between the word line 320 and the active structure 300 can be avoided, thereby preventing semiconductor structure abnormalities.

[0056] In some embodiments, the material of the gate dielectric layer 340 may be an insulating material such as silicon oxide, silicon nitride, or hafnium oxide, and the material of the gate dielectric layer 340 may be selected according to the required dielectric constant of the gate dielectric layer 340.

[0057] In some embodiments, the thickness of the gate dielectric layer 340 can be 8 to 20 nm. It is understood that, under the same conditions, the thinner the gate dielectric layer 340, the better the performance of the semiconductor structure, but the lower the reliability of the semiconductor structure and the more prone it is to current tunneling. Correspondingly, the thicker the gate dielectric layer 340, the higher the reliability of the semiconductor structure, but the performance of the semiconductor structure will decrease. By setting the thickness of the gate dielectric layer 340 to 8 to 20 nm, the performance of the semiconductor structure can be improved while ensuring a certain level of reliability.

[0058] By forming the gate dielectric layer 340 and the first isolation layer 120, the oxide semiconductor layer 280 of the active structure 300 can also be isolated from oxygen and water vapor in the air, thereby improving the reliability of the semiconductor structure.

[0059] refer to Figures 18 to 23 A word line 320 is formed. In some embodiments, the word line 320 includes a first word line 321 and a second word line 322. The first word line 321 is disposed around the active structure 300, and the second word line 322 covers the sidewall of the first word line 321. By forming the first word line 321 surrounding the active structure 300, the contact area between the word line 320 and the active structure 300 can be increased. By forming the second word line 322, a contact basis can be provided for the subsequent formation of conductive posts corresponding to and connected to the word line 320. In other embodiments, the first word line may only cover a portion of the surface of the active structure. Taking the shape of the active structure as a cuboid as an example, the first word line may only cover the top and bottom surfaces of the active structure, or cover the top surface, bottom surface, and one of the side surfaces connected to the top and bottom surfaces of the active structure.

[0060] refer to Figure 18 In some embodiments, a first word line 321 is formed, which is located on the surface of the gate dielectric layer 340.

[0061] refer to Figure 19 , Figure 19 For along Figure 1 A cross-sectional view along the BB direction can be understood as follows: Figure 19 Not in Figure 18 Based on the process steps, these are just cross-sectional views of the semiconductor structure from different perspectives.

[0062] refer to Figure 20The stacked structure 110 is etched along the second direction Y to form a fifth trench 330. The fifth trench 330 exposes the sidewall of the first word line 321. The formation of the fifth trench 330 can provide a process basis for the formation of the second word line 322.

[0063] refer to Figure 21 This forms the second initial character line 323, which fills the fifth groove 330.

[0064] refer to Figure 22 The second initial word line 323 and the first isolation layer 120 are etched, and the remaining second initial word line 323 serves as the second word line 322. In some embodiments, the lengths of the second word lines 322 arranged along the first direction X decrease sequentially along the second direction Y. That is, the lengths of the second word lines 322 decrease sequentially from the direction closest to the substrate 100 toward the direction away from the substrate 100. Taking the three second word lines 322 in the figure as an example, the second word line 322 closest to the substrate 100 is called the first sub-word line, the second word line 322 in the middle is called the second sub-word line, and the second word line 322 farthest from the substrate 100 becomes the third sub-word line. The lengths of the first sub-word line, the second sub-word line, and the third sub-word line decrease sequentially along the second direction. This allows conductive pillars to be formed on the portion of the first sub-word line longer than the second sub-word line, and on the portion of the second sub-word line longer than the third sub-word line. This enables the signals from different word lines 320 to be extracted or corresponding electrical signals to be provided to different word lines 320.

[0065] refer to Figure 23 The first word line 321 and the gate dielectric layer 340 are etched to expose part of the surface of the active structure 300, thereby providing a process basis for the subsequent formation of bit lines.

[0066] refer to Figure 24 In some embodiments, taking the bit line 350 extending along the first direction X as an example, a bit line 350 can contact and connect with multiple active structures 300 arranged along the first direction. That is, a bit line 350 can transmit signals to multiple active structures 300 arranged along the first direction X, thereby increasing the stacking density of the semiconductor structure and improving the space utilization of the semiconductor structure.

[0067] However, it is understandable that the extension direction of bit line 350 intersects the extension direction of word line 320, and there is only one intersection point between bit line 350 and word line 320. In other words, an active structure 300 can be selected through word line 320 and bit line 350.

[0068] In some embodiments, before forming the bit line 350, the method further includes: forming a fourth isolation layer 360, the fourth isolation layer 360 covering a portion of the surface of the active structure 300, and the fourth isolation layer 360 contacting and connecting with the sidewalls of the word line 320 arranged in a third direction Z; forming the bit line 350, the bit line 350 contacting and connecting with the sidewalls of the fourth isolation layer 360 arranged in a third direction Z, and the bit line 350 covering the active structure 300. By forming the fourth isolation layer 360, the bit line 350 can be isolated from the first word line 321, thereby avoiding electrical connection between the bit line 350 and the word line 320, thereby improving the reliability of the semiconductor structure. The formation of the bit line 350 provides a basis for reading and writing data in the semiconductor structure.

[0069] In some embodiments, the step of forming the fourth isolation layer 360 may include: forming a fourth initial isolation layer, the fourth initial isolation layer being located between the first isolation layer 120 and the active structure 300; etching the fourth initial isolation layer, the remaining fourth initial isolation layer serving as the fourth isolation layer 360.

[0070] In some embodiments, etching the fourth initial isolation layer also includes etching the first isolation layer 120. During the formation of the bit line 350, the formed bit line 350 may also cover the sidewall of the first isolation layer 120.

[0071] refer to Figure 1 and Figure 25 The method for fabricating a semiconductor structure also includes: forming a conductive post 370, with each conductive post 370 correspondingly connected to a word line 320. The conduction and disconnection of the word line 320 can be controlled by providing an electrical signal to the conductive post 370. By providing signals to different conductive posts 370, an electrical signal can be provided to the word line 320 connected to that conductive post 370. In other words, different word lines 320 can be controlled by controlling different conductive posts 370.

[0072] In this embodiment, a first isolation layer 120 is formed between adjacent stacked structures 110 spaced along a first direction X on the surface of a substrate 100. Then, an initial active layer 140 is etched to form a first trench 160. A first metal conductive layer 170 is formed in the first trench 160. A portion of the first interlayer dielectric layer 130 and the second interlayer dielectric layer 150 are etched to form a second trench 180. A second metal conductive layer 190 is formed in the second trench 180. The first metal conductive layer 170 and the second metal conductive layer 190 are etched to form an arrayed lower electrode structure 200. The lower electrode structure 200 formed by the first metal conductive layer 170 and the second metal conductive layer 190 can increase the capacitance of the capacitor 240, thereby improving the performance of the semiconductor structure.

[0073] This disclosure also provides a semiconductor structure that can be formed by some or all of the steps of the above-described semiconductor structure fabrication method. The same or corresponding parts can be referred to the above embodiments, and will not be repeated below. The semiconductor structure provided by this disclosure will be described below with reference to the accompanying drawings.

[0074] refer to Figure 1 , Figure 22 , Figure 24 and Figure 25 The semiconductor structure may include: a substrate 100; active structures 300 located on the surface of the substrate 100 and spaced apart along a first direction X and a second direction Y; lower electrode structures 200 electrically connected to the active structures 300 in a one-to-one correspondence, the first direction X being perpendicular to the surface of the substrate 100 and the second direction Y being parallel to the surface of the substrate 100; a first isolation layer 120 located between adjacent active structures 300 in the first direction X and between adjacent lower electrode structures 200 in the first direction X; the lower electrode structure 200 includes: a first metal conductive layer 170 and a second metal conductive layer 190, the second metal conductive layer 190 including a first side surface that is in contact with the first metal conductive layer 170, a second side surface that is directly opposite to the first side surface and in contact with the first isolation layer 120, and a third side surface that is connected to the first side surface and the second side surface.

[0075] By providing the second metal conductive layer 190 with three sides, wherein the first side is in contact with the first metal conductive layer 170, the second side is opposite to the first side and in contact with the first isolation layer 120, and the third side is connected to the first and second sides, the facing area between the lower electrode structure 200 of the capacitor and the capacitor dielectric layer and the upper electrode structure can be increased, thereby increasing the capacitance of the capacitor and improving the performance of the semiconductor structure.

[0076] In some embodiments, the semiconductor structure may further include: a capacitor dielectric layer 220, which covers the surface of the second metal conductive layer 190 and the sidewalls of the first metal conductive layer 170; an upper electrode structure 230, which covers the surface of the capacitor dielectric layer 220; and a lower electrode structure 200, the capacitor dielectric layer 220, and the upper electrode structure 230, which together constitute a capacitor 240. The distance between the lower electrode structure 200 and the upper electrode structure 230 of the capacitor 240, as well as the material of the capacitor dielectric layer 220, may affect the capacitance of the capacitor 240. Therefore, the spacing between the lower electrode structure 200 and the upper electrode structure 230, the facing area between the lower electrode structure 200 and the upper electrode structure 230, and the material of the capacitor dielectric layer 220 can be set according to actual needs.

[0077] In some embodiments, the capacitor dielectric layer 220 may further cover the sidewalls of the first isolation layer 120 to form a capacitor 240 sharing the capacitor dielectric layer 220 along the first direction X. By providing the capacitor dielectric layer 220 to cover the sidewalls of the first isolation layer 120, the process steps of the semiconductor structure can be reduced, and by providing the capacitor 240 sharing the capacitor dielectric layer 220, the space utilization of the semiconductor structure can also be improved.

[0078] In some embodiments, the projection of the upper electrode structure 230 onto the substrate 100 lies within the projection of the lower electrode structure 200 onto the substrate 100. In other words, in the third direction Z, the length of the upper electrode structure 230 is less than the length of the lower electrode structure 200. By setting the length of the upper electrode structure 230 to be less than the length of the lower electrode structure 200, the fabrication difficulty of the semiconductor structure can be reduced, and the exposure of the second metal conductive layer 190 during the formation of the word line 320 can be avoided, thereby improving the reliability of the semiconductor structure.

[0079] In some embodiments, the active structure 300 may be made of an oxide semiconductor and is in contact with the first metal conductive layer 170. By using an oxide semiconductor as the material of the active structure 300, the activity of charge carriers within the active structure 300 can be improved, thereby increasing the carrier mobility within the active structure 300.

[0080] In some embodiments, the system may further include: a word line 320, which surrounds the surface of the active structure 300 and extends along either a first direction X or a second direction Y; and a bit line 350, which surrounds the surface of the active structure 300, is spaced from the word line 320, and extends along either the first direction X or the second direction Y. By setting the word line 320 to surround the surface of the active structure 300, the conduction of the active structure 300 can be controlled. By setting the bit line 350 to surround the surface of the active structure 300, the reading and writing of the semiconductor structure can be achieved through the bit line 350.

[0081] In some embodiments, the semiconductor structure further includes a gate dielectric layer 340, which is located on the surface of the active structure 300. By forming the gate dielectric layer 340, direct contact between the word line 320 and the active structure 300 can be avoided, thereby preventing semiconductor structure abnormalities.

[0082] In some embodiments, the word line 320 includes a first word line 321 and a second word line 322. The first word line 321 is disposed around the active structure 300, and the second word line 322 covers the sidewall of the first word line 321. By forming the first word line 321 surrounding the active structure 300, the contact area between the word line 320 and the active structure 300 can be increased. By forming the second word line 322, a contact basis can be provided for the subsequent formation of conductive posts corresponding to and connected to the word line 320.

[0083] In some embodiments, the first word line 321 surrounds the surface of the gate dielectric layer 340.

[0084] In some embodiments, the semiconductor structure further includes a first interlayer dielectric layer 130 and a second interlayer dielectric layer 150. By providing the first interlayer dielectric layer 130 and the second interlayer dielectric layer 150, the insulation of the capacitor 240 and the word line 320 can be improved, and the semiconductor structure can also be supported, thereby preventing the semiconductor structure from deforming and improving the reliability of the semiconductor structure.

[0085] In some embodiments, the semiconductor structure may further include a second isolation layer 310, which is located between adjacent active structures 300 arranged along the second direction Y. The second isolation layer 310 can improve the insulation of the adjacent active structures 300, thereby improving the reliability of the semiconductor structure.

[0086] In some embodiments, the semiconductor structure may further include: a fourth isolation layer 360, which covers a portion of the surface of the active structure 300, and the fourth isolation layer 360 is in contact with the sidewall of the word line 320 arranged in the third direction Z. The fourth isolation layer 360 can isolate the bit line 350 from the word line 320, thereby avoiding electrical connection between the bit line 350 and the word line 320, thereby improving the reliability of the semiconductor structure.

[0087] In some embodiments, the semiconductor structure may further include: a conductive post 370, which is connected to a word line 320. The word line 320 can be turned on and off by providing an electrical signal to the conductive post 370. By providing signals to different conductive posts 370, an electrical signal can be provided to the word line 320 connected to the conductive post 370. In other words, different word lines 320 can be controlled by controlling different conductive posts 370.

[0088] This embodiment of the disclosure provides an active structure 300 located on the surface of a substrate 100, and a lower electrode structure 200 electrically connected to the active structure in a one-to-one correspondence. The lower electrode structure 200 includes a first metal conductive layer 170 and a second metal conductive layer 190. The second metal conductive layer 190 includes a first side surface that is in contact with the first metal conductive layer 170, a second side surface that is directly opposite to the first side surface and in contact with the first isolation layer 120, and a third side surface that is connected to the first and second side surfaces. By increasing the surface area of ​​the second metal conductive layer 190, the area between the lower electrode structure 200 and the upper electrode structure 230 in the capacitor 240 can be increased, thereby increasing the capacitance of the capacitor 240 and improving the performance of the semiconductor structure.

[0089] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the embodiments of this disclosure. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of the embodiments of this disclosure; therefore, the scope of protection of the embodiments of this disclosure should be determined by the scope defined in the claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: Provide a base; A stacked structure arranged at intervals along a first direction and a first isolation layer located between adjacent stacked structures are formed on the surface of the substrate. The stacked structure includes a first interlayer dielectric layer, an initial active layer, and a second interlayer dielectric layer. The initial active layer is etched to form a first trench; A first metal conductive layer is formed in the first trench, the first metal conductive layer fills the first trench and is in contact with the retained initial active layer; Etch portions of the first interlayer dielectric layer and the second interlayer dielectric layer to form a second trench; A second metal conductive layer is formed in the second trench, the second metal conductive layer covers the sidewall of the second trench and is in contact with the first metal conductive layer; Etch portions of the first and second metal conductive layers to form a lower electrode structure arranged in an array along the first and second directions; The first direction is perpendicular to the substrate surface, and the second direction is parallel to the substrate surface.

2. The method for fabricating a semiconductor structure according to claim 1, characterized in that, After forming the lower electrode structure, the process further includes: A capacitor dielectric layer is formed, which covers the surfaces of the first metal conductive layer and the second metal conductive layer; An upper electrode structure is formed, which is located on the surface of the capacitor dielectric layer and fills the second trench. The lower electrode structure, the capacitor dielectric layer, and the upper electrode structure constitute the capacitor.

3. The method for fabricating a semiconductor structure according to claim 2, characterized in that, Before forming the capacitor dielectric layer, the method further includes: forming a filler layer, wherein the filler layer fills the second trench and exposes the sidewalls of the first metal conductive layer and the second metal conductive layer; The sidewalls of the first and second metal conductive layers are etched to form the lower electrode structure; Remove the filler layer to expose the surface of the lower electrode structure.

4. The method for fabricating a semiconductor structure according to claim 2, characterized in that, The step of forming the capacitor dielectric layer includes: forming the capacitor dielectric layer covering the sidewall of the first isolation layer to form a capacitor that shares the capacitor dielectric layer in the first direction.

5. The method for fabricating a semiconductor structure according to claim 1, characterized in that, Also includes: The remaining initial active layer is etched to form a third trench; An oxide semiconductor layer is formed, which is located within the third trench and is in contact with the first metal conductive layer.

6. The method for fabricating a semiconductor structure according to claim 5, characterized in that, After forming the oxide semiconductor layer, the method for fabricating the semiconductor structure includes: The oxide semiconductor layer and the remaining first metal conductive layer are etched to form a fourth trench and spaced oxide semiconductor layers and spaced first metal conductive layers, the fourth trench spacing the stacked structure along the second direction; The retained oxide semiconductor layer constitutes an active structure.

7. The method for fabricating a semiconductor structure according to claim 6, characterized in that, After etching a portion of the oxide semiconductor layer, the method for fabricating the semiconductor structure further includes: forming a second isolation layer, wherein the second isolation layer is located between adjacent oxide semiconductor layers arranged along the second direction and the second isolation layer fills the fourth trench.

8. The method for fabricating a semiconductor structure according to claim 5, characterized in that, The materials of the oxide semiconductor layer include indium gallium zinc oxide or zinc tin oxide.

9. The method for fabricating a semiconductor structure according to claim 5, characterized in that, After forming the oxide semiconductor layer, the method further includes: forming word lines that surround the surface of the oxide semiconductor layer and extend along either the first direction or the second direction; Bit lines are formed that surround the surface of the oxide semiconductor layer, are spaced apart from word lines, and extend along either the first direction or the second direction.

10. A semiconductor structure, characterized in that, include: Base; Active structures located on the surface of the substrate and arranged at intervals along a first direction and a second direction; The lower electrode structure is electrically connected to the active structure in a one-to-one correspondence, wherein the first direction is perpendicular to the substrate surface and the second direction is parallel to the substrate surface; A first isolation layer is located between adjacent active structures in a first direction and between adjacent lower electrode structures in a first direction; The lower electrode structure includes: a first metal conductive layer and a second metal conductive layer. The second metal conductive layer includes a first side surface, which is in contact with the first metal conductive layer; a second side surface, which is directly opposite to the first side surface and in contact with the first isolation layer; and a third side surface, which is connected to the first side surface and the second side surface. A capacitor dielectric layer, which covers the surface of the second metal conductive layer and the sidewalls of the first metal conductive layer.

11. The semiconductor structure according to claim 10, characterized in that, Also includes: An upper electrode structure covers the surface of the capacitor dielectric layer, and the lower electrode structure, the capacitor dielectric layer, and the upper electrode structure constitute a capacitor.

12. The semiconductor structure according to claim 11, characterized in that, The capacitor dielectric layer also covers the sidewall of the first isolation layer to form a capacitor that shares the capacitor dielectric layer along the first direction.

13. The semiconductor structure according to claim 11, characterized in that, The projection of the upper electrode structure onto the substrate lies within the projection of the lower electrode structure onto the substrate.

14. The semiconductor structure according to claim 10, characterized in that, The active structure is made of oxide semiconductor.

15. The semiconductor structure according to claim 14, characterized in that, Also includes: The word line surrounds the surface of the active structure and extends along either the first direction or the second direction; Bit lines surround the surface of the active structure, the bit lines are spaced apart from the word lines, and the bit lines extend along either the first direction or the second direction.

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