Chip, package structure and manufacturing method of chip

Abstract

The embodiment of the present disclosure relates to the field of semiconductor, and provides a chip, a packaging structure and a manufacturing method of the chip, wherein the chip comprises: a chip, the chip has opposite first and second surfaces, and comprises an electrical connection region and a support region; wherein the first surface of the electrical connection region is protruded in a direction away from the second surface relative to the first surface of the support region. At least the problems of mutual crosstalk between different signals and large signal time delay in the packaging structure can be solved.

Description

Technical Field

[0001] This disclosure relates to the semiconductor field, and in particular to a chip, a packaging structure, and a method for manufacturing the chip. Background Technology

[0002] Generally speaking, chips using wire bond packaging technology transmit signals through metal wires of a certain length. This method can produce an impedance effect when transmitting high-frequency signals, creating an obstacle in the signal's path.

[0003] FC-BGA (Flip Chip Ball Grid Array) is a flip-chip ball grid array packaging technology and the most common packaging technology for graphics accelerator chips. FC-BGA uses small balls instead of pins used in wirebonding packaging to connect to the processor, providing the shortest possible external connection distance. This packaging technology not only provides excellent electrical performance but also reduces interconnect losses and inductance, lowers electromagnetic interference, and can withstand higher frequencies, making it possible to push overclocking limits. Summary of the Invention

[0004] This disclosure provides a chip, a packaging structure, and a method for manufacturing the chip, which at least helps to solve the problems of crosstalk between different signals and large signal delay in the packaging structure.

[0005] According to some embodiments of this disclosure, one aspect of this disclosure provides a chip, including: a chip having a first side and a second side opposite to each other, wherein the first side includes an electrical connection region and a support region; wherein the first side of the electrical connection region protrudes in a direction away from the second side relative to the first side of the support region.

[0006] According to other embodiments of this disclosure, the thickness between the first surface and the second surface of the electrical connection region is a first thickness; the thickness between the first surface and the second surface of the support region is a second thickness, and the difference between the first thickness and the second thickness is in the range of 5 μm to 85 μm.

[0007] According to other embodiments of this disclosure, the first thickness is 120 μm to 200 μm.

[0008] According to other embodiments of this disclosure, the second thickness is 125 μm to 205 μm.

[0009] According to other embodiments of this disclosure, the chip has two of the said support regions, and the electrical connection region is located between the two said support regions.

[0010] According to other embodiments of this disclosure, the support region surrounds the periphery of the electrical connection region.

[0011] According to other embodiments of this disclosure, the chip has two of the electrical connection regions, and the support region is located between the two electrical connection regions.

[0012] According to other embodiments of this disclosure, in the arrangement direction of the electrical connection region and the support region, the width of the support region is a first width, and the sum of the widths of the support region and the two support regions is a second width, wherein the ratio of the first width to the second width is less than or equal to 1 / 3.

[0013] According to other embodiments of this disclosure, the second surface of the electrical connection region is flush with the second surface of the support region.

[0014] According to other embodiments of this disclosure, the first side is the front side of the chip; the second side is the back side of the chip.

[0015] According to other embodiments of this disclosure, the support area further includes a through hole that connects the first surface and the second surface of the chip in a direction perpendicular to the first surface.

[0016] According to some embodiments of this disclosure, another aspect of this disclosure provides a packaging structure, including: a substrate; a chip as described in any of the above embodiments, wherein the first surface of the chip faces the substrate; an electrical connection portion, one end of which is located on the first surface of the electrical connection region, and the other end of which is electrically connected to the substrate; a support portion, one end of which is located on the first surface of the support region, and the other end of which is in contact with the surface of the substrate; and the length of the electrical connection portion is less than the length of the support portion in a direction from the first surface to the second surface.

[0017] According to other embodiments of this disclosure, the length of the electrical connection portion is 30 μm to 60 μm in the direction from the first surface to the second surface.

[0018] According to other embodiments of this disclosure, the length of the support portion is 50 μm to 90 μm in the direction from the first surface to the second surface.

[0019] According to other embodiments of this disclosure, the electrical connection portion includes a first conductive post; the support portion includes a second conductive post; wherein, in the direction from the first surface to the second surface, the length of the first conductive post is less than the length of the second conductive post.

[0020] According to other embodiments of this disclosure, the electrical connection portion further includes: a first solder ball located away from the first conductive post and the first surface; the support portion further includes: a second solder ball located away from the second conductive post and the first surface.

[0021] According to some embodiments of this disclosure, another aspect of this disclosure also provides a method for manufacturing a chip, comprising: providing an initial chip, the initial chip having a first initial surface and a second initial surface opposite to each other, the initial chip including an initial electrical connection region and an initial support region; performing a thinning process on the initial chip of the initial support region from the direction of the first initial surface to the second initial surface, the initial chip after thinning processing serving as a chip, and the first initial surface, the second initial surface, the initial electrical connection region and the initial support region after thinning processing serving as the first surface, the second surface, the electrical connection region and the support region respectively.

[0022] According to other embodiments of this disclosure, the thinning process includes: forming a mask layer on the first initial surface of the initial electrical connection region; using the mask layer as a mask, etching the first initial surface of the initial support region; and removing the mask layer.

[0023] According to other embodiments of this disclosure, the thinning process includes: using a local polishing process to polish away a portion of the thickness of the initial chip from the initial support region.

[0024] According to other embodiments of this disclosure, after the thinning process, the method further includes: forming an electrical connection portion, one end of which is located on the first surface of the electrical connection region; forming a support portion, one end of which is located on the first surface of the support region; wherein, in the direction from the first surface to the second surface, the length of the electrical connection portion is less than the length of the support portion.

[0025] The technical solutions provided in this disclosure have at least the following advantages:

[0026] In the chip technical solution provided in this disclosure embodiment, the chip has a first surface and a second surface opposite to each other, and includes an electrical connection area and a support area; wherein, the first surface of the electrical connection area protrudes in a direction away from the second surface relative to the first surface of the support area. Thus, when this chip is applied to a packaging structure, the length of the electrical connection portion connected to the electrical connection area of ​​the chip is small, while the length of the support portion connected to the support area of ​​the chip is large. The electrical connection portion serves to transmit signals, while the support portion serves to support the chip. Since the parasitic parameters, signal delay, and crosstalk between different signals introduced by the electrical connection portion are positively correlated with the length of the electrical connection portion used for signal transmission, reducing the length of the electrical connection portion used for signal transmission can reduce the parasitic parameters introduced by the electrical connection portion, reduce signal delay, and mitigate crosstalk between different signals. Attached Figure Description

[0027] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a cross-sectional schematic diagram of a packaging structure.

[0029] Figure 2 A schematic cross-sectional view of a chip provided in an embodiment of this disclosure;

[0030] Figure 3 This is a top view of a chip structure provided in an embodiment of the present disclosure;

[0031] Figure 4 This is a top view schematic diagram of a chip according to an embodiment of the present disclosure;

[0032] Figure 5 A cross-sectional structural diagram of another chip provided in an embodiment of this disclosure;

[0033] Figure 6 This is a schematic diagram of a packaging structure provided in an embodiment of the present disclosure;

[0034] Figure 7 A schematic diagram of another packaging structure provided in an embodiment of this disclosure;

[0035] Figures 8 to 9 This is a schematic diagram of the structure of each step in a chip manufacturing method provided in an embodiment of the present disclosure. Detailed Implementation

[0036] Current packaging structures may lead to crosstalk between different signals and significant signal delays.

[0037] refer to Figure 1 , Figure 1 This is a cross-sectional schematic diagram of a packaging structure. The packaging structure includes a substrate 11 and a chip 10 stacked together. The chip 10 is a complete sheet structure. Multiple electrical connection portions 12 located between the chip 10 and the substrate 11 connect the chip 10 and the substrate 11. The packaging structure also includes solder balls 13 located on the bottom surface of the substrate 11.

[0038] In the above-described packaging structure, each electrical connection portion 12 has the same length, and the length of each electrical connection portion 12 is relatively long. When the packaging structure is in operation, the signal is transmitted through the electrical connection portion 12. The long electrical connection portion 12 will introduce a larger parasitic parameter to the electrical connection portion 12, reduce impedance, increase signal delay, and cause problems such as impedance discontinuity and signal crosstalk between different electrical connection portions 12.

[0039] This disclosure provides a chip with opposing first and second surfaces. The chip includes an electrical connection region and a support region, wherein the first surface of the electrical connection region protrudes away from the second surface of the chip relative to the first surface of the support region. This reduces the distance between the electrical connection region and the substrate, and also reduces the length of the electrical connection portion connecting the electrical connection region and the substrate. Since the parasitic parameters, signal delay, and crosstalk between different signals generated by the electrical connection portion are positively correlated with the length of the electrical connection portion, reducing the length of the electrical connection portion reduces the parasitic parameters, signal delay, and crosstalk between different signals. Furthermore, this disclosure also reduces impedance discontinuities by providing such a chip.

[0040] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0041] Figures 2 to 5 These are schematic diagrams illustrating different chip structures provided in embodiments of this disclosure. Figure 2 This is a cross-sectional structural diagram of a chip provided in one embodiment of the present disclosure. Figure 3 for Figure 2 A top-view diagram of the chip's structure; Figure 4 for Figure 2 Another top-view diagram of the chip structure.

[0042] refer to Figure 2 and Figure 3 The chip 100 has a first surface 21 and a second surface 22 opposite to each other, and the first surface 21 includes an electrical connection region 101 and a support region 102; the first surface 21 of the electrical connection region 101 protrudes in a direction away from the second surface 22 relative to the first surface 21 of the support region 102. In some embodiments, the chip 100 has two support regions 102, and the electrical connection region 101 is located between the two support regions 102.

[0043] Chip 100 can be a memory semiconductor chip. Each of the memory semiconductor chips can be, for example, a volatile memory semiconductor chip, which can be Dynamic Random Access Memory (DRAM) or Static Random Access Memory (SRAM). Non-volatile memory semiconductor chips can be Phase-Change Random Access Memory (PRAM), Magnetoresistive Random Access Memory (MRAM), Ferroelectric Random Access Memory (FeRAM), or Resistive Random Access Memory (RRAM). Chip 100 can also be flash memory, such as NAND (Not AND) flash memory.

[0044] Alternatively, chip 100 can also be a logic chip. For example, chip 100 can be a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, or an application processor (AP) chip.

[0045] Chip 100 has a front side and a back side. In some embodiments, the first side 21 can be the front side of chip 100, and the second side 22 can be the back side of chip 100. In other embodiments, the first side 21 can be the back side of chip 100, and the second side 22 can be the front side of chip 100. The front side of chip 100 has electrical connection areas distributed thereon, which are used for electrical connection with other devices in subsequent packaging structures.

[0046] The second surface 22 can be a flat surface. It is understood that "flat" here means that the second surface 22 is planar and its surface roughness is within the allowable threshold of the process. That is, in some embodiments, the second surface 22 of the electrical connection region 101 and the second surface 22 of the support region 102 can be flush. In the fabrication of the chip 100, both sides of the initial chip are flush. Furthermore, changing only the first surface 21 of the electrical connection region 101 and the first surface 21 of the support region 102 can achieve the technical effects of reducing latency, reducing parasitic parameters, and mitigating crosstalk between different signals; whether or not the second surface 22 is processed does not affect the technical effects. To simplify process steps, reduce process costs, and improve production efficiency, the second surface 22 of the electrical connection region 101 and the support region 102 may not be processed; therefore, the second surface 22 of the electrical connection region 101 can be flush with the second surface 22 of the support region 102.

[0047] Chip 100 will subsequently be used to form a package structure, which typically includes a substrate and multiple stacked chips 100. Electrical connection area 101 is the area where electrical connections are to be formed, enabling electrical connections between chip 100 and adjacent chips, or between chip 100 and the substrate. Support area 102 is the area where support portions are to be formed, used to support chip 100 and adjacent chips, or to support chip 100 and the substrate.

[0048] In some embodiments, reference Figure 2 and Figure 4 The support area 102 can be disposed around the periphery of the electrical connection area 101, wherein the support area 102 can be disposed in a circle around the electrical connection area 101 to form a closed area. The support area 102 may also include multiple spaced sub-support areas, and the multiple sub-support areas are arranged sequentially around the electrical connection area. In other embodiments, refer to Figure 5 The chip 100 may also have two electrical connection regions 101, with the support region 102 located between the two electrical connection regions 101. In some other embodiments, the chip 100 may also have multiple support regions 102 and multiple electrical connection regions 101, and the specific distribution of the support regions 102 and electrical connection regions 101 can be reasonably set according to actual electrical connection requirements and support requirements. Specifically, the quantitative and positional relationships between the electrical connection regions 101 and the support regions 102 can vary to some extent. For example, the electrical connection regions 101 may surround the periphery of the support regions 102, with the support regions 102 located at the center of the chip; or, the chip 100 may have multiple electrical connection regions 101 and multiple support regions 102, with each electrical connection region 101 and each support region 102 arranged alternately, etc.

[0049] In some embodiments, along the arrangement direction of the electrical connection region 101 and the support region 102, the width of the support region 102 is a first width, and the sum of the widths of the two support regions 102 is a second width, with the ratio of the first width to the second width being less than or equal to 1 / 3. If the width of the support region 102 is too large, the size range of the electrical connection region 101 will be too small, affecting the performance of the device and increasing the manufacturing difficulty. Therefore, the width of the support region 102 needs to be selected within a suitable range. When the width of the support region 102 is less than or equal to one-third of the width of the chip 100, it will not affect the performance of the device, and the manufacturing difficulty will be lower. It is understandable that if the width of the support region 102 is too small, it will also increase the manufacturing difficulty. Therefore, the width of the support region 102 should not be too small either. The width of the support region 102 is the first width, and the sum of the widths of the two support regions 102 is the second width, with the ratio of the first width to the second width being less than or equal to 1 / 3.

[0050] The thickness of the chip corresponding to the electrical connection area 101 is greater than the thickness of the chip corresponding to the support area 102. It can be understood that the thickness here refers to the thickness along the direction from the first surface 11 to the second surface 12.

[0051] In some embodiments, the thickness between the first surface 21 and the second surface 22 of the electrical connection region 101 is a first thickness; the thickness between the first surface 21 and the second surface 22 of the support region 102 is a second thickness, and the difference between the first thickness and the second thickness can be in the range of 5 μm to 85 μm. The first thickness is greater than the second thickness, and the first thickness can be 5 μm to 85 μm thicker than the second thickness, that is, the thickness of the chip 100 corresponding to the electrical connection region 101 can be 5 μm to 85 μm thicker than the thickness of the chip 100 corresponding to the support region 102. For example, the thickness of the chip 100 corresponding to the electrical connection region 101 can be 8 μm, 11 μm, 20 μm, 22 μm, 35 μm, 44 μm, 58 μm, 63 μm, 77 μm, 83 μm, etc., thicker than the thickness of the chip 100 corresponding to the support region 102. Such a thickness range setting allows the chip 100 to achieve a better reduction in latency while still functioning normally. If the difference between the first and second thicknesses is too small, it may not effectively reduce time delay; if the difference is too large, it will result in material waste. Therefore, it is necessary to select an appropriate range for the thickness difference.

[0052] Regarding the specific values ​​of the first and second thicknesses in chip 100, in some embodiments, the first thickness can be 120μm to 200μm. For example, the first thickness can be 130μm, 145μm, 158μm, 164μm, 178μm, 183μm, 199μm, etc. In other embodiments, the second thickness can be 125μm to 205μm. For example, the second thickness can be 130μm, 149μm, 156μm, 168μm, 172μm, 183μm, 194μm, 203μm, etc. Such thickness settings ensure that when this chip 100 is applied to a packaging structure, the length of the electrical connection portion 120 can be reduced without changing the overall size of the packaging structure.

[0053] In some embodiments, the support region 102 may further include a through-hole, which connects the first surface 21 and the second surface 22 of the chip 100 in a direction perpendicular to the first surface 21. The through-hole can be used to connect wiring, allowing the chip 100 to be electrically connected to other devices along the through-hole in subsequent packaging structures.

[0054] The chip 100 provided in the above embodiment includes an electrical connection region 101 and a support region 102. The electrical connection region 101 protrudes from the support region 102 on one side of the chip 100, and the thickness of the electrical connection region 101 is greater than the thickness of the support region 102. Thus, when this chip 100 is applied to a packaging structure, the protruding side of the electrical connection region 101 faces the substrate, and the length of the electrical connection portion 101 connected to the electrical connection region 101 is less than the length of the support portion connected to the support region 102. This reduces the length of the electrical connection portion used for signal transmission connected to the electrical connection region 101. Since the parasitic parameters, signal delay, and crosstalk between different signals introduced by the electrical connection portion are positively correlated with the length of the electrical connection portion, reducing the length of the electrical connection portion used for signal transmission can reduce the parasitic parameters introduced by the electrical connection portion, reduce signal delay, and alleviate crosstalk between different signals.

[0055] Accordingly, another embodiment of this disclosure also provides a packaging structure, which includes the chip provided in the above embodiments. The packaging structure provided in another embodiment of this disclosure will be described in detail below with reference to the accompanying drawings. For parts that are the same as or corresponding to the previous embodiment, please refer to the corresponding descriptions of the foregoing embodiments; detailed descriptions will not be repeated below.

[0056] Figure 6 This is a cross-sectional schematic diagram of a packaging structure provided in an embodiment of the present disclosure.

[0057] refer to Figure 6The packaging structure includes: a chip 100 as provided in any of the above embodiments, wherein the first surface 21 of the chip 100 is directly opposite to the substrate 110; an electrical connection portion 120, one end of which is located on the first surface 21 of the electrical connection region 101, and the other end of which is electrically connected to the substrate 110; and a support portion 130, one end of which is located on the first surface 21 of the support region 102, and the other end of which is in contact with the surface of the substrate 110. In the direction from the first surface 21 to the second surface 22 (i.e., from bottom to top), the length of the electrical connection portion 120 is less than the length of the support portion 130.

[0058] When the packaged structure is in operation, the electrical connection portion 120 transmits electrical signals between the substrate 110 and the chip 100. The support portion 130 does not transmit electrical signals; it only supports the chip 100, maintains its balance, and ensures the stability of the packaged structure. Therefore, the number of support portions 130 is selected based on the number of support portions 102 that can stably support the chip 100. For example, the number of support portions 130 corresponding to one support area 102 can be one, two, or three, etc.

[0059] Because the chip 100 has a special structure including an electrical connection region 101 and a support region 102, and the electrical connection region 101 protrudes relative to the support region 102 in the direction connecting the electrical connection portion 120 and the support portion 130. The distance from the first surface 21 of the electrical connection region 101 to the substrate surface is smaller than the distance from the first surface 21 of the support region 102 to the substrate surface. The distance from the first surface 21 of the electrical connection region 101 to the substrate surface corresponds to the length of the electrical connection portion 120, and the distance from the first surface 21 of the support region 102 to the substrate surface corresponds to the length of the support portion 130. Therefore, the length of the support portion 130 is greater than the length of the electrical connection portion 120, and the length of the electrical connection portion 120 can be effectively reduced. Crosstalk between different signals will also be reduced, the impedance discontinuity length will be shortened, the additional parasitic parameters introduced will be reduced, and the signal delay will be reduced.

[0060] Specifically, in some embodiments, the length of the electrical connection portion 120 in the direction from the first surface to the second surface can be 30μm to 60μm. For example, the length of the electrical connection portion 120 can be 31μm, 38μm, 45μm, 50μm, 59μm, etc. If the length of the electrical connection portion 120 is too long, it may not be able to achieve the desired effect of reducing latency and crosstalk between different signals. If the length of the electrical connection portion 120 is too short, it may cause short-circuit errors in the packaging structure, affecting the yield of the packaging structure. Therefore, it is necessary to select a suitable length range for the electrical connection portion 120. When the length of the electrical connection portion 120 is within this range, it can achieve the desired effect of reducing latency and crosstalk between different signals, while also avoiding short-circuit errors in the packaging structure.

[0061] In some embodiments, the length of the support portion 130 in the direction from the first surface 21 to the second surface 22 is 50 μm to 90 μm. For example, the length of the support portion 130 can be 52 μm, 58 μm, 65 μm, 77 μm, 86 μm, etc. If the length of the support portion 130 is too long or too short, it may prevent the support portion 130 from effectively supporting the chip 100 and the substrate 110 and maintaining the stability of the package structure. Therefore, it is necessary to select an appropriate range for the length of the support portion 130. When the length of the support portion 130 is within this range, the support portion 130 can effectively support the chip 100 and the substrate 110 and maintain the stability of the package structure.

[0062] Figure 7 This is a cross-sectional schematic diagram of another packaging structure provided according to an embodiment of this disclosure. (See reference...) Figure 7 In some embodiments, the electrical connection portion 120 may include a first conductive post 121, and the support portion 130 may include a second conductive post 131. Specifically, in the direction from the first surface 21 to the second surface 22, the length of the first conductive post 121 is less than the length of the second conductive post 131. Since the crosstalk and signal delay generated by the electrical connection portion 120 between different signals mainly originate from the first conductive post 121, to reduce the length of the electrical connection portion 120, it is necessary to ensure that the length of the first conductive post 121 can be effectively reduced; that is, in the direction from the first surface 21 to the second surface 22, the length of the first conductive post 121 is less than the length of the second conductive post 131. This reduces the length of the electrical connection portion 120, thereby reducing signal delay and crosstalk between different signals.

[0063] Specifically, the material of the first conductive post 121 may include at least one of copper (Cu), nickel (Ni), or gold (Au). The material of the second conductive post 131 may include at least one of copper (Cu), nickel (Ni), or gold (Au).

[0064] In some embodiments, the electrical connection portion 120 may further include a first solder ball 122 located on the first conductive post 121 away from the first surface 21; the support portion 130 may further include a second solder ball 132 located on the second conductive post 131 away from the first surface 21. The solder ball can effectively connect different components to achieve a good consolidation and fixation effect.

[0065] The packaging structure may further include a substrate 110, which may be a printed circuit board (PCB). The substrate 110 may be a rigid PCB or a flexible PCB. An electrical connection portion 120 may be located on the surface of the substrate 110. In some embodiments, the electrical connection portion 110 may be electrically connected to a circuit within the substrate 110, thereby allowing the electrical connection area 101 of the chip 100 to be electrically connected to the circuit within the substrate 110 via the electrical connection portion 102. In other embodiments, the substrate 110 may also be a wafer carrier, serving as a carrier for the electrical connection portion 120 and the support portion 130, and the substrate 110 may not have any circuitry.

[0066] Additionally, the substrate 110 may also include solder balls 140, which may be made of tin.

[0067] The packaging structure provided in this disclosure includes the chip 100 provided in the above-described chip 100 embodiments. The protruding side of the electrical connection region 101 in the chip 100 faces the substrate. An electrical connection portion 120 connects the first surface 21 of the electrical connection region 120 of the chip 100 to the surface of the substrate 110, and the electrical connection portion 120 is used to transmit electrical signals. A support portion 130 connects the first surface 21 of the support region 102 of the chip 100 to the surface of the substrate 110, serving to support the chip 100. The length of the electrical connection portion 120 is less than the length of the support portion 130, effectively reducing the length of the electrical connection portion 120 used for signal transmission. Since the parasitic parameters, signal delay, and crosstalk between different signals introduced by the electrical connection portion 120 are positively correlated with the length of the electrical connection portion 120, reducing the length of the electrical connection portion 120 used for signal transmission can reduce the parasitic parameters introduced by the electrical connection portion 120, reduce signal delay, and alleviate crosstalk between different signals.

[0068] Accordingly, another embodiment of this disclosure also provides a chip manufacturing method, which can be used to manufacture the chip provided in the above embodiments. The chip manufacturing method provided in another embodiment of this disclosure will be described in detail below with reference to the accompanying drawings. For parts that are the same as or corresponding to the previous embodiment, please refer to the corresponding descriptions of the foregoing embodiments; detailed descriptions will not be repeated below.

[0069] Figure 8 and Figure 9 This is a schematic diagram of the structure corresponding to each step of the chip manufacturing process.

[0070] refer to Figure 8An initial chip 200 is provided, having a first initial surface 23 and a second initial surface 24 opposite to each other. The initial chip 200 includes an initial electrical connection region 201 and an initial support region 202. Both the first initial surface 23 and the second initial surface 24 of the initial chip 200 can be flat surfaces. It is understood that "flat" here means that the second surface 22 is planar and its surface roughness is within the process tolerance threshold. That is, the first initial surface 23 of the initial electrical connection region 201 can be flush with the first initial surface 23 of the initial support region 202, and the second initial surface 24 of the initial electrical connection region 201 can be flush with the second initial surface 24 of the initial support region 202.

[0071] refer to Figure 9 From the first initial surface 23 to the second initial surface 24 (reference) Figure 8 The initial support region 202 is thinned in the direction of (i.e. from bottom to top). The thinned initial chip 200 is used as chip 100. The thinned first initial surface 23, second initial surface 24, initial electrical connection region 201 and initial support region 202 are used as first surface 21, second surface 22, electrical connection region 101 and support region 102, respectively.

[0072] After the thinning process, the thickness of the support region 102 is greater than the thickness of the electrical connection region 101, and on the first surface 21, the electrical connection region 101 protrudes away from the second surface 22 relative to the support region 102. That is, the length of the support portion 130 connected to the first surface 21 of the support region 102 is greater than the length of the electrical connection portion 120 connected to the first surface 21 of the electrical connection region 101. Therefore, the embodiments provided in this disclosure can effectively reduce the length of the electrical connection portion 120 for transmitting signals, thereby reducing signal delay and mitigating crosstalk between different signals.

[0073] In some embodiments, the thinning process includes: forming a mask layer on the first initial surface 23 of the initial electrical connection region 201; etching the first initial surface 23 of the initial support region 202 using the mask layer as a mask; and removing the mask layer. The mask layer ensures that the first initial surface 23 of the electrical connection region 101 is not exposed to the etching environment, the initial electrical connection region 201 is not affected by etching, and the thickness of the initial electrical connection region 201 remains unchanged before and after etching.

[0074] The mask layer may include a photoresist layer. The steps for forming the photoresist layer may include: firstly, forming a photoresist layer over the entire surface of the first initial surface 23 of the initial electrical connection region 201 and the initial support region 202; then, exposing the photoresist using an exposure process; and finally, removing the photoresist layer on the first initial surface 23 of the initial support region 202 using a development process, while retaining the patterned photoresist layer on the first initial surface 23 of the initial electrical connection region 201. The patterned photoresist layer on the first initial surface 23 of the initial electrical connection region 201 can protect the first initial surface 23 of the initial electrical connection region 101 during subsequent wet etching processes.

[0075] In some embodiments, the mask layer may also include a hard mask layer. Since subsequent etching processes also affect the hard mask layer, the material for the hard mask layer must be selected to ensure that the etching rate of the hard mask layer is lower than the etching rate of the initial support region 202. This way, during wet etching, the hard mask layer on the first initial surface of the initial electrical connection region 201 and the first initial surface 23 of the initial support region 202 are simultaneously exposed to the etching environment, and the etching rate of the initial support region 202 is greater than the etching rate of the hard mask layer on the first initial surface 23 of the initial electrical connection region 201. In this way, the hard mask layer can provide better protection for the first initial surface 23 of the initial electrical connection region 101.

[0076] In other embodiments, the thinning process may further include: employing a local polishing process to polish away a portion of the thickness of the initial chip 200 in the initial support region 202. Specifically, local polishing may be performed using a polishing head with a special structure, or a mask may be first applied to the first initial surface 23 of the initial electrical connection region 201 before polishing.

[0077] In some embodiments, after the thinning process, an electrical connection portion 120 may be formed, with one end of the electrical connection portion 120 located on the first surface 21 of the electrical connection region 101. A support portion 130 may also be formed, with one end of the support portion 130 located on the first surface 21 of the support region 102. In the direction from the first surface 21 to the second surface 22, the length of the electrical connection portion 120 is less than the length of the support portion 130. This reduces the length of the electrical connection portion 120, reduces parasitic parameters introduced by the electrical connection portion 120, reduces signal delay, and mitigates crosstalk between different signals.

[0078] The chip fabrication method provided in this embodiment includes providing an initial chip 200, which has an initial electrical connection region 201 and an initial support region 202. One surface of the initial support region 202 is thinned. The thinned initial chip 200, initial electrical connection region 201, and initial support region 202 serve as chip 100, electrical connection region 101, and support region 102, respectively. This results in the electrical connection region 101 protruding relative to the support region 102 in a direction away from the other side of the chip 100's surface. Thus, the length of the electrical connection portion 120 used for signal transmission can be effectively reduced. Since the parasitic parameters, signal delay, and crosstalk between different signals introduced by the electrical connection portion 120 are positively correlated with the length of the electrical connection portion 120, reducing the length of the electrical connection portion 120 used for signal transmission can reduce the parasitic parameters introduced by the electrical connection portion 120, reduce signal delay, and alleviate crosstalk between different signals.

[0079] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this disclosure. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure should be determined by the scope defined in the claims.

Claims

1. A packaging structure, characterized in that, include: substrate; A chip having opposing first and second surfaces, wherein the first surface includes an electrical connection region and a support region; The first surface of the electrical connection area protrudes away from the second surface relative to the first surface of the support area, and the first surface of the chip faces the substrate. An electrical connection portion, one end of which is located on the first surface of the electrical connection area, and the other end of which is electrically connected to the substrate; The support portion has one end located on the first surface of the support area and the other end in contact with the surface of the substrate; in the direction from the first surface to the second surface, the length of the electrical connection portion is less than the length of the support portion.

2. The packaging structure as described in claim 1, characterized in that, The thickness between the first and second surfaces of the electrical connection area is the first thickness; the thickness between the first and second surfaces of the support area is the second thickness, and the difference between the first thickness and the second thickness is in the range of 5μm to 85μm.

3. The packaging structure as described in claim 2, characterized in that, The first thickness is 120μm ~ 200μm.

4. The packaging structure as described in claim 2, characterized in that, The second thickness is 125μm ~ 205μm.

5. The packaging structure according to any one of claims 1-4, characterized in that, The chip has two support regions, and the electrical connection region is located between the two support regions.

6. The packaging structure according to any one of claims 1-4, characterized in that, The support area surrounds the periphery of the electrical connection area.

7. The packaging structure according to any one of claims 1-4, characterized in that, The chip has two electrical connection regions, and the support region is located between the two electrical connection regions.

8. The packaging structure according to any one of claims 1-4, characterized in that, The second surface of the electrical connection area is flush with the second surface of the support area.

9. The packaging structure as described in claim 1, characterized in that, The first side is the front side of the chip; the second side is the back side of the chip.

10. The packaging structure as described in claim 1, characterized in that, The support area further includes a through hole, which connects the first surface and the second surface of the chip in a direction perpendicular to the first surface.

11. The packaging structure as described in claim 1, characterized in that, The length of the electrical connection portion is 30 μm to 60 μm in the direction from the first surface to the second surface.

12. The packaging structure as described in claim 1, characterized in that, The length of the support portion is 50 μm to 90 μm in the direction from the first surface to the second surface.

13. The packaging structure as described in claim 1, characterized in that, The electrical connection portion includes a first conductive post; the support portion includes a second conductive post; wherein, in the direction from the first surface to the second surface, the length of the first conductive post is less than the length of the second conductive post.

14. The packaging structure as described in claim 13, characterized in that, The electrical connection portion further includes: a first solder ball located away from the first surface of the first conductive post; the support portion further includes: a second solder ball located away from the first surface of the second conductive post.

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