Layout structure and design method for process miniaturization

Abstract

The present invention provides a layout structure for process miniaturization, including: an original layout, the original layout including a Fin layer and a mandrel layer; the Fin layer including a plurality of Fin graphics distributed in sequence, wherein the distance between some two Fin graphics is a first size, and the distance between another part of two Fin graphics is a second size; the mandrel layer including a plurality of mandrel graphics, corresponding to two Fin graphics with a distance of the first size, a mandrel graphic with a line width of a third size is arranged between the two Fin graphics, the distance between the mandrel graphics is a fourth size, the third size is greater than the first size, and the fourth size is greater than the second size. The present invention changes the cell layout to avoid the process challenge of small Mandrel and solve the demand for 98% process miniaturization; there is no pseudo gate in the cell, so FineCut can be omitted, and the problem of fin residue and the risk of fin damage can be solved at the same time; the process challenges are solved in the early Test Vehicle verification stage to avoid the difficulties encountered by customers in improving the yield during processing.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a process miniaturization layout structure and a design method thereof. Background Art

[0002] In the prior art, the Mandrel (sacrificial layer pattern after etching) drawing method used in random static memory cells is similar to the small Mandrel structure. However, due to the requirement of 98% miniaturization in the subsequent process, the Mandrel=36nm part will cause problems in process implementation and control. The original design of Mandrel has a regular width, which is more beneficial to both lithography and etching. However, when encountering limitations in lithography equipment, the spacing cannot be reduced.

[0003] See also Figure 1 , exemplary, Figure 1 The cell layout of the current 6T SRAM (6-transistor static random access memory) is shown, which includes a Fin layer, a mandrel layer, a contact hole layer pattern (301) for connecting the gate, connecting the source and drain metal layers, and connecting the metal wires, and a FinCut pattern for cutting the Fin structure. The Fin is defined by the side wall of the Mandrel. One Mandrel can define two Fins (fin-type structures). The original design is that two bitcells need to use 10 Mandrels (101 to 110) to define the Fin, but there are only 12 Fins (201 to 212) that are really useful, so the extra 8 need to be cut off. The part of Mandrel=36nm will cause problems that are difficult to implement and control in terms of process.

[0004] In order to solve the above problems, it is necessary to propose a new process miniaturization layout structure and its design method. Summary of the invention

[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a process miniaturized layout structure and a design method thereof, which are used to solve the problem in the prior art that the Mandrel width is designed to be regular, which is beneficial for both lithography and etching, but when the lithography equipment is limited, the spacing cannot be reduced.

[0006] To achieve the above-mentioned and other related purposes, the present invention provides a process miniaturization layout structure and a design method thereof, including:

[0007] An original layout, wherein the original layout includes a Fin layer and a mandrel layer;

[0008] The Fin layer includes a plurality of Fin graphics distributed in sequence, wherein the distance between two of the Fin graphics in some parts is a first size, and the distance between two of the Fin graphics in another part is a second size;

[0009] The mandrel layer includes a plurality of mandrel graphics, and a mandrel graphic with a line width of a third size is provided between two corresponding Fin graphics with a distance of the first size, and the distance between the mandrel graphics is a fourth size, the third size is larger than the first size, and the fourth size is larger than the second size; wherein,

[0010] The mandrel pattern is used to transfer to a sacrificial layer on a wafer to form a mandrel structure, and then a sidewall is formed on the sidewall of the mandrel structure. After that, the mandrel structure is removed and a Fin structure is formed by etching using the sidewall as a mask.

[0011] Preferably, the original layout also includes contact hole layer patterns for connecting the gate, connecting the source and drain metal layers, and connecting the metal wires.

[0012] Preferably, the original layout is a SRAM layout.

[0013] Preferably, the two Fin patterns whose distance is the first size are located in a bit line unit in the SRAM layout.

[0014] Preferably, the first dimension is less than or equal to 36 nanometers.

[0015] Preferably, the second size is larger than the first size.

[0016] A method for designing a layout structure for process miniaturization, comprising:

[0017] Step 1: obtaining design parameters of the original layout, wherein the original layout includes a Fin layer and a mandrel layer;

[0018] The Fin layer includes a plurality of Fin graphics distributed in sequence, wherein the distance between two of the Fin graphics in some parts is a first size, and the distance between two of the Fin graphics in another part is a second size;

[0019] Step 2: changing the design parameters of the mandrel graphic in the mandrel layer to obtain a modified layout, so that the line width of the mandrel graphic between the two Fin graphics whose distance is the first size is a third size, the distance between the mandrel graphics is a fourth size, the third size is larger than the first size, and the fourth size is larger than the second size; wherein,

[0020] The mandrel pattern is used to transfer to the sacrificial layer on the wafer to form a mandrel structure, and then a sidewall is formed on the sidewall of the mandrel structure. After that, the mandrel structure is removed and the sidewall is used as a mask for etching to form a Fin structure.

[0021] Step 3: Verify whether the process range and process window of the modified layout meet the target values. If so, publish the modified layout.

[0022] Preferably, the original layout also includes a contact hole layer pattern for connecting the gate, connecting the source and drain metal layers, and connecting the metal wires, and the contact hole layer pattern is retained in step two.

[0023] Preferably, the original layout is a SRAM layout.

[0024] Preferably, the two Fin patterns whose distance is the first size are located in a bit line unit in the SRAM layout.

[0025] Preferably, the original layout further includes a FinCut graphic for cutting the Fin structure, and step two deletes the FinCut graphic.

[0026] Preferably, the first dimension is less than or equal to 36 nanometers.

[0027] Preferably, the second size is larger than the first size.

[0028] As described above, the process miniaturization layout structure and design method of the present invention have the following beneficial effects:

[0029] The present invention changes the cell layout to avoid the process challenge of small Mandrel and meet the demand of 98% process miniaturization; there is no dummy gate in the cell, so FineCut can be omitted, and the fin residue problem and the risk of fin damage can be solved at the same time; the process challenges are solved in the early Test Vehicle verification stage to avoid the difficulties encountered by customers in improving the yield during processing. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 Shown is a schematic diagram of a random static memory cell layout of the prior art;

[0031] Figure 2A 1 to 2 are schematic diagrams of a cell layout, a Fin layer, a mandrel layer and a contact hole layer of an improved random static memory according to an embodiment of the present invention;

[0032] Figure 3A Figures 1 to 2 show schematic diagrams of the actual process of the layout of the present invention;

[0033] Figure 4 It is a schematic diagram showing a design method of a layout structure for process miniaturization of the present invention. DETAILED DESCRIPTION

[0034] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0035] See also Figure 2A The present invention provides a process miniaturized layout structure, comprising:

[0036] The original layout includes the Fin layer (such as Figure 2B As shown), mandrel layers (as shown Figure 2C As shown in Figure 1); that is, using the self-aligned double patterning (SADP) technology, after one lithography is completed, non-lithography process steps (thin film deposition, etching, etc.) are used successively to achieve spatial frequency doubling of the lithography pattern. Finally, another lithography and etching are used to remove the redundant pattern.

[0037] Therefore, the difficulty of the SADP process lies mainly in how to integrate processes such as lithography, etching and thin film deposition. It also poses new challenges to design engineers, as the designed layout must comply with certain rules: in other words, only designs that comply with certain rules are suitable for the SADP process.

[0038] The key process of SADP is as follows: Figure 3AAs shown in D: First, a layer of sacrificial material 503 (sacrifice layer) is deposited on the surface of the substrate, which is generally a CVD material. The surface of the sacrificial material 503 is formed with an anti-reflective coating 504 and a photoresist layer 506; then photolithography and etching are performed to transfer the pattern on the mask to the sacrificial material 503 layer. The pattern on the sacrificial material 503 is also called "mandrel507" or "core". A layer of thin film with relatively uniform thickness (called "spacer508" material) is deposited on the surface and side of "mandrel507" using atomic layer deposition (ALD) technology. The deposited "spacer508" material is etched away using a reactive ion etching process. This step is called "etchback". Due to the geometric effect of the sidewalls of "mandrel507", the material deposited on both sides of the pattern will remain, forming the so-called "spacer508". Use a highly selective etching solution to remove "mandrel507", leaving only "spacer508" on the substrate surface. The period of the "spacer508" pattern is half of that of the photolithography pattern, which doubles the density of the spatial pattern. Finally, plasma etching is used to transfer the "spacer508" pattern to the hard mask 502 in the substrate. Some literatures call this technology the sidewall imaging process (SIP).

[0039] The selection of "mandrel507", "spacer508" and hard mask materials is the key to the success of the process, and they must ensure good etching selectivity. For example, the "mandrel507" material can be polysilicon, the "spacer508" material can be SiO2, and the hard mask 502 on the substrate can be SiN or polysilicon. The pattern on the mask can be designed to have a duty cycle (line width: spacing) of 1:3; by accurately adjusting the process parameters of ALD and "etch back", the width of "spacer508" can be made the same as the line width of "mandrel507", and finally a 1:1 pattern is formed on the hard mask to double the spatial frequency.

[0040] In the embodiment of the present invention, please refer to Figure 2D The original layout also includes contact hole layer patterns for connecting the gate, connecting the source and drain metal layers, and connecting the metal wires.

[0041] In an embodiment of the present invention, the original layout is a SRAM layout.

[0042] The Fin layer includes a plurality of Fin graphics distributed in sequence, wherein the distance between two Fin graphics in some parts is a first size, and the distance between two Fin graphics in another part is a second size;

[0043] The mandrel layer includes a plurality of mandrel graphics, wherein a mandrel graphic with a line width of a third size is provided between two corresponding Fin graphics with a distance of a first size, and the distance between the mandrel graphics is a fourth size, the third size is greater than the first size, and the fourth size is greater than the second size; wherein,

[0044] The mandrel pattern is used to transfer to the sacrificial layer on the wafer to form a mandrel structure, and then form a sidewall on the sidewall of the mandrel structure. After that, the mandrel structure is removed and the Fin structure is formed by etching using the sidewall as a mask, which slightly increases the difficulty of etching but allows a larger process margin for the photolithography process.

[0045] In an embodiment of the present invention, two Fin patterns with a first distance between them are located in a bit line unit in an SRAM layout.

[0046] In an embodiment of the present invention, the first dimension is less than or equal to 36 nanometers.

[0047] In an embodiment of the present invention, the second size is greater than the first size.

[0048] For example, Figure 1 The cell layout of the current 6T SRAM (6-transistor static random access memory) is shown, which includes a Fin layer, a mandrel layer, a contact hole layer pattern (301) for connecting the gate, connecting the source and drain metal layers, and connecting the metal wires, and a FinCut pattern for cutting the Fin structure. The Fin is defined by the sidewall of the Mandrel. One Mandrel can define two Fins (fin-type structures). The original design is that two bitcells need to use 10 Mandrels (101 to 110) to define the Fin, but there are only 12 Fins (201 to 212) that are really useful, so the extra 8 need to be cut off. The widths of some Mandrel patterns are 36 nanometers and 46 nanometers respectively. The part with a Mandrel width of 36nm will cause problems that are difficult to implement and control in terms of process.

[0049] Exemplarily, FIG. 2 shows a cell layout of an improved 6T SRAM (6-transistor static random access memory) according to an embodiment of the present invention, which includes a Fin layer, a mandrel layer, and a contact hole layer pattern (301) for connecting a gate, connecting a source and drain metal layer, and connecting a metal wire. The distance between some Fins is 36 nanometers, and the distance between some Fins is 92 nanometers, 82 nanometers, and 102 nanometers, respectively. The new design has only 6 Mandrel patterns (401 to 406). The smaller width of the 6 Mandrel patterns is selected to be appropriately enlarged, for example, the original width of 36 nanometers is adjusted to 38 nanometers, and the distance between the Mandrel patterns is increased, for example, the original 92 nanometer part is adjusted to 101 nanometers, the 82 nanometer part is adjusted to 101 nanometers, and the 102 nanometer part is adjusted to 120 nanometers. Therefore, there is no need to perform Fine Cut, and only the Mandrel layer and the FineCut layer are changed. By adjusting the effective Fin, sufficient process range and process window are ensured, so that the difficulty of etching is slightly increased, but a larger process margin can be given to the photolithography process.

[0050] The present invention also provides a design method corresponding to a layout structure supporting miniaturization, comprising:

[0051] Step 1: Get the design parameters of the original layout, which includes the Fin layer (such as Figure 2B As shown), mandrel layers (as shown Figure 2C As shown in Figure 1); that is, using the self-aligned double patterning (SADP) technology, after one lithography is completed, non-lithography process steps (thin film deposition, etching, etc.) are used successively to achieve spatial frequency doubling of the lithography pattern. Finally, another lithography and etching are used to remove the redundant pattern.

[0052] Therefore, the difficulty of the SADP process lies mainly in how to integrate processes such as lithography, etching and thin film deposition. It also poses new challenges to design engineers, as the designed layout must comply with certain rules: in other words, only designs that comply with certain rules are suitable for the SADP process.

[0053] The key process of SADP is as follows: Figure 3AAs shown in D: First, a layer of sacrificial material 503 (sacrifice layer) is deposited on the surface of the substrate, which is generally a CVD material. The surface of the sacrificial material 503 is formed with an anti-reflective coating 504 and a photoresist layer 506; then photolithography and etching are performed to transfer the pattern on the mask to the sacrificial material 503 layer. The pattern on the sacrificial material 503 is also called "mandrel507" or "core". A layer of thin film with relatively uniform thickness (called "spacer508" material) is deposited on the surface and side of "mandrel507" using atomic layer deposition (ALD) technology. The deposited "spacer508" material is etched away using a reactive ion etching process. This step is called "etchback". Due to the geometric effect of the sidewalls of "mandrel507", the material deposited on both sides of the pattern will remain, forming the so-called "spacer508". Use a highly selective etching solution to remove "mandrel507", leaving only "spacer508" on the substrate surface. The period of the "spacer508" pattern is half of that of the photolithography pattern, which doubles the density of the spatial pattern. Finally, plasma etching is used to transfer the "spacer508" pattern to the hard mask 502 in the substrate. Some literatures call this technology the sidewall imaging process (SIP).

[0054] The selection of "mandrel507", "spacer508" and hard mask materials is the key to the success of the process, and they must ensure good etching selectivity. For example, the "mandrel507" material can be polysilicon, the "spacer508" material can be SiO2, and the hard mask 502 on the substrate can be SiN or polysilicon. The pattern on the mask can be designed to have a duty cycle (line width: spacing) of 1:3; by accurately adjusting the process parameters of ALD and "etch back", the width of "spacer508" can be made the same as the line width of "mandrel507", and finally a 1:1 pattern is formed on the hard mask to double the spatial frequency.

[0055] The Fin layer includes a plurality of Fin graphics distributed in sequence, wherein the distance between two Fin graphics in some parts is a first size, and the distance between two Fin graphics in another part is a second size;

[0056] In an embodiment of the present invention, the original layout also includes a contact hole layer pattern for connecting the gate, connecting the source and drain metal layers, and connecting the metal wires, and the contact hole layer pattern is retained in step two.

[0057] In an embodiment of the present invention, the original layout is a SRAM layout.

[0058] Step 2: Change the design parameters of the mandrel graphics in the mandrel layer to obtain a modified layout, so that the line width of the mandrel graphics between the two Fin graphics with a distance of the first size is the third size, the distance between the mandrel graphics is the fourth size, the third size is larger than the first size, and the fourth size is larger than the second size; wherein,

[0059] The mandrel pattern is used to transfer to the sacrificial layer on the wafer to form a mandrel structure, and then form a sidewall on the sidewall of the mandrel structure. After that, the mandrel structure is removed and the Fin structure is formed by etching using the sidewall as a mask, which slightly increases the difficulty of etching but allows a larger process margin for the photolithography process.

[0060] In an embodiment of the present invention, two Fin patterns with a first distance between them are located in a bit line unit in an SRAM layout.

[0061] In an embodiment of the present invention, the original layout also includes a FinCut graphic for cutting the Fin structure. Step 2 deletes the FinCut graphic to form Figure 2D The structure shown.

[0062] In an embodiment of the present invention, the first dimension is less than or equal to 36 nanometers.

[0063] In an embodiment of the present invention, the second size is greater than the first size.

[0064] Step 3: Verify whether the process range and process window of the modified layout meet the target values. If so, publish the modified layout. Specifically, the corrected Fin layer and mandrel layer can be transferred to the photoresist through two masks respectively, and then the developed photoresist layer is measured.

[0065] For example, Figure 1The cell layout of the current 6T SRAM (6-transistor static random access memory) is shown, which includes a Fin layer, a mandrel layer, a contact hole layer pattern (301) for connecting the gate, connecting the source and drain metal layers, and connecting the metal wires, and a FinCut pattern for cutting the Fin structure. The Fin is defined by the sidewall of the Mandrel. One Mandrel can define two Fins (fin-type structures). The original design is that two bitcells need to use 10 Mandrels (101 to 110) to define the Fin, but there are only 12 Fins (201 to 212) that are really useful, so the extra 8 need to be cut off. The widths of some Mandrel patterns are 36 nanometers and 46 nanometers respectively. The part with a Mandrel width of 36nm will cause problems that are difficult to implement and control in terms of process.

[0066] Exemplarily, FIG. 2 shows a cell layout of an improved 6T SRAM (6-transistor static random access memory) according to an embodiment of the present invention, which includes a Fin layer, a mandrel layer, and a contact hole layer pattern (301) for connecting a gate, connecting a source and drain metal layer, and connecting a metal wire. The distance between some Fins is 36 nanometers, and the distance between some Fins is 92 nanometers, 82 nanometers, and 102 nanometers, respectively. The new design has only 6 Mandrel patterns (401 to 406). The smaller width of the 6 Mandrel patterns is selected to be appropriately enlarged, for example, the original width of 36 nanometers is adjusted to 38 nanometers, and the distance between the Mandrel patterns is increased, for example, the original 92 nanometer portion is adjusted to 101 nanometers, the 82 nanometer portion is adjusted to 101 nanometers, and the 102 nanometer portion is adjusted to 120 nanometers. Therefore, there is no need to perform Fine Cut, and only the Mandrel layer and the FineCut layer are changed. By adjusting the effective Fins, sufficient process range and process window are ensured, so that the difficulty of etching is slightly increased, but a larger process margin can be given to the photolithography process.

[0067] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0068] In summary, the present invention changes the cell layout to avoid the process challenge of small Mandrel and solve the requirement of 98% process miniaturization; there is no pseudo gate in the cell, so FineCut can be omitted, and the fin residue problem and the risk of fin damage can be solved at the same time; the process challenges are solved in the early Test Vehicle verification stage to avoid the difficulties encountered by customers in improving the yield during processing. Therefore, the present invention effectively overcomes various shortcomings in the existing technology and has high industrial utilization value.

[0069] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A layout structure with miniaturized process, characterized in that: include: An original layout, wherein the original layout includes a Fin layer and a mandrel layer; The Fin layer includes a plurality of Fin graphics distributed in sequence, wherein the distance between two of the Fin graphics in some parts is a first size, and the distance between two of the Fin graphics in another part is a second size, and the second size is greater than the first size; The mandrel layer includes a plurality of mandrel graphics, and a mandrel graphic with a line width of a third size is provided between two corresponding Fin graphics with a distance of the first size, and the distance between the mandrel graphics is a fourth size, the third size is larger than the first size, and the fourth size is larger than the second size; wherein, The mandrel pattern is used to transfer to a sacrificial layer on a wafer to form a mandrel structure, and then a sidewall is formed on the sidewall of the mandrel structure. After that, the mandrel structure is removed and a Fin structure is formed by etching using the sidewall as a mask.

2. The process miniaturized layout structure according to claim 1, characterized in that: The original layout also includes contact hole layer patterns for connecting the gate, connecting the source and drain metal layers, and connecting the metal wires.

3. The process miniaturized layout structure according to claim 1, characterized in that: The original layout is a SRAM layout.

4. The process miniaturized layout structure according to claim 3, characterized in that: The two Fin patterns whose distance is the first size are located in the bit line unit in the SRAM layout.

5. The process miniaturized layout structure according to claim 1, characterized in that: The first dimension is less than or equal to 36 nanometers.

6. The method for designing a layout structure for process miniaturization according to any one of claims 1 to 5, characterized in that: At least: Step 1: obtaining design parameters of the original layout, wherein the original layout includes a Fin layer and a mandrel layer; The Fin layer includes a plurality of Fin graphics distributed in sequence, wherein the distance between two of the Fin graphics in some parts is a first size, and the distance between two of the Fin graphics in another part is a second size, and the second size is greater than the first size; Step 2: changing the design parameters of the mandrel graphic in the mandrel layer to obtain a modified layout, so that the line width of the mandrel graphic between the two Fin graphics whose distance is the first size is a third size, the distance between the mandrel graphics is a fourth size, the third size is larger than the first size, and the fourth size is larger than the second size; wherein, The mandrel pattern is used to transfer to the sacrificial layer on the wafer to form a mandrel structure, and then a sidewall is formed on the sidewall of the mandrel structure. After that, the mandrel structure is removed and the sidewall is used as a mask for etching to form a Fin structure. Step 3: Verify whether the process range and process window of the modified layout meet the target values. If so, publish the modified layout.

7. The method for designing a layout structure for process miniaturization according to claim 6, characterized in that: The original layout also includes contact hole layer patterns for connecting the gate, connecting the source and drain metal layers, and connecting the metal wires. The contact hole layer patterns are retained in step two.

8. The method for designing a layout structure for process miniaturization according to claim 7, characterized in that: The original layout is a SRAM layout.

9. The method for designing a layout structure for process miniaturization according to claim 8, characterized in that: The two Fin patterns whose distance is the first size are located in the bit line unit in the SRAM layout.

10. The method for designing a layout structure for process miniaturization according to claim 6, characterized in that: The original layout also includes a FinCut graphic for cutting the Fin structure, and step 2 deletes the FinCut graphic.

11. The method for designing a layout structure for process miniaturization according to claim 6, characterized in that: The first dimension is less than or equal to 36 nanometers.

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