Display panel

Abstract

This application discloses a display panel. The thin-film transistor includes: a first gate, comprising a first bevel, a second bevel, and a top surface disposed opposite to each other; a first gate insulating layer covering a substrate, the first bevel, the second bevel, and the top surface; and a semiconductor layer disposed on the first gate insulating layer, the semiconductor layer including a first end, a second end, and a channel located between the first end and the second end, the second end being at least partially located on the top surface, and the channel being at least partially located on the first bevel. This application utilizes the semiconductor layer being at least disposed on the first bevel of the first gate. The shorter length of the first bevel results in a shorter channel length for the semiconductor layer. Seed crystals are more easily formed at the corner of the first bevel near the substrate, providing conditions for the channel on the first bevel to consist of a single grain. The shorter channel length and inclusion of a single grain in the thin-film transistor improves its mobility.

Description

Technical Field

[0001] This application relates to the field of displays, specifically to a display panel. Background Technology

[0002] Integrating integrated circuits onto a substrate (such as a glass or flexible substrate) (System on Glass, SOG) can significantly improve the integration level of display panels and reduce their manufacturing costs. However, achieving this requires improving the mobility of traditional thin-film transistors (TFTs) and also necessitates smaller TFT sizes.

[0003] However, current thin-film transistors suffer from insufficient mobility and excessively large size. Summary of the Invention

[0004] This application provides a display panel to address the problems of insufficient mobility and excessive size of current thin-film transistors.

[0005] This application provides a display panel, including a substrate and thin-film transistors disposed on the substrate, the thin-film transistors including:

[0006] A first gate is disposed on the substrate. The first gate includes a first side slope and a second side slope disposed opposite to each other, and a top surface sandwiched between the first side slope and the second side slope.

[0007] A first gate insulating layer covers the substrate, the first side slope, the second side slope, and the top surface;

[0008] A semiconductor layer is disposed on the first gate insulating layer. The semiconductor layer includes a first end, a second end, and a channel located between the first end and the second end. The second end is at least partially located on the top surface, and the channel is at least partially located on the first side slope.

[0009] Optionally, in some embodiments of this application, the orthographic projection of the channel on the substrate overlaps with the orthographic projection of the first side slope on the substrate.

[0010] Optionally, in some embodiments of this application, the slope angle between the first side slope and the base is greater than or equal to 45 degrees and less than or equal to 90 degrees.

[0011] Optionally, in some embodiments of this application, the thickness of the first gate insulating layer at the substrate is greater than the thickness of the first gate insulating layer at the first side slope.

[0012] Optionally, in some embodiments of this application, the thickness of the first gate insulating layer at the substrate is 1.2 to 2 times the thickness of the first gate insulating layer at the first side slope.

[0013] Optionally, in some embodiments of this application, the thickness of the first gate is 0.1 micrometers to 1 micrometer.

[0014] Optionally, in some embodiments of this application, the length of the first side slope is less than or equal to 0.3 micrometers.

[0015] Optionally, in some embodiments of this application, the channel is at least a portion of a single grain.

[0016] Optionally, in some embodiments of this application, the length of the channel ranges from 0.1 micrometers to 1 micrometer.

[0017] Optionally, in some embodiments of this application, the first gate insulating layer forms a corner portion corresponding to the end of the first side slope near the substrate, and the channel covers the corner portion.

[0018] Optionally, in some embodiments of this application, the thin-film transistor further includes:

[0019] A first insulating layer is disposed on the semiconductor layer;

[0020] The first through hole penetrates the first insulating layer;

[0021] The second through hole penetrates the first insulating layer;

[0022] A source and a drain are disposed on the first insulating layer. One of the source and the drain is electrically connected to the first end through the first through hole, and the other is electrically connected to the second end through the second through hole.

[0023] Optionally, in some embodiments of this application, the thin-film transistor further includes:

[0024] A light-shielding layer is disposed between the substrate and the gate, wherein the orthogonal projection of the light-shielding layer on the substrate covers the orthogonal projection of the channel on the substrate;

[0025] A passivation layer is disposed between the light-shielding layer and the gate.

[0026] Optionally, in some embodiments of this application, the thin-film transistor further includes an extension extending from the first side slope toward the side close to the semiconductor layer, the thickness of the extension being less than the thickness of the first gate, and the orthographic projection of the extension on the substrate at least partially overlapping the orthographic projection of the channel on the substrate.

[0027] Optionally, in some embodiments of this application, the thin-film transistor further includes:

[0028] A second gate insulating layer is disposed between the semiconductor layer and the first insulating layer;

[0029] The second gate is disposed between the second gate insulating layer and the first insulating layer, and the second gate is disposed corresponding to the channel.

[0030] Optionally, in some embodiments of this application, the second gate insulating layer forms a third side slope corresponding to the first side slope, and the second gate is located on the third side slope.

[0031] Optionally, in some embodiments of this application, the thin-film transistor further includes:

[0032] The third via penetrates the first gate insulating layer and the second gate insulating layer, and the second gate is connected to the first gate through the third via.

[0033] This application provides a display panel, which includes a substrate and thin-film transistors disposed on the substrate. The thin-film transistors include: a first gate disposed on the substrate, the first gate including a first side slope and a second side slope disposed opposite to each other, and a top surface sandwiched between the first side slope and the second side slope; a first gate insulating layer covering the substrate, the first side slope, the second side slope and the top surface; and a semiconductor layer disposed on the first gate insulating layer, the semiconductor layer including a first end, a second end and a channel located between the first end and the second end, the second end being at least partially located on the top surface and the channel being at least partially located on the first side slope. This application utilizes a semiconductor layer at least disposed on the first bevel of the first gate. The gate thickness is small, and the length of the first bevel is short, resulting in a shorter channel length for the semiconductor layer. Furthermore, during the crystallization process to form the semiconductor layer, seed crystals are more easily formed at the corner of the first bevel near the substrate. When the seed crystal grows along the first bevel to form a single grain, the short channel length on the first bevel provides the conditions for the channel to consist of single grains. Since there are no grain boundaries in the single grains, the channel length of the thin-film transistor (TFT) is short and includes single grains, improving the TFT's mobility. Simultaneously, the semiconductor layer being at least disposed on the first bevel of the gate, and the short channel length of the semiconductor layer, reduces the TFT's layout space, thus reducing the TFT's size. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 This is a schematic diagram of a conventional thin-film transistor in the prior art;

[0036] Figure 2 A top view schematic diagram of a first type of thin-film transistor for a display panel provided in an embodiment of this application;

[0037] Figure 3 This application provides a first cross-sectional schematic diagram of a first type of thin-film transistor for a display panel.

[0038] Figure 4 A second cross-sectional schematic diagram of a first type of thin-film transistor for a display panel provided in an embodiment of this application;

[0039] Figure 5 A third cross-sectional schematic diagram of a first type of thin-film transistor for a display panel provided in an embodiment of this application;

[0040] Figure 6 A top view schematic diagram of a second type of thin-film transistor for a display panel provided in an embodiment of this application;

[0041] Figure 7 A first cross-sectional schematic diagram of a second type of thin-film transistor for a display panel provided in an embodiment of this application;

[0042] Figure 8 This application provides a second cross-sectional schematic diagram of a second type of thin-film transistor for a display panel.

[0043] Figure 9 A top view schematic diagram of a third type of thin-film transistor for a display panel provided in an embodiment of this application;

[0044] Figure 10 This is a first cross-sectional schematic diagram of a third type of thin-film transistor for a display panel provided in an embodiment of this application;

[0045] Figure 11 A first cross-sectional schematic diagram of a fourth type of thin-film transistor for a display panel provided in an embodiment of this application;

[0046] Figure 12 A schematic diagram of the first intermediate process of a method for manufacturing a first / second type of thin-film transistor for a display panel provided in an embodiment of this application;

[0047] Figure 13 A schematic diagram of the second intermediate process of a method for manufacturing a first / second type of thin-film transistor for a display panel provided in an embodiment of this application;

[0048] Figure 14 A schematic diagram of the third intermediate process of a method for manufacturing a first / second type of thin-film transistor for a display panel provided in an embodiment of this application;

[0049] Figure 15 A schematic diagram of the fourth intermediate process of a method for manufacturing a first / second type of thin-film transistor for a display panel provided in an embodiment of this application;

[0050] Figure 16 A schematic diagram of the fifth intermediate process of a first thin-film transistor manufacturing method for a display panel provided in an embodiment of this application;

[0051] Figure 17 A schematic diagram of the fifth intermediate process of a method for manufacturing two thin-film transistors for a display panel provided in an embodiment of this application;

[0052] Figure 18 A schematic diagram of the sixth intermediate process of a method for manufacturing two thin-film transistors for a display panel provided in an embodiment of this application;

[0053] Figure 19 A schematic diagram of the seventh intermediate process of a method for manufacturing two thin-film transistors of a display panel provided in an embodiment of this application;

[0054] Figure 20 A schematic diagram of a first intermediate process in a method for manufacturing the first gate 14 of a thin-film transistor in a display panel, as provided in an embodiment of this application;

[0055] Figure 21 A schematic diagram of a second intermediate process for manufacturing a first gate 14 of a thin-film transistor in a display panel, provided in an embodiment of this application;

[0056] Figure 22 This is a schematic diagram of a display terminal 200 provided in an embodiment of this application. Detailed Implementation

[0057] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In addition, it should be understood that the specific embodiments described herein are only for illustration and explanation of this application and are not intended to limit this application. In this application, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, specifically the drawing directions in the accompanying drawings; while "inner" and "outer" refer to the outline of the device.

[0058] Please see Figure 1 , Figure 1 This is a schematic diagram of a conventional thin-film transistor (TFT) in the prior art. A conventional TFT includes a gate 14 disposed on a substrate 11, a gate insulating layer 15 disposed on the gate 14, a semiconductor layer 16 disposed on the gate insulating layer 15, a first insulating layer 17 disposed on the semiconductor layer 16, and a source 181 and a drain 182 disposed on the first insulating layer 17 and electrically connected to the semiconductor layer 16. The semiconductor layer 16 is located on a plane. Due to limitations in exposure and etching precision in display panel manufacturing processes, the length L1 of the channel 163 in the semiconductor layer 16 is often greater than 2 micrometers. Channels 163 longer than 2 micrometers have more grain boundaries, resulting in lower TFT mobility. The semiconductor layer 16 being located on a plane and having a large channel length results in a larger layout space for the TFT, leading to a larger TFT size.

[0059] This application provides a display panel, which includes a substrate and thin-film transistors disposed on the substrate. The thin-film transistors include: a first gate disposed on the substrate, the first gate including a first side slope and a second side slope disposed opposite to each other, and a top surface sandwiched between the first side slope and the second side slope; a first gate insulating layer covering the substrate, the first side slope, the second side slope and the top surface; and a semiconductor layer disposed on the first gate insulating layer, the semiconductor layer including a first end, a second end and a channel located between the first end and the second end, the second end being at least partially located on the top surface and the channel being at least partially located on the first side slope.

[0060] This application also provides a display terminal including the aforementioned display panel. These will be described in detail below. It should be noted that the order of description of the following embodiments is not intended to limit the preferred order of the embodiments.

[0061] Example 1

[0062] Please see Figure 2and Figure 3 ; Figure 2 A top view schematic diagram of a first type of thin-film transistor for a display panel provided in an embodiment of this application; Figure 3 This is a first cross-sectional schematic diagram of a first type of thin-film transistor for a display panel provided in an embodiment of this application. Figure 2 To clearly present the important structure of thin-film transistors, Figure 2 The diagram only shows a portion of the film layers or structure of a thin-film transistor. Figure 3 for Figure 2 A cross-sectional diagram of the section marked by the dashed line AA.

[0063] This application provides a display panel 100, which includes a substrate 11 and a thin-film transistor 101 disposed on the substrate 11. The thin-film transistor 101 includes a first gate 14, a first gate insulating layer 15, and a semiconductor layer 16. The first gate 14 is disposed on the substrate 11 and includes a first side slope 141 and a second side slope 142 disposed opposite to each other, and a top surface 143 sandwiched between the first side slope 141 and the second side slope 142. The first gate insulating layer 15 covers the substrate 11, the first side slope 141, the second side slope 142, and the top surface 143. The semiconductor layer 16 is disposed on the first gate insulating layer 15 and includes a first end 161, a second end 162, and a channel 163 located between the first end 161 and the second end 162. The second end 162 is at least partially located on the top surface 143, and the channel 163 is at least partially located on the first side slope 141.

[0064] Specifically, the substrate 11 can be a glass or flexible substrate, which is not limited here.

[0065] Specifically, a first gate 14 is disposed on a substrate 11. The first gate 14 includes a first side slope 141 and a second side slope 142 disposed opposite to each other, and a top surface 143 sandwiched between the first side slope 141 and the second side slope 142. The cross-sectional shape of the first gate 14 can be trapezoidal, but is not limited thereto. The top surface 143 is the surface of the first gate 14 away from the substrate 11. The top surface 143 connects between the first side slope 141 and the second side slope 142. In the cross-sectional schematic diagram, the surface of the first side slope 141 and the surface of the second side slope 142 can be straight, or it can be arc-shaped or multi-segmented, and is not limited here.

[0066] Specifically, the first gate insulating layer 15 covers the substrate 11, the first side slope 141, the second side slope 142, and the top surface 143. That is, the first gate insulating layer 15 is disposed on the first gate 14, and the parts of the substrate 11 without the first gate 14 are also covered by the first gate insulating layer 15.

[0067] Specifically, a semiconductor layer 16 is disposed on a first gate insulating layer 15. The semiconductor layer 16 includes a first end 161, a second end 162, and a channel 163 located between the first end 161 and the second end 162. The second end 162 is at least partially located on a top surface 143, and the channel 163 is at least partially located on a first side slope 141. The semiconductor layer 16 is disposed on the gate insulating layer 15, and the channel 163 is at least partially located on the first side slope 141. The orthographic projection of the channel 163 on the substrate 11 at least partially overlaps with the orthographic projection of the first side slope 141 on the substrate 11. The first end 161 and the second end 162 connect the channel 163 on both sides.

[0068] Specifically, the orthographic projection of the first end 161 on the substrate 11 does not overlap with the orthographic projection of the first gate 14 on the substrate 11 at least partially, and the orthographic projection of the second end 162 on the substrate 11 overlaps with the orthographic projection of the top surface 143 of the first gate 14 on the substrate 11 at least partially.

[0069] Specifically, the first gate insulating layer 15 covers the first gate 14, the second end 162 is at least partially located on the top surface 143, and the channel 163 is at least partially located on the first side slope 141. This means that the second end 162 is located on the first gate insulating layer 15 and at least partially corresponds to or overlaps with the top surface 143; and that the channel 163 is located on the first gate insulating layer 15 and at least partially corresponds to or overlaps with the first side slope 141.

[0070] Specifically, the channel 163 is at least partially located on the first side slope 141, meaning that the entire channel 163 of the semiconductor layer 16 is located on the first side slope 141; or, a portion of the channel 163 of the semiconductor layer 16 is located on the first side slope 141, and another portion of the channel 163 of the semiconductor layer 16 is located on the first gate insulating layer 15 on the substrate; or, a portion of the channel 163 of the semiconductor layer 16 is located on the first side slope 141, and another portion of the channel 163 of the semiconductor layer 16 is located on the top surface 143 of the first gate 14; or, a portion of the channel 163 of the semiconductor layer 16 is located on the first side slope 141, and another portion of the channel 163 of the semiconductor layer 16 is located on the first gate insulating layer 15 and the top surface 143 of the first gate 14 on the substrate.

[0071] It should be noted that when the channel 163 is designed to be located on the first side slope 141, due to process deviation issues, the channel 163 may not be completely on the first side slope 141.

[0072] Specifically, the first gate 14 can be at least one of a protruding truncated pyramid structure, a protruding cubic structure, or a protruding cuboid structure, but the structure of the first gate 14 is not limited to these.

[0073] Specifically, the material of the first gate 14 can be any material in the prior art, such as one or more of copper, aluminum, titanium, etc., which will not be elaborated here.

[0074] Specifically, the first end 161 includes a first heavily doped portion 1611 and a first lightly doped portion 1612, with the first lightly doped portion 1612 connected between the heavily doped portion 1611 and the channel 163. The second end 162 includes a second heavily doped portion 1621 and a second lightly doped portion 1622, with the second lightly doped portion 1622 connected between the heavily doped portion 1621 and the channel 163. The dopant ions in the first heavily doped portion 1611, the first lightly doped portion 1612, the second heavily doped portion 1621, and the second lightly doped portion 1622 are the same as those in the prior art, and will not be described again here.

[0075] In this embodiment, the semiconductor layer 16 is at least disposed on the first side slope 141 of the gate 14. The gate 14 has a small thickness, and the first side slope 141 has a small length, resulting in a small channel 163 length for the semiconductor layer 16. Furthermore, during the crystallization process to form the semiconductor layer 16, seed crystals are more easily formed at the corner 31 of the first side slope 141 near the substrate 11. When the seed crystal grows along the first side slope 141 to form a single grain, the small length of the channel 163 on the first side slope 141 provides the conditions for the channel 163 on the first side slope 141 to consist of single grains. Since there are no grain boundaries in the single grains, the short channel 163 of the thin-film transistor 101, including single grains, improves the mobility of the thin-film transistor 101. Simultaneously, the semiconductor layer 16 is at least disposed on the first side slope 141 of the gate 14, and the short channel 163 length of the semiconductor layer 16 reduces the layout space of the thin-film transistor 101, thus reducing the size of the thin-film transistor 101.

[0076] Example 2

[0077] This embodiment is the same as or similar to Embodiment 1, except that the features of the display panel 100 are further described.

[0078] Please see Figure 2 , Figure 3 , Figure 4 and Figure 5 ; Figure 4 A second cross-sectional schematic diagram of a first type of thin-film transistor for a display panel provided in an embodiment of this application; Figure 5 This is a third cross-sectional schematic diagram of a first type of thin-film transistor for a display panel provided in an embodiment of this application. Figure 5 for Figure 2 A cross-sectional diagram of the section marked by the dashed line BB. Figure 4 and Figure 3same, Figure 4 The label shows some dimensional information of the thin-film transistor 101.

[0079] In some embodiments, the orthographic projection of the channel 163 on the substrate 11 overlaps with the orthographic projection of the first side slope 141 on the substrate 11.

[0080] Specifically, the orthographic projection of the channel 163 on the substrate 11 overlaps with the orthographic projection of the first side slope 141 on the substrate 11, that is, the channel 163 is only located on the first side slope 141. At this time, the channel 163 can occupy a smaller layout space, which helps to reduce the size of the thin film transistor.

[0081] In some embodiments, the slope angle α between the first side slope 141 and the base 11 is greater than or equal to 45 degrees and less than or equal to 90 degrees.

[0082] Specifically, the slope angle α between the first side slope 141 and the substrate 11 is greater than or equal to 45 degrees and less than or equal to 90 degrees. The slope angle α refers to the angle between the plane containing the first side slope 141 and the substrate 11 at the corner 31, or the slope angle α refers to the angle between the first side slope 141 and the bottom surface 144 at the corner 31. The first gate 14 includes a bottom surface 144, which refers to the surface of the first gate 14 near the substrate 11, or the surface opposite to the top surface 143.

[0083] Specifically, the slope angle α between the first inclined surface 141 and the base 11 can be 45 degrees, 50 degrees, 55 degrees, 60 degrees, 65 degrees, 70 degrees, 75 degrees, 80 degrees, 85 degrees or 90 degrees.

[0084] Specifically, the slope angle α between the first side slope 141 and the base 11 is greater than or equal to 45 degrees and less than or equal to 90 degrees, which is conducive to the easier formation of seed crystals at the corner 31. The seed crystals grow along the first side slope 141, making it easier for the channel 163 to be composed of single grains.

[0085] In some embodiments, the thickness h1 of the first gate insulating layer 15 at the substrate 11 is greater than the thickness h3 of the first gate insulating layer 15 at the first side slope 141.

[0086] Specifically, the thickness h3 of the first gate insulating layer 15 at the first side slope 141 refers to the thickness of the first gate insulating layer 15 in the direction perpendicular to the first side slope 141.

[0087] Specifically, the thickness h1 of the first gate insulating layer 15 at the substrate 11 is greater than the thickness h3 of the first gate insulating layer 15 at the first side slope 141. This can be achieved by controlling the film deposition process parameters of the first gate insulating layer 15, thereby changing the step coverage of the first gate insulating layer 15 so that the thickness h1 of the first gate insulating layer 15 on the first side slope 141 is thinner, and the thickness h1 of the first gate insulating layer 15 at the substrate 11 and / or the thickness h2 of the first gate insulating layer 15 on the top surface 143 is thicker. For example, the thickness of the first gate insulating layer 15 at the substrate 11... h1 is 1800 angstroms, and the thickness h3 of the first gate insulating layer 15 at the first side slope 141 is 900 angstroms, thereby enhancing the control capability of the first gate 14 over the channel 163. At the same time, the thickness h1 of the first gate insulating layer 15 at the substrate 11 and / or the thickness h3 of the first gate insulating layer 15 on the top surface 143 is relatively thick, which reduces the coupling (capacitive coupling) between the source 181 and / or the drain 182 and the first gate 14, avoids the potential interference between the source 181 and / or the drain 182 and the first gate 14, and improves the performance of the thin film transistor 101.

[0088] In some embodiments, the thickness h1 of the first gate insulating layer 15 at the substrate 11 is 1.2 to 2 times the thickness h3 of the first gate insulating layer 15 at the first side slope 141.

[0089] Specifically, the thickness h1 of the first gate insulating layer 15 at the substrate 11 is 1.2 to 2 times the thickness h3 of the first gate insulating layer 15 at the first side slope 141. The thickness h1 of the first gate insulating layer 15 at the substrate 11 can be 1.2, 1.3, 1.4, 1.5, 1.6, 1.7, 1.8, 1.9, 2.0, 2.1, or 2.2 times the thickness h3 of the first gate insulating layer 15 at the first side slope 141, thereby enhancing the control capability of the first gate 14 over the channel 163, reducing the coupling (capacitive coupling) between the source 181 or / and the drain 182 and the first gate 14, avoiding mutual interference between the potentials of the source 181 or / and the drain 182 and the first gate 14, and improving the performance of the thin film transistor 101.

[0090] In some embodiments, the thickness of the first gate 14 is 0.1 micrometers to 1 micrometer.

[0091] Specifically, the thickness of the first gate 14 is from 0.1 micrometers to 1 micrometer. The thickness of the first gate 14 can be 0.1 micrometers, 0.3 micrometers, 0.5 micrometers, 0.7 micrometers, 0.9 micrometers, or 1 micrometer. The smaller thickness of the first gate 14 results in a shorter length of the first bevel 141 and a shorter length of the channel 163 on the first bevel 141. The length of the channel 163 on the first bevel 141 is less than the length of channels in conventional technology (the length of channels in conventional technology is 2 micrometers or more). Furthermore, during crystallization to form the semiconductor layer 16, seed crystals are more easily formed at the corner portion 31 of the semiconductor layer 16 before crystallization. When the seed crystal grows along the first bevel 141 to form a single grain, the length of the first bevel 141 is smaller, providing conditions for the channel 163 on the first bevel 141 to be composed of single grains. Since there are no grain boundaries in the single grain, conditions are provided for forming a semi-thin-film transistor including a single-grain channel and having high mobility.

[0092] In some embodiments, the length of the first side slope 141 is less than or equal to 0.3 micrometers.

[0093] Specifically, the length of the first bevel 141 is less than or equal to 0.3 micrometers, which makes the length of the channel 163 smaller. For example, the length of the channel 163 is less than or equal to 0.3 micrometers, thereby reducing the number of grain boundaries in the channel 163 or making it a single grain.

[0094] Specifically, in one embodiment, the thickness of the first gate 14 is 2100 angstroms, the slope angle α is 45 degrees, the length of the first side slope 141 is 0.3 micrometers, and the channel 163 is a single crystal.

[0095] In some embodiments, the channel 163 is at least a portion of a single grain.

[0096] Specifically, the channel 163 is at least a portion of a single grain, resulting in the absence of grain boundaries in the channel 163. This increases the mobility of charge carriers in the channel 163, thereby improving the mobility of the thin-film transistor 101. This facilitates the integration of integrated chips onto the substrate, thereby reducing the manufacturing cost of the display panel.

[0097] In some embodiments, the length of the channel 163 ranges from 0.1 micrometers to 1 micrometer.

[0098] Specifically, the length of channel 163 ranges from 0.1 micrometers to 1 micrometer, and the length of channel 163 can be 0.1 micrometers, 0.2 micrometers, 0.3 micrometers, 0.4 micrometers, 0.5 micrometers, 0.6 micrometers, 0.7 micrometers, 0.8 micrometers, 0.9 micrometers, and 1.0 micrometers. Currently, the grain size obtained by crystallizing amorphous silicon through excimer laser annealing is relatively small, and the difference between this and the current channel length (greater than 2 micrometers) is significant, making it impossible for the channel to consist of a single grain. However, by reducing the length of channel 163 from 0.1 micrometers to 1 micrometer, the length of channel 163 becomes closer to the same as or similar to the size of a single grain obtained by current laser annealing processes, thereby reducing the number of grain boundaries in channel 163 or making it a single grain.

[0099] Specifically, the thickness and slope angle α of the first gate 14 determine the length of the first side slope 141, which in turn determines the length of the channel 163. Controlling the length of the first side slope 141 controls the length of the channel 163. Therefore, the length of the channel 163 can be controlled to be less than or equal to 1 micrometer, making the channel 163 a single crystal. Thus, in the production process of forming the first gate 14, controlling the thickness and slope angle α of the first gate 14 controls the length of the first side slope 141 and the length of the channel 163.

[0100] Furthermore, in conjunction with the design of the display panel 100 or the thin-film transistor 101, the width of the channel 163 can be designed to be greater than or equal to 0.3 micrometers and less than or equal to 10 micrometers. This allows the thin-film transistor 101 to simultaneously possess high mobility and a smaller size.

[0101] It should be noted that, understandably, in other embodiments, the channel 163 may also include polycrystalline materials; in other words, the channel 163 includes multiple grain boundaries. After the channel 163 is disposed on the first side slope 141, the length of the channel 163 is reduced to 0.1 micrometers to 1 micrometer. When the channel 163 includes polycrystalline materials, the number of grain boundaries in the channel 163 is correspondingly reduced, which is beneficial for improving the mobility of thin-film transistors and for enabling integrated chips to be integrated onto the substrate, thereby reducing the manufacturing cost of the display panel.

[0102] In some embodiments, the first gate insulating layer 15 forms a corner portion 31 at one end of the first side slope 141 near the substrate 11, and the channel 163 covers the corner portion 31.

[0103] Specifically, the channel 163 covers the corner portion 31. During the crystallization process to form the semiconductor layer 16, the corner portion 31 at the end of the first side slope 141 near the substrate 11 is more likely to form a seed crystal. When the seed crystal grows along the first side slope 141 to form a single crystal, the channel 163 on the first side slope 141 is relatively short, which provides the formation conditions for the channel 163 on the first side slope 141 to be composed of single crystals. There are no grain boundaries in the single crystal. The channel 163 of the thin film transistor 101 is relatively short and includes single crystals, which improves the mobility of the thin film transistor 101.

[0104] Specifically, such as Figure 3 and Figure 4 As shown, the corner portion 31 refers to the end of the first side slope 141 near the substrate 11, or the end of the first gate insulating layer 15 corresponding to the first side slope 141 near the substrate 11.

[0105] Preferably, in some embodiments, the semiconductor layer 16 is made of polycrystalline silicon.

[0106] Specifically, the semiconductor layer 16 is a low-temperature polycrystalline silicon active pattern, but it is not limited to this; the semiconductor layer 16 can also be a crystalline metal oxide active pattern.

[0107] In some embodiments, the thin-film transistor 101 further includes a first insulating layer 17, a first via 171, a second via 172, a source 181, and a drain 182. The first insulating layer 17 is disposed on the semiconductor layer 16; the first via 171 penetrates the first insulating layer 17; the second via 172 penetrates the first insulating layer 17; the source 181 and the drain 182 are disposed on the first insulating layer 17, one of the source 181 and the drain 182 is electrically connected to a first terminal 161 through the first via 171, and the other is electrically connected to a second terminal 162 through the second via 172.

[0108] In some embodiments, the thin-film transistor 101 further includes a light-shielding layer 12 and a passivation layer 13. The light-shielding layer 12 is disposed between the substrate 11 and the gate 14, and the orthogonal projection of the light-shielding layer 12 on the substrate 11 covers the orthogonal projection of the channel 163 on the substrate 11. The passivation layer 13 is disposed between the light-shielding layer 12 and the gate 14.

[0109] Specifically, the light-shielding layer 12 is used to block external light such as backlight from entering the channel 163, thereby preventing the generation of photocurrent and improving the stability of the thin-film transistor 101.

[0110] Example 3

[0111] This embodiment is the same as or similar to the thin-film transistor 101 or display panel 100 in any of the above embodiments, except that: the features of the thin-film transistor 101 or display panel 100 are further described.

[0112] Please see Figure 6 , Figure 7 and Figure 8 ; Figure 6 A top view schematic diagram of a second type of thin-film transistor for a display panel provided in an embodiment of this application; Figure 7 A first cross-sectional schematic diagram of a second type of thin-film transistor for a display panel provided in an embodiment of this application; Figure 8 This is a second cross-sectional schematic diagram of a second type of thin-film transistor for a display panel provided in an embodiment of this application. Figure 6 To clearly present the important structure of thin-film transistors, Figure 6 The diagram only shows a portion of the film layers or structure of a thin-film transistor. Figure 7 for Figure 6 A cross-sectional diagram of the section marked CC by the dashed line. Figure 8 for Figure 6 A cross-sectional diagram of the section marked by the dashed line DD.

[0113] In some embodiments, the thin-film transistor 101 further includes a second gate insulating layer 19 and a second gate 20. The second gate insulating layer 19 is disposed between the semiconductor layer 16 and the first insulating layer 17. The second gate 20 is disposed between the second gate insulating layer 19 and the first insulating layer 17, and the second gate 20 is disposed corresponding to the channel 163.

[0114] Specifically, the thin-film transistor 101 includes a first gate 14 and a second gate 20, with a semiconductor layer 16 sandwiched between the first gate 14 and the second gate 20. The first gate 14 and the second gate 20 form a dual-gate structure. The dual-gate structure can enhance the control capability of the channel 163, reduce the short-channel effect, and increase the on-state current of the thin-film transistor 101. In addition, adding the second gate 20 can perform a self-aligned doping process to enhance device stability.

[0115] In some embodiments, the second gate insulating layer 19 forms a third side slope 191 corresponding to the first side slope 141, and the second gate 20 is located on the third side slope 191.

[0116] Specifically, the second gate insulating layer 19 is attached to the first side slope 141 to form the third side slope 191, and the second gate 20 is located on the third side slope 191, so that the channel 163 is sandwiched between the first gate 14 and the second gate 20. At the same time, the second gate 20 occupies a smaller layout space, which reduces the size of the thin film transistor 101.

[0117] In some embodiments, the thin-film transistor 101 further includes a third via, which penetrates the first gate insulating layer 15 and the second gate insulating layer 19, and the second gate 20 is connected to the first gate 14 through the third via.

[0118] Specifically, although the third via is not shown in the schematic diagram, it is easy to understand that the third via penetrates the first gate insulating layer 15 and the second gate insulating layer 19, so that the second gate 20 is connected to the first gate 14 through the third via. The first gate 14 and the second gate 20 form a dual-gate structure. The first gate 14 and the second gate 20 have the same potential. The first gate 14 and the second gate 20 together control the channel 163.

[0119] Example 4

[0120] This embodiment is the same as or similar to the thin-film transistor 101 or display panel 100 in any of the above embodiments, except that: the features of the thin-film transistor 101 or display panel 100 are further described.

[0121] Please see Figure 9 , Figure 10 and Figure 11 ; Figure 9 A top view schematic diagram of a third type of thin-film transistor for a display panel provided in an embodiment of this application; Figure 10 This is a first cross-sectional schematic diagram of a third type of thin-film transistor for a display panel provided in an embodiment of this application; Figure 11 This is a first cross-sectional schematic diagram of a fourth type of thin-film transistor for a display panel provided in an embodiment of this application. Figure 9 To clearly present the important structure of thin-film transistors, Figure 9 The diagram only shows a portion of the film layers or structure of a thin-film transistor. Figure 10 for Figure 9 A cross-sectional diagram of the section marked by the dashed line EE.

[0122] In some embodiments, the thin-film transistor 101 further includes an extension 148 extending from the first side slope 141 toward the side close to the semiconductor layer 16, the thickness of the extension 148 being less than the thickness of the first gate 14, and the orthographic projection of the extension 148 on the substrate 11 at least partially overlapping the orthographic projection of the channel 163 on the substrate 11.

[0123] Specifically, the thin-film transistor 101 also includes an extension 148 extending from the first side slope 141 toward the side near the semiconductor layer 16. The extension 148 is connected to the end of the first side slope 141 near the substrate 11. The orthographic projection of the extension 148 on the substrate 11 at least partially overlaps with the orthographic projection of the channel 163 on the substrate 11. The first gate 14 is used to control the channel 163, and the extension 148 acts as a light-shielding layer to block external light from entering the channel 163.

[0124] Specifically, the extension 148 is connected to the first gate 14 at one end of the first side slope 141 near the base 11, that is, the connection between the extension 148 and the first gate 14 forms a corner portion 31.

[0125] Specifically, the thickness of the extension 148 is less than the thickness of the first gate 14 to form the corner portion 31 and the first side slope 141.

[0126] Preferably, in some embodiments, the orthogonal projections of the extension 148 and the first gate 14 on the substrate 11 completely cover the orthogonal projection of the channel 163 on the substrate 11. The extension 148 and the first gate 14 can better block external light such as backlight from entering the channel 163, avoid generating photocurrent, and improve the stability of the thin film transistor 101.

[0127] It should be noted that in some implementations, when the thin-film transistor 101 does not include the extension 148, such as in Embodiments 1 to 3, the display panel 100 further includes a light-shielding layer 12. The light-shielding layer 12 is disposed on the substrate 11, the passivation layer 13 is disposed on the light-shielding layer 12, and the first gate 14 is disposed on the passivation layer 13. The light-shielding layer 12 is used to block external light from entering the channel 163. The orthographic projection of the light-shielding layer 12 on the substrate 11 at least partially overlaps with the orthographic projection of the channel 163 on the substrate 11, and the orthographic projection of the light-shielding layer 12 and the first gate 14 together on the substrate 11 covers the orthographic projection of the channel 163 on the substrate 11.

[0128] Example 5

[0129] This embodiment also provides a method for manufacturing the display panel 100 according to any of the embodiments in Embodiment 2, that is, providing a first thin-film transistor or Figure 3 Method for manufacturing the thin-film transistor 101 shown.

[0130] Please see Figures 12 to 16 , Figure 3 ; Figure 12 A schematic diagram of the first intermediate process of a method for manufacturing a first / second type of thin-film transistor for a display panel provided in an embodiment of this application; Figure 13 A schematic diagram of the second intermediate process of a method for manufacturing a first / second type of thin-film transistor for a display panel provided in an embodiment of this application; Figure 14 A schematic diagram of the third intermediate process of a method for manufacturing a first / second type of thin-film transistor for a display panel provided in an embodiment of this application; Figure 15 A schematic diagram of the fourth intermediate process of a method for manufacturing a first / second type of thin-film transistor for a display panel provided in an embodiment of this application; Figure 16 This is a schematic diagram of the fifth intermediate process of a first thin-film transistor manufacturing method for a display panel provided in an embodiment of this application.

[0131] The manufacturing method of the display panel in this embodiment includes the following steps: S100, S200, S300, S400, S500, S600, and S700.

[0132] Step S100, as follows Figure 12 As shown, a substrate 11 is provided.

[0133] Step S200, as follows Figure 12 As shown, a light-shielding layer 12 is formed on the substrate 11.

[0134] Step S300, as follows Figure 13 As shown, a passivation layer 13 is formed on the light-shielding layer 12, and a first gate 14 is formed on the passivation layer 13.

[0135] Specifically, the structure and features of the first gate 14 are the same as those in Embodiments 1 to 2. Figure 3 The first gate 14 shown is the same as or similar to that shown, and will not be described again here.

[0136] Step S400, as follows Figure 14 As shown, a first gate insulating layer 15 is formed on the first gate 14, and a semiconductor layer 16 is formed on the first gate insulating layer 15.

[0137] Step S500, as follows Figure 15 As shown, semiconductor layer 16 is doped.

[0138] Specifically, in steps S400 and S500, the structure and features of the semiconductor layer 16 are the same as those in Embodiments 1 to 2 and / or Figure 3 The semiconductor layer 16 shown is the same as or similar to that shown, and will not be described again here.

[0139] Step S600, as follows Figure 16 As shown, a first insulating layer 17 is formed on the semiconductor layer 16, and the first insulating layer 17 includes a first through-hole 171 and a second through-hole 172.

[0140] Specifically, the structure and features of the first insulating layer 17 in step S600 are the same as those in Embodiments 1 to 2. Figure 3 The first insulating layer 17 shown is the same as or similar to that shown, and will not be described again here.

[0141] Step S700, as follows Figure 3 As shown, source 181 and drain 182 are formed.

[0142] Specifically, a source / drain metal layer 18 is formed on the first insulating layer 17. The source / drain metal layer 18 is patterned to form a source 181 and a drain 182. The structure and features of the source 181 and the drain 182 are the same as those in Embodiments 1 to 2. Figure 3The source 181 and drain 182 shown are the same or similar, and will not be described again here.

[0143] Example 6

[0144] This embodiment also provides a method for manufacturing the display panel 100 according to any of the embodiments in Embodiment 3, that is, providing a second type of thin-film transistor or Figure 7 Method for manufacturing the thin-film transistor 101 shown.

[0145] Please see Figures 12 to 15 , Figures 17 to 19 , Figure 7 ; Figure 12 A schematic diagram of the first intermediate process of a method for manufacturing a first / second type of thin-film transistor for a display panel provided in an embodiment of this application; Figure 13 A schematic diagram of the second intermediate process of a method for manufacturing a first / second type of thin-film transistor for a display panel provided in an embodiment of this application; Figure 14 A schematic diagram of the third intermediate process of a method for manufacturing a first / second type of thin-film transistor for a display panel provided in an embodiment of this application; Figure 15 A schematic diagram of the fourth intermediate process of a method for manufacturing a first / second type of thin-film transistor for a display panel provided in an embodiment of this application; Figure 17 A schematic diagram of the fifth intermediate process of a method for manufacturing two thin-film transistors for a display panel provided in an embodiment of this application; Figure 18 A schematic diagram of the sixth intermediate process of a method for manufacturing two thin-film transistors for a display panel provided in an embodiment of this application; Figure 19 This is a schematic diagram of the seventh intermediate process of a method for manufacturing two thin-film transistors for a display panel provided in an embodiment of this application.

[0146] The manufacturing method of the display panel in this embodiment includes the following steps: S100, S200, S300, S400, S500, S600, and S700.

[0147] Step S100, as follows Figure 12 As shown, a substrate 11 is provided.

[0148] Step S200, as follows Figure 12 As shown, a light-shielding layer 12 is formed on the substrate 11.

[0149] Step S300, as follows Figure 13 As shown, a passivation layer 13 is formed on the light-shielding layer 12, and a first gate 14 is formed on the passivation layer 13.

[0150] Specifically, the structure and features of the first gate 14 are the same as those in Embodiments 1 to 3. Figure 3 / Figure 7The first gate 14 shown is the same as or similar to that shown, and will not be described again here.

[0151] Step S400, as follows Figure 14 As shown, a first gate insulating layer 15 is formed on the first gate 14, and a semiconductor layer 16 is formed on the first gate insulating layer 15.

[0152] Step S500, as follows Figure 15 As shown, semiconductor layer 16 is doped.

[0153] Specifically, in steps S400 and S500, the structure and features of the semiconductor layer 16 are the same as those in Embodiments 1 to 3. Figure 3 / Figure 7 The semiconductor layer 16 shown is the same as or similar to that shown, and will not be described again here.

[0154] Step S600, as follows Figure 17 As shown, a second gate insulating layer 19 is formed on the semiconductor layer 16.

[0155] Specifically, the structure and features of the second gate insulating layer 19 are the same as those in Embodiment 3 or Figure 7 The same or similar examples will not be repeated here.

[0156] Step S700, as follows Figure 18 As shown, a second gate 20 is formed on the second gate insulating layer.

[0157] Specifically, the structure and features of the second gate 20 are the same as those in Embodiment 3 or Figure 7 The same or similar examples will not be repeated here.

[0158] Step S800, as follows Figure 19 As shown, a first insulating layer 17 is formed on the second gate 20, and the first insulating layer 17 includes a first through hole 171 and a second through hole 172.

[0159] Specifically, in step S800, the structure and features of the first insulating layer 17 are the same as those in Embodiment 3 or Figure 7 The same or similar examples will not be repeated here.

[0160] Step S900, as follows Figure 7 As shown, source 181 and drain 182 are formed.

[0161] Specifically, a source / drain metal layer 18 is formed on the first insulating layer 17. The source / drain metal layer 18 is patterned to form a source 181 and a drain 182. The structure and features of the source 181 and the drain 182 are the same as in Embodiment 3 or Figure 7 The same or similar examples will not be repeated here.

[0162] Example 7

[0163] This embodiment also provides a method for manufacturing the display panel 100 according to any of the four embodiments, that is, providing a third / fourth thin-film transistor or Figure 10 / Figure 11 Method for manufacturing the thin-film transistor 101 shown.

[0164] Please see Figure 20 and Figure 21 ; Figure 20 A schematic diagram of a first intermediate process in a method for manufacturing the first gate 14 of a thin-film transistor in a display panel, as provided in an embodiment of this application; Figure 21 This is a schematic diagram of a second intermediate process in a method for manufacturing the first gate 14 of a thin-film transistor in a display panel, as provided in an embodiment of this application.

[0165] This embodiment provides a third type of thin-film transistor or Figure 10 The manufacturing method of the thin-film transistor 101 shown, the third type of thin-film transistor or Figure 10 The manufacturing method of the thin-film transistor 101 shown is similar to that of Embodiment 5, except that there is no light-shielding layer 12 and the manufacturing process of the first gate 14 is different.

[0166] This embodiment provides a fourth type of thin-film transistor or Figure 11 The manufacturing method of the thin-film transistor 101 shown, the fourth type of thin-film transistor or Figure 11 The manufacturing method of the thin-film transistor 101 shown is similar to that of Embodiment Six, except that there is no light-shielding layer 12 and the manufacturing process of the first gate 14 is different.

[0167] like Figure 20 and Figure 21 As shown, a preset pattern 1401 of the pattern of the first gate 14 is first formed by a first etching, and then the first gate 14 and the extension 148 are formed by a second etching.

[0168] Specifically, such as Figure 20 As shown, a preset pattern 1401 of the pattern of the first gate 14 is first formed by the first etching, at which time the extension 148 has the same thickness as the first gate 14.

[0169] Specifically, such as Figure 21 As shown, the first gate 14 and the extension 148 are formed by a second etching, that is, the thickness of the extension 148 is reduced by the second etching.

[0170] Specifically, the structure and features of the first gate 14 and the extension 148 are the same as in Embodiment 4, or Figure 10 or Figure 11 The same or similar examples will not be repeated here.

[0171] It should be noted that in any of the above embodiments of the display panel 100 or the thin film transistor 101, controlling the length of the first side slope 141 can control the length of the channel 163, so that the channel 163 is composed of a single crystal, which is beneficial to improving the mobility of the thin film transistor and to realizing the integration of the integrated chip on the substrate, thereby reducing the manufacturing cost of the display panel.

[0172] It should be noted that, as can be understood, in any of the display panel 100 or thin-film transistor 101 in the above embodiments, the channel 163 may also include polycrystalline materials; in other words, the channel 163 includes multiple grain boundaries. When the channel 163 is disposed on the first side slope 141, and the channel 163 includes polycrystalline materials, the number of grain boundaries in the channel 163 is correspondingly reduced. This is beneficial for improving the mobility of the thin-film transistor and for enabling the integrated chip to be integrated onto the substrate, thereby reducing the manufacturing cost of the display panel.

[0173] Example 8

[0174] Please see Figure 22 , Figure 22 This is a schematic diagram of a display terminal 200 provided in an embodiment of this application.

[0175] This application also provides a display terminal 200, which includes the display panel 100 of any of the above embodiments.

[0176] Specifically, the display terminal 200 can be a mobile phone, a laptop computer, or a television, etc. The display terminal 200 may also include a terminal body 201, which is integrated with the display panel 100. The terminal body 201 can be the shell, driving structure, or other structures and components of the display terminal 200.

[0177] The above provides a detailed description of a display panel provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A display panel, characterized in that, Includes a substrate and a thin-film transistor disposed on the substrate, the thin-film transistor comprising: A first gate is disposed on the substrate. The first gate includes a first side slope and a second side slope disposed opposite to each other, and a top surface sandwiched between the first side slope and the second side slope. A first gate insulating layer covers the substrate, the first side slope, the second side slope, and the top surface; A semiconductor layer is disposed on the first gate insulating layer. The semiconductor layer includes a first end, a second end, and a channel located between the first end and the second end. The second end is at least partially located on the top surface, and the channel is at least partially located on the first side slope. A first insulating layer is disposed on the semiconductor layer; A source and a drain are disposed on the first insulating layer, one of which is electrically connected to the first terminal and the other is electrically connected to the second terminal; Wherein, the thickness of the first gate insulating layer at the substrate is greater than the thickness of the first gate insulating layer at the first side slope.

2. The display panel as described in claim 1, characterized in that, The orthographic projection of the channel on the substrate overlaps with the orthographic projection of the first side slope on the substrate.

3. The display panel as described in claim 1, characterized in that, The slope angle between the first side slope and the base is greater than or equal to 45 degrees and less than or equal to 90 degrees.

4. The display panel as described in claim 1, characterized in that, The thickness of the first gate insulating layer at the substrate is 1.2 to 2 times the thickness of the first gate insulating layer at the first side slope.

5. The display panel as described in claim 1, characterized in that, The thickness of the first gate is 0.1 micrometers to 1 micrometer.

6. The display panel as described in claim 5, characterized in that, The length of the first inclined plane is less than or equal to 0.3 micrometers.

7. The display panel as described in claim 1, characterized in that, The channel is at least a portion of a single grain.

8. The display panel as described in claim 1, characterized in that, The length of the channel ranges from 0.1 micrometers to 1 micrometer.

9. The display panel as claimed in claim 1, characterized in that, The first gate insulating layer forms a corner portion at one end of the first side slope near the substrate, and the channel covers the corner portion.

10. The display panel as claimed in any one of claims 1 to 9, characterized in that, The thin-film transistor further includes: The first through hole penetrates the first insulating layer; The second through hole penetrates the first insulating layer; In this configuration, one of the source and the drain is electrically connected to the first terminal through the first via, and the other is electrically connected to the second terminal through the second via.

11. The display panel as claimed in claim 10, characterized in that, The thin-film transistor further includes: A light-shielding layer is disposed between the substrate and the gate, wherein the orthogonal projection of the light-shielding layer on the substrate covers the orthogonal projection of the channel on the substrate; A passivation layer is disposed between the light-shielding layer and the gate.

12. The display panel as claimed in claim 10, characterized in that, The thin-film transistor further includes an extension extending from the first side slope toward the side close to the semiconductor layer, the thickness of the extension being less than the thickness of the first gate, and the orthographic projection of the extension on the substrate at least partially overlapping the orthographic projection of the channel on the substrate.

13. The display panel as claimed in claim 10, characterized in that, The thin-film transistor further includes: A second gate insulating layer is disposed between the semiconductor layer and the first insulating layer; The second gate is disposed between the second gate insulating layer and the first insulating layer, and the second gate is disposed corresponding to the channel.

14. The display panel as claimed in claim 13, characterized in that, The second gate insulating layer forms a third side slope corresponding to the first side slope, and the second gate is located on the third side slope.

15. The display panel as claimed in claim 13, characterized in that, The thin-film transistor further includes: The third via penetrates the first gate insulating layer and the second gate insulating layer, and the second gate is connected to the first gate through the third via.

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