Thin film transistor and its manufacturing method, array substrate

Abstract

The present application discloses a thin film transistor and a preparation method thereof, and an array substrate. The thin film transistor includes a substrate, an active part, a gate, a gate insulating part, a source and a drain. The active part arranged on the substrate includes a semiconductor part, a first conductor part and a second conductor part which are in the same layer and connected, and the first conductor part and the second conductor part are arranged on both sides of the semiconductor part; the gate insulating part is arranged between the gate and the active part, and the gate and the semiconductor part are arranged correspondingly. The gate includes a first end and a second end which are opposite to each other, and the first end and the second end are respectively located on both sides of the gate close to the first conductor part and the second conductor part; the end of the gate does not overlap with the end of the gate insulating part and the end of the semiconductor part; the source and the drain are in the same layer and are arranged at intervals, the source is connected to the first conductor part, and the drain is connected to the second conductor part; the distance from the first end to the first conductor part is smaller than the distance from the second end to the second conductor part, so that the warping effect of the thin film transistor can be reduced.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a thin film transistor and a preparation method thereof, and an array substrate. Background Art

[0002] As the resolution gets higher and higher, the size of thin film transistors needs to get smaller and smaller. In existing thin film transistors, the gate insulating layer and the gate are arranged on the semiconductor part of the active layer, and the ends of the gate insulating layer and the gate usually coincide with the ends of the semiconductor part, that is, the distances from the ends of the gate to the source and drain are equal, resulting in a serious increase and multiplication of carriers near the drain end of the thin film transistor under a higher drain voltage, so that the drain current increases rapidly with the drain voltage, resulting in a serious warping effect of the thin film transistor, resulting in the problem that the threshold voltage of the thin film transistor is easily unsaturated, resulting in abnormal driving of the thin film transistor. Summary of the invention

[0003] The embodiments of the present application provide a thin film transistor and a method for manufacturing the same, and an array substrate to improve the warping effect of the thin film transistor.

[0004] The present application provides a thin film transistor, comprising:

[0005] substrate;

[0006] an active portion, disposed on the substrate, the active portion comprising a semiconductor portion, a first conductor portion, and a second conductor portion that are connected and disposed in the same layer, the first conductor portion and the second conductor portion being disposed on opposite sides of the semiconductor portion;

[0007] a gate, arranged at one side of the active portion and corresponding to the semiconductor portion, wherein an edge of an orthographic projection of the gate on the substrate is located within an orthographic projection of the semiconductor portion on the substrate, and the gate comprises a first end and a second end that are arranged opposite to each other, wherein the first end is located at a side of the gate close to the first conductor portion, and the second end is located at a side of the gate close to the second conductor portion;

[0008] a gate insulating portion, disposed between the active portion and the gate and corresponding to the semiconductor portion, wherein an edge of an orthographic projection of the gate on the substrate is located within the orthographic projection of the gate insulating portion on the substrate; and

[0009] A source electrode and a drain electrode, wherein the source electrode and the drain electrode are in the same layer and are spaced apart from each other, the source electrode is connected to the first conductor portion, and the drain electrode is connected to the second conductor portion;

[0010] The distance from the edge of the orthographic projection of the first end on the substrate to the edge of the orthographic projection of the first conductor portion on the substrate is smaller than the distance from the edge of the orthographic projection of the second end on the substrate to the edge of the orthographic projection of the second conductor portion on the substrate.

[0011] Optionally, in some embodiments of the present application, the distance from the edge of the orthographic projection of the first end on the substrate to the edge of the orthographic projection of the first conductor portion on the substrate is 0, and the distance from the edge of the orthographic projection of the second end on the substrate to the edge of the orthographic projection of the second conductor portion on the substrate is greater than 0.

[0012] Optionally, in some embodiments of the present application, the distance from the edge of the orthographic projection of the second end on the substrate to the edge of the orthographic projection of the second conductor portion on the substrate is greater than 1 micron.

[0013] Optionally, in some embodiments of the present application, the semiconductor portion includes a first part and a second part that are connected and arranged in the same layer, the first part is located on a side of the second part away from the second conductor portion, the first part is arranged corresponding to the gate and the gate insulating portion, and the second part is staggered with the gate, and when the thin film transistor is working, the resistance of the first part is less than the resistance of the second part.

[0014] Optionally, in some embodiments of the present application, an edge of an orthographic projection of the gate insulating portion on the substrate coincides with an edge of an orthographic projection of the semiconductor portion on the substrate.

[0015] Optionally, in some embodiments of the present application, the active portion is arranged on the substrate, the gate insulating portion is arranged on a side of the active portion away from the substrate, the gate is arranged on a side of the gate insulating portion away from the active portion, and the source and the drain are in the same layer and are arranged at intervals on a side of the active portion away from the substrate.

[0016] Optionally, in some embodiments of the present application, the source and the drain are arranged on the substrate, the active portion is arranged on the substrate, on a side of the source away from the substrate, and on a side of the drain away from the substrate, the gate insulating portion is arranged on a side of the active portion away from the substrate, and the gate is arranged on a side of the gate insulating portion away from the active portion.

[0017] The present application also provides an array substrate, which includes a plurality of thin film transistors, at least one of the thin film transistors is any of the thin film transistors described above.

[0018] The present application also provides a method for preparing the thin film transistor, wherein the substrate comprises a first region, a second region and a third region connected to each other, the first region and the third region are respectively located on both sides of the second region, and the method for preparing the thin film transistor comprises:

[0019] forming a patterned active layer on the substrate;

[0020] forming a gate insulating layer on a side of the patterned active layer away from the substrate;

[0021] forming a gate layer on a side of the gate insulating layer away from the patterned active layer;

[0022] A photoresist layer is formed on a side of the gate layer away from the gate insulating layer, the photoresist layer comprising a first photoresist portion, a second photoresist portion and a third photoresist portion which are connected and arranged in the same layer, the first photoresist portion is arranged on the gate layer located on the first region, the second photoresist portion is arranged on the gate layer located on the second region, and the third photoresist portion is arranged on the gate layer located on the third region;

[0023] removing the third light blocking portion;

[0024] Using the first photoresist portion and the second photoresist portion as shields, performing a first etching process on the gate layer to remove the gate layer located on the third region and a portion of the gate layer located on the second region;

[0025] removing the first light blocking portion;

[0026] Using the second photoresist portion as a shield, a second etching process is performed on the gate layer on the first area and a portion of the gate layer located on the second area to form a gate, and the gate is located on the second area; wherein the edge of the orthographic projection of the gate on the substrate is located within the orthographic projection of the second photoresist portion on the substrate, and the distance between the edge of the orthographic projection of the first end on the substrate and the side of the second photoresist portion close to the first area is smaller than the distance between the edge of the orthographic projection of the second end on the substrate and the side of the second photoresist portion close to the third area;

[0027] Performing patterning on the gate insulating layer, wherein the gate insulating layer forms a gate insulating portion;

[0028] Conducting the patterned active layer, the patterned active layer forms an active portion, the semiconductor portion is located in the second region, the first conductor portion is located in the first region, and the second conductor portion is located in the third region; and

[0029] The second photoresist portion is removed.

[0030] Optionally, in some embodiments of the present application, one end of the gate layer is etched once to form a first end of the gate, so that the distance from the edge of the orthographic projection of the first end on the substrate to the edge of the orthographic projection of the first conductor part on the substrate is 0, and the other end of the gate layer is etched twice to form a second end of the gate, so that the distance from the edge of the orthographic projection of the second end on the substrate to the edge of the orthographic projection of the second conductor part on the substrate is greater than 0.

[0031] The present application discloses a thin film transistor and a preparation method thereof, and an array substrate. The thin film transistor comprises a substrate, an active part, a gate, a gate insulating part, a source electrode and a drain electrode. The active part is arranged on the substrate, and the active part comprises a semiconductor part, a first conductor part and a second conductor part which are connected and arranged in the same layer, and the first conductor part and the second conductor part are arranged on opposite sides of the semiconductor part; the gate is arranged on one side of the active part and is arranged corresponding to the semiconductor part, and the edge of the gate's orthographic projection on the substrate is located within the edge of the semiconductor part's orthographic projection on the substrate, and the gate comprises a first end and a second end which are arranged oppositely, the first end is located on a side of the gate close to the first conductor part, and the second end is located on a side of the gate close to the second conductor part; the gate insulating part is arranged between the active part and the gate, and is arranged corresponding to the semiconductor part, and the edge of the gate's orthographic projection on the substrate is located within the orthographic projection of the gate insulating part on the substrate; the source electrode and the drain electrode are in the same layer and arranged at intervals, the source electrode is connected to the first conductor part, and the drain electrode is connected to the second conductor part; wherein the distance from the edge of the orthographic projection of the first end on the substrate to the edge of the orthographic projection of the first conductor part on the substrate is smaller than the distance from the edge of the orthographic projection of the second end on the substrate to the edge of the orthographic projection of the second conductor part on the substrate. In the present application, the edge of the gate's orthographic projection on the substrate is set to be located within the orthographic projection of the gate insulating portion on the substrate, and the distance from the edge of the orthographic projection of the first end on the substrate to the edge of the orthographic projection of the first conductor portion on the substrate is set to be smaller than the distance from the edge of the orthographic projection of the second end on the substrate to the edge of the orthographic projection of the second conductor portion on the substrate, so that a high-resistance region is formed in the semiconductor portion where no gate is provided and close to the drain, that is, a region without gate regulation is formed at one end of the semiconductor portion close to the drain, thereby avoiding the problem that under the drain voltage, the carriers near the drain will multiply, and the drain current will increase rapidly with the drain voltage, that is, reducing the warping effect, thereby improving the saturation characteristics of the transistor, and thus improving the performance of the thin film transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0033] Figure 1 It is a plan view schematic diagram of a thin film transistor provided in an embodiment of the present application.

[0034] Figure 2 The embodiment of this application provides Figure 1 Schematic diagram of the first structure along line AB.

[0035] Figure 3 The embodiment of this application provides Figure 1 Schematic diagram of the second structure along line AB.

[0036] Figure 4 It is a schematic flow chart of the steps of the method for preparing a thin film transistor provided in an embodiment of the present application.

[0037] Figure 5-10 It is a schematic diagram of the step flow structure of the method for preparing a thin film transistor provided in an embodiment of the present application.

[0038] Reference numerals:

[0039] Thin film transistor 10; patterned active layer 20; gate insulating layer 30; gate layer 40; photoresist layer 50; first photoresist portion 51; second photoresist portion 52; substrate 100; first region 101; second region 102; third region 103; buffer layer 200; active portion 300; semiconductor portion 310; first portion 311; second portion 312; first conductor portion 320; second conductor portion 330; gate insulating portion 400; gate 500; first end 501; second end 502; interlayer dielectric portion 600; through hole 601; source 700; drain 800; passivation layer 900. DETAILED DESCRIPTION

[0040] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise stated, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the accompanying drawings; and "inside" and "outside" refer to the outline of the device. In the present application, "reaction" can be a chemical reaction or a physical reaction.

[0041] The present application discloses a thin film transistor and a preparation method thereof, and an array substrate. The thin film transistor includes a substrate, an active part, a gate, a gate insulating part, a source electrode and a drain electrode. The active part is arranged on the substrate, and the active part includes a semiconductor part, a first conductor part and a second conductor part which are connected and arranged in the same layer, and the first conductor part and the second conductor part are arranged on opposite sides of the semiconductor part; the gate is arranged on one side of the active part and is arranged corresponding to the semiconductor part, and the edge of the gate's orthographic projection on the substrate is located within the edge of the semiconductor part's orthographic projection on the substrate, and the gate includes a first end and a second end which are arranged oppositely, the first end is located on a side of the gate close to the first conductor part, and the second end is located on a side of the gate close to the second conductor part; the gate insulating part is arranged between the active part and the gate, and is arranged corresponding to the semiconductor part, and the edge of the gate's orthographic projection on the substrate is located within the orthographic projection of the gate insulating part on the substrate; the source electrode and the drain electrode are in the same layer and arranged at intervals, the source electrode is connected to the first conductor part, and the drain electrode is connected to the second conductor part; wherein the distance from the edge of the orthographic projection of the first end on the substrate to the edge of the orthographic projection of the first conductor part on the substrate is smaller than the distance from the edge of the orthographic projection of the second end on the substrate to the edge of the orthographic projection of the second conductor part on the substrate.

[0042] In the present application, the edge of the gate's orthographic projection on the substrate is set to be located within the orthographic projection of the gate insulating portion on the substrate, and the distance from the edge of the orthographic projection of the first end on the substrate to the edge of the orthographic projection of the first conductor portion on the substrate is set to be smaller than the distance from the edge of the orthographic projection of the second end on the substrate to the edge of the orthographic projection of the second conductor portion on the substrate, so that a high-resistance region is formed in the semiconductor portion where no gate is provided and close to the drain, that is, a region without gate regulation is formed at one end of the semiconductor portion close to the drain, thereby avoiding the problem that under the drain voltage, the carriers near the drain will multiply, and the drain current will increase rapidly with the drain voltage, that is, the warping effect is reduced, thereby improving the saturation characteristics of the transistor, thereby improving the performance of the thin film transistor.

[0043] See also Figure 1 and Figure 2 The present application provides a thin film transistor 10 . The thin film transistor 10 includes a substrate 100 , an active portion 300 , a gate 500 , a gate insulating portion 400 , a source 700 , and a drain 800 .

[0044] The substrate 100 includes a first region 101 , a second region 102 , and a third region 103 which are in the same layer and connected. The first region 101 and the third region 103 are located on both sides of the second region 102 .

[0045] The active part 300 is disposed on the substrate 100. The active part 300 includes a semiconductor part 310, a first conductor part 320 and a second conductor part 330 in the same layer and connected, and the first conductor part 320 and the second conductor part 330 are disposed on opposite sides of the semiconductor part 310. Specifically, the active part 300 is disposed on a side of the buffer layer 200 away from the substrate 100. The semiconductor part 310 is located in the second region 102. The first conductor part 320 is located in the first region 101. The second conductor part 330 is located in the third region 103. The material of the active part 300 includes at least one of IGZO and IGZTO, and the material of the active part 300 may also be other metal oxides, which are not limited here. The semiconductor part 310 includes a first part 311 and a second part 312 in the same layer and connected. The first part 311 is located on a side of the second part 312 away from the second conductor part 330. The first portion 311 is arranged corresponding to the gate 500 and the gate insulating portion 400, that is, the orthographic projection of the gate 500 on the substrate 100 is located within the orthographic projection of the first portion 311 on the substrate 100, or the orthographic projection of the gate 500 on the substrate 100 coincides with the orthographic projection of the first portion 311 on the substrate 100. The second portion 312 is arranged staggered with the gate 500, that is, the orthographic projection of the second portion 312 on the substrate 100 is arranged staggered with the orthographic projection of the gate 500 on the substrate 100. When the thin film transistor 10 is working, the resistance of the first portion 311 is less than the resistance of the second portion 312. d is the width of the semiconductor portion 310.

[0046] In one embodiment, the thickness of the active portion 300 is 20-200 nm. Specifically, the thickness of the active portion 300 may be 20 nm, 50 nm, 100 nm, 150 nm or 200 nm.

[0047] The gate insulating portion 400 is disposed on a side of the active portion 300 away from the substrate 100, and is disposed corresponding to the semiconductor portion 310. Specifically, the material of the gate insulating portion 400 includes at least one of silicon oxide and silicon nitride. The edge of the orthographic projection of the gate insulating portion 400 on the substrate 100 coincides with the edge of the orthographic projection of the semiconductor portion 310 on the substrate 100.

[0048] The gate 500 is disposed on a side of the active portion 300 away from the substrate 100, and is disposed corresponding to the semiconductor portion 310. The edge of the orthographic projection of the gate 500 on the substrate 100 is located within the orthographic projection of the semiconductor portion 310 on the substrate 100. The gate 500 includes a first end 501 and a second end 502 that are disposed opposite to each other. The first end 501 is located on a side of the gate 500 close to the first conductor portion 320. The second end 502 is located on a side of the gate 500 close to the second conductor portion 330. The edge of the orthographic projection of the gate 500 on the substrate 100 is located within the orthographic projection of the gate insulating portion 400 on the substrate 100. The distance h from the edge of the orthographic projection of the first end 501 on the substrate 100 to the edge of the orthographic projection of the first conductor portion 320 on the substrate 100 is smaller than the distance w from the edge of the orthographic projection of the second end 502 on the substrate 100 to the edge of the orthographic projection of the second conductor portion 330 on the substrate 100. Specifically, the distance h from the edge of the orthographic projection of the first end 501 on the substrate 100 to the edge of the orthographic projection of the first conductor portion 320 on the substrate 100 is 0. The distance w from the edge of the orthographic projection of the second end 502 on the substrate 100 to the edge of the orthographic projection of the second conductor portion 330 on the substrate 100 is greater than 0.

[0049] In the present application, the edge of the orthographic projection of the gate insulating portion 400 on the substrate 100 is set to coincide with the edge of the orthographic projection of the semiconductor portion 310 on the substrate 100, and the edge of the orthographic projection of the gate 500 on the substrate 100 is set to be located within the orthographic projection of the gate insulating portion 400 on the substrate 100, that is, the ends of the gate insulating portion 400 and the gate 500 do not coincide, so that the semiconductor portion 310 where the gate 500 is not provided and close to the drain 800 end is not controlled by the gate 500, that is, when the thin film transistor 10 is working, the semiconductor portion 310 where the gate 500 is not provided and close to the drain 800 end forms a high-resistance region, thereby avoiding the multiplication of carriers near the drain 800 under the drain 800 voltage, and the problem that the drain 800 current will increase rapidly with the drain 800 voltage, that is, reducing the warping effect, thereby improving the saturation characteristics of the transistor, thereby improving the performance of the thin film transistor 10. At the same time, the edge of the orthographic projection of the gate insulating portion 400 on the substrate 100 is set to coincide with the edge of the orthographic projection of the semiconductor portion 310 on the substrate 100, so that when the active portion 300 is subjected to a plasma doping process, the gate insulating portion 400 can be used as a shield, thereby simplifying the preparation process of the active portion 300 and facilitating the rapid preparation of the thin film transistor 10.

[0050] If the end of the gate insulating portion 400 and the end of the gate 500 are set to overlap; or if the end of the gate insulating portion 400 is set to exceed the end of the gate 500, the second portion 312 will be regulated by the electric field of the gate 500, that is, carriers will be introduced into the semiconductor portion 310 under the electric field of the gate 500, thereby causing the resistance of the second portion 312 to decrease, and thus a high-resistance region cannot be formed.

[0051] The distance w from the edge of the orthographic projection of the second end 502 on the substrate 100 to the edge of the orthographic projection of the second conductor portion 330 on the substrate 100 is greater than 1 micron. Specifically, the distance w from the edge of the orthographic projection of the second end 502 on the substrate 100 to the edge of the orthographic projection of the second conductor portion 330 on the substrate 100 may be 1 micron, 2 microns, 5 microns, or 8 microns, etc.

[0052] In the present application, the distance w from the edge of the orthographic projection of the second end 502 on the substrate 100 to the edge of the orthographic projection of the second conductor portion 330 on the substrate 100 is set to be greater than 1 micron. According to the resistance formula R=ρ*w / s, w is the length and s is the cross-sectional area. At this time, the resistance of the second portion 312 is further improved, so that the warping effect can be further reduced, thereby improving the saturation characteristics of the transistor, thereby improving the performance of the thin film transistor 10.

[0053] In one embodiment, the thin film transistor further includes a buffer layer 200 , an interlayer dielectric portion 600 , and a passivation layer 900 .

[0054] The buffer layer 200 is disposed on the substrate 100. The interlayer dielectric portion 600 is disposed on a side of the active portion 300 away from the substrate 100, a side of the gate insulating portion 400 away from the substrate 100, a side of the gate 500 away from the substrate 100, and a side of the buffer layer 200 away from the substrate 100. The interlayer dielectric portion 600 is provided with a through hole 601. The through hole 601 penetrates the interlayer dielectric portion 600 to expose the first conductor portion 320 and the second conductor portion 330.

[0055] The source electrode 700 and the drain electrode 800 are in the same layer and are spaced apart. The source electrode 700 is connected to the first conductor part 320, and the drain electrode 800 is connected to the second conductor part 330. Specifically, the source electrode 700 and the drain electrode 800 are in the same layer and are spaced apart on a side of the active part 300 away from the substrate 100. The source electrode 700 and the drain electrode 800 extend into the through hole 601 and are connected to the first conductor part 320 and the second conductor part 330.

[0056] The active portion 300, the gate insulating portion 400, the gate 500, the source 700 and the drain 800 constitute a transistor. The transistor is a top-gate transistor.

[0057] The passivation layer 900 is disposed on the interlayer dielectric portion 600 , the source electrode 700 , and the drain electrode 800 .

[0058] It should be noted that in order to more clearly know the position between the gate 500 and the active part 300, Figure 1 Only some of the film layers are drawn, but it does not mean that there are no other film layers.

[0059] In another embodiment, the transistor may be a bottom-gate transistor.

[0060] It should be noted that other structures in the thin film transistor 10 , such as the buffer layer, can be removed as needed.

[0061] See also Figure 3 It should be noted that the difference between the second structure and the first structure is:

[0062] The source 700 and the drain 800 are arranged in the same layer and spaced apart on the side of the buffer layer 200 away from the substrate 100. The active part 300 is arranged on the side of the buffer layer 200 away from the substrate 100, the side of the source 700 away from the substrate 100, and the side of the drain 800 away from the substrate 100. The interlayer dielectric part 600 is removed. The passivation layer 900 is directly arranged on the side of the active part 300 away from the substrate 100, the side of the gate insulating part 400 away from the substrate 100, and the side of the gate 500 away from the substrate 100. The rest is the same as the first structure and will not be repeated here.

[0063] The present application also provides a method for preparing a thin film transistor, which is used to prepare the thin film transistor provided in the present application, comprising:

[0064] B11: The substrate includes a first region, a second region and a third region which are connected and in the same layer, the first region and the third region are located on both sides of the second region, and a patterned active layer is formed on the substrate.

[0065] B12: forming a gate insulating layer on a side of the patterned active layer away from the substrate.

[0066] B13: forming a gate layer on a side of the gate insulating layer away from the patterned active layer.

[0067] B14: A photoresist layer is formed on a side of the gate layer away from the gate insulating layer, the photoresist layer includes a first photoresist portion, a second photoresist portion and a third photoresist portion which are connected and arranged in the same layer, the first photoresist portion is arranged on the gate layer located on the first area, the second photoresist portion is arranged on the gate layer located on the second area, and the third photoresist portion is arranged on the gate layer located on the third area.

[0068] B15: Remove the third photoresist portion.

[0069] B16: Using the first photoresist portion and the second photoresist portion as shields, a first etching process is performed on the gate layer to remove the gate layer located on the third region and a portion of the gate layer located on the second region.

[0070] B17. Remove the first photoresist portion.

[0071] B18. Using the second photoresist portion as a shield, perform a second etching process on the gate layer on the first area and part of the gate layer on the second area to form a gate, and the gate is located on the second area; wherein the edge of the gate's orthographic projection on the substrate is located within the orthographic projection of the second photoresist portion on the substrate, and the distance between the edge of the orthographic projection of the first end on the substrate and the side of the second photoresist portion close to the first area is smaller than the distance between the edge of the orthographic projection of the second end on the substrate and the side of the second photoresist portion close to the third area.

[0072] B19: Patterning the gate insulating layer to form a gate insulating portion.

[0073] B20: Conducting the patterned active layer, the patterned active layer forms an active portion, the semiconductor portion is located in the second region, the first conductor portion is located in the first region, and the second conductor portion is located in the third region.

[0074] B21: removing the second photoresist portion.

[0075] In the present application, the other end of the gate is formed by two etchings, and one end of the gate is formed by one etching, so that the etching amount of the end of the gate close to the second conductor part during the etching process is greater than the etching amount of the end of the gate close to the first semiconductor part, so that the distance h from the edge of the orthogonal projection of the first end on the substrate 100 to the edge of the orthogonal projection of the first conductor part on the substrate 100 is smaller than the distance w from the edge of the orthogonal projection of the second end on the substrate 100 to the edge of the orthogonal projection of the second conductor part on the substrate 100, that is, the distance from the edge of the orthogonal projection of the gate on the substrate 100 to the edge of the orthogonal projection of the source on the substrate 100 is greater than the distance from the edge of the orthogonal projection of the gate on the substrate 100 to the edge of the orthogonal projection of the source on the substrate 100, so that a high-resistance region is formed in the semiconductor part near the drain end, that is, the second part is a high-resistance region, so as to avoid the problem that the drain current will increase rapidly with the drain voltage due to the multiplication of carriers near the drain under the drain voltage, that is, the warping effect is reduced, thereby improving the saturation characteristics of the transistor, thereby improving the performance of the thin film transistor.

[0076] The following is a detailed description:

[0077] See also Figure 4 The present application also provides a method for preparing the thin film transistor 10 provided in the present application, comprising:

[0078] The substrate 100 includes a first region 101 , a second region 102 and a third region 103 which are in the same layer and connected. The first region 101 and the third region 103 are located on both sides of the second region 102 .

[0079] Please continue reading Figure 1 In one embodiment, before step B11, the method further includes:

[0080] The buffer layer 200 is formed on the substrate 100 .

[0081] B11: The substrate includes a first region, a second region and a third region which are connected and in the same layer, the first region and the third region are located on both sides of the second region, and a patterned active layer is formed on the substrate.

[0082] See also Figure 5 Specifically, a patterned active layer 20 is formed on the buffer layer 200 .

[0083] B12: forming a gate insulating layer on a side of the patterned active layer away from the substrate.

[0084] B13: forming a gate layer on a side of the gate insulating layer away from the patterned active layer.

[0085] B14: A photoresist layer is formed on a side of the gate layer away from the gate insulating layer, the photoresist layer includes a first photoresist portion, a second photoresist portion and a third photoresist portion which are connected and arranged in the same layer, the first photoresist portion is arranged on the gate layer located on the first area, the second photoresist portion is arranged on the gate layer located on the second area, and the third photoresist portion is arranged on the gate layer located on the third area.

[0086] See also Figure 6 Specifically, a photoresist layer is formed on the gate layer 40. The photoresist layer 50 includes a first photoresist portion 51, a second photoresist portion 52 and a third photoresist portion connected to each other. The first photoresist portion 51 is disposed on the gate layer 40 located on the first region 101. The second photoresist portion 52 is disposed on the gate layer 40 located on the second region 102. The third photoresist portion is disposed on the gate layer located on the third region.

[0087] B15: Remove the third photoresist portion.

[0088] The photoresist layer 50 is processed by a half mask process to remove the third photoresist portion.

[0089] B16: Using the first photoresist portion and the second photoresist portion as shields, a first etching process is performed on the gate layer to remove the gate layer located on the third region and a portion of the gate layer located on the second region.

[0090] Specifically, after the gate layer 40 is etched for the first time, at this time, the distance between one end of the gate layer 40 close to the third region 103 and one end of the second photoresist portion 52 close to the third region 103 is x.

[0091] B17. Remove the first photoresist portion.

[0092] The photoresist layer 50 is ashed to remove the first photoresist portion 51 .

[0093] B18. Using the second photoresist portion as a shield, perform a second etching process on the gate layer on the first area and part of the gate layer on the second area to form a gate, and the gate is located on the second area; wherein the edge of the gate's orthographic projection on the substrate is located within the orthographic projection of the second photoresist portion on the substrate, and the distance between the edge of the orthographic projection of the first end on the substrate and the side of the second photoresist portion close to the first area is smaller than the distance between the edge of the orthographic projection of the second end on the substrate and the side of the second photoresist portion close to the third area.

[0094] See also Figure 7 Specifically, then, with the second photoresist portion 52 as a shield, the gate layer 40 on the first region 101 and a portion of the gate layer 40 located on the second region 102 are subjected to a second etching process to form the gate 500, and the gate 500 is located on the second region 102. The edge of the orthographic projection of the gate 500 on the substrate 100 is located within the orthographic projection of the second photoresist portion 52 on the substrate 100, and the distance h between the edge of the orthographic projection of the first end 501 on the substrate 100 and the side of the second photoresist portion 52 close to the first region 101 is smaller than the distance w between the edge of the orthographic projection of the second end 502 on the substrate 100 and the side of the second photoresist portion 52 close to the third region 103, that is, the distance h between the edge of the orthographic projection of the first end 501 on the substrate 100 and the edge of the orthographic projection of the first conductor portion 320 on the substrate 100 is smaller than the distance w between the edge of the orthographic projection of the second end 502 on the substrate 100 and the edge of the orthographic projection of the second conductor portion 330 on the substrate 100. Wherein, w is greater than x.

[0095] In one embodiment, the value of h may be 0.

[0096] B19: Patterning the gate insulating layer to form a gate insulating portion.

[0097] B20: Conducting the patterned active layer to form an active portion.

[0098] See also Figure 8Specifically, the patterned active layer 20 is subjected to conductorization processing with the second photoresist portion 52 and the gate insulating portion 400 as shielding, and the patterned active layer 20 forms an active portion 300. The active portion 300 includes a semiconductor portion 310, a first conductor portion 320, and a second conductor portion 330 that are in the same layer and connected. The edge of the orthographic projection of the gate insulating portion 400 on the substrate 100 coincides with the edge of the orthographic projection of the semiconductor portion 310 on the substrate 100. The semiconductor portion 310 is located in the second region 102. The first conductor portion 320 is located in the first region 101. The second conductor portion 330 is located in the third region 103. The semiconductor portion 310 includes a first portion 311 and a second portion 312 that are connected. The first portion 311 is located on a side of the second portion 312 away from the second conductor portion 330. The first portion 311 is arranged corresponding to the subsequent gate 500 and the subsequent gate insulating portion 400.

[0099] The second portion 312 is only provided corresponding to the subsequent gate insulating portion 400. When the thin film transistor 10 is working.

[0100] The resistance of the first portion 311 is smaller than the resistance of the second portion 312. d is the width of the semiconductor portion 310.

[0101] In the present application, the edge of the orthographic projection of the gate insulating portion 400 on the substrate 100 is set to coincide with the edge of the orthographic projection of the semiconductor portion 310 on the substrate 100, so that when the active portion 300 is subjected to a plasma doping process, the gate insulating portion 400 can be used as a shield, thereby simplifying the preparation process of the active portion 300 and facilitating the rapid preparation of the thin film transistor 10.

[0102] B21: removing the second photoresist portion.

[0103] See also Fig. 9 Specifically, the second photoresist portion 52 is removed by a stripping or etching process.

[0104] See also Fig.10 In one embodiment, after B18, it further includes:

[0105] An interlayer dielectric layer is formed on the side of the active portion 300 away from the substrate 100, and patterned to form an interlayer dielectric portion 600. The interlayer dielectric portion 600 includes a through hole 601, which penetrates the interlayer dielectric portion 600 to expose the first conductor portion 320 and the second conductor portion 330. Then, a source electrode 700 and a drain electrode 800 are formed on the side of the interlayer dielectric portion 600 away from the substrate 100, and the source electrode 700 and the drain electrode 800 extend into the through hole 601 and are connected to the first conductor portion 320 and the second conductor portion 330 respectively.

[0106] In the present application, the second end 502 of the gate 500 is formed by two etchings, and the one end 501 of the gate 500 is formed by one etching, so that the etching amount of the end of the gate 500 close to the second conductor part 330 during the etching process is greater than the etching amount of the end of the gate 500 close to the first semiconductor part 310, so that the distance h from the edge of the orthogonal projection of the first end 501 on the substrate 100 to the edge of the orthogonal projection of the first conductor part 320 on the substrate 100 is smaller than the distance w from the edge of the orthogonal projection of the second end 502 on the substrate 100 to the edge of the orthogonal projection of the second conductor part 330 on the substrate 100, that is, the orthogonal projection of the gate 500 on the substrate 100 is greater than the distance w from the edge of the orthogonal projection of the second end 502 on the substrate 100 to the edge of the orthogonal projection of the second conductor part 330 on the substrate 100. The distance from the edge of the projection to the edge of the orthographic projection of the source 700 on the substrate 100 is greater than the distance from the edge of the orthographic projection of the gate 500 on the substrate 100 to the edge of the orthographic projection of the source 700 on the substrate 100, thereby forming a high-resistance region in the semiconductor portion 310 near one end of the drain 800, that is, the second portion 312 is a high-resistance region, thereby avoiding carrier multiplication near one end of the semiconductor portion 310 near the drain 800 under the drain 800 voltage, which causes the drain 800 current to increase rapidly with the drain 800 voltage, that is, reducing the warping effect, thereby improving the saturation characteristics of the transistor, and thereby improving the performance of the thin film transistor 10.

[0107] The present application provides a thin film transistor 10 and a method for manufacturing the same, wherein the edge of the orthographic projection of the gate 500 on the substrate 100 is set to be located within the orthographic projection of the gate insulating portion 400 on the substrate 100, and the orthographic projection of the gate 500 on the substrate 100 is set to be located within the orthographic projection of the semiconductor portion 310 on the substrate 100, and the distance h from the edge of the orthographic projection of the first end 501 on the substrate 100 to the edge of the orthographic projection of the first conductor portion 320 on the substrate 100 is set to be smaller than the distance h from the edge of the orthographic projection of the second end 502 on the substrate 100 to the second conductor portion 330. 0 on the substrate 100, so that the semiconductor portion 310 without the gate 500 and close to the drain 800 forms a high-resistance region, that is, a region without gate 500 regulation is formed in the semiconductor portion 310 close to the drain 800, thereby avoiding carrier multiplication near one end of the semiconductor portion 310 close to the drain 800 under the drain 800 voltage, which causes the drain 800 current to increase rapidly with the drain 800 voltage, that is, reducing the warping effect, thereby improving the saturation characteristics of the transistor, and thus improving the performance of the thin film transistor 10.

[0108] The present application also provides an array substrate, which includes a plurality of thin film transistors, at least one of which is the thin film transistor 10 described in any of the above embodiments.

[0109] In some embodiments, each thin film transistor in the array substrate is the thin film transistor 10 described in any of the above embodiments, thereby improving the quality of the array substrate.

[0110] The above is a detailed introduction to a thin film transistor and its preparation method, and an array substrate provided in an embodiment of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A thin film transistor, characterized in that: include: substrate; an active portion, disposed on the substrate, the active portion comprising a semiconductor portion, a first conductor portion, and a second conductor portion that are connected and disposed in the same layer, the first conductor portion and the second conductor portion being disposed on opposite sides of the semiconductor portion; a gate, arranged at one side of the active portion and corresponding to the semiconductor portion, wherein an edge of an orthographic projection of the gate on the substrate is located within an orthographic projection of the semiconductor portion on the substrate, and the gate comprises a first end and a second end that are arranged opposite to each other, wherein the first end is located at a side of the gate close to the first conductor portion, and the second end is located at a side of the gate close to the second conductor portion; A gate insulating portion, disposed between the active portion and the gate and corresponding to the semiconductor portion, wherein an edge of an orthographic projection of the gate on the substrate is located within an orthographic projection of the gate insulating portion on the substrate; as well as A source electrode and a drain electrode, wherein the source electrode and the drain electrode are in the same layer and are spaced apart from each other, the source electrode is connected to the first conductor portion, and the drain electrode is connected to the second conductor portion; wherein the distance from the edge of the orthographic projection of the first end on the substrate to the edge of the orthographic projection of the first conductor portion on the substrate is smaller than the distance from the edge of the orthographic projection of the second end on the substrate to the edge of the orthographic projection of the second conductor portion on the substrate; The semiconductor part includes a first part and a second part that are connected and arranged in the same layer, the first part is located on a side of the second part away from the second conductor part, the first part is arranged corresponding to the gate and the gate insulating part, and the second part is staggered with the gate. When the thin film transistor is working, the resistance of the first part is smaller than the resistance of the second part.

2. The thin film transistor according to claim 1, characterized in that: The distance from the edge of the orthographic projection of the first end on the substrate to the edge of the orthographic projection of the first conductor portion on the substrate is 0, and the distance from the edge of the orthographic projection of the second end on the substrate to the edge of the orthographic projection of the second conductor portion on the substrate is greater than 0.

3. The thin film transistor according to claim 2, characterized in that: A distance from an edge of an orthographic projection of the second end on the substrate to an edge of an orthographic projection of the second conductor portion on the substrate is greater than 1 micrometer.

4. The thin film transistor according to claim 1, characterized in that: An edge of an orthographic projection of the gate insulating portion on the substrate coincides with an edge of an orthographic projection of the semiconductor portion on the substrate.

5. The thin film transistor according to claim 4, characterized in that: The active part is arranged on the substrate, the gate insulating part is arranged on a side of the active part away from the substrate, the gate is arranged on a side of the gate insulating part away from the active part, and the source and the drain are in the same layer and are arranged at intervals on a side of the active part away from the substrate.

6. The thin film transistor according to claim 4, characterized in that: The source and the drain are arranged on the substrate, the active part is arranged on the substrate, on a side of the source away from the substrate, and on a side of the drain away from the substrate, the gate insulating part is arranged on a side of the active part away from the substrate, and the gate is arranged on a side of the gate insulating part away from the active part.

7. An array substrate, characterized in that: It comprises a plurality of thin film transistors, at least one of the thin film transistors is a thin film transistor as claimed in any one of claims 1 to 6.

8. A method for preparing a thin film transistor as claimed in claim 1, characterized in that: The substrate includes a first region, a second region and a third region which are connected to each other, wherein the first region and the third region are respectively located on both sides of the second region, and the method for preparing the thin film transistor includes: forming a patterned active layer on the substrate; forming a gate insulating layer on a side of the patterned active layer away from the substrate; forming a gate layer on a side of the gate insulating layer away from the patterned active layer; A photoresist layer is formed on a side of the gate layer away from the gate insulating layer, the photoresist layer comprising a first photoresist portion, a second photoresist portion and a third photoresist portion which are connected and arranged in the same layer, the first photoresist portion is arranged on the gate layer located on the first region, the second photoresist portion is arranged on the gate layer located on the second region, and the third photoresist portion is arranged on the gate layer located on the third region; removing the third light blocking portion; Using the first photoresist portion and the second photoresist portion as shields, performing a first etching process on the gate layer to remove the gate layer located on the third region and a portion of the gate layer located on the second region; removing the first light blocking portion; Using the second photoresist portion as a shield, a second etching process is performed on the gate layer on the first area and a portion of the gate layer located on the second area to form a gate, and the gate is located on the second area; wherein the edge of the orthographic projection of the gate on the substrate is located within the orthographic projection of the second photoresist portion on the substrate, and the distance between the edge of the orthographic projection of the first end on the substrate and the side of the second photoresist portion close to the first area is smaller than the distance between the edge of the orthographic projection of the second end on the substrate and the side of the second photoresist portion close to the third area; Performing patterning on the gate insulating layer, wherein the gate insulating layer forms a gate insulating portion; The patterned active layer is subjected to conductor processing by using the second photoresistance part and the gate insulating part as shielding, and the patterned active layer forms an active part, wherein the active part includes a semiconductor part, a first conductor part, and a second conductor part which are in the same layer and connected, the edge of the orthographic projection of the gate insulating part on the substrate coincides with the edge of the orthographic projection of the semiconductor part on the substrate, the semiconductor part is located in the second region, the first conductor part is located in the first region, and the second conductor part is located in the third region, the semiconductor part includes a first part and a second part which are connected, the first part is located on a side of the second part away from the second conductor part, and the first part is respectively arranged corresponding to the gate and the gate insulating part; when the thin film transistor is working, the resistance of the first part is less than the resistance of the second part; and The second photoresist portion is removed.

9. The method for preparing a thin film transistor according to claim 8, characterized in that: One end of the gate layer is etched once to form a first end of the gate, so that a distance from an edge of an orthographic projection of the first end on the substrate to an edge of an orthographic projection of the first conductor portion on the substrate is 0, and the other end of the gate layer is etched twice to form a second end of the gate, so that a distance from an edge of an orthographic projection of the second end on the substrate to an edge of an orthographic projection of the second conductor portion on the substrate is greater than 0.

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