Array microchip preparation method and chip

Abstract

The present invention relates to the field of chip preparation and discloses a method for preparing an array microchip and the chip. This method can address the problem of epitaxial layer damage during sapphire substrate stripping. This method effectively addresses the issue of oversized chips through the design of first and second through-holes. By segmenting the chips, stress is alleviated during the stripping of large-area chips. Furthermore, the first and second through-holes shorten the chemical entry path during chemical wet stripping, enabling simultaneous and uniform stripping of the chips, ultimately improving the yield of the array microchip.

Description

Technical Field

[0001] The present invention relates to the field of chip preparation and provides a method for preparing an array micro chip and a chip. Background Art

[0002] Current micro array chips or AR display chips generally use laser stripping sapphire technology to realize modular GaN materials, and then use semiconductor graphic etching technology to achieve pixel size isolation and segmentation to achieve pixel miniaturization of micro display products. Due to laser damage to GaN, the chip yield and reliability are greatly unstable.

[0003] However, a new sapphire stripping technology has emerged in the industry - chemical wet stripping technology. Because this technology does not damage the GaN material, it can achieve high yield and high reliability of the chip.

[0004] However, when the chip size reaches a certain level, wet stripping has the following drawbacks: 1. Large chips generate significant stress when they are released from the sapphire, making subsequent processing difficult for large modules. 2. Due to their large size, chemical stripping can cause uneven stripping between the chip edges and the interior. This leads to uneven stress release in different areas of the chip during the stripping process, causing cracking of large chips and ultimately low chip yield. Summary of the Invention

[0005] The present invention provides a method for preparing an array microchip and a chip, so as to solve the problem of uneven stress release in different areas of the chip during the chemical stripping process, which leads to cracking of large-sized chips, and improve the chip yield.

[0006] According to a first aspect of the present invention, there is provided a method for preparing an array microchip, comprising:

[0007] S1: Providing a DPSS substrate, the DPSS substrate comprising a growth base and a patterned mask layer, and performing epitaxial growth on the patterned mask layer of the DPSS substrate to form an epitaxial layer; the epitaxial layer comprises a transition layer, an N-type epitaxial layer, a light-emitting layer, and a P-type epitaxial layer sequentially formed on the DPSS substrate from bottom to top;

[0008] S2: etching the epitaxial layer to form a first through hole on the epitaxial layer that penetrates the transition layer, the P-type epitaxial layer, the light-emitting layer, and the N-type epitaxial layer;

[0009] S3: covering the first through hole and the epitaxial layer with a first conductive layer; and forming a first insulating layer on the first conductive layer;

[0010] S4: etching the first insulating layer to form a second through hole penetrating the first insulating layer; wherein positions of the first through hole and the second through hole are staggered;

[0011] S5: depositing a second conductive layer, the second conductive layer filling the second through hole and covering the first insulating layer; etching the second conductive layer in the second through hole to remove the second conductive layer in the second through hole, and continuing etching until the second through hole penetrates the first conductive layer and stays on the epitaxial layer;

[0012] S6: depositing a third conductive layer, wherein the third conductive layer fills the second through hole and covers the second conductive layer;

[0013] S7: bonding the third conductive layer to a transfer substrate;

[0014] S8: peeling off the DPSS substrate;

[0015] S9: thinning the N-type epitaxial layer and filling the corresponding first through holes with insulating material;

[0016] S10: preparing a pixel point in an area of the epitaxial layer not filled with the insulating material, wherein the position of the pixel point is consistent with the position of the second through hole;

[0017] S11: removing the epitaxial layer not filled with the insulating material and not the pixel points, and filling the area where the epitaxial layer is removed with an insulating reflective material;

[0018] S12: forming a first N electrode on the pixel and forming a first P electrode around the insulating reflective structure;

[0019] S13: Arranging a second N electrode corresponding to the first N electrode and a second P electrode corresponding to the first P electrode on a CMOS substrate, and bonding the first N electrode to the second N electrode and the first P electrode to the second P electrode to form the microchip.

[0020] Optionally, the material of the epitaxial layer is gallium nitride.

[0021] Optionally, the thickness of the epitaxial layer ranges from 4 microns to 15 microns.

[0022] Optionally, the material of the first insulating layer is: SiN or SiO2.

[0023] Optionally, the thickness of the first insulating layer is in the range of 500 nanometers to 1 micrometer.

[0024] Optionally, the transfer substrate is a transparent substrate.

[0025] Optionally, in step S7, it specifically includes: applying adhesive on the transparent substrate to adhere the third conductive layer to the transparent substrate.

[0026] Optionally, the adhesive is a transparent adhesive.

[0027] Optionally, in step S9 , the thinning process includes: removing the patterned mask layer on the DPSS substrate and the epitaxial layer on the mask layer by polishing or ICP thinning.

[0028] Optionally, the first conductive layer and the third conductive layer are transparent conductive layers, and the first conductive layer is a transparent conductive film; and the second conductive layer is a metal conductive layer.

[0029] Optionally, the thickness of the first conductive layer and the third conductive layer ranges from 100 nanometers to 500 nanometers.

[0030] Optionally, the material of the transparent conductive layer is: a metal film material, an oxide film material, or a polymer film material.

[0031] Optionally, the material of the metal conductive layer is: metal element material, alloy material or composite metal material.

[0032] Optionally, the reflectivity of the insulating reflective material is greater than fifty percent.

[0033] Optionally, in step S13 , the bonding is achieved by at least one of the following methods: high temperature bonding, high pressure bonding, and vacuum bonding.

[0034] According to the second aspect of the present invention, an array micro chip is further provided. The array micro chip is prepared according to the method for preparing the array micro chip according to the first aspect of the present invention.

[0035] The array microchip fabrication method provided by the present invention etches staggered through-holes in the epitaxial layer and the first insulating layer, effectively solving the problem of large-sized chips generating significant stress when they are released from the sapphire barrier, which makes subsequent processing of large-sized modules difficult. It also solves the problem of uneven peeling due to chemical stripping affecting the chip edges and interior, which can lead to uneven stress release in different chip regions during the peeling process and cause chip breakage. This improves the yield of array microchips. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0037] Figure 1 1 is a schematic flow chart of a method for preparing an array microchip provided by an embodiment of the present invention;

[0038] Figure 2 This is a schematic diagram of the structure of devices at different process stages manufactured according to a method for preparing an array microchip provided by an embodiment of the present invention. Figure 1 ;

[0039] Figure 3 This is a schematic diagram of the structure of devices at different process stages manufactured according to a method for preparing an array microchip provided by an embodiment of the present invention. Figure 2 ;

[0040] Figure 4 This is a schematic diagram of the structure of devices at different process stages manufactured according to a method for preparing an array microchip provided by an embodiment of the present invention. Figure 3 ;

[0041] Figure 5 This is a schematic diagram of the structure of devices at different process stages manufactured according to a method for preparing an array microchip provided by an embodiment of the present invention. Figure 4 ;

[0042] Figure 6 This is a schematic diagram of the structure of devices at different process stages manufactured according to a method for preparing an array microchip provided by an embodiment of the present invention. Figure 5 ;

[0043] Figure 7 This is a schematic diagram of the structure of devices at different process stages manufactured according to a method for preparing an array microchip provided by an embodiment of the present invention. Figure 6 ;

[0044] Figure 8 This is a schematic diagram of the structure of devices at different process stages manufactured according to a method for preparing an array microchip provided by an embodiment of the present invention. Figure 7 ;

[0045] Figure 9 This is a schematic diagram of the structure of devices at different process stages manufactured according to a method for preparing an array microchip provided by an embodiment of the present invention. Figure 8 ;

[0046] Figure 10 This is a schematic diagram of the structure of devices at different process stages manufactured according to a method for preparing an array microchip provided by an embodiment of the present invention. Figure 9 ;

[0047] Figure 11 This is a schematic diagram of the structure of devices at different process stages manufactured according to a method for preparing an array microchip provided by an embodiment of the present invention. Figure 10 ;

[0048] Description of the accompanying drawings:

[0049] 100-DPSS substrate;

[0050] 101-production substrate;

[0051] 102-patterned mask layer;

[0052] 200-epitaxial layer;

[0053] 201-transition layer;

[0054] 202-N type epitaxial layer;

[0055] 203-luminescent layer;

[0056] 204-P type epitaxial layer;

[0057] 205-first through hole;

[0058] 206-pixel points;

[0059] 2061 - first N electrode;

[0060] 2062-first P electrode;

[0061] 300-first conductive layer;

[0062] 400-first insulating layer;

[0063] 401- second through hole;

[0064] 500- second conductive layer;

[0065] 600-third conductive layer;

[0066] 700-transfer substrate;

[0067] 800-CMOS substrate;

[0068] 801- second N electrode;

[0069] 802-second P electrode. DETAILED DESCRIPTION

[0070] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0071] The terms "first," "second," "third," "fourth," and the like (if any) in the description and claims of the present invention and in the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. In addition, the terms "including" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions, e.g., a process, method, system, product, or apparatus comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to these processes, methods, products, or apparatus.

[0072] The following specific embodiments are used to describe the technical solution of the present invention in detail. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0073] In the manufacture of semiconductor devices, etching refers to a technique that selectively removes material from a thin film on a substrate (with or without pre-existing structures on its surface) and forms a pattern of that material on the substrate through this removal.

[0074] Please refer to Figure 1 In one embodiment of the present invention, a method for preparing an array microchip is provided, comprising:

[0075] S1: Provide a DPSS substrate 100, the DPSS substrate 100 includes a growth base 101 and a patterned mask layer 102, and perform epitaxial growth on the patterned mask layer 102 of the DPSS substrate 100 to form an epitaxial layer 200; the epitaxial layer 200 includes a transition layer 201, an N-type epitaxial layer 202, a light-emitting layer 203, and a P-type epitaxial layer 204 formed on the DPSS substrate from bottom to top. Figure 2 .

[0076] In one embodiment, the growth substrate 101 may be, for example, a DPSS sapphire substrate. However, it should be appreciated that the present invention is not limited thereto, and other growth substrates are also within the scope of protection of the present invention.

[0077] In an embodiment of the present invention, the epitaxial layer 200 is made of gallium nitride. Specifically, the epitaxial layer is formed using a metal organic chemical vapor deposition (MOCVD) device, and its thickness is measured using a PL photoluminescence device, ensuring that the thickness of the epitaxial layer ranges from 4 microns to 15 microns.

[0078] S2: Etching the epitaxial layer 200 to form a first through hole 205 on the epitaxial layer that passes through the transition layer 201, the P-type epitaxial layer 202, the light-emitting layer 203 and the N-type epitaxial layer 204. Figure 3 shown.

[0079] As a specific embodiment, the first through hole is etched on the epitaxial layer by ICP. Of course, the present invention is not limited to the method of etching through holes, and other methods such as etching the first through hole on the epitaxial layer by photolithography are also within the scope of protection of the present invention.

[0080] It is understood that the shape, size and number of the first through holes are not limited, and as long as holes penetrating the epitaxial layer are formed on the epitaxial layer, they are within the protection scope of the present invention.

[0081] S3 : covering the first through hole 205 and the epitaxial layer 200 with a first conductive layer 300 ; and forming a first insulating layer 400 on the first conductive layer 300 .

[0082] S4: Etching the first insulating layer 400 to form a second through hole 401 penetrating the first insulating layer 400; wherein the positions of the first through hole 205 and the second through hole 401 are staggered. Figure 4 shown.

[0083] The method of etching the second through hole is the same as the method of etching the first through hole, and it is sufficient as long as the positions of the second through hole and the first through hole are staggered with each other.

[0084] S5: Depositing a second conductive layer 500, which fills the second through hole 401 and covers the first insulating layer 400; etching the second conductive layer 500 in the second through hole 401 to remove the second conductive layer in the second through hole, and continuing to etch until the second through hole 401 penetrates the first conductive layer and stays on the epitaxial layer.

[0085] Among them, the preparation of the second conductive layer can also be to first make a pattern with photoresist, the shape of the pattern is the shape of the corresponding position of the second through hole, and the material of the second conductive layer is evaporated on the pattern, that is, the material of the second conductive layer is in the position of the photoresist and the position without photoresist, and the material of the second conductive layer on the photoresist will be removed as the photoresist is removed, and finally the required second conductive layer is obtained.

[0086] The material of the first insulating layer in the embodiment of the present invention is SiN or SiO2 or SiOxN1-x silicon oxynitride, and the thickness of the first insulating layer is in the range of 500 nanometers to 1 micrometer.

[0087] It is understood that the present invention is not limited to the material of the first insulating layer, and the first insulating layer formed of other insulating layer materials such as SiOxN1-x or silicon nitride is also within the protection scope of the present invention.

[0088] S6: depositing a third conductive layer 600, the third conductive layer 600 filling the second through hole 401 and covering the second conductive layer 500. After the device is filled with the third conductive layer, Figure 5 shown.

[0089] S7: Bond the third conductive layer 600 to a transfer substrate 700. The device after transfer is as follows: Figure 6 Wherein, the transfer substrate is a transparent substrate.

[0090] And in step S7, it specifically includes: applying adhesive on the transparent substrate to adhere the third conductive layer to the transparent substrate. The adhesive is transparent adhesive.

[0091] In one embodiment, the transparent substrate is a growth transparent substrate. In another embodiment, the transparent substrate is a bonding transparent substrate, and the chip structure is peeled from the growth transparent substrate and then bonded to the bonding transparent substrate via a bonding layer. The transparent substrate in this embodiment can be a growth transparent substrate, such as a sapphire transparent substrate, or the growth transparent substrate can be peeled and then bonded to another transparent substrate via a bonding layer.

[0092] In the embodiment of the present invention, the first conductive layer and the third conductive layer are transparent conductive layers, and the first conductive layer is a transparent conductive film; the second conductive layer is a metal conductive layer. Furthermore, the thickness of the first conductive layer and the third conductive layer ranges from 100 nanometers to 500 nanometers.

[0093] In an embodiment of the present invention, the material of the transparent conductive layer is a metal film material, an oxide film material, or a polymer film material. The material of the metal conductive layer is a metal element material, an alloy material, or a composite metal material. The present invention is not limited to the materials forming the transparent conductive layer or the metal conductive layer; transparent conductive layers or metal conductive layers formed from other materials are also within the scope of protection of the present invention.

[0094] S8: peeling off the DPSS substrate.

[0095] In the embodiment of the present invention, the design of the first through hole and the second through hole effectively solves the problem of chip size being too large, that is, by dividing the chip, the stress of the large-area chip is relieved when peeling off the DPSS substrate; and the first through hole and the second through hole shorten the entry path of the chemical solution when using the chemical wet stripping technology, so as to achieve the purpose of synchronous and uniform stripping on the chip, and ultimately provide high yield and high reliability of the chip.

[0096] S9: Thinning the N-type epitaxial layer. Figure 7 As shown, the corresponding first through hole is filled with insulating material. Figure 8 shown.

[0097] Among them, the thinning process in the embodiment of the present invention can be achieved by polishing or ICP technology. Specifically, the patterned mask layer on the DPSS substrate and the transition layer on the mask layer are removed by polishing or ICP technology to achieve the thinning process of the N-type epitaxial layer.

[0098] S10 : preparing a pixel point 206 in a region of the epitaxial layer not filled with the insulating material, wherein the position of the pixel point 206 is consistent with the position of the second through hole 401 .

[0099] S11: Remove the epitaxial layer 200 that is not filled with the insulating material and the non-pixel points, and fill the area where the epitaxial layer is removed with an insulating reflective material. Figure 9 shown.

[0100] Wherein, the reflectivity of the insulating reflective material is greater than fifty percent.

[0101] S12: Prepare a first N electrode 2061 on the pixel point 206 and a first P electrode 2062 around the insulating reflective structure. Figure 10 shown.

[0102] S13: Arrange a second N electrode corresponding to the first N electrode and a second P electrode corresponding to the first P electrode on the CMOS substrate 800, and bond the first N electrode to the second N electrode and the first P electrode to the second P electrode to form the microchip.

[0103] The schematic diagram of the array structure composed of pixels is as follows Figure 11 As shown, the N-type epitaxial layer of each pixel is interconnected through the metal conductive layer and the transparent conductive layer, and is exported to the N electrode outside the pixel area to form a common N-electrode structure. The P electrode on the edge pixel is driven separately by the peripheral driving circuit, thereby realizing independent control of each pixel.

[0104] The bonding method includes at least one of the following: high temperature bonding, high pressure bonding, and vacuum bonding. Of course, it is understood that the bonding methods are not limited to the above-listed methods, and other bonding methods are also within the scope of the present invention.

[0105] In the array microchip fabrication method provided in the embodiments of the present invention, staggered through-holes are etched in the epitaxial layer and the first insulating layer. This effectively solves the problem of large-sized chips generating significant stress when they are released from the sapphire, which makes subsequent processing of large-sized modules difficult. It also solves the problem of uneven peeling due to chemical stripping affecting the peeling rate at the chip edges and interior due to excessive size, thereby improving the yield of large-sized chips due to uneven stress release in different chip regions during the peeling process.

[0106] An embodiment of the present invention further provides an array micro chip, which is manufactured according to the above-mentioned array micro chip manufacturing method.

[0107] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or make equivalent replacements for some or all of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for preparing an array microchip, characterized in that: include: S1: Providing a DPSS substrate, the DPSS substrate comprising a growth substrate and a patterned mask layer located on the growth substrate, and performing epitaxial growth on the patterned mask layer of the DPSS substrate to form an epitaxial layer; the epitaxial layer comprises a transition layer, an N-type epitaxial layer, a light-emitting layer, and a P-type epitaxial layer sequentially formed on the DPSS substrate from bottom to top; S2: etching the epitaxial layer to form a first through hole on the epitaxial layer that penetrates the transition layer, the P-type epitaxial layer, the light-emitting layer, and the N-type epitaxial layer; S3: covering the first through hole and the epitaxial layer with a first conductive layer; and forming a first insulating layer on the first conductive layer; S4: etching the first insulating layer to form a second through hole penetrating the first insulating layer; wherein positions of the first through hole and the second through hole are staggered; S5: depositing a second conductive layer, the second conductive layer filling the second through hole and covering the first insulating layer; etching the second conductive layer in the second through hole to remove the second conductive layer in the second through hole, and continuing etching until the second through hole penetrates the first conductive layer and stays on the epitaxial layer; S6: depositing a third conductive layer, wherein the third conductive layer fills the second through hole and covers the second conductive layer; S7: bonding the third conductive layer to a transfer substrate; S8: peeling off the DPSS substrate; S9: thinning the N-type epitaxial layer and filling the corresponding first through holes with insulating material; S10: preparing a pixel point in a region of the epitaxial layer not filled with the insulating material, wherein the position of the pixel point is consistent with the position of the second through hole; S11: removing the epitaxial layer not filled with the insulating material and not the pixel points, and filling the area where the epitaxial layer is removed with an insulating reflective material; S12: forming a first N electrode on the pixel and forming a first P electrode around the insulating reflective material; S13: Bonding the first N electrode and the first P electrode to a second N electrode and a second P electrode on a CMOS substrate respectively to form the array microchip.

2. The method for preparing an array microchip according to claim 1, wherein: The material of the epitaxial layer is gallium nitride.

3. The method for preparing an array microchip according to claim 2, wherein: The thickness of the epitaxial layer ranges from 4 microns to 15 microns.

4. The method for preparing an array microchip according to claim 1, wherein: The material of the first insulating layer is SiN or SiO2.

5. The method for preparing an array microchip according to claim 4, wherein: The thickness of the first insulating layer ranges from 500 nanometers to 1 micrometer.

6. The method for preparing an array microchip according to claim 1, wherein: The transfer substrate is a transparent substrate.

7. The method for preparing an array microchip according to claim 6, wherein: In step S7, it specifically includes: applying adhesive on the transparent substrate to adhere the third conductive layer to the transparent substrate.

8. The method for preparing an array microchip according to claim 7, wherein: The adhesive is a transparent adhesive.

9. The method for preparing an array microchip according to claim 1, wherein: In step S9 , the thinning process includes removing the patterned mask layer on the DPSS substrate and the transition layer on the mask layer by polishing or ICP thinning.

10. The method for preparing an array microchip according to claim 1, wherein: The first conductive layer and the third conductive layer are transparent conductive layers, and the first conductive layer is a transparent conductive film; the second conductive layer is a metal conductive layer.

11. The method for preparing an array microchip according to claim 10, wherein: The thickness of the first conductive layer and the third conductive layer ranges from 100 nanometers to 500 nanometers.

12. The method for preparing an array microchip according to claim 10, wherein: The material of the transparent conductive layer is: metal film material, oxide film material or polymer film material.

13. The method for preparing an array microchip according to claim 10, wherein: The material of the metal conductive layer is: metal element material, alloy material or composite metal material.

14. The method for preparing an array microchip according to claim 1, wherein: The reflectivity of the insulating reflective material is greater than fifty percent.

15. The method for preparing an array microchip according to claim 1, wherein: In step S13 , the bonding is achieved by at least one of the following methods: high temperature bonding, high pressure bonding, and vacuum bonding.

16. An array micro chip, characterized in that: The array microchip is prepared according to any one of claims 1 to 15.

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