A PWM output lockout protection circuit, a direct-current brushless motor and a control method

Abstract

The application discloses a PWM output lockout protection circuit, a direct-current brushless motor and a control method, and relates to the technical field of motor control. The PWM output lockout protection circuit comprises a microprocessor MCU, a buffer chip U1, a flip-flop U2 and a fault detection unit. The PWM signals output by the microprocessor MCU are output through the buffer chip U1. The signals output by the fault detection unit are input to the microprocessor MCU and the buffer chip U1 through the flip-flop U2. When the fault detection unit detects a fault, the fault signal output by the fault detection unit is input to the flip-flop U2. The flip-flop U2 outputs a first lockout signal to the buffer chip U1 to close the output of the PWM signal in advance. At the same time, the flip-flop U2 outputs a second lockout signal to the microprocessor MCU to stop the output of the PWM signal. When the fault is removed, the microprocessor MCU outputs a rising edge signal to the flip-flop U2 to control the flip-flop U2 to remove the lockout signal output, so that the buffer chip U1 normally outputs. The two-way output simultaneously operates, which greatly increases the reliability of the circuit, provides comprehensive protection, and enables the circuit to respond in time.

Description

Technical fields:

[0001] This invention relates to a PWM output lockout protection circuit, a brushless DC motor, and a control method. Background technology:

[0002] The motor controller uses a drive circuit to control the switching transistors, converting DC power into AC power to control the motor. Therefore, the reliability of the drive circuit is crucial for the normal operation of the entire controller. Any fault on the inverter side could cause a serious accident to the entire controller. Therefore, it is necessary to monitor the operating status of the drive circuit in real time so that the controller drive circuit can quickly shut down the switching transistors in the event of a fault, thus protecting the entire machine.

[0003] like Figure 1 As shown, existing PWM output protection technologies for motor controllers can effectively prevent DC bus short circuits to ground caused by direct connection between upper and lower bridges through interlocking drive circuits of the same bridge arm, and achieve short circuit and overcurrent protection by detecting current through external circuits, but cannot achieve over- and under-voltage protection at the controller end.

[0004] like Figure 2 As shown, there is also a self-locking protection circuit designed with multiple logic gates and latches, connected to the detection feedback circuit and the PWM buffer circuit. When a fault is detected, the fault signal is output to the protection circuit for interlocking, and the output of the control signal is turned off. After the fault is cleared, the controller unlocks the circuit and the control signal is output normally. However, the overall structure of this scheme is relatively complex and the response time to system faults is too long.

[0005] In general, current common drive protection circuits suffer from problems such as incomplete protection, untimely circuit response, complex hardware design, and high cost. Summary of the Invention:

[0006] The purpose of this invention is to provide a PWM output lockout protection circuit, a brushless DC motor, and a control method that offer comprehensive protection, timely circuit response, simple hardware design, and low cost.

[0007] The objective of this invention is achieved through the following technical solution.

[0008] The purpose of this invention is to provide a PWM output latch-up protection circuit, including a microprocessor MCU, a buffer chip U1, a trigger U2, and a fault detection unit. Several PWM signals output by the microprocessor MCU are output through the buffer chip U1. The signal output by the fault detection unit is input to the microprocessor MCU and the buffer chip U1 respectively through the trigger U2. When the fault detection unit detects a fault, the output fault signal is input to the trigger U2. The trigger U2 outputs a first latch-up signal to the buffer chip U1 to shut down the output of the PWM signal in advance. At the same time, the trigger U2 outputs a second latch-up signal to the microprocessor MCU to stop the output of the PWM signal. When the fault is cleared, the microprocessor MCU outputs a rising edge signal to the trigger U2 to control the trigger U2 to release the latch-up signal output, so that the buffer chip U1 can output normally.

[0009] Preferably, the fault detection unit includes multiple parallel fault signal acquisition terminals, each fault signal acquisition terminal is connected to the negative terminal of a diode, and the positive terminals of all diodes are connected in parallel to form the output terminal of the fault detection unit. The output terminal of the fault detection unit is connected to pin 7 of the trigger U2.

[0010] Preferably, pin 3 of the trigger U2 is used to output a second latching signal. Pin 3 of the trigger U2 is connected to the input terminal of the microprocessor MCU. Pin 3 of the trigger U2 is grounded through capacitor C17. Resistor R13 is connected in parallel across the two ends of capacitor C17. Pin 3 of the trigger U2 is connected to the second DC source VCC2 through resistor R11.

[0011] Preferably, pin 5 of the trigger U2 is used to output a first latching signal, pin 5 of the trigger U2 is connected to the enable terminal of the buffer chip U1, a resistor R7 is connected between pin 5 of the trigger U2 and the enable terminal of the buffer chip U1, and pin 5 of the trigger U2 is connected to the third DC source VCC3 through a resistor R8.

[0012] Preferably, one output terminal of the microprocessor MCU is connected to pin 1 of the trigger U2, and a resistor R12 is connected between the output terminal of the microprocessor MCU and pin 1 of the trigger U2. Pin 1 of the trigger U2 is connected to the second DC source VCC2 through a resistor R10, and pin 1 of the trigger U2 is grounded through a capacitor C15. When the fault is cleared, the microprocessor MCU outputs a rising edge signal to pin 1 of the trigger U2 to control the trigger U2 to release the latch, so that the buffer chip U1 can output normally.

[0013] Preferably, the multiple PWM signals output by the buffer chip U1 enter the inverter circuit through multiple drive circuits. The inverter circuit includes multiple bridge arms, each bridge arm consisting of an upper bridge arm switch Q1 and a lower bridge arm switch Q2. Each drive circuit includes an upper bridge arm drive circuit and a lower bridge arm drive circuit. The upper and lower bridge arm drive circuits share a non-isolated power supply VCC. The upper and lower bridge arm drive circuits each use an optocoupler isolation circuit. The first input signal PWM1 and the second input signal PWM2 are respectively connected to the first input terminal A and the second input terminal B of the upper bridge arm drive circuit, and the upper bridge arm drive circuit outputs the upper transistor drive signal HU. The first input signal PWM1 and the second input signal PWM2 are respectively connected to the second input terminal B and the first input terminal A of the lower bridge arm drive circuit, and the lower bridge arm drive circuit outputs the lower transistor drive signal HL. The first input signal PWM1 and the second input signal PWM2 are interlocked to the upper and lower bridge arm drive circuits, respectively, so that the upper transistor drive signal HU and the lower transistor drive signal HL do not output high-level signals at the same time.

[0014] The second objective of this invention is to provide a brushless DC motor, comprising a motor unit and a motor controller, wherein the motor unit is controlled by the motor controller, and the motor controller integrates the PWM output lockout protection circuit as described above.

[0015] A third objective of this invention is to provide a control method for a PWM output latch-up protection circuit, employing the aforementioned PWM output latch-up protection circuit. The control method includes the following steps:

[0016] Step 1: Use the fault detection unit to detect various faults in the circuit. These faults include overcurrent, overvoltage, undervoltage, overheating, and phase loss. When a fault occurs in the circuit, the fault detection unit transmits a fault signal to the trigger U2.

[0017] Step 2: When the trigger U2 receives a fault signal from the fault detection unit, the trigger U2 outputs the first latch signal to the buffer chip U1 to turn off the output of the PWM signal in advance, and at the same time outputs the second latch signal to the microprocessor MCU to stop the output of the PWM signal.

[0018] Step 3: After the fault is cleared, the microprocessor MCU outputs a rising edge signal to the flip-flop U2 to control the flip-flop U2 to release the latch signal output, so that the buffer chip U1 can output normally.

[0019] Compared with the prior art, the present invention has the following advantages:

[0020] 1) The PWM output latch-up protection circuit provided by this invention outputs a first latch-up signal to the buffer chip U1 through the trigger U2 to shut down the output of the PWM signal in advance, and simultaneously outputs a second latch-up signal to the microprocessor MCU to stop the output of the PWM signal. When the circuit hardware fails, the output of the buffer chip U1 to the PWM signal can be shut down in advance before the microprocessor MCU responds, and then the output of the microprocessor MCU to the PWM signal can be stopped. This achieves dual protection at the source and in the middle. The simultaneous action of the two outputs greatly increases the reliability of the circuit, provides comprehensive protection, and the circuit responds in a timely manner. In addition, the components are common, highly substitutable, and easy to purchase, making the circuit design simple and low-cost.

[0021] 2) Other advantages of the present invention are described in detail in the Embodiments section. Attached image description:

[0022] Figure 1 This is a topology for the interlocking drive circuit of the upper and lower bridge arms provided for existing technology;

[0023] Figure 2 This is a self-locking drive circuit topology provided for existing technology;

[0024] Figure 3 This is a block diagram of the PWM output latch-up protection circuit provided in Embodiment 1 of the present invention;

[0025] Figure 4 This is a schematic diagram of the circuit structure of the PWM output latch-up protection circuit provided in Embodiment 1 of the present invention;

[0026] Figure 5 This is a block diagram of the driving circuit provided in Embodiment 1 of the present invention;

[0027] Figure 6 This is a schematic diagram of the circuit structure of the driving circuit provided in Embodiment 1 of the present invention;

[0028] Figure 7 This is a schematic diagram of the circuit structure showing the connection relationship between the buffer chip U1, the driving circuit, the inverter circuit, and the microprocessor MCU provided in Embodiment 1 of the present invention.

[0029] Figure 8 This is a schematic diagram of the circuit structure of a brushless DC motor provided in Embodiment 2 of the present invention. Detailed implementation method:

[0030] The present invention will now be described in further detail through specific embodiments and in conjunction with the accompanying drawings.

[0031] Example 1:

[0032] like Figure 3 and Figure 4As shown, this embodiment provides a PWM output latch-up protection circuit, including a microprocessor (MCU), a buffer chip U1, a trigger U2, and a fault detection unit. Several PWM signals output by the MCU are output through the buffer chip U1. The signal output by the fault detection unit is input to both the MCU and the buffer chip U1 via the trigger U2. When the fault detection unit detects a fault, it outputs a fault signal to the trigger U2. The trigger U2 outputs a first latch-up signal to the buffer chip U1 to prematurely shut down the PWM signal output. Simultaneously, the trigger U2 outputs a second latch-up signal to the MCU to stop the PWM signal output. After the fault is cleared, the MCU outputs a rising edge signal to the trigger U2 to control... Trigger U2 releases the latch signal output, allowing buffer chip U1 to output normally. When a hardware fault occurs in the circuit, the output of buffer chip U1 to the PWM signal can be turned off in advance before the microprocessor MCU responds, and then the output of the microprocessor MCU to the PWM signal can be stopped. This achieves dual protection at the source and in the middle. The simultaneous action of the two outputs greatly increases the reliability of the circuit, providing comprehensive protection and timely circuit response. In addition, the components are common, highly substitutable, and easy to procure, making the circuit design simple and low-cost. Moreover, using buffer chip U1 can improve the driving capability of the microprocessor MCU port and reduce its own power consumption. In this embodiment, the fault detection unit is used for overcurrent detection, overvoltage detection, undervoltage detection, overheat detection, and phase loss detection.

[0033] It should be noted that, Figure 4 R1 to R6 are resistors, C1 to C14 are capacitors, and the flip-flop U2 is a D flip-flop.

[0034] The fault detection unit includes multiple parallel fault signal acquisition terminals, each connected to the negative terminal of a diode. The positive terminals of all diodes are connected in parallel to form the output terminal of the fault detection unit. The output terminal of the fault detection unit is connected to pin 7 of the flip-flop U2. By using diodes to form a logic circuit, multiple fault signals can be integrated into one port for output, which can improve the utilization rate of the device. The output terminal of the fault detection unit is connected to the first DC source VCC1 through resistor R9, and the output terminal of the fault detection unit is grounded through capacitor C16. In this embodiment, pin 7 of the flip-flop U2 is the set terminal of the flip-flop U2.

[0035] Pin 3 of the trigger U2 is used to output the second latching signal. Pin 3 of the trigger U2 is connected to the input terminal of the microprocessor MCU. Pin 3 of the trigger U2 is grounded through capacitor C17. Resistor R13 is connected in parallel across capacitor C17. Pin 3 of the trigger U2 is also connected to the second DC source VCC2 through resistor R11. In this embodiment, pin 3 of the trigger U2 is the inverting output terminal of the trigger U2.

[0036] Pin 5 of the trigger U2 is used to output a first latching signal. Pin 5 of the trigger U2 is connected to the enable terminal of the buffer chip U1. A resistor R7 is connected between pin 5 of the trigger U2 and the enable terminal of the buffer chip U1. Pin 5 of the trigger U2 is connected to the third DC source VCC3 through a resistor R8. In this embodiment, the enable terminal of the buffer chip U1 is formed by the parallel output of pins 1 and 19 of the buffer chip U1. Pin 1 of the buffer chip U1 is the first enable terminal 1OE of the buffer chip U1, and pin 19 of the buffer chip U1 is the second enable terminal 2OE of the buffer chip U1. Pin 5 of the trigger U2 is the non-inverting output terminal of the trigger U2.

[0037] One output terminal of the microprocessor MCU is connected to pin 1 of the trigger U2. A resistor R12 is connected between the output terminal of the microprocessor MCU and pin 1 of the trigger U2. Pin 1 of the trigger U2 is connected to the second DC source VCC2 through resistor R10. Pin 1 of the trigger U2 is grounded through capacitor C15. When the fault is cleared, the microprocessor MCU outputs a rising edge signal to pin 1 of the trigger U2 to control the trigger U2 to release the latch, so that the buffer chip U1 can output normally. In this embodiment, pin 1 of the trigger U2 is the clear terminal of the trigger U2.

[0038] It should be noted that the first DC source VCC1, the second DC source VCC2, and the third DC source VCC3 are all +5V power supplies.

[0039] like Figures 5 to 7As shown, the several PWM signals output by the buffer chip U1 enter the inverter circuit through several drive circuits. The inverter circuit includes several bridge arms, each bridge arm consisting of an upper bridge arm switch Q1 and a lower bridge arm switch Q2. Each drive circuit includes an upper bridge arm drive circuit and a lower bridge arm drive circuit. The upper and lower bridge arm drive circuits share a non-isolated power supply VCC. The upper and lower bridge arm drive circuits each use an optocoupler isolation circuit. The first input signal PWM1 and the second input signal PWM2 are respectively connected to the first input terminal A and the second input terminal Q2 of the upper bridge arm drive circuit. The upper bridge arm drive circuit outputs the upper transistor drive signal HU at the two input terminals B. The first input signal PWM1 and the second input signal PWM2 are connected to the second input terminal B and the first input terminal A of the lower bridge arm drive circuit, respectively. The lower bridge arm drive circuit outputs the lower transistor drive signal HL. The first input signal PWM1 and the second input signal PWM2 are interlocked to the upper bridge arm drive circuit and the lower bridge arm drive circuit, respectively, so that the upper transistor drive signal HU and the lower transistor drive signal HL do not output high-level signals at the same time. The PWM signal input logic interlock design can effectively avoid the upper and lower bridges from shoot-through caused by microprocessor MCU output errors.

[0040] Specifically, the upper bridge arm drive circuit mainly includes an optocoupler chip OC1, and the lower bridge arm drive circuit mainly includes an optocoupler chip OC2. The first input signal PWM1 and the second input signal PWM2 are connected to pins 1 and 3 of the optocoupler chip OC1, respectively; the first input signal PWM1 and the second input signal PWM2 are connected to pins 3 and 1 of the optocoupler chip OC2, respectively, to implement a logic interlock design for the PWM input, which can effectively prevent the upper and lower bridges from passing through due to microprocessor MCU output errors. Both the optocoupler chip OC1 and the optocoupler chip OC2 have 6 pins. Pin 1 of the optocoupler chip OC1 is connected to the first input signal PWM1, pin 1 of the optocoupler chip OC1 is connected to pin 3 of the optocoupler chip OC2, and pin 3 of the optocoupler chip OC1 is connected to pin 1 of the optocoupler chip OC2. The pin connections are as follows: pin 1 of optocoupler chip OC2 is connected to the second input signal PWM2; pin 5 of optocoupler chip OC1 is used as an output signal pin, outputting the upper MOSFET drive signal HU; pin 5 of optocoupler chip OC2 is used as an output signal pin, outputting the lower MOSFET drive signal HL; pin 6 of optocoupler chip OC1 is connected to power supply VCC; pin 4 of optocoupler chip OC1 is grounded; pin 4 of optocoupler chip OC2 is grounded; the upper bridge arm drive circuit also includes capacitors C18, C19, C20, C21, and C22, resistors R14, R15, and R16, and diode D6; the lower bridge arm drive circuit also includes capacitors C23, C24, and C25, resistors R17 and R18.

[0041] The working principle of this PWM output lockout protection circuit is as follows: When the fault detection unit does not detect a fault, it outputs a high level to pin 7 of trigger U2. According to the peripheral circuit design of trigger U2, pin 5 of trigger U2 outputs a low level. At this time, the enable terminal of buffer chip U1 is low. According to the characteristics of buffer chip U1, the PWM signal can be output normally. Once the fault detection unit detects a fault, pin 5 of trigger U2 outputs a high level. At this time, the enable terminal of buffer chip U1 is high, and buffer chip U1 shuts down the output of the PWM signal. At the same time, pin 3 of trigger U2 outputs a low level to the microprocessor MCU. When the microprocessor MCU detects the low level, it shuts down the internal PWM output, thus achieving the protection purpose. When the microprocessor MCU detects that the fault has been cleared, the microprocessor sends a rising edge signal to pin 1 of trigger U2, trigger U2 is released from lockout, and buffer chip U1 outputs the PWM signal normally.

[0042] Example 2:

[0043] like Figure 8 As shown, this embodiment provides a brushless DC motor, including a motor unit M and a motor controller. The motor unit M is controlled by the motor controller. The motor unit includes a stator assembly and a rotor assembly. The rotor assembly is installed inside or outside the stator assembly. The motor controller integrates a PWM output lockout protection circuit, a power supply circuit, and a rotor position measurement circuit as described in Embodiment 1. The power supply circuit supplies power to each part of the circuit. The PWM signal output by the microprocessor MCU of the PWM output lockout protection circuit controls the inverter circuit after passing through the buffer chip U1 and several drive circuits. The inverter circuit controls the on / off of the windings of each phase coil of the stator assembly to realize the start and stop control of the motor unit M. The rotor position measurement circuit is used to transmit the real-time operating parameters of the motor unit M to the microprocessor MCU.

[0044] Example 3:

[0045] This embodiment provides a control method for a PWM output latch-up protection circuit, using the PWM output latch-up protection circuit described in Embodiment 1. The control method includes the following steps:

[0046] Step 1: Use the fault detection unit to detect various faults in the circuit. These faults include overcurrent, overvoltage, undervoltage, overheating, and phase loss. When a fault occurs in the circuit, the fault detection unit transmits a fault signal to the trigger U2.

[0047] Step 2: When the trigger U2 receives a fault signal from the fault detection unit, the trigger U2 outputs the first latch signal to the buffer chip U1 to turn off the output of the PWM signal in advance, and at the same time outputs the second latch signal to the microprocessor MCU to stop the output of the PWM signal.

[0048] Step 3: After the fault is cleared, the microprocessor MCU outputs a rising edge signal to the flip-flop U2 to control the flip-flop U2 to release the latch signal output, so that the buffer chip U1 can output normally.

[0049] The above embodiments are preferred embodiments of the present invention, but the embodiments of the present invention are not limited thereto. Any changes, modifications, substitutions, combinations, or simplifications made without departing from the spirit and principle of the present invention are equivalent substitutions and are included within the protection scope of the present invention.

Claims

1. A PWM output latch-up protection circuit, characterized in that: The system includes a microprocessor (MCU), a buffer chip U1, a trigger U2, and a fault detection unit. Several PWM signals output by the microprocessor (MCU) are output through the buffer chip U1. The signal output by the fault detection unit is input to the microprocessor (MCU) and the buffer chip U1 respectively through the trigger U2. When the fault detection unit detects a fault, it outputs a fault signal to the trigger U2. The trigger U2 outputs a first latching signal to the buffer chip U1 to turn off the output of the PWM signal in advance. At the same time, the trigger U2 outputs a second latching signal to the microprocessor (MCU) to stop the output of the PWM signal. When the fault is cleared, the microprocessor (MCU) outputs a rising edge signal to the trigger U2 to control the trigger U2 to release the latching signal output, so that the buffer chip U1 can output normally. The buffer chip U1 outputs several PWM signals, which enter the inverter circuit through several driving circuits. The inverter circuit includes several bridge arms, each of which is formed by connecting the upper bridge arm switch Q1 and the lower bridge arm switch Q2. Each driving circuit includes an upper bridge arm driving circuit and a lower bridge arm driving circuit. The upper bridge arm driving circuit and the lower bridge arm driving circuit share a non-isolated power supply VCC. The upper bridge arm driving circuit and the lower bridge arm driving circuit each use an optocoupler isolation circuit. The first input signal PWM1 and the second input signal PWM2 are respectively connected to the first input terminal A and the second input terminal B of the upper bridge arm driving circuit. The upper bridge arm driving circuit outputs the upper transistor driving signal HU. The first input signal PWM1 and the second input signal PWM2 are respectively connected to the second input terminal B and the first input terminal A of the lower bridge arm drive circuit. The lower bridge arm drive circuit outputs the lower MOSFET drive signal HL. The first input signal PWM1 and the second input signal PWM2 are interlocked and connected to the upper bridge arm drive circuit and the lower bridge arm drive circuit respectively, so that the upper MOSFET drive signal HU and the lower MOSFET drive signal HL do not output high-level signals at the same time. The fault detection unit includes multiple parallel fault signal acquisition terminals. Each fault signal acquisition terminal is connected to the negative terminal of a diode. The positive terminals of all diodes are connected in parallel to form the output terminal of the fault detection unit. The output terminal of the fault detection unit is connected to pin 7 of the trigger U2.

2. The PWM output latch-up protection circuit according to claim 1, characterized in that: Pin 3 of the trigger U2 is used to output the second latching signal. Pin 3 of the trigger U2 is connected to the input terminal of the microprocessor MCU. Pin 3 of the trigger U2 is grounded through capacitor C17. Resistor R13 is connected in parallel across the two ends of capacitor C17. Pin 3 of the trigger U2 is connected to the second DC source VCC2 through resistor R11.

3. The PWM output latch-up protection circuit according to claim 1, characterized in that: Pin 5 of the trigger U2 is used to output the first latching signal. Pin 5 of the trigger U2 is connected to the enable terminal of the buffer chip U1. A resistor R7 is connected between pin 5 of the trigger U2 and the enable terminal of the buffer chip U1. Pin 5 of the trigger U2 is connected to the third DC source VCC3 through a resistor R8.

4. The PWM output latch-up protection circuit according to claim 1, characterized in that: One output terminal of the microprocessor MCU is connected to pin 1 of the trigger U2. A resistor R12 is connected between the output terminal of the microprocessor MCU and pin 1 of the trigger U2. Pin 1 of the trigger U2 is connected to the second DC source VCC2 through a resistor R10. Pin 1 of the trigger U2 is grounded through a capacitor C15. When the fault is cleared, the microprocessor MCU outputs a rising edge signal to pin 1 of the trigger U2 to control the trigger U2 to release the latch, so that the buffer chip U1 can output normally.

5. A brushless DC motor, comprising a motor unit and a motor controller, wherein the motor unit is controlled by the motor controller, characterized in that: The motor controller integrates the PWM output lockout protection circuit as described in any one of claims 1 to 4.

6. A control method for a PWM output lockout protection circuit, characterized in that: The control method, employing the PWM output latch-up protection circuit as described in any one of claims 1 to 4, includes the following steps: Step 1: Use the fault detection unit to detect various faults in the circuit. These faults include overcurrent, overvoltage, undervoltage, overheating, and phase loss. When a fault occurs in the circuit, the fault detection unit transmits a fault signal to the trigger U2. Step 2: When the trigger U2 receives a fault signal from the fault detection unit, the trigger U2 outputs the first latch signal to the buffer chip U1 to turn off the output of the PWM signal in advance, and at the same time outputs the second latch signal to the microprocessor MCU to stop the output of the PWM signal. Step 3: After the fault is cleared, the microprocessor MCU outputs a rising edge signal to the flip-flop U2 to control the flip-flop U2 to release the latch signal output, so that the buffer chip U1 can output normally.

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