A driving circuit for a gallium nitride power device

Abstract

The application discloses a driving circuit of a gallium nitride power device, which comprises a high-level input end, a low-level input end, a driving output end, a VDD voltage end, a VB voltage end, a Vs end, an input stage driving circuit, an adaptive dead zone circuit, two shift circuits, two output stage driving circuits, a negative voltage detection circuit, a first resistor, a second resistor, a third resistor, a fourth resistor, an eleventh PMOS tube and an eleventh NMOS tube, the two output stage driving circuits comprise a first output stage driving circuit and a second output stage driving circuit, and the two shift circuits comprise a high-level shift circuit and a low-level shift circuit. The driving circuit in the application can not only ensure the normal power supply of the high-voltage side circuit of the gallium nitride power device, but also realize the gate clamping protection function of the gallium nitride power device on the basis of not losing the VS negative bias voltage capability of the driving circuit chip.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, and in particular relates to a driving circuit for a gallium nitride power device. Background Technology

[0002] GaN (Gallium Nitride) power devices offer higher current density, higher operating frequency, and lower switching losses compared to traditional Si (Silicon)-based power devices. These advantages are driving GaN power devices to gradually replace Si-based power devices and become the mainstream choice for high-density power modules in cloud computing, 5G communication, and other devices. However, the driver chip for GaN power devices is currently the main factor limiting their application.

[0003] To fully utilize the high-frequency switching performance of GaN devices, the matching GaN driver chip must possess strong driving capability to quickly turn the GaN devices on and off. Currently, traditional output stage driver circuits use an inverter chain with progressively increasing driving capability and size. When driving high-voltage, high-current devices, this driver stage inevitably experiences a shoot-through process between the power transistors MP and MN in the power output stage. Due to the very high current capability of the output stage, this shoot-through process significantly increases chip losses and may even damage the output stage. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of the prior art and provide a driving circuit for gallium nitride power devices that can ensure the normal power supply of the high-voltage side circuit of gallium nitride power devices.

[0005] The objective of this invention is achieved through the following technical solution: a driving circuit for a gallium nitride power device, comprising a high-level input terminal, a low-level input terminal, a driving output terminal, a VDD voltage terminal, a VB voltage terminal, a Vs terminal, an input stage driving circuit, an adaptive dead-time circuit, two shift circuits, two output stage driving circuits, a negative voltage detection circuit, a first resistor, a second resistor, a third resistor, a fourth resistor, an eleventh PMOS transistor, and an eleventh NMOS transistor; the two output stage driving circuits include a first output stage driving circuit and a second output stage driving circuit; and the two shift circuits include a high-level shift circuit and a low-level shift circuit. The first input terminal of the input stage driver circuit is connected to the high-level input terminal, the second input terminal of the input stage driver circuit is connected to the low-level input terminal, the high-level output terminal of the input stage driver circuit is connected to the high-level input terminal of the adaptive dead-time circuit, and the low-level output terminal of the input stage driver circuit is connected to the low-level input terminal of the adaptive dead-time circuit. The high-level output terminal of the adaptive dead-time circuit is connected to the second input terminal of the high-level shift circuit and the fourth input terminal of the low-level shift circuit; the low-level output terminal of the adaptive dead-time circuit is connected to the first input terminal of the high-level shift circuit and the third input terminal of the low-level shift circuit; the high-level output terminal of the high-level shift circuit is connected to the input terminal of the first output stage driver circuit; and the low-level output terminal of the low-level shift circuit is connected to the input terminal of the second output stage driver circuit. The high-level output terminal of the first output stage driving circuit is connected to the gate of the eleventh PMOS transistor via a first resistor, and the low-level output terminal of the first output stage driving circuit is connected to the gate of the eleventh PMOS transistor via a second resistor; the high-level output terminal of the second output stage driving circuit is connected to the gate of the eleventh NMOS transistor via a third resistor, and the low-level output terminal of the second output stage driving circuit is connected to the gate of the eleventh NMOS transistor via a fourth resistor; the drain of the eleventh PMOS transistor is connected to the power supply voltage, the source of the eleventh PMOS transistor is connected to the drain of the eleventh NMOS transistor, the source of the eleventh NMOS transistor is grounded, and the connection point between the source and drain of the eleventh PMOS transistor is connected to the driving output terminal. The input terminal of the negative pressure detection circuit is connected to the Vs terminal, the Vs terminal is connected to the drive output terminal, the output terminal of the negative pressure detection circuit is connected to the control terminal of the adaptive dead-time circuit, the power supply terminal of the high-level shift circuit and the power supply terminal of the first output stage drive circuit are both connected to the VB voltage terminal, and the power supply terminal of the input stage drive circuit, the power supply terminal of the low-voltage level shift circuit and the power supply terminal of the second output stage drive circuit are all connected to the VDD voltage terminal.

[0006] Furthermore, the driving circuit also includes a clamping protection circuit, the first control terminal of the clamping protection circuit is connected to the VB voltage terminal, the output terminal of the clamping protection circuit is connected to the clamping protection terminal of the high-level shift circuit, the output terminal of the negative voltage detection circuit is connected to the second control terminal of the clamping protection circuit, and the power supply terminal of the clamping protection circuit is connected to the VDD voltage terminal.

[0007] Further, the input stage driving circuit includes a first NOR gate, a first NAND gate, a first NOT gate, a second NOT gate, a third NOT gate, a fourth NOT gate, and a fifth NOT gate; the first input terminal of the first NAND gate serves as the high-level input terminal of the input stage driving circuit, the output terminal of the first NAND gate is connected to the input terminal of the first NOT gate, the output terminal of the first NOT gate is connected to the input terminal of the second NOT gate, the output terminal of the second NOT gate is connected to the input terminal of the third NOT gate, the output terminal of the third NOT gate is connected to the first input terminal of the first NOR gate, and the output terminal of the third NOT gate serves as the high-level output terminal of the input stage driving circuit; the second input terminal of the first NOR gate serves as the low-level input terminal of the input stage driving circuit, the output terminal of the first NOR gate is connected to the input terminal of the fourth NOT gate, the output terminal of the fourth NOT gate is connected to the input terminal of the fifth NOT gate, the output terminal of the fifth NOT gate is connected to the second input terminal of the first NAND gate, and the output terminal of the fifth NOT gate serves as the low-level output terminal of the input stage driving circuit.

[0008] Furthermore, the adaptive dead-time circuit includes a sixth NOT gate, a seventh NOT gate, a second NAND gate, a third NAND gate, a first XOR gate, a second XOR gate, a first dynamic delay unit, and a second dynamic delay unit. The input terminal of the sixth NOT gate serves as the high-level input terminal of the adaptive dead-time circuit. The output terminal of the sixth NOT gate is connected to the first input terminal of the second NAND gate and the first input terminal of the first XOR gate. The input terminal of the first dynamic delay unit is connected to the input terminal of the sixth NOT gate. The output terminal of the first dynamic delay unit is connected to the second input terminal of the first XOR gate. The output terminal of the first XOR gate is connected to the first input terminal of the third NAND gate. The input terminal of the seventh NOT gate serves as the low-level input terminal of the adaptive dead-time circuit. The output terminal of the seventh NOT gate is connected to the second input terminal of the second XOR gate and the second input terminal of the third NAND gate. The input terminal of the second dynamic delay unit is connected to the input terminal of the seventh NOT gate. The output terminal of the second dynamic delay unit is connected to the first input terminal of the second XOR gate. The output terminal of the second XOR gate is connected to the second input terminal of the second NAND gate. The output terminal of the third NAND gate serves as the high-level output terminal of the adaptive dead-time circuit.

[0009] Furthermore, the shift circuit is a double-interlocked level shift circuit.

[0010] Furthermore, the shift circuit includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, a first diode, a second diode, a third XOR gate, a fourth XOR gate, an eighth NOT gate, a ninth NOT gate, a first interlock signal terminal, a second interlock signal terminal, and a feedback terminal; The gate of the first NMOS transistor serves as the first input terminal of the shift circuit, and the source of the first NMOS transistor is grounded. The gate of the second NMOS transistor serves as the second input terminal of the shift circuit, and the source of the second NMOS transistor is grounded. The gate of the third NMOS transistor is connected to the gate of the fourth NMOS transistor, and the gate of the fourth NMOS transistor is connected to the drain of the fourth NMOS transistor. The gate of the fifth NMOS transistor is connected to the gate of the sixth NMOS transistor, and the gate of the fifth NMOS transistor is connected to the drain of the fifth NMOS transistor. The sources of the third, fourth, fifth, sixth, seventh, eighth, ninth, and tenth NMOS transistors are all connected to the feedback terminal. The gates of the seventh, eighth, ninth, and tenth NMOS transistors are all connected to the first interlock signal terminal. The anodes of the first diode and the second diode are both connected to the feedback terminal. The cathode of the first diode is connected to the drain of the first NMOS transistor, and the cathode of the second diode is connected to the drain of the second NMOS transistor. The gate of the first PMOS transistor serves as the third input terminal of the shift circuit, and the gate of the second PMOS transistor serves as the fourth input terminal of the shift circuit. The drain of the first PMOS transistor is connected to the drain of the first NMOS transistor. The gates of the first, third, and fourth PMOS transistors are all connected to the drain of the first PMOS transistor. The drain of the second PMOS transistor is connected to the drain of the second PMOS transistor. The drain of the second PMOS transistor, the gate of the fifth PMOS transistor, and the gate of the sixth PMOS transistor are all connected to the drain of the first NMOS transistor. The gates of the two PMOS transistors are connected; the sources of the first, second, third, fourth, fifth, and sixth PMOS transistors are all connected to the VDD voltage terminal; the drain of the third PMOS transistor is connected to the drain of the third NMOS transistor, the drain of the fourth PMOS transistor is connected to the drain of the fifth NMOS transistor, the drain of the fifth PMOS transistor is connected to the drain of the fourth NMOS transistor, and the drain of the sixth PMOS transistor is connected to the drain of the sixth NMOS transistor. The first input terminal of the third XOR gate is connected to the drain of the sixth PMOS transistor, and the output terminal of the third XOR gate serves as the high-level output terminal of the shift circuit. The first input terminal of the fourth XOR gate is connected to the output terminal of the third XOR gate, and the second input terminal of the fourth XOR gate is connected to the drain of the third NMOS transistor. The output terminal of the fourth XOR gate serves as the low-level output terminal of the shift circuit, and the output terminal of the fourth XOR gate is connected to the second input terminal of the third XOR gate. The sources of the seventh PMOS transistor, the eighth PMOS transistor, the ninth PMOS transistor, and the tenth PMOS transistor... The sources of all MOS transistors are connected to the VB voltage terminal. The gates of the seventh PMOS transistor and the eighth PMOS transistor are both connected to the second interlock signal terminal. The drain of the seventh PMOS transistor is connected to the drain of the seventh NMOS transistor. The drain of the eighth PMOS transistor is connected to the drain of the eighth NMOS transistor. The gate of the ninth PMOS transistor is connected to the output terminal of the fourth XOR gate. The drain of the ninth PMOS transistor is connected to the drain of the ninth NMOS transistor. The gate of the tenth PMOS transistor is connected to the output terminal of the third XOR gate. The drain of the tenth PMOS transistor is connected to the drain of the tenth NMOS transistor. The input of the eighth NOT gate is connected to the drain of the tenth PMOS transistor, the output of the eighth NOT gate is connected to the second input of the fourth XOR gate, the input of the ninth NOT gate is connected to the drain of the ninth NMOS transistor, and the output of the ninth NOT gate is connected to the first input of the third XOR gate.

[0011] Further, the output stage driving circuit includes a twelfth PMOS transistor, a thirteenth PMOS transistor, a fourteenth PMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, and a fourteenth NMOS transistor; the sources of the twelfth, thirteenth, and fourteenth PMOS transistors are all connected to the power supply terminal of the output stage driving circuit, and the sources of the twelfth, thirteenth, and fourteenth NMOS transistors are all grounded; the gate of the twelfth PMOS transistor and the gate of the twelfth NMOS transistor are connected at a first connection point, which serves as the input terminal of the output stage driving circuit, and the drain of the twelfth PMOS transistor... The drain of the 12th NMOS transistor is connected to the second connection point. The gate of the 13th PMOS transistor and the gate of the 13th NMOS transistor are connected to the third connection point, which is connected to the second connection point. The drain of the 13th PMOS transistor and the drain of the 13th NMOS transistor are connected to the fourth connection point. The gate of the 14th PMOS transistor and the gate of the 14th NMOS transistor are connected to the fifth connection point, which is connected to the fourth connection point. The fifth connection point serves as the output terminal of the output stage drive circuit. The source of the 14th PMOS transistor and the drain of the 14th NMOS transistor are connected to the sixth connection point, which is connected to the third connection point.

[0012] Furthermore, the driving circuit of the gallium nitride power device also includes two undervoltage protection circuits, referred to as the first undervoltage protection circuit and the second undervoltage protection circuit, respectively. The input terminal of the first undervoltage protection circuit is connected to the low-level output terminal of the high-level shift circuit, and the output terminal of the first undervoltage protection circuit is connected to the second interlock signal terminal of the high-level shift circuit. The input terminal of the second undervoltage protection circuit is connected to the low-level output terminal of the low-level shift circuit, and the output terminal of the second undervoltage protection circuit is connected to the first interlock signal terminal of the low-level shift circuit.

[0013] Furthermore, the undervoltage protection circuit includes a comparator, a first RS flip-flop, a second RS flip-flop, a current-frequency oscillator, a first frequency divider, a second frequency divider, a first D flip-flop, a second D flip-flop, a second NOR gate, a first XOR gate, a fourth NAND gate, and a first AND gate. The first input terminal of the comparator is connected to the VDD voltage terminal, the second input terminal of the comparator is connected to the low-level output terminal of the shift circuit, and the output terminal of the comparator is connected to the S terminal of the first RS flip-flop, the Reset terminal of the first frequency divider, the Reset terminal of the first D flip-flop, the second input terminal of the second NOR gate, the first input terminal of the first XOR gate, and the first input terminal of the fourth NAND gate, respectively. The output terminal of the first RS flip-flop is connected to the input terminal of the current-frequency oscillator, and the output terminal of the current-frequency oscillator is connected to the CLK terminal of the first frequency divider and the CLK terminal of the second frequency divider, respectively. The output terminal of the first frequency divider is connected to the CLK terminal of the first D flip-flop, the Q(-) terminal of the first D flip-flop is connected to the first input terminal of the second NOR gate, and the output terminal of the second NOR gate is connected to the S terminal of the second RS flip-flop. The output of the second frequency divider is connected to the CLK terminal of the second D flip-flop. The Q(-) terminal of the second D flip-flop is connected to the second input terminal of the first XOR gate. The output terminal of the first XOR gate is connected to the first input terminal of the first AND gate. The second input terminal of the first AND gate is connected to the output terminal of the fourth NAND gate. The second input terminal of the fourth NAND gate is connected to the Reset terminal of the second frequency divider and the Reset terminal of the second D flip-flop. The output terminal of the first AND gate is connected to the R terminal of the first RS flip-flop and the R terminal of the second RS flip-flop. The output terminal of the second RS flip-flop is connected to the second input terminal of the fourth NAND gate. The output terminal of the second RS flip-flop serves as the output terminal of the undervoltage protection circuit.

[0014] The beneficial effects of the present invention are: the driving circuit in the present invention can not only ensure the normal power supply of the high voltage side circuit of the gallium nitride power device, but also realize the gate clamping protection function of the gallium nitride power device without losing the VS negative bias voltage capability of the driving circuit chip. Attached Figure Description

[0015] Figure 1 This is a block diagram illustrating one embodiment of the driving circuit for the gallium nitride power device in this invention. Figure 2 This is a block diagram of one embodiment of the input stage drive circuit in this invention; Figure 3 This is a block diagram of one embodiment of the adaptive dead-time circuit in this invention; Figure 4 This is the functional timing diagram of the adaptive dead-time circuit in this invention; Figure 5 This is a block diagram of one embodiment of the shift circuit in the present invention; Figure 6 This is a functional timing diagram of the shift circuit in this invention; Figure 7This is a block diagram of one embodiment of the output stage drive circuit in this invention; Figure 8 This is a block diagram of one embodiment of the undervoltage protection circuit in this invention. Detailed Implementation

[0016] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0017] See Figures 1-8 This embodiment provides a driving circuit for a gallium nitride power device: like Figure 1 As shown, a driving circuit for a gallium nitride power device includes a high-level input terminal, a low-level input terminal, a driving output terminal, a VDD voltage terminal, a VB voltage terminal, a Vs terminal, an input stage driving circuit, an adaptive dead-time circuit, two shift circuits, two output stage driving circuits, a negative voltage detection circuit, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, an eleventh PMOS transistor MP11 and an eleventh NMOS transistor MN11, the two output stage driving circuits including a first output stage driving circuit and a second output stage driving circuit, and the two shift circuits including a high-level shift circuit and a low-level shift circuit.

[0018] The first input terminal of the input stage driver circuit is connected to the high-level input terminal, the second input terminal of the input stage driver circuit is connected to the low-level input terminal, the high-level output terminal of the input stage driver circuit is connected to the high-level input terminal of the adaptive dead-time circuit, and the low-level output terminal of the input stage driver circuit is connected to the low-level input terminal of the adaptive dead-time circuit.

[0019] The high-level output terminal of the adaptive dead-time circuit is connected to the second input terminal of the high-level shift circuit and the fourth input terminal of the low-level shift circuit. The low-level output terminal of the adaptive dead-time circuit is connected to the first input terminal of the high-level shift circuit and the third input terminal of the low-level shift circuit. The high-level output terminal of the high-level shift circuit is connected to the input terminal of the first output stage driver circuit, and the low-level output terminal of the low-level shift circuit is connected to the input terminal of the second output stage driver circuit.

[0020] The high-level output terminal of the first output stage driving circuit is connected to the gate of the eleventh PMOS transistor MP11 via a first resistor R1, and the low-level output terminal of the first output stage driving circuit is connected to the gate of the eleventh PMOS transistor MP11 via a second resistor R2. The high-level output terminal of the second output stage driving circuit is connected to the gate of the eleventh NMOS transistor MN11 via a third resistor R3, and the low-level output terminal of the second output stage driving circuit is connected to the gate of the eleventh NMOS transistor MN11 via a fourth resistor R4. The drain of the eleventh PMOS transistor MP11 is connected to the power supply voltage, the source of the eleventh PMOS transistor MP11 is connected to the drain of the eleventh NMOS transistor MN11, the source of the eleventh NMOS transistor MN11 is grounded, and the connection point between the source of the eleventh PMOS transistor MP11 and the drain of the eleventh NMOS transistor MN11 is connected to the driving output terminal.

[0021] The input terminal of the negative pressure detection circuit is connected to the Vs terminal, the Vs terminal is connected to the drive output terminal, the output terminal of the negative pressure detection circuit is connected to the control terminal of the adaptive dead-time circuit, the power supply terminal of the high-level shift circuit and the power supply terminal of the first output stage drive circuit are both connected to the VB voltage terminal, and the power supply terminal of the input stage drive circuit, the power supply terminal of the low-voltage level shift circuit and the power supply terminal of the second output stage drive circuit are all connected to the VDD voltage terminal.

[0022] In this embodiment, the input signal is transmitted to the high-level input terminal of the GaN power device driver chip ( Figure 1 HI in the middle) and low level input terminal ( Figure 1 In the LI stage, both the high-voltage and low-voltage channels employ identical transmission logic to achieve strict delay matching. After being shaped by the input stage driver circuit, the signal becomes a standard square wave. This shaped signal then enters the adaptive dead-time generation circuit, which improves the signal-to-noise ratio of the input signal. The adaptive dead-time circuit resolves the contradiction between fixed dead time and reverse conduction loss of GaN power devices, and also addresses the problem in traditional adaptive dead-time technology used in Buck-type switching power converters where level-shifted signals are difficult to transmit to the low-voltage region in high-voltage applications. A negative voltage detection circuit monitors the Vs terminal voltage to determine the direction of adjustment for the internal dead-time delay. The output stage driver circuit uses a two-port output. Different gate resistors (e.g., R1, R2, R3, and R4, with values ​​ranging from 1-100 ohms depending on the situation; too high a value increases losses, while too low a value leads to severe electromagnetic interference noise and overshoot) are externally connected to control the rise / fall speed of the GaN power devices, achieving a trade-off between turn-on losses and electromagnetic interference.

[0023] In one embodiment, the driving circuit further includes a clamping protection circuit, wherein the first control terminal of the clamping protection circuit is connected to the VB voltage terminal, the output terminal of the clamping protection circuit is connected to the clamping protection terminal of the high-level shift circuit, the output terminal of the negative voltage detection circuit is connected to the second control terminal of the clamping protection circuit, and the power supply terminal of the clamping protection circuit is connected to the VDD voltage terminal.

[0024] The clamping protection circuit reduces the buffer stage's response voltage by using a PMOS transistor as a buffer stage. It also employs a dual-level bootstrap power supply circuit to provide two separate power supplies to the high-voltage side, ensuring the chip's negative bias capability. A negative bias detection circuit generates a control signal to control the operation of the dual bootstrap power supply circuit, achieving output voltage clamping. This clamping protection circuit is a negative bias clamping protection circuit. It not only meets the requirements of high-voltage side voltage clamping for GaN high-voltage gate driver chips, protecting subsequent GaN devices, but also improves the chip's negative bias capability, thereby enhancing its stability.

[0025] like Figure 2 As shown, in one embodiment, the input stage driving circuit includes a first NOR gate (NOR1), a first NAND gate (NAND1), a first NOT gate (INV1), a second NOT gate (INV2), a third NOT gate (INV3), a fourth NOT gate (INV4), and a fifth NOT gate (INV5). The first input terminal of the first NAND gate (NAND1) serves as the high-level input terminal of the input stage driving circuit. The output terminal of the first NAND gate (NAND1) is connected to the input terminal of the first NOT gate (INV1). The output terminal of the first NOT gate (INV1) is connected to the input terminal of the second NOT gate (INV2). The output terminal of the second NOT gate (INV2) is connected to the input terminal of the third NOT gate (INV3). The output of NOT gate INV3 is connected to the first input of the first NOR gate NOR1, and the output of the third NOT gate INV3 serves as the high-level output of the input stage driver circuit. The second input of the first NOR gate NOR1 serves as the low-level input of the input stage driver circuit. The output of the first NOR gate NOR1 is connected to the input of the fourth NOT gate INV4, and the output of the fourth NOT gate INV4 is connected to the input of the fifth NOT gate INV5. The output of the fifth NOT gate INV5 is connected to the second input of the first NAND gate NAND1, and the output of the fifth NOT gate INV5 serves as the low-level output of the input stage driver circuit.

[0026] like Figure 3As shown, in one embodiment, the adaptive dead-time circuit includes a sixth NOT gate INV6, a seventh NOT gate INV7, a second NAND gate NAND2, a third NAND gate NAND3, a first XOR gate XOR1, a second XOR gate XOR2, a first dynamic delay unit DELAY1, and a second dynamic delay unit DELAY2. The input terminal of the sixth NOT gate INV6 serves as the high-level input terminal of the adaptive dead-time circuit. The output terminal of the sixth NOT gate INV6 is connected to the first input terminal of the second NAND gate NAND2 and the first input terminal of the first XOR gate XOR1. The input terminal of the first dynamic delay unit DELAY1 is connected to the input terminal of the sixth NOT gate INV6, and the output terminal of the first dynamic delay unit DELAY1 is connected to the second input terminal of the first XOR gate XOR1. The input terminals are connected as follows: the output terminal of the first XOR gate XOR1 is connected to the first input terminal of the third NAND gate NAND3; the input terminal of the seventh NOT gate INV7 serves as the low-level input terminal of the adaptive dead-time circuit; the output terminal of the seventh NOT gate INV7 is connected to the second input terminal of the second XOR gate XOR2 and the second input terminal of the third NAND gate NAND3; the input terminal of the second dynamic delay unit DELAY2 is connected to the input terminal of the seventh NOT gate INV7; the output terminal of the second dynamic delay unit DELAY2 is connected to the first input terminal of the second XOR gate XOR2; the output terminal of the second XOR gate XOR2 is connected to the second input terminal of the second NAND gate NAND2; and the output terminal of the third NAND gate NAND3 serves as the high-level output terminal of the adaptive dead-time circuit.

[0027] like Figure 4As shown, if the input signals of the high-level input terminal (IN_H) and the low-level input terminal (IN_L) of the adaptive dead-time circuit overlap, the adaptive dead-time circuit will force the two signals OUT_H and OUT_L to zero in the overlapping area to ensure the normal output signal. In addition, a certain dead time will be added. To illustrate more clearly, the input signals IN_H and IN_L here are two interleaved square wave signals. The C1 signal is the output signal of IN_H after passing through the dynamic delay unit. The dynamic delay unit only delays the falling edge of the input signal and outputs an inverted signal. Therefore, the falling edge of IN_H is delayed. The output is the A1 signal, which is used to control the opening time of the low-voltage side channel. Similarly, B1 is the output signal of IN_L with the falling edge delayed, which is used to control the opening time of the high-voltage side channel. Finally, the inverted signal A of IN_H, after being output as a NOT signal with B1, turns on the eleventh PMOS transistor MP11, forming the dead time between the turn-off of the eleventh NMOS transistor MN11 and the turn-on of the eleventh PMOS transistor MP11. Meanwhile, the inverted signal B of IN_L, after being output as a NOT signal with A1, turns on the eleventh NMOS transistor MN11, forming the dead time between the turn-off of the eleventh PMOS transistor MP11 and the turn-on of the eleventh NMOS transistor MN11.

[0028] In one embodiment, the shift circuit is a double-interlocked level shift circuit.

[0029] like Figure 5 As shown, in one embodiment, the shift circuit includes a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, a ninth NMOS transistor MN9, a tenth NMOS transistor MN10, a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, a ninth PMOS transistor MP9, and a tenth PMOS transistor MP10, a first diode D1, a second diode D2, a third XOR gate XOR3, a fourth XOR gate XOR4, an eighth NOT gate INV8, a ninth NOT gate INV9, a first interlock signal terminal, a second interlock signal terminal, and a feedback terminal.

[0030] The gate of the first NMOS transistor MN1 serves as the first input terminal of the shift circuit, and the source of the first NMOS transistor MN1 is grounded. The gate of the second NMOS transistor MN2 serves as the second input terminal of the shift circuit, and the source of the second NMOS transistor MN2 is grounded. The gate of the third NMOS transistor MN3 is connected to the gate of the fourth NMOS transistor MN4, and the gate of the fourth NMOS transistor MN4 is connected to the drain of the fourth NMOS transistor MN4. The gate of the fifth NMOS transistor MN5 is connected to the gate of the sixth NMOS transistor MN6, and the gate of the fifth NMOS transistor MN5 is connected to the drain of the fifth NMOS transistor MN6. The drain of S-channel transistor MN5 is connected, and the sources of the third NMOS transistor MN3, the fourth NMOS transistor MN4, the fifth NMOS transistor MN5, the sixth NMOS transistor MN6, the seventh NMOS transistor MN7, the eighth NMOS transistor MN8, the ninth NMOS transistor MN9, and the tenth NMOS transistor MN10 are all connected to the feedback terminal; the gates of the seventh NMOS transistor MN7, the eighth NMOS transistor MN8, the ninth NMOS transistor MN9, and the tenth NMOS transistor MN10 are all connected to the first interlock signal terminal.

[0031] The anodes of the first diode D1 and the second diode D2 are both connected to the feedback terminal. The cathode of the first diode D1 is connected to the drain of the first NMOS transistor MN1, and the cathode of the second diode D2 is connected to the drain of the second NMOS transistor MN2.

[0032] The gate of the first PMOS transistor MP1 serves as the third input terminal of the shift circuit, and the gate of the second PMOS transistor MP2 serves as the fourth input terminal of the shift circuit. The drain of the first PMOS transistor MP1 is connected to the drain of the first NMOS transistor MN1. The gates of the first PMOS transistor MP1, the third PMOS transistor MP3, and the fourth PMOS transistor MP4 are all connected to the drain of the first PMOS transistor MP1. The drain of the second PMOS transistor MP2 is connected to the drain of the second PMOS transistor MP2. The drains of the second PMOS transistor MP2, the gates of the fifth PMOS transistor MP5, and the gates of the sixth PMOS transistor MP6 are all connected to the second PMOS transistor MP1. The gate of PMOS transistor MP2 is connected; the sources of the first PMOS transistor MP1, the second PMOS transistor MP2, the third PMOS transistor MP3, the fourth PMOS transistor MP4, the fifth PMOS transistor MP5, and the sixth PMOS transistor MP6 are all connected to the VDD voltage terminal; the drain of the third PMOS transistor MP3 is connected to the drain of the third NMOS transistor MN3, the drain of the fourth PMOS transistor MP4 is connected to the drain of the fifth NMOS transistor MN5, the drain of the fifth PMOS transistor MP5 is connected to the drain of the fourth NMOS transistor MN4, and the drain of the sixth PMOS transistor MP6 is connected to the drain of the sixth NMOS transistor MN6.

[0033] The first input terminal of the third XOR gate XOR3 is connected to the drain of the sixth PMOS transistor MP6. The output terminal of the third XOR gate XOR3 serves as the high-level output terminal of the shift circuit. The first input terminal of the fourth XOR gate XOR4 is connected to the output terminal of the third XOR gate XOR3. The second input terminal of the fourth XOR gate XOR4 is connected to the drain of the third NMOS transistor MN3. The output terminal of the fourth XOR gate XOR4 serves as the low-level output terminal of the shift circuit. The output terminal of the fourth XOR gate XOR4 is connected to the second input terminal of the third XOR gate XOR3. The sources of the seventh PMOS transistor MP7, the eighth PMOS transistor MP8, the ninth PMOS transistor MP9, and the tenth PMOS transistor MP6 are also connected. The source of S-channel transistor MP10 is connected to the VB voltage terminal. The gates of the seventh PMOS transistor MP7 and the eighth PMOS transistor MP8 are connected to the second interlock signal terminal. The drain of the seventh PMOS transistor MP7 is connected to the drain of the seventh NMOS transistor MN7. The drain of the eighth PMOS transistor MP8 is connected to the drain of the eighth NMOS transistor MN8. The gate of the ninth PMOS transistor MP9 is connected to the output terminal of the fourth XOR gate XOR4. The drain of the ninth PMOS transistor MP9 is connected to the drain of the ninth NMOS transistor MN9. The gate of the tenth PMOS transistor MP10 is connected to the output terminal of the third XOR gate XOR3. The drain of the tenth PMOS transistor MP10 is connected to the drain of the tenth NMOS transistor MN10.

[0034] The input terminals of the eighth NOT gate INV8 and the seventh NOT gate INV7 are connected to the drain of the tenth PMOS transistor MP10. The output terminals of the eighth NOT gate INV8 and the seventh NOT gate INV7 are connected to the second input terminal of the fourth XOR gate XOR4. The input terminal of the ninth NOT gate INV9 is connected to the drain of the ninth NMOS transistor MN9. The output terminal of the ninth NOT gate INV9 is connected to the first input terminal of the third XOR gate XOR3.

[0035] When the shift circuit is used as a low-level shift circuit, the feedback terminal is grounded, and the third input terminal of the low-level shift circuit ( Figure 5 The Set(———) in the circuit is connected to the OUT_H terminal of the adaptive dead-time circuit, and the fourth input terminal of the low-level shift circuit. Figure 5 The Reset(---) is connected to the OUT_L terminal of the adaptive dead-time circuit, and the C_O(--)U(--)T(--) of the low-level shift circuit is connected to the input terminal of the second output stage driver circuit. When the shift circuit is used as a high-level shift circuit, the feedback terminal is connected to the VS terminal, and the first input terminal of the high-level shift circuit ( Figure 5 The Set terminal is connected to the OUT_H terminal of the adaptive dead-time circuit, and the second input terminal of the low-level shift circuit. Figure 5The Reset pin is connected to the OUT_L terminal of the adaptive dead-time circuit, and the C_OUT pin of the high-level shift circuit is connected to the input terminal of the first output stage driver circuit.

[0036] In this embodiment, the shift circuit consists of three parts: a level shift circuit, a common-mode noise cancellation circuit, and a double interlock circuit. The input signals to the level shift circuit are two narrow pulse signals generated by the pulse generation circuit. The common-mode noise cancellation circuit filters out the common-mode quantity in transient noise, and the double interlock circuit filters out the differential-mode quantity introduced by process variations in the noise. Since no RC filter circuit is used, the delay characteristics of this structure overcome the shortcomings of traditional transient noise suppression circuits, breaking the contradiction between delay and transient noise suppression capabilities in traditional level shift circuits. Reset and Set correspond to the input signals HI or LI of the level shift circuit section, and BiasP and BiasN are connected to the interlock signals.

[0037] like Figure 6 As shown, in the initial stage (t0~t1): In the initial state, the IN signal is kept at a low level, so Reset='0' and Set='0'. By using the power-on reset circuit, the initial state of C_OUT is set to a low level. Under the action of the second-level interlock, S(——)='1' and R(——)='0' are maintained, thus keeping C_OUT at a low level. Turn-on phase (t1~t2): When the IN signal goes high and a rising edge is generated, the pulse generation circuit will output a narrow pulse signal at the SET terminal to set the signal. At this time, Set='1' and Reset='0'. By making the pull-down capability of the sixth NMOS transistor MN6 stronger than the current capability of the seventh PMOS transistor MP7, the current source of the ninth NOT gate INV9 in the second-stage interlocking structure, S(——)='0' is made stronger. By making the pull-up capability of the seventh PMOS transistor MP7 stronger than the current capability of the eighth NMOS transistor MN8 below the seventh NOT gate INV7 in the second-stage interlocking structure, R(——)='1' is made stronger, and finally C_OUT becomes high.

[0038] Latching phase (t2-t3): During this period, the duration of the narrow pulse signal generated by the pulse generation circuit of IN ends, causing the Set signal to... The signal goes low, i.e., Set='0' and Reset='0'. At this time, the third PMOS transistor MP3 to the sixth PMOS transistor MP6 are turned off, and the third NMOS transistor MN3 to the sixth NMOS transistor MN6 are also turned off. For the S(-) signal, under the combined action of the ninth NOT gate INV9 and the current source seventh NMOS transistor MN7 in the second-stage interlock structure, S(-) remains at a low level. The voltage overshoot in stage t2 is caused by the turn-off process of the sixth NMOS transistor MN6. For the R(-) signal, under the combined action of the eighth NOT gate INV8, the seventh NOT gate INV7, and the current source eighth PMOS transistor MP8 in the second-stage interlock structure, R(-) remains at a high level. The voltage spike in stage t2 is caused by the turn-off process of the third PMOS transistor MP3.

[0039] Turn-off phase (t3-t4): During this phase, the IN signal changes from high to low, generating a falling edge. The pulse generation circuit outputs a narrow pulse signal at the RESET terminal. At this time, the LDMOS gate state is Set='0', Reset='1'. By making the pull-down capability of the ninth NMOS transistor MN9 stronger than the current capability of the eighth PMOS transistor MP8 at the upper end of the seventh NOT gate INV7 in the second-stage interlock structure, R(-)='0'. By making the pull-up capability of the sixth PMOS transistor MP6 stronger than the current capability of the seventh NMOS transistor MN7 connected in series with the ninth NOT gate INV9 in the second-stage interlock structure, S(-)='1', ultimately causing C_OUT to go low. The operation after t4 is the same as the latching phase. The spike in S(-) during t4 is caused by the turn-off of the sixth PMOS transistor MP6, and the overshoot in R(-) during t4 is caused by the turn-off of the seventh NMOS transistor MN7.

[0040] like Figure 7As shown, in one embodiment, the output stage driving circuit includes a twelfth PMOS transistor MP12, a thirteenth PMOS transistor MP13, a fourteenth PMOS transistor MP14, a twelfth NMOS transistor MN12, a thirteenth NMOS transistor MN13, and a fourteenth NMOS transistor MN14; the sources of the twelfth PMOS transistor MP12, the thirteenth PMOS transistor MP13, and the fourteenth PMOS transistor MP14 are all connected to the power supply terminal of the output stage driving circuit, and the sources of the twelfth NMOS transistor MN12, the thirteenth NMOS transistor MN13, and the fourteenth NMOS transistor MN14 are all grounded; the gate of the twelfth PMOS transistor MP12 and the gate of the twelfth NMOS transistor MN12 are connected at a first connection point, which serves as the input terminal of the output stage driving circuit. The drain of the twelfth PMOS transistor MP12 and the drain of the twelfth NMOS transistor MN12 are connected to the second connection point. The gate of the thirteenth PMOS transistor MP13 and the gate of the thirteenth NMOS transistor MN13 are connected to the third connection point. The third connection point is connected to the second connection point. The drain of the thirteenth PMOS transistor MP13 and the drain of the thirteenth NMOS transistor MN13 are connected to the fourth connection point. The gate of the fourteenth PMOS transistor MP14 and the gate of the fourteenth NMOS transistor MN14 are connected to the fifth connection point. The fifth connection point is connected to the fourth connection point. The fifth connection point serves as the output terminal of the output stage drive circuit. The source of the fourteenth PMOS transistor MP14 and the drain of the fourteenth NMOS transistor MN14 are connected to the sixth connection point. The sixth connection point is connected to the third connection point.

[0041] In this embodiment, when the input Vin is low, the twelfth PMOS transistor MP12, the fourteenth PMOS transistor MP14, and the thirteenth NMOS transistor MN13 are turned on, while the thirteenth PMOS transistor MP13, the twelfth NMOS transistor MN12, and the fourteenth NMOS transistor MN14 are turned off. When Vin begins to rise to the threshold voltage of the NMOS transistors, the twelfth NMOS transistor MN12 slowly turns on. However, the current of the twelfth PMOS transistor MP12 and the fourteenth PMOS transistor MP14 is much greater than the current of the twelfth NMOS transistor MN12. Vin reaches the forward flip threshold when the current capability of the twelfth NMOS transistor MN12 equals the sum of the current capabilities of the twelfth PMOS transistor MP12 and the fourteenth PMOS transistor MP14. Similarly, when Vin transitions from high to low, Vin reaches the inverting threshold of the Schmitt trigger if and only if the current capability of the twelfth PMOS transistor MP12 is equal to the sum of the current capabilities of the twelfth NMOS transistor MN12 and the fourteenth NMOS transistor MN14 when they are turned off.

[0042] In one embodiment, the driving circuit of the gallium nitride power device further includes two undervoltage protection circuits, referred to as the first undervoltage protection circuit and the second undervoltage protection circuit. The input terminal of the first undervoltage protection circuit is connected to the low-level output terminal of the high-level shift circuit, and the output terminal of the first undervoltage protection circuit is connected to the second interlock signal terminal of the high-level shift circuit. The input terminal of the second undervoltage protection circuit is connected to the low-level output terminal of the low-level shift circuit, and the output terminal of the second undervoltage protection circuit is connected to the first interlock signal terminal of the low-level shift circuit. When the power supply voltage drops to 2.5V, the detection circuit detects that the voltage division value of the power supply voltage is lower than the reference voltage, and the undervoltage protection output is activated, putting the entire circuit into a protection state. The circuit restarts only after the voltage returns to normal.

[0043] like Figure 8 As shown, in one embodiment, the undervoltage protection circuit includes a comparator, a first RS flip-flop RS1, a second RS flip-flop RS2, a current-frequency oscillator, a first frequency divider, a second frequency divider, a first D flip-flop DFF1, a second D flip-flop DFF2, a second NOR gate NOR2, a first XNOR gate XNOR1, a fourth NAND gate NAND4, and a first AND gate AND1.

[0044] The first input terminal of the comparator is connected to the VDD voltage terminal, and the second input terminal of the comparator is connected to the low-level output terminal of the shift circuit. The output terminal of the comparator is connected to the S terminal of the first RS flip-flop RS1, the Reset terminal of the first frequency divider, the Reset terminal of the first D flip-flop DFF1, the second input terminal of the second NOR gate NOR2, the first input terminal of the first XNOR gate XNOR1, and the first input terminal of the fourth NAND gate NAND4, respectively. The output terminal of the first RS flip-flop RS1 is connected to the input terminal of the current-frequency oscillator, and the output terminal of the current-frequency oscillator is connected to the CLK terminal of the first frequency divider and the CLK terminal of the second frequency divider, respectively. The output terminal of the first frequency divider is connected to the CLK terminal of the first D flip-flop DFF1, the Q(-) terminal of the first D flip-flop DFF1 is connected to the first input terminal of the second NOR gate NOR2, and the output terminal of the second NOR gate NOR2 is connected to the S terminal of the second RS flip-flop RS2.

[0045] The output of the second frequency divider is connected to the CLK terminal of the second D flip-flop DFF2. The Q(-) terminal of the second D flip-flop DFF2 is connected to the second input terminal of the first XNOR gate XNOR1. The output terminal of the first XNOR gate XNOR1 is connected to the first input terminal of the first AND gate AND1. The second input terminal of the first AND gate AND1 is connected to the output terminal of the fourth NAND gate NAND4. The second input terminal of the fourth NAND gate NAND4 is connected to the Reset terminal of the second frequency divider and the Reset terminal of the second D flip-flop DFF2. The output terminal of the first AND gate AND1 is connected to the R terminal of the first RS flip-flop RS1 and the R terminal of the second RS flip-flop RS2. The output terminal of the second RS flip-flop RS2 is connected to the second input terminal of the fourth NAND gate NAND4. The output terminal of the second RS flip-flop RS2 serves as the output terminal of the undervoltage protection circuit.

[0046] When the undervoltage protection circuit is connected to the high-level shift circuit, the output of the undervoltage protection circuit is connected to the second interlock signal terminal (BiasP) of the high-level shift circuit; when the undervoltage protection circuit is connected to the low-level shift circuit, the output of the undervoltage protection circuit is connected to the first interlock signal terminal (BiasN) of the low-level shift circuit. The undervoltage protection circuit used in this embodiment combines undervoltage filtering and fault recovery. When the VDD voltage drops to 2.5V, the comparator detects that the voltage division value of the power supply voltage is lower than the reference voltage, so it outputs a high-level signal at point A. Simultaneously, it sets the first RS flip-flop, outputting a high-level enable signal at point B to start the current-frequency oscillator. When the power supply voltage recovers from 2.5V to 5V, there is still no output signal at point D, indicating that the undervoltage time has not reached the filtering width of the undervoltage filter. At this time, the circuit determines that the chip is not in an abnormal working state and outputs a falling edge signal at point E to shut down the current-frequency oscillator. The output signal at point F (i.e., the undervoltage protection output signal) remains unchanged throughout the entire process.

[0047] The first and second frequency dividers consist of several rising-edge triggered D flip-flops. The output frequency is halved after each D flip-flop, and the period doubles. The overall period is equivalent to increasing exponentially from the period of a current-frequency oscillator. The significance of using a frequency divider lies not only in the fact that the filtering time is inversely proportional to the power supply voltage, but also in the fact that most drive circuit fault recovery circuits require millisecond-level delays. Using a simple RC delay would occupy a large chip area, while using an oscillator plus a frequency divider can effectively generate precise delays and, given the increasingly high integration of transistors, can significantly reduce chip area.

[0048] The above description is merely a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the concept described herein through the above teachings or related technologies or knowledge. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.

Claims

1. A driving circuit for a gallium nitride power device, characterized in that, It includes a high-level input terminal, a low-level input terminal, a drive output terminal, a VDD voltage terminal, a VB voltage terminal, a Vs terminal, an input stage drive circuit, an adaptive dead-time circuit, two shift circuits, two output stage drive circuits, a negative voltage detection circuit, a first resistor, a second resistor, a third resistor, a fourth resistor, an eleventh PMOS transistor, and an eleventh NMOS transistor. The two output stage drive circuits include a first output stage drive circuit and a second output stage drive circuit. The two shift circuits include a high-level shift circuit and a low-level shift circuit. The first input terminal of the input stage driver circuit is connected to the high-level input terminal, the second input terminal of the input stage driver circuit is connected to the low-level input terminal, the high-level output terminal of the input stage driver circuit is connected to the high-level input terminal of the adaptive dead-time circuit, and the low-level output terminal of the input stage driver circuit is connected to the low-level input terminal of the adaptive dead-time circuit. The high-level output terminal of the adaptive dead-time circuit is connected to the second input terminal of the high-level shift circuit and the fourth input terminal of the low-level shift circuit; the low-level output terminal of the adaptive dead-time circuit is connected to the first input terminal of the high-level shift circuit and the third input terminal of the low-level shift circuit; the high-level output terminal of the high-level shift circuit is connected to the input terminal of the first output stage driver circuit; and the low-level output terminal of the low-level shift circuit is connected to the input terminal of the second output stage driver circuit. The high-level output terminal of the first output stage driving circuit is connected to the gate of the eleventh PMOS transistor via a first resistor, and the low-level output terminal of the first output stage driving circuit is connected to the gate of the eleventh PMOS transistor via a second resistor; the high-level output terminal of the second output stage driving circuit is connected to the gate of the eleventh NMOS transistor via a third resistor, and the low-level output terminal of the second output stage driving circuit is connected to the gate of the eleventh NMOS transistor via a fourth resistor; the drain of the eleventh PMOS transistor is connected to the power supply voltage, the source of the eleventh PMOS transistor is connected to the drain of the eleventh NMOS transistor, the source of the eleventh NMOS transistor is grounded, and the connection point between the source and drain of the eleventh PMOS transistor is connected to the driving output terminal. The input terminal of the negative pressure detection circuit is connected to the Vs terminal, the Vs terminal is connected to the drive output terminal, the output terminal of the negative pressure detection circuit is connected to the control terminal of the adaptive dead-time circuit, the power supply terminal of the high-level shift circuit and the power supply terminal of the first output stage drive circuit are both connected to the VB voltage terminal, and the power supply terminal of the input stage drive circuit, the power supply terminal of the low-voltage level shift circuit and the power supply terminal of the second output stage drive circuit are all connected to the VDD voltage terminal.

2. The driving circuit for a gallium nitride power device according to claim 1, characterized in that, The driving circuit also includes a clamping protection circuit. The first control terminal of the clamping protection circuit is connected to the VB voltage terminal. The output terminal of the clamping protection circuit is connected to the clamping protection terminal of the high-level shift circuit. The output terminal of the negative voltage detection circuit is connected to the second control terminal of the clamping protection circuit. The power supply terminal of the clamping protection circuit is connected to the VDD voltage terminal.

3. The driving circuit for a gallium nitride power device according to claim 1, characterized in that, The input stage driving circuit includes a first NOR gate, a first NAND gate, a first NOT gate, a second NOT gate, a third NOT gate, a fourth NOT gate, and a fifth NOT gate. The first input terminal of the first NAND gate serves as the high-level input terminal of the input stage driving circuit. The output terminal of the first NAND gate is connected to the input terminal of the first NOT gate. The output terminal of the first NOT gate is connected to the input terminal of the second NOT gate. The output terminal of the second NOT gate is connected to the input terminal of the third NOT gate. The output terminal of the third NOT gate is connected to the first input terminal of the first NOR gate. The output terminal of the third NOT gate serves as the high-level output terminal of the input stage driving circuit. The second input terminal of the first NOR gate serves as the low-level input terminal of the input stage driving circuit. The output terminal of the first NOR gate is connected to the input terminal of the fourth NOT gate. The output terminal of the fourth NOT gate is connected to the input terminal of the fifth NOT gate. The output terminal of the fifth NOT gate is connected to the second input terminal of the first NAND gate. The output terminal of the fifth NOT gate serves as the low-level output terminal of the input stage driving circuit.

4. The driving circuit for a gallium nitride power device according to claim 1, characterized in that, The adaptive dead-time circuit includes a sixth NOT gate, a seventh NOT gate, a second NAND gate, a third NAND gate, a first XOR gate, a second XOR gate, a first dynamic delay unit, and a second dynamic delay unit. The input terminal of the sixth NOT gate serves as the high-level input terminal of the adaptive dead-time circuit. The output terminal of the sixth NOT gate is connected to the first input terminal of the second NAND gate and the first input terminal of the first XOR gate. The input terminal of the first dynamic delay unit is connected to the input terminal of the sixth NOT gate. The output terminal of the first dynamic delay unit is connected to the second input terminal of the first XOR gate. The output terminal of the first XOR gate is connected to the first input terminal of the third NAND gate. The input terminal of the seventh NOT gate serves as the low-level input terminal of the adaptive dead-time circuit. The output terminal of the seventh NOT gate is connected to the second input terminal of the second XOR gate and the second input terminal of the third NAND gate. The input terminal of the second dynamic delay unit is connected to the input terminal of the seventh NOT gate. The output terminal of the second dynamic delay unit is connected to the first input terminal of the second XOR gate. The output terminal of the second XOR gate is connected to the second input terminal of the second NAND gate. The output terminal of the third NAND gate serves as the high-level output terminal of the adaptive dead-time circuit.

5. The driving circuit for a gallium nitride power device according to claim 1, characterized in that, The shift circuit is a double-interlocked level shift circuit.

6. The driving circuit for a gallium nitride power device according to claim 5, characterized in that, The shift circuit includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, a first diode, a second diode, a third XOR gate, a fourth XOR gate, an eighth NOT gate, a ninth NOT gate, a first interlock signal terminal, a second interlock signal terminal, and a feedback terminal; The gate of the first NMOS transistor serves as the first input terminal of the shift circuit, and the source of the first NMOS transistor is grounded. The gate of the second NMOS transistor serves as the second input terminal of the shift circuit, and the source of the second NMOS transistor is grounded. The gate of the third NMOS transistor is connected to the gate of the fourth NMOS transistor, and the gate of the fourth NMOS transistor is connected to the drain of the fourth NMOS transistor. The gate of the fifth NMOS transistor is connected to the gate of the sixth NMOS transistor, and the gate of the fifth NMOS transistor is connected to the drain of the fifth NMOS transistor. The sources of the third, fourth, fifth, sixth, seventh, eighth, ninth, and tenth NMOS transistors are all connected to the feedback terminal. The gates of the seventh, eighth, ninth, and tenth NMOS transistors are all connected to the first interlock signal terminal. The anodes of the first diode and the second diode are both connected to the feedback terminal. The cathode of the first diode is connected to the drain of the first NMOS transistor, and the cathode of the second diode is connected to the drain of the second NMOS transistor. The gate of the first PMOS transistor serves as the third input terminal of the shift circuit, and the gate of the second PMOS transistor serves as the fourth input terminal of the shift circuit. The drain of the first PMOS transistor is connected to the drain of the first NMOS transistor. The gates of the first, third, and fourth PMOS transistors are all connected to the drain of the first PMOS transistor. The drain of the second PMOS transistor is connected to the drain of the second PMOS transistor. The drain of the second PMOS transistor, the gate of the fifth PMOS transistor, and the gate of the sixth PMOS transistor are all connected to the drain of the first NMOS transistor. The gates of the two PMOS transistors are connected; the sources of the first, second, third, fourth, fifth, and sixth PMOS transistors are all connected to the VDD voltage terminal; the drain of the third PMOS transistor is connected to the drain of the third NMOS transistor, the drain of the fourth PMOS transistor is connected to the drain of the fifth NMOS transistor, the drain of the fifth PMOS transistor is connected to the drain of the fourth NMOS transistor, and the drain of the sixth PMOS transistor is connected to the drain of the sixth NMOS transistor. The first input terminal of the third XOR gate is connected to the drain of the sixth PMOS transistor, and the output terminal of the third XOR gate serves as the high-level output terminal of the shift circuit. The first input terminal of the fourth XOR gate is connected to the output terminal of the third XOR gate, and the second input terminal of the fourth XOR gate is connected to the drain of the third NMOS transistor. The output terminal of the fourth XOR gate serves as the low-level output terminal of the shift circuit, and the output terminal of the fourth XOR gate is connected to the second input terminal of the third XOR gate. The sources of the seventh PMOS transistor, the eighth PMOS transistor, the ninth PMOS transistor, and the tenth PMOS transistor... The sources of all MOS transistors are connected to the VB voltage terminal. The gates of the seventh PMOS transistor and the eighth PMOS transistor are both connected to the second interlock signal terminal. The drain of the seventh PMOS transistor is connected to the drain of the seventh NMOS transistor. The drain of the eighth PMOS transistor is connected to the drain of the eighth NMOS transistor. The gate of the ninth PMOS transistor is connected to the output terminal of the fourth XOR gate. The drain of the ninth PMOS transistor is connected to the drain of the ninth NMOS transistor. The gate of the tenth PMOS transistor is connected to the output terminal of the third XOR gate. The drain of the tenth PMOS transistor is connected to the drain of the tenth NMOS transistor. The input of the eighth NOT gate is connected to the drain of the tenth PMOS transistor, the output of the eighth NOT gate is connected to the second input of the fourth XOR gate, the input of the ninth NOT gate is connected to the drain of the ninth NMOS transistor, and the output of the ninth NOT gate is connected to the first input of the third XOR gate.

7. The driving circuit for a gallium nitride power device according to claim 1, characterized in that, The output stage driving circuit includes a 12th PMOS transistor, a 13th PMOS transistor, a 14th PMOS transistor, a 12th NMOS transistor, a 13th NMOS transistor, and a 14th NMOS transistor. The sources of the 12th, 13th, and 14th PMOS transistors are all connected to the power supply terminal of the output stage driving circuit, and the sources of the 12th, 13th, and 14th NMOS transistors are all grounded. The gate of the 12th PMOS transistor is connected to the gate of the 12th NMOS transistor at a first connection point, which serves as the input terminal of the output stage driving circuit. The drain of the 12th PMOS transistor is connected to the gate of the 14th NMOS transistor. The drain of the 12th NMOS transistor is connected to the second connection point. The gate of the 13th PMOS transistor and the gate of the 13th NMOS transistor are connected to the third connection point, which is connected to the second connection point. The drain of the 13th PMOS transistor and the drain of the 13th NMOS transistor are connected to the fourth connection point. The gate of the 14th PMOS transistor and the gate of the 14th NMOS transistor are connected to the fifth connection point, which is connected to the fourth connection point. The fifth connection point serves as the output terminal of the output stage drive circuit. The source of the 14th PMOS transistor and the drain of the 14th NMOS transistor are connected to the sixth connection point, which is connected to the third connection point.

8. The driving circuit for a gallium nitride power device according to claim 1, characterized in that, The driving circuit of the gallium nitride power device further includes two undervoltage protection circuits, referred to as the first undervoltage protection circuit and the second undervoltage protection circuit. The input terminal of the first undervoltage protection circuit is connected to the low-level output terminal of the high-level shift circuit, and the output terminal of the first undervoltage protection circuit is connected to the second interlock signal terminal of the high-level shift circuit. The input terminal of the second undervoltage protection circuit is connected to the low-level output terminal of the low-level shift circuit, and the output terminal of the second undervoltage protection circuit is connected to the first interlock signal terminal of the low-level shift circuit.

9. The driving circuit for a gallium nitride power device according to claim 8, characterized in that, The undervoltage protection circuit includes a comparator, a first RS flip-flop, a second RS flip-flop, a current-frequency oscillator, a first frequency divider, a second frequency divider, a first D flip-flop, a second D flip-flop, a second NOR gate, a first XOR gate, a fourth NAND gate, and a first AND gate. The first input terminal of the comparator is connected to the VDD voltage terminal, the second input terminal of the comparator is connected to the low-level output terminal of the shift circuit, and the output terminal of the comparator is connected to the S terminal of the first RS flip-flop, the Reset terminal of the first frequency divider, the Reset terminal of the first D flip-flop, the second input terminal of the second NOR gate, the first input terminal of the first XOR gate, and the first input terminal of the fourth NAND gate, respectively. The output of the first RS flip-flop is connected to the input of the current-frequency oscillator, and the output of the current-frequency oscillator is connected to the CLK terminal of the first frequency divider and the CLK terminal of the second frequency divider, respectively; the output of the first frequency divider is connected to the CLK terminal of the first D flip-flop, the Q(-) terminal of the first D flip-flop is connected to the first input of the second NOR gate, and the output of the second NOR gate is connected to the S terminal of the second RS flip-flop. The output of the second frequency divider is connected to the CLK terminal of the second D flip-flop. The Q(-) terminal of the second D flip-flop is connected to the second input terminal of the first XOR gate. The output terminal of the first XOR gate is connected to the first input terminal of the first AND gate. The second input terminal of the first AND gate is connected to the output terminal of the fourth NAND gate. The second input terminal of the fourth NAND gate is connected to the Reset terminal of the second frequency divider and the Reset terminal of the second D flip-flop. The output terminal of the first AND gate is connected to the R terminal of the first RS flip-flop and the R terminal of the second RS flip-flop. The output terminal of the second RS flip-flop is connected to the second input terminal of the fourth NAND gate. The output terminal of the second RS flip-flop serves as the output terminal of the undervoltage protection circuit.

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