Low cost power supply timing control circuit and server

Abstract

This invention provides a low-cost power supply timing control circuit and a server. The low-cost power supply timing control circuit includes: a MOSFET, with its drain connected to a first output terminal and its source connected to a third output terminal; a first transistor, with its base connected to a second output terminal and its collector connected to the gate of the MOSFET; a second transistor, with its collector connected to the emitter of the first transistor and its emitter connected to ground; a power supply; a first resistor and a second resistor, with one end of the first resistor connected to the positive terminal of the power supply and the other end connected to one end of the second resistor and the base of the second transistor; and the other end of the second resistor connected to ground and the negative terminal of the power supply. By using the solution of this invention, the power-on timing control of a product can be achieved without relying on software and chips. It is applicable to products with timing control requirements but no requirements for absolute timing difference. The implementation solution is simple, inexpensive, and highly scalable.

Description

Technical Field

[0001] This invention relates to the field of computers, and more specifically to a low-cost power timing control circuit and server. Background Technology

[0002] Common power supply timing control methods include GPIO control by the main control chip, cascaded control of power supply chips, or control of power supply timing relationships by other dedicated chips, ultimately achieving the goal of power supply timing conforming to the expected design. However, these methods have different drawbacks: 1. They rely on software control and cannot operate independently; 2. They can only control the power-on or power-off timing, and cannot control both; 3. They require special chips to implement, which results in higher costs. Summary of the Invention

[0003] In view of this, the purpose of this invention is to provide a low-cost power supply timing control circuit and server. By using the technical solution of this invention, the power-on timing control of a product can be achieved without relying on software and chips. It can be applied to products that have timing control requirements but no requirements for absolute timing difference. The implementation solution is simple, inexpensive, and highly scalable.

[0004] To achieve the above objectives, one aspect of the present invention provides a low-cost power supply timing control circuit, comprising:

[0005] The drain of the MOSFET is connected to the first output terminal, and the source is connected to the third output terminal.

[0006] The first transistor has its base connected to the second output terminal and its collector connected to the gate of the MOSFET.

[0007] The collector of the second transistor is connected to the emitter of the first transistor, and the emitter is connected to ground.

[0008] A power supply, a first resistor, and a second resistor are connected. One end of the first resistor is connected to the positive terminal of the power supply, and the other end is connected to one end of the second resistor and the base of the second transistor. The other end of the second resistor is connected to ground and the negative terminal of the power supply.

[0009] According to one embodiment of the present invention, it further includes:

[0010] The first capacitor has one end connected to the base of the second transistor and the other end grounded.

[0011] The second capacitor has one end connected to the base of the first transistor and the other end grounded.

[0012] According to one embodiment of the present invention, it further includes:

[0013] The third resistor has one end connected to the drain of the MOSFET and the other end connected to the gate of the MOSFET.

[0014] According to one embodiment of the present invention, the first transistor and the second transistor are NPN transistors.

[0015] According to one embodiment of the present invention, the MOS transistor is a PMOS transistor.

[0016] Another aspect of the embodiments of the present invention also provides a server, the server including a low-cost power timing control circuit, the low-cost power timing control circuit including:

[0017] The drain of the MOSFET is connected to the first output terminal, and the source is connected to the third output terminal.

[0018] The first transistor has its base connected to the second output terminal and its collector connected to the gate of the MOSFET.

[0019] The collector of the second transistor is connected to the emitter of the first transistor, and the emitter is connected to ground.

[0020] A power supply, a first resistor, and a second resistor are connected. One end of the first resistor is connected to the positive terminal of the power supply, and the other end is connected to one end of the second resistor and the base of the second transistor. The other end of the second resistor is connected to ground and the negative terminal of the power supply.

[0021] According to one embodiment of the present invention, it further includes:

[0022] The first capacitor has one end connected to the base of the second transistor and the other end grounded.

[0023] The second capacitor has one end connected to the base of the first transistor and the other end grounded.

[0024] According to one embodiment of the present invention, it further includes:

[0025] The third resistor has one end connected to the drain of the MOSFET and the other end connected to the gate of the MOSFET.

[0026] According to one embodiment of the present invention, the first transistor and the second transistor are NPN transistors.

[0027] According to one embodiment of the present invention, the MOS transistor is a PMOS transistor.

[0028] The present invention has the following beneficial technical effects: The low-cost power supply timing control circuit provided in the embodiments of the present invention, by setting a MOS transistor, with the drain of the MOS transistor connected to the first output terminal and the source connected to the third output terminal; a first transistor, with the base of the first transistor connected to the second output terminal and the collector connected to the gate of the MOS transistor; a second transistor, with the collector of the second transistor connected to the emitter of the first transistor and the emitter connected to ground; a power supply, a first resistor, and a second resistor, with one end of the first resistor connected to the positive terminal of the power supply and the other end connected to one end of the second resistor and the base of the second transistor, and the other end of the second resistor connected to ground and the negative terminal of the power supply, can realize the control of the power-on timing of the product without relying on software and chips. It can be applied to products with timing control requirements but no requirements for absolute timing difference. The implementation scheme is simple, inexpensive, and highly scalable. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other embodiments can be obtained based on these drawings without creative effort.

[0030] Figure 1 This is a schematic diagram of a low-cost power supply timing control circuit according to an embodiment of the present invention;

[0031] Figure 2 This is a schematic diagram of a power supply system according to an embodiment of the present invention. Detailed Implementation

[0032] The following describes embodiments of the present disclosure. However, it should be understood that the disclosed embodiments are merely examples, and other embodiments may take various alternative forms. The drawings are not necessarily drawn to scale; certain functions may be exaggerated or minimized to show details of particular components. Therefore, the specific structural and functional details disclosed herein should not be construed as limiting, but merely as a representative basis for teaching those skilled in the art to use the invention in various ways. As will be understood by those skilled in the art, various features shown and described with reference to any of the drawings may be combined with features shown in one or more other drawings to produce embodiments not explicitly shown or described. The combinations of features shown provide representative embodiments for typical applications. However, various combinations and modifications of features consistent with the teachings of this disclosure may be desirable for certain particular applications or implementations.

[0033] Based on the above objectives, a first aspect of the embodiments of the present invention provides an embodiment of a low-cost power supply timing control circuit. Figure 1The diagram shown is a schematic of the low-cost power supply timing control circuit.

[0034] like Figure 1 As shown, the low-cost power supply timing control circuit may include:

[0035] MOSFET T1 has its drain connected to the first output terminal and its source connected to the third output terminal.

[0036] The base of the first transistor T2 is connected to the second output terminal, and the collector is connected to the gate of the MOSFET.

[0037] The collector of the second transistor T3 is connected to the emitter of the first transistor T2, and the emitter is connected to ground.

[0038] Power supply V1, first resistor R1 and second resistor R2. One end of the first resistor R1 is connected to the positive terminal of power supply V1, and the other end is connected to one end of the second resistor R2 and the base of the second transistor T3. The other end of the second resistor R2 is connected to ground and the negative terminal of power supply V1.

[0039] The first capacitor C1 has one end connected to the base of the second transistor T3, and the other end grounded.

[0040] The second capacitor C2 has one end connected to the base of the first transistor T2 and the other end grounded.

[0041] The third resistor R3 has one end connected to the drain of MOSFET T1 and the other end connected to the gate of MOSFET T1.

[0042] The sixth resistor R6 has one end connected to the base of the first transistor T2 and the other end connected to the second output terminal.

[0043] The circuit of the present invention can be used in, for example Figure 2 The power supply system shown, Figure 2 The discrete control circuit in this invention is a low-cost power supply timing control circuit. Control point 1 ensures that system power supply 2 powers on before system power supply 1, and control point 2 ensures that system power supply 1 powers off before system power supply 2. This circuit implements two reverse timing logic controls without involving special chips or software control. Timing control of the control circuit unit is achieved through switching transistors, and voltage monitoring is implemented using voltage divider resistors as thresholds. VOUT1 and VOUT2 are the two power inputs to the backend system. They must satisfy the following timing logic: when powering on, VOUT2 powers on before VOUT1, and when powering off, VOUT2 powers off later than VOUT1.

[0044] The circuit control logic is as follows:

[0045] During the initial power-on phase, due to the presence of voltage V1, transistor T3 is in the conducting state. As VOUT2 powers on, after a delay by R6 and C2, transistor T2 is turned on. After transistors T2 and T3 are turned on, transistor T1 is turned on, thus enabling power output of VOUT1 (control point 1). During the system power-off phase, as the voltage of V1 decreases, the voltage divider network composed of R1 and R2 will detect insufficient voltage of V1 (there are many implementation schemes for this, and this diagram shows one low-cost method), which causes transistor T3 to turn off due to insufficient driving capability, which in turn causes transistors T2 and T1 to turn off, and the VOUT1_D output to turn off. Then VOUT2 is powered off with the system (control point 2). This circuit can completely avoid software intervention and can realize the reverse timing process control of power-on and power-off of a pure hardware circuit.

[0046] The technical solution of this invention enables the control of product power-on timing without relying on software and chips. It is applicable to products with timing control requirements but no requirements for absolute timing difference. The solution is simple, inexpensive, and highly scalable.

[0047] In a preferred embodiment of the present invention, it further includes:

[0048] The first capacitor has one end connected to the base of the second transistor and the other end grounded.

[0049] The second capacitor has one end connected to the base of the first transistor and the other end grounded.

[0050] In a preferred embodiment of the present invention, it further includes:

[0051] The third resistor has one end connected to the drain of the MOSFET and the other end connected to the gate of the MOSFET.

[0052] In a preferred embodiment of the present invention, the first transistor and the second transistor are NPN transistors.

[0053] In a preferred embodiment of the present invention, the MOS transistor is a PMOS transistor.

[0054] The technical solution of this invention enables the control of product power-on timing without relying on software and chips. It is applicable to products with timing control requirements but no requirements for absolute timing difference. The solution is simple, inexpensive, and highly scalable.

[0055] Based on the above objectives, a second aspect of the embodiments of the present invention provides a server, the server including a low-cost power timing control circuit, the low-cost power timing control circuit comprising:

[0056] The drain of the MOSFET is connected to the first output terminal, and the source is connected to the third output terminal.

[0057] The first transistor has its base connected to the second output terminal and its collector connected to the gate of the MOSFET.

[0058] The collector of the second transistor is connected to the emitter of the first transistor, and the emitter is connected to ground.

[0059] A power supply, a first resistor, and a second resistor are connected. One end of the first resistor is connected to the positive terminal of the power supply, and the other end is connected to one end of the second resistor and the base of the second transistor. The other end of the second resistor is connected to ground and the negative terminal of the power supply.

[0060] The server of this invention may include, for example: Figure 2 The power supply system shown, Figure 2 The discrete control circuit in this invention is a low-cost power supply timing control circuit. Control point 1 ensures that system power supply 2 powers on before system power supply 1, and control point 2 ensures that system power supply 1 powers off before system power supply 2. This circuit implements two reverse timing logic controls without involving special chips or software control. Timing control of the control circuit unit is achieved through switching transistors, and voltage monitoring is implemented using voltage divider resistors as thresholds. VOUT1 and VOUT2 are the two power inputs to the backend system. They must satisfy the following timing logic: when powering on, VOUT2 powers on before VOUT1, and when powering off, VOUT2 powers off later than VOUT1.

[0061] The circuit control logic is as follows:

[0062] During the initial power-on phase, due to the presence of voltage V1, transistor T3 is in the conducting state. As VOUT2 powers on, after a delay by R6 and C2, transistor T2 is turned on. After transistors T2 and T3 are turned on, transistor T1 is turned on, thus enabling power output of VOUT1 (control point 1). During the system power-off phase, as the voltage of V1 decreases, the voltage divider network composed of R1 and R2 will detect insufficient voltage of V1 (there are many implementation schemes for this, and this diagram shows one low-cost method), which causes transistor T3 to turn off due to insufficient driving capability, which in turn causes transistors T2 and T1 to turn off, and the VOUT1_D output to turn off. Then VOUT2 is powered off with the system (control point 2). This circuit can completely avoid software intervention and can realize the reverse timing process control of power-on and power-off of a pure hardware circuit.

[0063] The technical solution of this invention enables the control of product power-on timing without relying on software and chips. It is applicable to products with timing control requirements but no requirements for absolute timing difference. The solution is simple, inexpensive, and highly scalable.

[0064] In a preferred embodiment of the present invention, it further includes:

[0065] The first capacitor has one end connected to the base of the second transistor and the other end grounded.

[0066] The second capacitor has one end connected to the base of the first transistor and the other end grounded.

[0067] In a preferred embodiment of the present invention, it further includes:

[0068] The third resistor has one end connected to the drain of the MOSFET and the other end connected to the gate of the MOSFET.

[0069] In a preferred embodiment of the present invention, the first transistor and the second transistor are NPN transistors.

[0070] In a preferred embodiment of the present invention, the MOS transistor is a PMOS transistor.

[0071] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

[0072] The above embodiments, especially any "preferred" embodiments, are possible examples of implementation and are presented merely for the purpose of clearly understanding the principles of the invention. Many variations and modifications can be made to the above embodiments without departing from the spirit and principles of the technology described herein. All modifications are intended to be included within the scope of this disclosure and protected by the appended claims.

Claims

1. A low-cost power supply timing control circuit, characterized in that, include: The MOSFET has its drain connected to the first power input terminal VOUT1 of the back-end system and its source connected to the third output terminal VOUT1_D. The third resistor has one end connected to the drain of the MOSFET and the other end connected to the gate of the MOSFET. The first transistor, whose collector is connected to the gate of the MOSFET; The second capacitor has one end connected to the base of the first transistor and the other end grounded. The sixth resistor has one end connected to the base of the first transistor and the other end connected to the second power input terminal VOUT2 of the back-end system. The second transistor has its collector connected to the emitter of the first transistor, and its emitter connected to ground. The first capacitor has one end connected to the base of the second transistor and the other end grounded. A power supply, a first resistor, and a second resistor. One end of the first resistor is connected to the positive terminal of the power supply, and the other end is connected to one end of the second resistor and the base of the second transistor. The other end of the second resistor is connected to ground and the negative terminal of the power supply. During the initial power-on phase, the second transistor is in the conducting state due to the presence of the power supply voltage. As the second power input terminal VOUT2 is powered on, the first transistor is turned on after the delay caused by the sixth resistor and the second capacitor. After the first and second transistors are turned on, the MOSFET is turned on, thereby realizing the power output of the third output terminal VOUT1_D. During the system power-off phase, as the power supply voltage decreases, the voltage divider network composed of the first and second resistors will detect insufficient power supply voltage, which will cause the second transistor to turn off due to insufficient driving capability. This will in turn cause the first transistor and the MOSFET to turn off, and the output of the third output terminal VOUT1_D will be turned off. Then the second power input terminal VOUT2 will power off with the system. During power-on, the second power input terminal VOUT2 is powered on earlier than the first power input terminal VOUT1, and during power-off, the second power input terminal VOUT2 is powered off later than the first power input terminal VOUT1.

2. The low-cost power supply timing control circuit according to claim 1, characterized in that, The first transistor and the second transistor are NPN transistors.

3. The low-cost power supply timing control circuit according to claim 1, characterized in that, The MOS transistor is a PMOS transistor.

4. A server, characterized in that, The server includes a low-cost power timing control circuit, which comprises: The MOSFET has its drain connected to the first power input terminal VOUT1 of the back-end system and its source connected to the third output terminal VOUT1_D. The third resistor has one end connected to the drain of the MOSFET and the other end connected to the gate of the MOSFET. The first transistor, whose collector is connected to the gate of the MOSFET; The second capacitor has one end connected to the base of the first transistor and the other end grounded. The sixth resistor has one end connected to the base of the first transistor and the other end connected to the second power input terminal VOUT2 of the back-end system. The second transistor has its collector connected to the emitter of the first transistor, and its emitter connected to ground. The first capacitor has one end connected to the base of the second transistor and the other end grounded. A power supply, a first resistor, and a second resistor. One end of the first resistor is connected to the positive terminal of the power supply, and the other end is connected to one end of the second resistor and the base of the second transistor. The other end of the second resistor is connected to ground and the negative terminal of the power supply. During the initial power-on phase, the second transistor is in the conducting state due to the presence of the power supply voltage. As the second power input terminal VOUT2 is powered on, the first transistor is turned on after the delay caused by the sixth resistor and the second capacitor. After the first and second transistors are turned on, the MOSFET is turned on, thereby realizing the power output of the third output terminal VOUT1_D. During the system power-off phase, as the power supply voltage decreases, the voltage divider network composed of the first and second resistors will detect insufficient power supply voltage, which will cause the second transistor to turn off due to insufficient driving capability. This will in turn cause the first transistor and the MOSFET to turn off, and the output of the third output terminal VOUT1_D will be turned off. Then the second power input terminal VOUT2 will power off with the system. During power-on, the second power input terminal VOUT2 is powered on earlier than the first power input terminal VOUT1, and during power-off, the second power input terminal VOUT2 is powered off later than the first power input terminal VOUT1.

5. The server according to claim 4, characterized in that, The first transistor and the second transistor are NPN transistors.

6. The server according to claim 4, characterized in that, The MOS transistor is a PMOS transistor.

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