Three-dimensional metal-insulator-metal (MIM) capacitor

Abstract

A three-dimensional metal-insulator-metal (MIM) capacitor is formed in an integrated circuit structure. The 3D MIM capacitor can include a bottom conductor including a floor portion (e.g., formed in a metal interconnect layer) and a vertically extending sidewall portion extending from the floor portion. An insulator layer is formed on the floor portion and the vertically extending sidewall portion of the bottom conductor. A top conductor is formed over the insulator layer such that the top conductor is capacitively coupled to both the floor portion and the vertically extending sidewall portion of the bottom conductor, defining an increased capacitive coupling area between the top conductor and the bottom conductor. The vertically extending sidewall portion of the bottom conductor can be formed in a single metal layer, or formed from components of multiple metal layers.

Description

[0001] Related patent applications

[0002] This application claims priority to jointly owned U.S. Provisional Patent Application No. 63 / 070,294, filed August 26, 2020, the entire contents of which are incorporated herein by reference for all purposes. Technical Field

[0003] This disclosure relates to metal-insulator-metal (MIM) capacitors, and more specifically, to three-dimensional (3D) MIM capacitors. Background Technology

[0004] A metal-insulator-metal (MIM) capacitor is a capacitor constructed of a metal top plate, a metal bottom plate, and an insulator (dielectric) sandwiched between the two metal plates.

[0005] MIM capacitors are important components in many circuits, such as many analog, mixed-signal, and radio frequency complementary metal-oxide-semiconductor (RF CMOS) circuits. Due to lower resistance, better matching, and / or better signal-to-noise ratio, MIM capacitors typically offer better performance than alternatives such as POP (polymer-oxide-polymer) capacitors and MOM (metal-oxide-metal lateral flux) capacitors.

[0006] MIM capacitors are typically located only beneath the top metal layer. For example, an existing top-1 metal layer can be used as the base plate, with a top plate constructed from a different metal (e.g., titanium or titanium nitride (Ti / TiN), tantalum or titanium nitride (Ta / TaN), or tungsten (W)). The overlying top metal layer is then connected to the capacitor's top and base plates via corresponding vias. The top plate typically has a higher resistance than the base plate, for example, because the top plate may be subject to thickness constraints and limitations in material selection for integration, thus limiting the performance of conventional MIM capacitors.

[0007] Figure 1A and Figure 1B Two examples of conventional MIM capacitor structures are shown. Figure 1A A conventional MIM capacitor 100A constructed on aluminum interconnects is shown. The MIM capacitor 100A includes an insulating layer 112A formed between an aluminum base plate 114A (top-1 metal layer) and a metal top plate 116A (e.g., Ti, TiN, or aluminum (Al)). The Al base plate 114A and the metal top plate 116A are each connected to corresponding contacts 120A and 122A (top metal layer) via one or more through-holes 124A and 126A, for example, each through-hole is formed by filling the via with tungsten or other suitable metal. The insulating layer 112A may, for example, have approximately A SiN layer of a certain thickness.

[0008] Figure 1B Another conventional MIM capacitor 100B constructed on a copper (Cu) interconnect is shown. The MIM capacitor 100B includes an insulating layer 112B formed between a Cu base plate 114B (top-1 metal layer) and a metal top plate 116B (e.g., Ta, TaN, or TiN). The Cu base plate 114B and the metal top plate 116B are each connected to corresponding contacts 120B and 122B (top metal layer) via one or more vias 124B and 126B, for example, each via is formed by filling the via with tungsten, copper, or other suitable metal. Similar to the capacitor 100A constructed on an Al interconnect, the insulating layer 112B of the capacitor 10B constructed on a Cu interconnect can be, for example, having approximately A SiN layer of a certain thickness. Layer 112B also serves as a dielectric diffusion barrier for the copper substrate 114B.

[0009] As used herein, "via" refers to a conductive via formed by blocking a through-hole or otherwise depositing a conductive material (e.g., tungsten) in the via, the via having a small diameter or width (e.g., less than 1 μm) and thus a relatively large resistance, e.g., at least 1 ohm per via. For example, conventional vias (e.g., Figure 1A and Figure 1B The vias 124A, 126A, 124B, and / or 126B shown typically have small diameters ranging from 0.1 μm to 0.5 μm, and can have a resistance of approximately 10 ohms per via, especially for vias formed of tungsten or other high-resistivity materials. Therefore, conventional MIM capacitors typically include multiple vias (e.g., multiple vias between top plates and top plate contacts and / or multiple vias between bottom plates and bottom plate contacts) to reduce the overall resistance to some extent. As used herein, in the context of MIM capacitors, "via connection" refers to a via extending from the capacitor plate (top or bottom plate) to the overlying conductive contacts.

[0010] Additionally, MIM capacitors are typically more expensive to build than certain other types of capacitors. For example, compared to POP capacitors and MOM capacitors, MIM capacitors usually require additional mask layers and many additional process steps. MIM capacitors also typically require a relatively large silicon area, resulting in inefficient area utilization, especially in the case of larger MIM capacitors.

[0011] Furthermore, in a conventional MIM capacitor 100B, the insulating layer 112B is in direct contact with the upper surface of the copper base plate 114B, resulting in a lower breakdown voltage typically due to the Cu lock (impact surface) at the upper surface of the base plate 114. For example, as... Figure 1B The "H" in the text indicates this. Furthermore, in conventional MIM capacitors, the top plate is thinner and therefore provides higher series resistance because the vertical thickness of the top plate is limited by the vertical distance between adjacent metal layers in which the MIM capacitor is formed (e.g., the top metal layer and the top-1 metal layer).

[0012] There is a need for MIM capacitors that can be manufactured at a lower cost, have improved space density, and have improved breakdown voltage. Summary of the Invention

[0013] An embodiment of the present invention provides a three-dimensional (3D) MIM capacitor formed in an integrated circuit structure. The 3D MIM capacitor may include:

[0014] (a) A bottom conductor, the bottom conductor comprising (i) a horizontally extending bottom plate portion and (ii) at least one vertically extending sidewall portion projecting upward from the bottom plate portion.

[0015] (b) Top conductor, and

[0016] (c) An insulating layer disposed between the horizontally extending base portion and the vertically extending sidewall portion of the top conductor and the bottom conductor.

[0017] Based on this structure, for example, with... Figure 1A and Figure 1B Compared to the conventional design shown, the top conductor is capacitively coupled to both the base plate portion and the sidewall portion of the bottom conductor, which defines a substantially larger capacitive coupling area between the top and bottom conductors.

[0018] Compared to existing "two-dimensional" (2D) MIM capacitors in which the capacitor extends only in a horizontal plane (x, y directions), the 3D MIM capacitor disclosed herein is referred to as "three-dimensional". The 3D MIM capacitor not only has a horizontal portion of the capacitor but also "sidewall" portions, in which the capacitor extends vertically (z direction). Therefore, the capacitor disclosed herein is referred to as 3D MIM because it extends in all three dimensions (x, y, and z).

[0019] In some implementations, the 3D MIM capacitor is constructed within a single layer between two adjacent metal interconnect layers (including these two adjacent metal interconnect layers) and is designated as a monolayer 3D MIM capacitor. In some implementations, the 3D MIM capacitor is constructed using multiple interconnect layers (involving two or more layers between two adjacent metal layers, and involving more than two adjacent metal interconnect layers) and is designated as a multilayer 3D MIM capacitor. Compared to monolayer 3D MIM capacitors, multilayer 3D MIM capacitors extend further in the vertical direction and achieve better area efficiency at the cost of process complexity.

[0020] Some embodiments provide a single-layer 3D MIM capacitor and a method of manufacturing it, while others provide a multi-layer 3D MIM capacitor and a method of manufacturing it. In some embodiments, the 3D MIM capacitor base plate is formed of copper and lined with W or TiN to improve breakage voltage (e.g., mitigate the negative effects from Cu locks), and the top plate is formed of aluminum, which can be fabricated simultaneously with the bonding pad metal and provides lower series resistance. In some embodiments, due to 3D integration, the 3D MIM capacitor exhibits significant area efficiency over conventional 2D MIM capacitors, and thus reduces cost.

[0021] In one aspect, a 3D MIM capacitor includes: (a) a bottom conductor including a base portion and at least one vertically extending sidewall portion extending upward from the base portion; (b) a top conductor and (c) an insulating layer disposed between the top conductor and the base portion of the bottom conductor and the at least one vertically extending sidewall portion.

[0022] In some implementations, the top conductor is formed in the bonding pad layer.

[0023] In some embodiments, the bottom conductor includes a cup-shaped portion formed on the base plate portion and includes the at least one vertically extending sidewall portion.

[0024] In some embodiments, the base portion of the bottom conductor comprises copper, the cup-shaped portion of the bottom conductor comprises tungsten or TiN, and the top conductor comprises aluminum.

[0025] In some implementations, the base portion of the bottom conductor is defined by a portion of a copper interconnect layer.

[0026] In some embodiments, at least one vertically extending sidewall portion of the bottom conductor includes elements of multiple metal layers of an integrated circuit device.

[0027] In some embodiments, at least one sidewall portion of the bottom conductor is formed in a wide barrel opening having a height-to-width ratio in the range of 0.5 to 2.0 (e.g., in the range of 0.8 to 1.2).

[0028] In some embodiments, the 3D MIM capacitor further includes bonding pads that are laterally offset from the top conductor and are electrically connected to the bottom conductor through at least a first vertically extending conductive via.

[0029] In some embodiments, the bonding pads are formed of the same material as the top conductor, and the conductive vias are formed of the same material as the at least one vertically extending sidewall portion of the bottom conductor.

[0030] In some embodiments, the vertically extending sidewall portion of the bottom conductor is formed in a bottom conductor opening, and the conductive via is formed in the via opening, wherein the lateral width of the bottom conductor opening is at least twice the lateral width of the conductive via. In some embodiments, the lateral width of the bottom conductor opening is at least five times the lateral width of the conductive via.

[0031] In some implementations, the bottom conductor opening and the conductive via are formed in a common passivation layer.

[0032] In some embodiments, at least one vertically extending sidewall portion of the bottom conductor is formed in a bottom conductor opening, at least a portion of the insulating layer is located in the bottom conductor opening, and at least a portion of the top conductor is located in the bottom conductor opening and covers at least a portion of the insulating layer. In some embodiments, the top conductor includes a first portion located above a top portion of the insulating layer and a second portion extending downward into the bottom conductor opening.

[0033] In some embodiments, the insulating layer is cup-shaped and defines an opening, and at least a portion of the top conductor is located in the opening of the cup-shaped insulating layer.

[0034] In another aspect, an integrated circuit device includes multiple electronic components and a 3DMIM capacitor as disclosed herein.

[0035] In another aspect, a method for forming a 3D MIM capacitor is provided. The method may include forming a base plate for a bottom conductor; forming at least one vertically extending sidewall portion of the bottom conductor extending upward from the base plate; forming an insulating layer having a first insulating portion on the base plate and at least one vertically extending second insulating portion on the at least one vertically extending sidewall portion of the bottom conductor; and forming a top conductor on the insulating layer such that the insulating layer is disposed between the top conductor and the base plate and the at least one vertically extending sidewall portion of the bottom conductor.

[0036] In some embodiments, forming a top conductor includes depositing a bonding pad layer and removing a portion of the bonding pad layer to define the top conductor and a plurality of bonding pads conductively connected to a plurality of integrated circuit elements, wherein the top conductor extends downward into an opening defined by the insulating layer.

[0037] In some embodiments, forming the bottom conductor plate includes forming a top metal layer that forms a multilayer interconnect structure, and removing portions of the top metal layer of the multilayer interconnect structure to define the bottom conductor plate.

[0038] In some embodiments, the method further includes forming a bottom conductor opening and a via opening laterally offset from the bottom conductor opening; forming a vertically extending sidewall portion of the bottom conductor in the bottom conductor opening; forming a conductive via in the via opening laterally offset from the bottom conductor opening; depositing a bonding pad layer; and removing a portion of the bonding pad layer to define (a) the top conductor and (b) a MIM bonding pad laterally offset from the top conductor and in contact with the conductive via, wherein the MIM bonding pad is electrically connected to the base plate of the bottom conductor through the conductive via.

[0039] In some embodiments, the method includes simultaneously forming the bottom conductor opening and the via opening, and simultaneously forming the vertically extending bottom conductor sidewall and the conductive via. Attached Figure Description

[0040] A more complete understanding of this disclosure can be obtained by referring to the following description taken in conjunction with the accompanying drawings, in which:

[0041] Figure 1A and Figure 1B Showing cross-sectional views of two conventional MIM capacitor structures;

[0042] Figure 2 A cross-sectional view showing a conventional structure of aluminum bonding pads connected to a copper interconnect structure via tungsten vias;

[0043] Figures 3A to 3C A cross-sectional view of an example single-layer 3D MIM capacitor according to an embodiment of the present invention is shown;

[0044] Figures 4A to 4I Demonstrating the formation of an embodiment according to the present invention Figures 3A to 3C The example process of the single-layer 3D MIM capacitor shown in the example is as follows; and

[0045] Figures 5A to 5H An example process for forming a multilayer 3D MIM capacitor according to one embodiment of the present invention is shown.

[0046] It should be understood that reference numerals for any illustrated element appearing in multiple different figures have the same meaning in all figures, and any illustrated element mentioned or discussed herein in the context of any particular figure also applies to every other figure (if any) in which the same illustrated element is shown. Detailed Implementation

[0047] In industry, copper (Cu) interconnects are typically terminated with aluminum (Al) bonding pads for full compatibility with conventional packaging processes. A set of tungsten (W) vias is usually used to connect the Al bonding pads to the top metal layer (MTOP) of the Cu interconnect. Figure 2 A cross-sectional view of a conventional structure 2000 showing an A1 bonding pad 220 connected to a Cu interconnect MTOP structure 202 via a W via 212 formed in a passivation layer 206.

[0048] Figures 3A to 3C An example of a single-layer 3D MIM capacitor 300 according to one embodiment of the present invention is jointly demonstrated. Specifically, Figure 3A Showing the first cross-sectional side view, Figure 3B Demonstration through Figure 3A The side view of the second cross-section cut by cutting line 3B-3B shown in the figure, and Figure 3C Demonstration through Figure 3A The image shows a top-view cross-sectional view taken along cutting line 3C-3C. Figures 3A to 3CTogether, the bottom conductor 301 of the MIM capacitor includes (a) a horizontally extending base plate 302 and (b) a cup-shaped conductor 314 formed on the base plate 302, having (i) a bottom portion 314A formed on the base plate 302 and (ii) a vertically extending sidewall portion 314B extending upward from the base plate 302. In some embodiments, the base plate 302 may be formed in a copper interconnect layer, such as a top copper interconnect layer referred to herein as a "Cu MTOP layer". The base plate 302 may be formed above a barrier layer 304 (e.g., a Ta or TaN barrier layer). The cup-shaped conductor 314 may be formed in a bottom conductor opening 310 formed in a passivation layer 306. The bottom conductor opening 310 may be a wide "barrel" opening, as discussed herein. The cup-shaped conductor 314 may be formed of tungsten (W) or other suitable materials, for example, of the same material as the conductive via 324, and formed simultaneously with the conductive via, as discussed below. The cup-shaped conductor 314 is in electrical contact with the base plate 302.

[0049] The 3D MIM capacitor 300 is called a "single-layer" MIM capacitor because it uses only a single metal interconnect layer to form the capacitor 300.

[0050] An insulating layer 320 is formed in the cup-shaped conductor 314 and includes (i) a bottom portion 320A formed on the bottom portion 314A of the cup-shaped conductor 314 and (ii) a sidewall portion 320B covering the vertically extending sidewall portion 314B of the cup-shaped conductor 314. The insulating layer 320 may be a conformal layer formed of SiN or other suitable dielectric material.

[0051] A top conductor 330 is formed above the insulating layer 320 and extends downward into a cup-shaped opening defined by the insulating layer 320, particularly by the top surface of the bottom portion 320A and the surface of the sidewall portion 320B. As shown, the cup-shaped conductor 314 of the bottom conductor 301 significantly increases the capacitance area between the top conductor 330 and the bottom conductor 301 through the horizontally extending bottom portion 320A and the vertically extending sidewall portion 320B of the insulating layer 320. The conductor 330 may be formed of aluminum or other suitable materials.

[0052] The bottom conductor 301 may also be electrically connected to the top-side bonding pad 334, for example, by connecting the bonding pad 334 to at least one conductive via 324 of the base plate 302. In some embodiments, the bottom conductor opening 310, in which the cup-shaped conductor 314 is formed, may be formed simultaneously with at least one narrow via opening in which at least one conductive via 324 is formed. The bottom conductor opening 310 and the via opening may be filled simultaneously, for example, by tungsten deposition, to form the cup-shaped conductor 314 and the conductive via 324.

[0053] like Figure 3C As shown in the diagram, from a top view, the bottom conductor opening 310, which forms a cup-shaped conductor 314 (followed by an insulating layer 320 and a top conductor 330), may have a square shape. In other embodiments, the barrel opening may have a square shape with rounded corners, a rectangular shape, a rectangular shape with rounded corners, a circular shape, an elliptical shape, a cross shape, or any other suitable shape.

[0054] like Figure 3A As shown, the three-dimensional structure of the MIM capacitor 300 not only defines the displacement current path through the bottom portion 320A of the insulating layer 320 (generally indicated by the dashed arrow CP), but also... 底部 The insulation layer 320A defines a displacement current path (generally indicated by the dashed arrow CP sidewall) through the vertically extending sidewall portion 320B of the insulating layer 320. Each insulating layer sidewall 320B provides an additional capacitive coupling region between the top conductor 330 and the bottom conductor 301. The bottom portion 320A of the insulating layer 320 effectively defines a plate capacitor, wherein the top and bottom plates extend horizontally, and each insulating layer sidewall 320B effectively defines an additional plate capacitor, wherein the top and bottom plates extend vertically. Thus, for example, compared to a conventional MIM capacitor, the three-dimensional structure of the MIM capacitor 300 thereby defines a significantly increased capacitive coupling region between the top conductor 330 and the bottom conductor 301.

[0055] Compared with existing IC manufacturing processes, Figures 3A to 3C The example 3D MIM capacitor 300 shown can be constructed using minimal additional process steps, such as only four additional process steps, including only one additional mask layer.

[0056] Figures 4A to 4I This illustration demonstrates an embodiment of the invention for forming a single-layer 3D MIM capacitor 450 (e.g., similar to...). Figures 3A to 3C The example shown is a cross-sectional view of an integrated circuit (IC) device using an example 3D MIM capacitor 300. Figures 4A to 4I The diagram shows cross-sectional views of an integrated circuit structure 400 under construction according to an embodiment of the present invention at two locations: a first location (labeled "bonding pad") where a first bonding pad (e.g., aluminum) is connected to a top interconnect layer (e.g., a Cu MTOP layer) via a conductive via, which is a typical process in integrated circuit construction; and a second location (labeled "3D MIM capacitor") forming a single-layer 3D MIM capacitor 450.

[0057] Figure 4AThis diagram shows a selected portion of the top interconnect layer 402 (e.g., a Cu MTOP layer) in the IC structure 400 under configuration. A first interconnect structure 402A of the top interconnect layer 402 is designated as a typical bonding pad, while a second interconnect structure 402B of the top interconnect layer 402 forms the substrate of the bottom conductor of the MIM capacitor 450 under configuration. Interconnect structures 402A and 402B may be formed over a corresponding barrier layer 404 (e.g., a Ta / TaN barrier layer), for example, through a process including Cu deposition on the barrier layer 404 followed by a copper CMP (chemical mechanical planarization) process.

[0058] like Figure 4B As shown, after forming the top interconnect layer 402, a passivation region 406 may be deposited over the top interconnect layer 402. The passivation region 406 may include a first passivation region portion 406A over the first interconnect structure 402A and a second passivation region portion 406B over the second interconnect structure 402B. The passivation region 406 is typically configured as a combination of multilayer dielectric films protecting the underlying active integrated circuit. For example, the passivation region 406 may include the following four layers deposited in the following order: (1) 0.1 μm silicon nitride, (2) 0.1 μm silicon-rich oxide (SRO), (3) 0.68 μm phosphosilicate glass (PSG) and (4) 0.59 μm silicon oxynitride (SiON).

[0059] Next, as Figure 4C As shown, a photoresist layer can be deposited and patterned, followed by at least one etching operation to define the number of via openings 408A, 408B and barrel openings 410 in the constructed 3D MIM capacitor 450. The via openings 408A, 408B and barrel openings 410 can be etched simultaneously. The shape and size of the barrel openings 410 can be selected based on various parameters, such as those for efficiently fabricating the MIM capacitor 450 (e.g., efficiently depositing a top plate material (e.g., aluminum) into the barrel openings 410) and / or for desired performance characteristics of the resulting MIM capacitor 450. In some embodiments, the barrel openings 410 can be formed to have a width W in the range of 1 μm to 10 μm. 桶 And the vertical height H in the range of 1μm to 10μm 桶 In some embodiments, the wide barrel opening 410 has a width ranging from 1 μm to 10 μm in the direction extending inward through the page, said width being comparable to the shown width W. 桶 The same applies, for example, in the case of a square or circular opening 410.

[0060] In some embodiments, the wide barrel opening 410 may be configured to have a height-to-width ratio (H) of less than or equal to 2.0. 桶 / W桶 For example, to allow efficient filling of the wide barrel opening 210 by means of conformal material. For example, the wide barrel opening 410 may be formed to have an aspect ratio H in the range of 0.1 to 2.0 (e.g., in the range of 0.5 to 2.0). 桶 / W 桶 In some embodiments, the wide barrel opening 410 may be configured to have an aspect ratio H of less than or equal to 1.5. 桶 / W 桶 For example, it can be used to effectively fill the barrel opening 210 with a conformal material. For instance, the wide barrel opening 410 may be formed to have an aspect ratio H in the range of 0.5 to 1.5, or more specifically in the range of 0.8 to 1.2. 桶 / W 桶 .

[0061] In some embodiments, the through-hole openings 408A and 408B may be formed to have a width W in the range of 0.1 μm to 0.8 μm. 通孔 The width W of the wide barrel opening is 410. 桶 The width W of the through-hole opening is greater than that of 408A and 408B. 通孔 For example, in some implementations, the width W of the wide barrel opening 410 桶 The width W of the through-hole openings 408A and 408B 通孔 At least twice the size. In a particular embodiment, the width W of the barrel opening 410 is... 桶 The width W of the through-hole openings 408A and 408B 通孔 It is at least five times larger.

[0062] Next, as Figure 4D As shown, a conductive conformal material 412 (e.g., TiN, W, or other suitable metal) is deposited over structure 400 such that the material 412 fills the via openings 408A, 408B to form one or more vias 424A, 424B, and forms a conformal layer on the bottom and sidewall surfaces of the wide barrel opening 410. Therefore, the conductive conformal material 412 is in electrical contact with the second interconnect structure 402B.

[0063] like Figure 4EAs shown, chemical mechanical planarization (CMP) can be performed to remove portions of conductive material (e.g., tungsten) 412 on the top side of structure 400, such as portions of material 412 outside via openings 408A, 408B and wide barrel opening 410. The remaining material 412 in barrel opening 410 defines a cup-shaped conductor 414, which includes a bottom portion 414A and sidewall portions 414B extending upward from the bottom portion 414A (i.e., extending upward from the base plate 402B). The cup-shaped conductor 414 (e.g., tungsten) and the underlying second interconnect structure 402B (e.g., copper) together define the bottom conductor 401 of the formed 3D MIM capacitor 450. As indicated above, the second interconnect structure 402B and the bottom portion 414A together form the base plate of the bottom conductor 401.

[0064] Next, as Figure 4F As shown, an insulating layer 420 (e.g., a silicon nitride (SiN) layer or other conformal dielectric material) is deposited over structure 400 and extends downward into the wide barrel opening 410, thereby covering the cup-shaped conductor 414. A bottom portion 420A of the insulating layer 420 is formed on the surface of the bottom portion 414A of the cup-shaped conductor 414, and a sidewall portion 420B of the insulating layer 420 is formed as a vertically extending sidewall portion 414B covering the cup-shaped conductor 414. The insulating layer 420 defines an insulating layer in the formed 3DMIM capacitor. The insulating layer 420 can have any suitable thickness, for example, in... to For example to For example to or about The thickness is within the range.

[0065] Next, as Figure 4G As shown, photoresist 418 can be deposited and etched (e.g., using an inexpensive i-line patterning stepper), followed by insulator etching to remove selected portions of the insulator layer 420 on the top side of the structure 400. Resin stripping can be performed to remove the remaining portion of photoresist 418.

[0066] Next, as Figure 4H As shown, a bonding pad metal 426, such as aluminum, can be deposited, which extends into the remaining unfilled portion of the wide barrel opening 410 to cover the insulating layer 420.

[0067] Finally, as Figure 4IAs shown, the bonding pad metal 426 (e.g., aluminum) can be patterned and etched to define bonding pads 428, 434 and a capacitor top conductor 430 extending downward into the wide barrel opening 410, thereby forming a single-layer 3DMIM capacitor 450. As shown, a second interconnect structure 402B (e.g., copper), forming part of the substrate, is electrically connected to the top bonding pad 434 via at least one conductive via 424B. Therefore, the capacitor top conductor 430 is formed in the bonding pad layer.

[0068] Figures 5A to 5H A cross-sectional view illustrating an example process according to an embodiment of the present invention for forming: (a) a multilayer 3D MIM capacitor 550 formed in a "3D MIM capacitor region", and (b) a nearby IC element 560 connected in an example IC device 500 to a top-side bonding pad 528 formed in a "bonding pad region". The completed multilayer 3D MIM capacitor 550 and the IC element 560 connected to the bonding pad 528 are discussed below. Figure 5H The 3D MIM capacitor 550 is described as a "multilayer" MIM capacitor because it uses multiple metal interconnect layers to form the multilayer 3D MIM capacitor 550. Specifically, as discussed below, the multilayer 3D MIM capacitor 550 uses three metal interconnect layers to form the cup-shaped bottom conductor of the capacitor. IC element 560 may include any type of integrated circuit element or component, such as a transistor, resistor, capacitor, inductor, diode, A / D converter, D / A converter, interconnect connected to one or more integrated circuit elements, or any other type of integrated circuit element. IC device 500 may include any number and type of IC elements 560.

[0069] First refer to Figure 5A The IC device 500 under construction includes a multilayer copper (Cu) interconnect structure 503, which includes Cu interconnect layers 503A, 503B, and 503C; and / or an additional lower layer (not shown); and a passivation region 506 deposited above the Cu interconnect structure 503. The top Cu interconnect layer 503C may be referred to as a Cu MTOP layer. As shown, the multilayer Cu interconnect structure 503 is configured to form (a) a cup-shaped conductor structure 502, which includes components 502A, 502B, and 502C formed in the Cu interconnect layers 503A, 503B, and 503C, respectively; and (b) IC element contacts 505 including components 505B and 505C formed in the Cu interconnect layers 503B and 503C, respectively. As shown, a barrier layer 504, such as a Ta / TaN barrier layer, may be deposited before depositing each respective Cu interconnect component.

[0070] A cup-shaped conductor structure 502 defines the cup-shaped bottom conductor of the formed 3D MIM capacitor 550. In the illustrated example, component 502A defines the base portion of the cup-shaped conductor structure 502 in the Cu interconnect layer 503A, component 502B is formed as a first copper ring in the Cu interconnect layer 503B, and component 502C is formed as a second copper ring in the Cu interconnect layer 503C. The first copper ring 502B and the second copper ring 502C can have any suitable shape (as viewed from above), such as circular, elliptical, square, rectangular, cross-shaped, or any other shape. The first copper ring 502B and the second copper ring 502C together define a sidewall extending upward from the base portion 502A and are in electrical contact with each other. Thus, in the illustrated embodiment, the two Cu interconnect layers 503B and 503C are used to form the vertically extending sidewall of the cup-shaped conductor structure 502 of the MIM capacitor 550. In other words, the height of the conductive sidewalls of the cup-shaped conductor structure 502 is two metal layers, and they are in electrical contact with the base plate of the cup-shaped conductor structure 502 formed in the Cu interconnect layer 503A, thereby forming a cup-shaped bottom conductor together. It should be understood that any number of metal interconnect layers (e.g., one, two (as shown), three, four, five, or more interconnect layers) can be used to form the vertically extending sidewalls of the cup-shaped conductor structure 502, for example, to provide a barrel opening 510 formed in the cup-shaped bottom conductor (see discussion below). Figure 5B The required height and width aspect ratio. That is to say, the height of the conductive sidewalls of the cup-shaped bottom conductor can be one, two, three, four, five or more metal layers.

[0071] In the illustrated embodiment, the top copper ring 502C may include an optional lateral extension, indicated by 502C', which is adapted to connect to the top-side bonding pad, as discussed below. Figure 5H As shown in the image.

[0072] like Figure 5B As shown, a photoresist layer 509 can be deposited and patterned, followed by etching to form a deep trench defining a wide barrel opening 510 in the cup-shaped conductor structure 502. In some embodiments, oxide etching can be used to efficiently etch multilayer deep trenches due to the high selectivity of oxide etching for Ta / TaN and Cu.

[0073] like Figure 5C As shown, a resist stripping process can be performed to remove the photoresist material 509, and a barrier layer 511 (e.g., a TiN liner) can be deposited over the IC device 500 and extend downward into the wide barrel opening 510. The barrier layer 511 may have... to or about The thickness is within the range.

[0074] like Figure 5D As shown, an insulating layer 512 (e.g., a SiN layer or other conformal material) is deposited above the barrier layer 511 and extends downward into the barrel opening 510. The deposited insulating layer 512 can have any suitable thickness, for example, in... to For example to For example to or about The thickness is within the range.

[0075] like Figure 5E As shown, a photoresist layer 518 can be deposited and patterned to form bonding pad openings 519 above structure 500. For example... Figure 5F As shown, bonding pad etching can be performed via bonding pad opening 519, insulating layer 512, barrier layer 511, and passivation layer 506 to expose selected surfaces of the top Cu interconnect layer 503C, particularly the top surfaces of components 505C and 502C as shown. In one embodiment, an optional lateral extension 502C' is exposed.

[0076] like Figure 5G As shown, a bonding pad metal 526, such as aluminum or other conformal metal, can be deposited, extending into the wide barrel opening 510 to cover the insulating layer 510. Similarly, the bonding pad metal 526 extends into the bonding pad opening 519 to contact components 502C and 505C, respectively. Thus, a portion of the bonding pad metal 526 is formed in the bonding pad layer, extending into the wide barrel opening 510, and forms the top conductor of the multilayer 3D MIM capacitor 550 as will be described below.

[0077] Finally, as Figure 5H As shown, bonding pad metal 526 (e.g., aluminum) can be patterned and etched to define (a) a top conductor 530 formed by a cup-shaped conductor 502 and a top-side bonding pad 534 of a multilayer 3D MIM capacitor 550, and (b) a bonding pad 528 connected to an IC component 560. The top-side bonding pad 534 of the multilayer 3D MIM capacitor 550 is connected to a lateral extension 502C' of the top copper ring 502C of the cup-shaped conductor 502. In other embodiments, the top-side bonding pad may be connected to any other component cup-shaped conductor 502. As shown, the top conductor 530 of the multilayer 3D MIM capacitor 550 includes a first portion 530A located above the top portion of the insulating layer 512 and a second portion 530B extending downward into a wide barrel opening 510.

Claims

1. An integrated circuit device, comprising: At least one integrated circuit element; as well as Metal-insulator-metal (MIM) capacitors include: The bottom conductor comprises: Base plate; and A cup-shaped conductor, the cup-shaped conductor being formed on the base plate and including a bottom portion and at least one vertically extending sidewall portion extending upward from the base plate; Top conductor; An insulating layer is disposed between the top conductor and the cup-shaped conductor; Bonding pads, the bonding pads being separate from and laterally spaced from the top conductor; and A conductive via, which is laterally spaced from the cup-shaped conductor and conductively connects the bonding pad to the base plate; The cup-shaped conductor includes a first metal layer that partially fills a first portion of the bottom conductor opening; and The conductive via includes a first portion of the conductive via opening completely filled by the first metal layer.

2. The integrated circuit device of claim 1, wherein the top conductor and the bonding pad are formed in a common bonding pad layer.

3. The integrated circuit device of claim 1, wherein the base plate comprises copper, the cup-shaped conductor comprises tungsten, and the top conductor comprises aluminum.

4. The integrated circuit device of claim 1, wherein the substrate is defined by a portion of a copper interconnect layer.

5. The integrated circuit device of claim 1, wherein the at least one vertically extending sidewall portion of the cup-shaped conductor comprises elements of a plurality of metal layers of the integrated circuit device.

6. The integrated circuit device of claim 1, wherein at least one sidewall portion of the cup-shaped conductor is formed in a wide barrel opening having a height-to-width ratio in the range of 0.5 to 2.

0.

7. The integrated circuit device of claim 1, wherein at least one sidewall portion of the cup-shaped conductor is formed in a wide barrel opening having a height-to-width ratio in the range of 0.8 to 1.

2.

8. The integrated circuit device according to claim 1, wherein: The bonding pads are formed of the same material as the top conductor; The conductive via is formed of the same material as the cup-shaped conductor.

9. The integrated circuit device according to claim 1, wherein: The at least one vertically extending sidewall portion of the cup-shaped conductor is formed in the bottom conductor opening; and The conductive via is formed in the via opening; The lateral width of the bottom conductor opening is at least twice the lateral width of the conductive via.

10. The integrated circuit device of claim 9, wherein the bottom conductor opening and the conductive via are formed in a passivation layer.

11. The integrated circuit device of claim 9, wherein the lateral width of the bottom conductor opening is at least five times greater than the lateral width of the conductive via.

12. The integrated circuit device according to claim 1, wherein: The at least one vertically extending sidewall portion of the cup-shaped conductor is formed in the bottom conductor opening; and At least a portion of the insulating layer is located in the bottom conductor opening; and At least a portion of the top conductor is located in the opening of the bottom conductor and covers at least a portion of the insulating layer.

13. The integrated circuit device of claim 12, wherein the top conductor comprises a first portion located above the top portion of the insulating layer and a second portion extending downward into the opening of the bottom conductor.

14. The integrated circuit device according to claim 1, wherein: The insulating layer is cup-shaped and defines an opening; and At least a portion of the top conductor is located in the opening of the cup-shaped insulating layer.

15. A method for forming a metal-insulator-metal (MIM) capacitor, the method comprising: The base plate that forms the bottom conductor; A cup-shaped conductor and a conductive via spaced laterally from the cup-shaped conductor are simultaneously formed above the base plate from the first metal layer, wherein the cup-shaped conductor and the conductive via are electrically connected to the base plate to define an electrical path through the base plate between the cup-shaped conductor and the conductive via. The cup-shaped conductor includes a bottom portion and at least one vertically extending sidewall portion extending upward from the bottom portion; An insulating layer is formed having a first insulating portion on the bottom portion of the cup-shaped conductor and at least one vertically extending second insulating portion on at least one vertically extending sidewall portion of the cup-shaped conductor. as well as A top conductor is formed on the insulating layer such that the insulating layer is disposed between the top conductor and the bottom conductor, the base plate, and the at least one vertically extending sidewall portion.

16. The method of claim 15, wherein forming the top conductor comprises: Deposited bonding pad layer; as well as A portion of the bonding pad layer is removed to define the top conductor and a plurality of bonding pads conductively connected to a plurality of integrated circuit elements, wherein the top conductor extends downward into an opening defined by the insulating layer.

17. The method of claim 16, wherein forming the base plate comprises: A top metal layer forming a multi-layer interconnect structure; as well as Remove a portion of the top metal layer of the multilayer interconnect structure to define the base plate.

18. The method according to any one of claims 15 to 17, further comprising: A bottom conductor opening and a through-hole opening offset laterally from the bottom conductor opening are formed; The simultaneous formation of the cup-shaped conductor and the conductive via includes: The first metal layer is deposited, and the deposited first metal layer extends into the bottom conductor opening and the via opening; as well as Remove the upper portion of the first metal layer, wherein the remaining portion of the first metal layer in the bottom conductor opening defines the cup-shaped conductor, and the remaining portion of the first metal layer in the via opening defines the conductive via.

19. The method of claim 18, wherein the method comprises: Simultaneously, the bottom conductor opening and the through hole opening are formed.

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