Server hardware power-on startup troubleshooting method, system, device and medium

Abstract

The application provides a server hardware power-on startup troubleshooting method, system, device and medium, the method comprises the following steps: using CPLD to control the power input control of each device on the mainboard in the server startup process, and monitoring the change state of the hardware signal all the time, and writing the fault information corresponding to the abnormal signal into the external EEPROM of the CPLD; logging in through the serial port or remotely accessing the baseboard management controller; reading the fault information of the EEPROM through the baseboard management controller and analyzing and displaying to the output end. The application can troubleshoot the corresponding fault reason in time when the server encounters a fault in the front and rear electric loading startup process.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and more specifically to a method, system, device, and medium for troubleshooting server hardware power-on startup failures. Background Technology

[0002] A typical server motherboard architecture is a hardware circuit assembly composed of core chips such as CPU, memory, PCH, BMC, and CPLD. The CPU is the core of a server's computing power, managed and scheduled by the operating system running on it. A CPLD is a programmable logic device that has a hardware controller bitstream programmed into it before the server leaves the factory, scheduling key hardware control and power control functions within the server. The BMC, also known as the board management controller, is the core of board-level hardware management and often undertakes important functions such as monitoring server hardware status and logging faults. Server startup consists of two processes: 1) the pre-power-on loading process, which is the process of powering on some components of the motherboard after the server hardware power supply is supplied, including the CPLD, BMC, and onboard core function chips; 2) the post-power-on loading process, which is the process of powering on the CPU and its peripheral power supply chips and function chips. The power-on process often requires the BIOS program to run hardware initialization operations before the operating system can be entered normally.

[0003] Currently, troubleshooting CPU startup failures is often done by the BIOS during the startup process. However, running the BIOS program often requires that important core chips such as the CPU, PCH, and VR chip are working properly before the server can start. This makes it impossible to promptly identify the cause of the failure when a fault occurs during the power-on and startup process of the server. Summary of the Invention

[0004] To address the above problems, the present invention aims to provide a method, system, device, and medium for troubleshooting server hardware power-on startup faults, which can promptly identify the cause of the fault when encountering faults during the power-on startup process of the server.

[0005] To achieve the above objectives, this invention provides the following technical solution: a method for troubleshooting server hardware power-on startup faults, comprising:

[0006] During server startup, the CPLD controls the power input of various components on the motherboard, monitors the changes in hardware signals throughout the process, and writes the fault information corresponding to abnormal signals into the CPLD's external EEPROM.

[0007] Serial port login or remote access to the baseboard management controller;

[0008] The fault information of the EEPROM is read by the baseboard management controller, parsed and displayed on the output terminal.

[0009] Furthermore, the method of using a CPLD to control the power input of various components on the motherboard during server startup, monitoring the changes in hardware signals throughout the process, and writing fault information corresponding to abnormal signals into the CPLD's external EEPROM includes:

[0010] The server controller starts running upon power-up, and the CPLD starts running its logic program upon power-up.

[0011] During the power-on process, the CPLD monitors the status of each power-on device. If a device malfunctions, it captures the relevant abnormal status and records it to the EEPROM according to the preset recording rules.

[0012] During the power-on process, the CPLD runs a logic program to power on the CPU, memory, and PCH one by one. During the power-on process, each power signal controls the power input in sequence. If the power-on process is abnormal, the signal information during this process is recorded in the EEPROM according to the preset recording rules.

[0013] Furthermore, the preset recording rules include recording using the device signal number plus the memory offset address.

[0014] Furthermore, the EEPROM memory address data is pre-divided by hardware into signals, with different areas storing fault information of power supply signals for different types of devices.

[0015] Furthermore, the step of reading fault information from the EEPROM via the baseboard controller, parsing it, and displaying it at the output includes:

[0016] The baseboard management controller sends a command to read startup fault information to the CPLD to determine if a startup fault has occurred; the baseboard management controller also sends an EEPROM information acquisition request command.

[0017] The baseboard management controller polls and monitors the CPLD and EEPROM bus status registers, and initiates fault information acquisition based on the status of these registers.

[0018] The baseboard management controller reads fault information from the EEPROM via the I2C interface. After successful reading, it sends a command to the CPLD indicating that the fault information acquisition is complete and manages the EEPROM access channel.

[0019] The baseboard management controller parses the startup fault code in the fault information, parses it into the corresponding fault type based on the data offset address and signal encoding, and displays the information at the output terminal.

[0020] Furthermore, the baseboard management controller sends a command to the CPLD to read startup fault information in order to determine that a startup fault has occurred, including:

[0021] If the CPLD fault information register is set, it indicates that a startup fault has occurred and the CPLD has detected the startup fault; otherwise, it indicates that there is no startup fault and exits directly.

[0022] Furthermore, the step of initiating fault information collection based on this register state includes:

[0023] If the register status is set, it indicates that the EEPROM is in an unqueryable read / write state; otherwise, it indicates that the EEPROM information acquisition instruction was successfully requested, and the baseboard management controller enters the fault information acquisition stage.

[0024] Accordingly, the present invention also discloses a server hardware power-on startup fault troubleshooting system, including: a status detection module, used to control the power input control of various devices on the motherboard using CPLD during the server startup process, monitor the changes in hardware signals throughout the process, and write the fault information corresponding to the abnormal signals into the external EEPROM of the CPLD;

[0025] The access module is used to log in or remotely access the baseboard management controller via serial port.

[0026] The parsing and display module is used to read the fault information of EEPROM through the baseboard management controller and parse and display it to the output terminal.

[0027] Accordingly, this invention discloses a server hardware power-on startup fault troubleshooting device, comprising:

[0028] The memory is used to store troubleshooting programs for server hardware power-on startup failures.

[0029] The processor is configured to implement the steps of the server hardware power-on startup fault troubleshooting method described above when executing the server hardware power-on startup fault troubleshooting program.

[0030] Accordingly, the present invention discloses a readable storage medium storing a server hardware power-on startup fault diagnosis program, wherein when the server hardware power-on startup fault diagnosis program is executed by a processor, it implements the steps of the server hardware power-on startup fault diagnosis method described in any of the above descriptions.

[0031] Compared with existing technologies, the advantages of this invention are as follows: This invention discloses a method, system, device, and medium for troubleshooting server hardware power-on startup faults. After the server controller is powered on, the CPLD device within the motherboard records the enable status of various hardware signals. If a hardware signal enable is abnormal, this signal is written into the external EEPROM of the CPLD device using a special code. Throughout the power-on startup process, the CPLD monitors the changes in important hardware signals within the motherboard until the entire server has powered on and the CPU enters the BIOS boot stage, and the x86 is in S5 power mode. If an abnormality occurs during this power-on process, the fault acquisition program can be run by logging into the BMC management interface via serial port or web page. The baseboard management controller reads the fault code stored in the external EEPROM of the CPLD and parses the cause of the current server power-on abnormality according to the encoding rules. This information is then fed back to the developers via file or message, thereby achieving the purpose of troubleshooting and locating server startup faults.

[0032] This invention enables rapid analysis and localization of server startup failures, providing R&D or maintenance personnel with an analysis and localization tool to quickly locate and resolve hardware failures such as power-on and component malfunctions that occur during the startup process.

[0033] Therefore, it is evident that the present invention has outstanding substantive features and significant progress compared with the prior art, and the beneficial effects of its implementation are also obvious. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0035] Figure 1 This is a flowchart illustrating a specific embodiment of the present invention.

[0036] Figure 2 This is a system structure diagram of a specific embodiment of the present invention.

[0037] In the diagram, 1 is the status detection module; 2 is the access module; and 3 is the parsing and display module. Detailed Implementation

[0038] The core of this invention is to provide a method for troubleshooting server hardware power-on startup faults. In the prior art, troubleshooting CPU startup fault records is often completed by the BIOS during the startup process. However, the conditions for running the BIOS program often require that important core chips such as the CPU, PCH, and VR chip are working properly before startup. Therefore, it is impossible to promptly troubleshoot the corresponding fault causes when encountering faults during the power-on and startup processes of the server.

[0039] The server hardware power-on startup fault troubleshooting method provided by this invention firstly uses a CPLD to control the power input of various important components on the motherboard during the server startup process. The CPLD saves fault information to an external EEPROM based on whether various hardware signals are abnormal. It achieves the recording function of startup hardware faults through a special encoding method using offset addresses and corresponding numbers. Simultaneously, a fault troubleshooting tool is provided on the board management controller side, which can read the fault information stored in the EEPROM through command interaction with the CPLD, and parse and display the startup fault information according to the hardware signal fault encoding rules. Therefore, this invention enables rapid analysis and location of server startup faults, providing R&D or maintenance personnel with an analysis and location tool to quickly locate and resolve hardware faults such as power-on failures and component anomalies during the startup process.

[0040] To enable those skilled in the art to better understand the present invention, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are merely some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0041] Example 1:

[0042] like Figure 1 As shown in the figure, this embodiment provides a method for troubleshooting server hardware power-on startup failures, including the following steps:

[0043] S1: During the server startup process, the CPLD is used to control the power input of each device on the motherboard, monitor the changes in hardware signals throughout the process, and write the fault information corresponding to abnormal signals into the external EEPROM of the CPLD.

[0044] Specifically, during the server startup process, the CPLD is used to control the power input of various important components on the motherboard. The CPLD saves fault information to the external EEPROM by checking whether various hardware signals are abnormal. It achieves the recording function of startup hardware faults through a special encoding method of offset address and corresponding number.

[0045] First, the signal recording process begins. After the CPLD powers on, it needs to power on various important components on the motherboard or monitor the status of the preceding devices. When an abnormal signal is detected, the startup signal information is written to the corresponding EEPROM memory address. The EEPROM memory address data is pre-divided by hardware, with different areas storing fault information for different types of device power supply signals. When a device malfunctions, the fault information is written to the corresponding memory address. During subsequent power-on, the power-on logic in the CPLD loads the power input of the CPU and surrounding devices sequentially according to the power supply timing sequence. When any timing abnormality occurs, the current timing stage and the fault signal type are specially encoded and written to a fixed EEPROM area.

[0046] As an example, the specific implementation process of this step is as follows:

[0047] 1. The server controller is powered on and running, and the CPLD is powered on and running its logic program.

[0048] 2. During the pre-power-on process, the CPLD monitors the status of each pre-power-on device. If a device malfunctions, the relevant abnormal status is captured and recorded in the EEPROM. The recording rule follows the format of device signal number plus memory offset address.

[0049] 3. During the power-on process, the CPLD runs its logic program to power on the CPU, memory, and PCH one by one. Each power signal controls the power input sequentially during power-on. If an abnormality occurs during power-on, the signal information is recorded in the EEPROM. The recording follows the format of device signal number plus memory offset address.

[0050] S2: Serial port login or remote access to the baseboard management controller.

[0051] In the field of server management, the baseboard management controller, as a core hardware management component, is responsible for the safe, reliable and stable operation of the entire server hardware. Therefore, the baseboard management controller can be used to troubleshoot hardware startup failures and provide developers with fault location tools.

[0052] S3: Read the fault information of EEPROM through the baseboard management controller, parse it and display it on the output terminal.

[0053] The purpose of this step is to provide a fault diagnosis tool on the BMC side, which can read the fault information stored in the EEPROM by interacting with the CPLD through instructions, and parse and display the startup fault information according to the hardware signal fault coding rules.

[0054] As an example, the process of reading EEPROM fault information through the baseboard management controller, parsing it, and displaying it at the output includes the following steps:

[0055] S31: The BMC sends a command to the CPLD to read the startup fault information. If the fault information register of the CPLD is set, it means that the CPLD has collected a startup fault. Otherwise, it indicates that there is no startup fault and exits.

[0056] S32: After the previous step reads that the current controller has failed, the BMC sends an EEPROM information acquisition request command.

[0057] S33: The BMC polls and monitors the CPLD and EEPROM bus status registers. When this register is set, it indicates that the EEPROM is in an unqueryable read / write state. Otherwise, it indicates that the EEPROM information acquisition instruction was successfully requested, and the BMC enters the fault information acquisition stage.

[0058] S34: The BMC successfully reads EEPROM information via the I2C interface and simultaneously sends a command indicating that fault information acquisition is complete. Upon receiving this command, the CPLD will manage the EEPROM access channel. If a 2-second timeout occurs during the acquisition process, the CPLD will also close this channel.

[0059] S35: The BMC program parses the startup fault code, parses it into the corresponding fault based on the data offset address and signal encoding, and displays the information.

[0060] This embodiment provides a method for troubleshooting server hardware power-on startup faults. After the server controller powers on, the CPLD device on the motherboard records the enable status of various hardware signals. If a hardware signal is abnormally enabled, this signal is written into the external EEPROM of the CPLD device using a special code. Throughout the power-on startup process, the CPLD monitors the changes in important hardware signals on the motherboard until the entire server has powered on and the CPU enters the BIOS boot stage, and the x86 is in S5 power mode. If an abnormality occurs during this power-on process, the fault acquisition program can be run by logging into the BMC management interface via serial port or web page. The baseboard management controller reads the fault code stored in the external EEPROM of the CPLD and parses it according to the encoding rules to determine the cause of the current server power-on abnormality. This information is then fed back to the developers via file or message, thereby achieving the purpose of troubleshooting and locating server startup faults.

[0061] Example 2:

[0062] Based on Example 1, such as Figure 2 As shown, the present invention also discloses a server hardware power-on startup fault troubleshooting system, including: a status detection module 1, an access module 2, and a parsing and display module 3.

[0063] Status detection module 1 is used to control the power input of various devices on the motherboard using CPLD during the server startup process, monitor the changes in hardware signals throughout the process, and write the fault information corresponding to abnormal signals into the external EEPROM of CPLD.

[0064] The status detection module 1 is specifically used for: the server controller powering on and running, and the CPLD powering on and running the logic program; during the pre-power-on process, the CPLD monitors the status of each pre-power-on device, and if a device is abnormal, it captures the relevant abnormal status and records it in the EEPROM according to the preset recording rules; during the post-power-on process, the CPLD runs the logic program to power on the CPU, memory, and PCH one by one, and each power signal controls the power input in sequence during the power-on process. If the power-on process is abnormal, the signal information during this process is recorded in the EEPROM according to the preset recording rules.

[0065] Access module 2 is used to log in or remotely access the baseboard management controller via serial port.

[0066] The parsing and display module 3 is used to read the fault information of EEPROM through the baseboard management controller and parse and display it to the output terminal.

[0067] The analysis and display module 3 is specifically used for: the baseboard management controller sending a command to read startup fault information to the CPLD to determine if a startup fault has occurred; the baseboard management controller sending an EEPROM information acquisition request command; the baseboard management controller polling and monitoring the CPLD and EEPROM bus status registers, and initiating fault information acquisition based on the status of these registers; the baseboard management controller reading the fault information in the EEPROM through the I2C interface, and after successful reading, sending a command to the CPLD indicating that fault information acquisition is complete, and managing the EEPROM access channel; the baseboard management controller parsing the startup fault code in the fault information, parsing it into the corresponding fault type based on the data offset address and signal encoding, and displaying the information at the output terminal.

[0068] This embodiment provides a server hardware power-on startup fault troubleshooting system. During server startup, a CPLD (Content Management Logic Controller) controls the power input of various critical components on the motherboard. The CPLD stores fault information in an external EEPROM based on anomalies in various hardware signals, using a special encoding method with offset addresses and corresponding numbers to record startup hardware faults. Simultaneously, a fault diagnosis tool is provided on the BMC (Browser Control Center) side. This tool can read the fault information stored in the EEPROM through command interaction with the CPLD, and parse and display the startup fault information according to hardware signal fault encoding rules.

[0069] Example 3:

[0070] This embodiment discloses a server hardware power-on startup fault diagnosis device, including a processor and a memory; wherein, when the processor executes the server hardware power-on startup fault diagnosis program stored in the memory, it performs the following steps:

[0071] 1. During the server startup process, the CPLD is used to control the power input of each component on the motherboard, monitor the changes in hardware signals throughout the process, and write the fault information corresponding to abnormal signals into the external EEPROM of the CPLD.

[0072] 2. Log in via serial port or access the baseboard management controller remotely.

[0073] 3. Read the fault information of EEPROM through the baseboard management controller, parse it and display it on the output terminal.

[0074] Furthermore, the server hardware power-on startup fault troubleshooting device in this embodiment may also include:

[0075] The input interface is used to acquire externally imported server hardware power-on startup troubleshooting programs and save these programs to the memory. It can also acquire various instructions and parameters transmitted from external terminal devices and transmit them to the processor, allowing the processor to perform corresponding processing using these instructions and parameters. In this embodiment, the input interface may specifically include, but is not limited to, a USB interface, a serial interface, a voice input interface, a fingerprint input interface, and a hard disk read interface.

[0076] An output interface is used to output various data generated by the processor to connected terminal devices, so that other terminal devices connected to the output interface can obtain the various data generated by the processor. In this embodiment, the output interface may include, but is not limited to, a USB interface, a serial interface, etc.

[0077] The communication unit is used to establish a remote communication connection between the server hardware power-on startup fault diagnosis device and the external server, so that the server hardware power-on startup fault diagnosis device can mount the image file to the external server. In this embodiment, the communication unit may specifically include, but is not limited to, a remote communication unit based on wireless communication technology or wired communication technology.

[0078] The keyboard is used to acquire various parameter data or commands input by the user through real-time keystrokes.

[0079] The monitor is used to display relevant information in real time regarding the process of locating a short circuit in the server's power supply line.

[0080] A mouse can be used to assist users in inputting data and simplifying user operations.

[0081] Example 4:

[0082] This embodiment also discloses a readable storage medium, which includes random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable hard disk, CD-ROM, or any other form of storage medium known in the art. The readable storage medium stores a server hardware power-on startup fault diagnosis program, which, when executed by a processor, performs the following steps:

[0083] 1. During the server startup process, the CPLD is used to control the power input of each component on the motherboard, monitor the changes in hardware signals throughout the process, and write the fault information corresponding to abnormal signals into the external EEPROM of the CPLD.

[0084] 2. Log in via serial port or access the baseboard management controller remotely.

[0085] 3. Read the fault information of EEPROM through the baseboard management controller, parse it and display it on the output terminal.

[0086] In summary, this invention enables rapid analysis and localization of server startup failures, providing R&D or maintenance personnel with an analysis and localization tool to quickly locate and resolve hardware failures such as power-on issues and component malfunctions that occur during the startup process.

[0087] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. The methods disclosed in the embodiments are described simply because they correspond to the systems disclosed in the embodiments; relevant details can be found in the method section.

[0088] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0089] In the embodiments provided by this invention, it should be understood that the disclosed systems, methods, and approaches can be implemented in other ways. For example, the system embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between systems or units may be electrical, mechanical, or other forms.

[0090] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0091] In addition, the functional modules in the various embodiments of the present invention can be integrated into one processing unit, or each module can exist physically separately, or two or more modules can be integrated into one unit.

[0092] Similarly, in the various embodiments of the present invention, each processing unit can be integrated into a functional module, or each processing unit can exist physically, or two or more processing units can be integrated into a functional module.

[0093] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0094] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0095] The foregoing has provided a detailed description of the server hardware power-on startup fault troubleshooting method, system, device, and readable storage medium provided by this invention. Specific examples have been used to illustrate the principles and implementation methods of this invention. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and core ideas of this invention. It should be noted that those skilled in the art can make various improvements and modifications to this invention without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this invention.

Claims

1. A method for troubleshooting server hardware power-on startup failures, characterized in that, include: During the server startup process, the CPLD is used to control the power input of each component on the motherboard, monitor the changes in hardware signals throughout the process, and write the fault information corresponding to abnormal signals into the external EEPROM of the CPLD. Serial port login or remote access to the baseboard management controller; The fault information of the EEPROM is read by the baseboard management controller, parsed and displayed to the output terminal; The process of using a CPLD to control the power input of various components on the motherboard during server startup, monitoring the changes in hardware signals throughout the process, and writing fault information corresponding to abnormal signals into the CPLD's external EEPROM includes: The server controller starts running upon power-up, and the CPLD starts running its logic program upon power-up. During the power-on process, the CPLD monitors the status of each power-on device. If a device malfunctions, it captures the relevant abnormal status and records it to the EEPROM according to the preset recording rules. During the power-on process, the CPLD runs a logic program to power on the CPU, memory, and PCH one by one. During the power-on process, each power signal controls the power input in sequence. If the power-on process is abnormal, the signal information during this process is recorded in the EEPROM according to the preset recording rules.

2. The method for troubleshooting server hardware power-on startup failures according to claim 1, characterized in that, The preset recording rules include recording using the device signal number plus the memory offset address.

3. The method for troubleshooting server hardware power-on startup failures according to claim 2, characterized in that, The memory address data of the EEPROM is pre-divided by hardware into signals, and different areas store fault information of power supply signals for different types of devices.

4. The method for troubleshooting server hardware power-on startup failures according to claim 1, characterized in that, The process of reading EEPROM fault information through the substrate management controller, parsing it, and displaying it at the output includes: The baseboard management controller sends a command to the CPLD to read startup fault information in order to determine if a startup fault has occurred. The substrate management controller sends an EEPROM information acquisition request command; The baseboard management controller polls and monitors the CPLD and EEPROM bus status registers, and initiates fault information acquisition based on the status of these registers. The baseboard management controller reads fault information from the EEPROM via the I2C interface. After successful reading, it sends a command to the CPLD indicating that the fault information acquisition is complete and manages the EEPROM access channel. The baseboard management controller parses the startup fault code in the fault information, parses it into the corresponding fault type based on the data offset address and signal encoding, and displays the information at the output terminal.

5. The method for troubleshooting server hardware power-on startup failures according to claim 4, characterized in that, The baseboard management controller sends a command to the CPLD to read startup fault information in order to determine if a startup fault has occurred, including: If the CPLD fault information register is set, it indicates that a startup fault has occurred and the CPLD has detected the startup fault; otherwise, it indicates that there is no startup fault and exits directly.

6. The method for troubleshooting server hardware power-on startup failures according to claim 4, characterized in that, The step of initiating fault information collection based on this register state includes: If the register status is set, it indicates that the EEPROM is in an unqueryable read / write state; otherwise, it indicates that the EEPROM information acquisition instruction was successfully requested, and the baseboard management controller enters the fault information acquisition stage.

7. A server hardware power-on startup fault troubleshooting system, characterized in that, include: The status detection module is used to control the power input of various components on the motherboard using CPLD during the server startup process, monitor the changes in hardware signals throughout the process, and write the fault information corresponding to abnormal signals into the external EEPROM of CPLD. The access module is used to log in or remotely access the baseboard management controller via serial port. The parsing and display module is used to read the fault information of EEPROM through the baseboard management controller and parse and display it to the output terminal; The process of using a CPLD to control the power input of various components on the motherboard during server startup, monitoring the changes in hardware signals throughout the process, and writing fault information corresponding to abnormal signals into the CPLD's external EEPROM includes: The server controller starts running upon power-up, and the CPLD starts running its logic program upon power-up. During the power-on process, the CPLD monitors the status of each power-on device. If a device malfunctions, it captures the relevant abnormal status and records it to the EEPROM according to the preset recording rules. During the power-on process, the CPLD runs a logic program to power on the CPU, memory, and PCH one by one. During the power-on process, each power signal controls the power input in sequence. If the power-on process is abnormal, the signal information during this process is recorded in the EEPROM according to the preset recording rules.

8. A server hardware power-on startup fault diagnosis device, characterized in that, include: The memory is used to store troubleshooting programs for server hardware power-on startup failures. A processor is configured to implement the steps of the server hardware power-on startup fault troubleshooting method as described in any one of claims 1 to 6 when executing the server hardware power-on startup fault troubleshooting program.

9. A readable storage medium, characterized in that: The readable storage medium stores a server hardware power-on startup fault diagnosis program, which, when executed by a processor, implements the steps of the server hardware power-on startup fault diagnosis method as described in any one of claims 1 to 6.

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