Error detection method and related apparatus

Abstract

The embodiment of the application discloses an error detection method, and relates to the technical field of computers, and the error detection method comprises the following steps: acquiring a first scheduling table of a first task, wherein the first scheduling table comprises a first test mode, and the first task is used for being executed within a target fault detection time interval (FDTI); if it is detected that the first test mode is not executed within the target FDTI, executing the first test mode within the target FDTI according to the first scheduling table (the test mode is related to a task executed in the FDTI). The application ensures that the same test mode is executed only once within the FDTI, and the test mode in the STL cannot be repeatedly executed, the load of a processor caused by the test mode is reduced, the time spent by the processor in detecting errors is reduced, and therefore the working efficiency of the processor is improved.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to an error detection method and related apparatus. Background Technology

[0002] In the field of computers, data processing devices may experience random hardware failures, such as permanent failures caused by short circuits or open circuits in integrated circuits, or temporary failures such as bit flips caused by exposure to natural radiation or particle impacts.

[0003] In certain applications with high safety requirements, such as the automotive industry where safety is paramount, error detection mechanisms can be provided for processors to ensure functional safety, detect hardware errors, and ensure safe operations are performed in the event of a hardware error.

[0004] Currently, related technologies detect errors in logic circuits by having the processor periodically execute test patterns from a Software Test Library (STL). However, since the STL contains a large number of test patterns, the periodic execution of these patterns by the processor leads to a high processor load, meaning the processor needs to spend a significant amount of time detecting errors, thus affecting its efficiency. Summary of the Invention

[0005] The first aspect of this application provides an error detection method for use in terminals with security requirements, such as vehicle terminals or control terminals in aerospace.

[0006] The method includes: obtaining a first schedule table for a first task, the first schedule table including a first test mode, the first test mode being used to detect errors in a target logic circuit, the target logic circuit being a logic circuit for executing the first task, the first task being used to be executed within a target fault detection time interval (FDTI);

[0007] The first task can be a task that needs to run within the target FDTI in the terminal, such as a process or thread that needs to run within the target FDTI in the terminal. The terminal can determine the first task by retrieving it from a task queue, where tasks are tasks that are ready to be executed but not yet executed (or tasks in a ready state). The terminal can determine the first task by obtaining its identifier (ID) or by determining it based on the data structure corresponding to the first task. The scheduling table corresponding to the first task can include at least one test mode (e.g., the first test mode and the second test mode mentioned in the embodiments of this application), which corresponds to the machine instruction code of the first task and is used to detect errors in the target logic circuit. The correspondence between the at least one test mode and the machine instruction code of the first task means that, based on the at least one test mode, error detection of the target logic circuit on which the machine instruction code of the first task depends can be achieved.

[0008] Detect whether the first test mode has been executed within the target FDTI; if it is detected that the first test mode has not been executed within the target FDTI, then execute the first test mode within the target FDTI according to the first scheduling table to detect errors in the target logic circuit;

[0009] There may be overlap between test pattern sets corresponding to different tasks within the same FDTI (i.e., the union of the two sets is not empty). To avoid repeated execution of test patterns within an FDTI cycle, the executed test patterns within the FDTI are analyzed to generate a reasonable schedule set. Before executing the test patterns included in the first schedule table, it is necessary to check whether the test patterns included in the first schedule table have already been executed within the current FDTI cycle. If they have already been executed, the execution of the test pattern can be skipped directly; otherwise, the test pattern can be executed.

[0010] In this application, the first test mode is executed only when it is the first time it needs to be executed in the target FDTI. If the first test mode has already been executed in the target FDTI, it will not be executed again in the target FDTI. This ensures that the same test mode is executed only once in the FDTI and will not be executed repeatedly. This reduces the load of the test modes in STL on the processor, reduces the time spent by the processor to detect errors, and thus improves the processor's working efficiency.

[0011] In some possible implementations, after executing the first test mode within the target FDTI, the method further includes: obtaining a second schedule table for a second task, the second schedule table including the first test mode, the target logic circuit being a logic circuit for executing the second task, the second task being executed within the target fault detection time interval FDTI; and skipping the execution of the first test mode within the target FDTI based on the fact that the first test mode has been executed within the target FDTI.

[0012] When the first test mode is to be executed for the first time in the target FDTI, the first test mode can be executed. If a second task (different from the first task) also needs to be executed in the FDTI, the second scheduling table of the second task can be obtained. The second scheduling table also includes the first test mode. Therefore, during task scheduling, the execution of the first test mode can be skipped in the target FDTI based on the fact that the first test mode has been executed in the target FDTI. This ensures that the first test mode is executed only once in the FDTI and is not executed repeatedly.

[0013] In some possible implementations, detecting whether the first test mode has been executed within the target FDTI includes: obtaining a first identifier corresponding to the first test mode, wherein the first identifier is used to indicate whether the first test mode has been executed within the target FDTI.

[0014] The first identifier can be represented by a bitmask (e.g., STLMask). For example, when the STLMask bit corresponding to the first test mode in the mask is 1, it indicates that the first test mode has been executed in the current FDTI period. When the STLMask bit corresponding to the first test mode in the mask is 0, it indicates that the first test mode has not been executed in the current FDTI period. During FDTI initialization, the first identifier STLMask is set to 0, and a timer is enabled with a timer period of FDTI. Each time the timer is triggered, the first identifier is reset to 0, and the timer is reset. For example, before executing the first task, it can be determined that the first test mode has not been executed within the target FDTI period based on the detection that the first identifier STLMask corresponding to the first test mode is 0.

[0015] In some possible implementations, detecting that the first test mode has not been executed within the target FDTI includes: detecting that a first identifier corresponding to the first test mode indicates that the first test mode has not been executed within the target FDTI; after executing the first test mode within the target FDTI, the method further includes: modifying the first identifier so that the first identifier indicates that the first test mode has been executed within the target FDTI.

[0016] In some possible implementations, after detecting that the first test mode has not been executed within the target FDTI, the method further includes: obtaining a second identifier corresponding to the first test mode, the second identifier being used to indicate whether the first test mode needs to be executed; before executing the first test mode within the target FDTI, the method further includes: detecting that the second identifier indicates that the first test mode needs to be executed.

[0017] Specifically, a second identifier can be used to indicate whether the first test mode needs to be executed. The first test mode is executed in the target FDTI only when the second identifier indicates that the first test mode needs to be executed. The second identifier is associated with the first identifier. The second identifier will only indicate that the first test mode needs to be executed when the first identifier indicates that the first test mode has not been executed in the target FDTI. When the first identifier indicates that the first test mode has been executed in the target FDTI, the second identifier indicates that the first test mode does not need to be executed.

[0018] In some possible implementations, after executing the first test mode within the target FDTI, the method further includes: modifying the second identifier such that the second identifier indicates that the first test mode does not need to be executed.

[0019] In some possible implementations, the target task includes a process or a thread.

[0020] A second aspect of this application provides a terminal, comprising: a processing unit and an acquisition unit; the acquisition unit is configured to acquire a first schedule table for a first task, the first schedule table including a first test mode, the first test mode being configured to detect errors in a target logic circuit, the target logic circuit being a logic circuit for executing the first task, the first task being executed within a target fault detection time interval (FDTI); the processing unit is configured to detect whether the first test mode has been executed within the target FDTI;

[0021] If it is detected that the first test mode has not been executed within the target FDTI, then the first test mode is executed within the target FDTI to detect errors in the target logic circuit.

[0022] In some possible implementations, the processing unit is further configured to skip the execution of the first test mode within the target FDTI if it is detected that the first test mode has been executed within the target FDTI.

[0023] In some possible implementations, the acquisition unit is further configured to acquire a second schedule table for a second task after executing the first test mode within the target FDTI, the second schedule table including the first test mode, the target logic circuit being a logic circuit for executing the second task, the second task being executed within the target fault detection time interval FDTI;

[0024] The processing unit is also configured to skip the execution of the first test mode within the target FDTI if the first test mode has been executed within the target FDTI.

[0025] In some possible implementations, the acquisition unit is further configured to acquire a first identifier corresponding to the first test mode, the first identifier being used to indicate whether the first test mode has been executed within the target FDTI.

[0026] In some possible implementations, the processing unit is further configured to detect that a first identifier corresponding to the first test mode indicates that the first test mode has not been executed within the target FDTI;

[0027] After the first test mode is executed within the target FDTI, the first identifier is modified so that the first identifier indicates that the first test mode has been executed within the target FDTI.

[0028] In some possible implementations, the processing unit is further configured to, after detecting that the first test mode has not been executed within the target FDTI, obtain a second identifier corresponding to the first test mode, the second identifier being used to indicate whether the first test mode needs to be executed;

[0029] Before executing the first test mode within the target FDTI, the second identifier is detected indicating that the first test mode needs to be executed.

[0030] In some possible implementations, the processing unit is further configured to modify the second identifier after executing the first test mode within the target FDTI, such that the second identifier indicates that the first test mode does not need to be executed.

[0031] In some possible implementations, the target task includes a process or a thread.

[0032] In this embodiment, the first test mode is executed only when it is the first time it needs to be executed in the target FDTI. If the first test mode has already been executed in the target FDTI, it will not be executed again in the target FDTI. This ensures that the same test mode is executed only once in the FDTI and will not be executed repeatedly, thereby reducing the load of the test modes in STL on the processor, reducing the time spent by the processor to detect errors, and thus improving the processor's working efficiency.

[0033] A third aspect of this application provides a terminal, the terminal comprising: a processor; the processor being configured to:

[0034] Obtain a first schedule table for a first task, the first schedule table including a first test mode, the first test mode being used to detect errors in a target logic circuit, the target logic circuit being a logic circuit used to execute the first task, the first task being used to be executed within a target fault detection time interval (FDTI).

[0035] Detect whether the first test mode has been executed within the target FDTI;

[0036] If it is detected that the first test mode has not been executed within the target FDTI, then the first test mode is executed within the target FDTI to detect errors in the target logic circuit.

[0037] In some possible implementations, the processor is further configured to:

[0038] If it is detected that the first test mode has been executed within the target FDTI, then the execution of the first test mode is skipped within the target FDTI.

[0039] In some possible implementations, the processor is further configured to:

[0040] After executing the first test mode within the target FDTI, a second schedule table for the second task is obtained. The second schedule table includes the first test mode. The target logic circuit is a logic circuit for executing the second task, which is used to be executed within the target fault detection time interval FDTI.

[0041] Since the first test mode has been executed within the target FDTI, the execution of the first test mode is skipped within the target FDTI.

[0042] In some possible implementations, the processor is specifically used for:

[0043] Obtain the first identifier corresponding to the first test mode, the first identifier being used to indicate whether the first test mode has been executed within the target FDTI.

[0044] In some possible implementations, the processor is specifically used for:

[0045] The detection of the first identifier corresponding to the first test mode indicates that the first test mode has not been executed within the target FDTI;

[0046] After the first test mode is executed within the target FDTI, the first identifier is modified so that the first identifier indicates that the first test mode has been executed within the target FDTI.

[0047] In some possible implementations, the processor is further configured to:

[0048] After detecting that the first test mode has not been executed within the target FDTI, the second identifier corresponding to the first test mode is obtained. The second identifier is used to indicate whether the first test mode needs to be executed.

[0049] Before executing the first test mode within the target FDTI, the second identifier is detected indicating that the first test mode needs to be executed.

[0050] In some possible implementations, the processor is further configured to:

[0051] After the first test mode is executed within the target FDTI, the second identifier is modified so that the second identifier indicates that the first test mode does not need to be executed.

[0052] In some possible implementations, the target task includes a process or a thread.

[0053] A fourth aspect of this application provides a computer-readable storage medium storing a computer program that, when run on a computer, causes the computer to perform a method as described in any of the implementations of the first aspect.

[0054] The fifth aspect of this application provides a computer program product that, when run on a computer, causes the computer to perform a method as implemented in any of the first aspects.

[0055] A sixth aspect of this application provides a chip including one or more processors. Part or all of the processors are used to read and execute a computer program stored in a memory to perform the methods in any possible implementation of any of the above aspects. Optionally, the chip includes a memory, which is connected to the processor via a circuit or wire. Further optionally, the chip also includes a communication interface, to which the processor is connected. The communication interface is used to receive data and / or information to be processed, the processor obtains the data and / or information from the communication interface, processes the data and / or information, and outputs the processing result through the communication interface. The communication interface can be an input / output interface. The methods provided in this application can be implemented by a single chip or by multiple chips working together.

[0056] This application provides an error detection method, comprising: obtaining a first scheduling table for a first task, the first scheduling table including a first test mode, the first test mode being used to detect errors in a target logic circuit, the target logic circuit being a logic circuit used to execute the first task, the first task being used to be executed within a target fault detection time interval (FDTI); detecting whether the first test mode has been executed within the target FDTI; if it is detected that the first test mode has not been executed within the target FDTI, then according to the first scheduling table, executing the first test mode within the target FDTI to detect errors in the target logic circuit. The first test mode is only executed when it is the first time it needs to be executed within the target FDTI, and if the first test mode has already been executed within the target FDTI, it will not be executed again within the target FDTI. This ensures that the same test mode is executed only once within the FDTI, and is not repeatedly executed, reducing the load of the test modes in the STL on the processor, reducing the time spent by the processor in detecting errors, and thus improving the processor's efficiency. Attached Figure Description

[0057] Figure 1a A schematic diagram of FDTI and FHTI provided for embodiments of this application;

[0058] Figure 1b This is a schematic diagram of the structure of a terminal provided in an embodiment of this application;

[0059] Figure 1c A schematic diagram of an application architecture provided for an embodiment of this application;

[0060] Figure 2 A flowchart illustrating an error detection method provided in an embodiment of this application;

[0061] Figure 3A flowchart illustrating an error detection method provided in an embodiment of this application;

[0062] Figure 4 A flowchart illustrating an error detection method provided in an embodiment of this application;

[0063] Figure 5 A flowchart illustrating an error detection method provided in an embodiment of this application;

[0064] Figure 6 A schematic diagram illustrating an error detection method provided in an embodiment of this application;

[0065] Figure 7 A flowchart illustrating an error detection method provided in an embodiment of this application;

[0066] Figure 8 A schematic diagram illustrating an error detection method provided in an embodiment of this application;

[0067] Figure 9 A schematic diagram of a state transition provided in an embodiment of this application;

[0068] Figure 10 and Figure 11 This is a schematic diagram of the structure of a terminal provided in an embodiment of this application. Detailed Implementation

[0069] The embodiments of this application are described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. As those skilled in the art will recognize, with the development of technology and the emergence of new scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.

[0070] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in a sequence other than that illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or device that includes a series of steps or modules is not necessarily limited to those explicitly listed, but may include other steps or modules not explicitly listed or inherent to such processes, methods, products, or devices. The naming or numbering of steps appearing in this application does not imply that the steps in the method flow must be performed in the chronological / logical order indicated by the naming or numbering. The execution order of named or numbered process steps can be changed according to the desired technical purpose, as long as the same or similar technical effect is achieved.

[0071] In the field of computers, data processing devices may experience random hardware failures, such as permanent failures caused by short circuits or open circuits in integrated circuits, or temporary failures such as bit flips caused by exposure to natural radiation or particle impacts.

[0072] With the widespread application of data processing devices in numerous fields, the concept of "functional safety" has been proposed to avoid losses caused by hardware failures in these devices. Functional safety refers to the absence of unacceptable risks due to electronic system failures, and its ultimate goal is to prevent personal injury or significant property damage caused by electronic system malfunctions.

[0073] In fields with high safety requirements, such as aerospace, transportation, and healthcare, corresponding safety mechanisms are in place to meet functional safety requirements. These mechanisms must ensure that the system reaches a safe state after detecting an error to prevent harm. For example, in the automotive industry, typical safety risks are often caused by errors in the electronic control units (ECUs) of anti-lock braking systems (ABS) or power steering systems. Errors in these ECUs can lead to fatal collisions. To ensure the system reaches a safe state and prevent safety incidents, it is necessary to detect and address errors promptly.

[0074] In simple terms, when a system error occurs, the safety mechanism must detect the error and handle it promptly to ensure the system reaches a safe state before a dangerous situation arises. Typically, the time interval from the occurrence of an error to its detection is called the Fault Detection Time Interval (FDTI); the interval from error detection to the system reaching a safe state is called the Fault Handling Time Interval (FHTI). For example, see [link to relevant documentation]. Figure 1a , Figure 1a This diagram illustrates an FDTI and FHTI provided in an embodiment of this application. To avoid danger, after a system error occurs, the system must reach a safe state within a certain period; that is, the sum of the FDTI and FHTI must be less than or equal to a certain time threshold. Therefore, to ensure a sufficiently long FHTI to handle errors and guarantee successful error processing, minimizing the FDTI is crucial.

[0075] Currently, one method for error detection in related technologies is Dual-core Lockstep (DCLS). DCLS works by having two processors run the same program and inputting their outputs into a comparison logic to determine if they are identical. If the outputs are the same, no error has occurred; if they are different, an error has occurred. While this method effectively detects errors, it requires two processors to run the same program, resulting in high cost and poor flexibility.

[0076] Therefore, another software-based error detection method has been provided in related technologies: software-based built-in self-test (SBIST). This method detects errors in logic circuits by having the processor periodically execute test modes in the STL. Compared to DCLS, this method is less costly and more flexible. However, since systems often have a large number of logic circuits, the STL typically includes many test modes to detect errors in all of them. Therefore, the processor's periodic execution of these STL test modes leads to a high processor load, meaning the processor needs to spend a significant amount of time detecting errors, thus impacting processor efficiency.

[0077] Therefore, during error detection, the terminal can determine the scheduling table corresponding to the currently running task and execute the test modes included in that scheduling table. Since the scheduling table only includes test modes corresponding to the machine instruction code of the task, the terminal can avoid executing all test modes in the software test library by detecting errors based on this scheduling table, thereby reducing the processor load and effectively improving the processor's efficiency.

[0078] Reference Figure 1c SBIST scheduling can be divided into two parts: Low-level (LL) scheduling and High-level (HL) scheduling. LL scheduling primarily handles context saving and restoration for test mode switching within the STL, as well as the invocation of specific test modes. HL scheduling treats SBIST as a single task. Since the full STL process is time-consuming, which significantly impacts system real-time performance, introducing HL Scheduler into the kernel increases scheduling flexibility, making it more suitable for real-time systems and the preferred approach.

[0079] However, in existing implementations, the HL scheduler obtains the runtime and cycle of STL in a relatively coarse-grained manner, with limited awareness of test patterns in STL, making fine-grained control impossible. Within a single FDTI, there may be multiple tasks that need to be executed, and within the FDTI, the test patterns corresponding to each of these multiple tasks need to be executed. However, the test patterns corresponding to different tasks may overlap. If the test patterns corresponding to each task need to be executed completely within the FDTI, multiple duplicate test models may be executed. Since the same test pattern only needs to be executed once within an FDTI to ensure system safety, the above-mentioned SBIST scheduling method will cause the SBIST task to block for a long time, resulting in a large processor load. That is, the processor needs to spend more time detecting errors, thus affecting the processor's working efficiency.

[0080] The terminals involved in the embodiments of this application can be devices used for data processing in fields with security requirements. Examples of such terminals include: vehicle-mounted terminals in transportation, control terminals in aerospace, wireless terminals in industrial control, wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, and wireless terminals in smart homes.

[0081] Please refer to Figure 1b , Figure 1b This is a schematic diagram of the structure of a terminal 101 provided in an embodiment of this application.

[0082] like Figure 1b As shown, terminal 101 includes a processor 103, which is coupled to a system bus 105. The processor 103 can be one or more processors, each of which can include one or more processor cores. A video adapter 107 drives a display 109, which is coupled to the system bus 105. The system bus 105 is coupled to an input / output (I / O) bus via a bus bridge 111. An I / O interface 115 is coupled to the I / O bus. The I / O interface 115 communicates with various I / O devices, such as an input device 117 (e.g., a touchscreen), a media tray 121 (e.g., a compact disc read-only memory, CD-ROM, multimedia interface, etc.), a transceiver 123 (capable of sending and / or receiving radio communication signals), a camera 155 (capable of capturing still and moving digital video images), and an external USB port 125. Optionally, the interface connected to the I / O interface 115 can be a USB interface.

[0083] The processor 103 can be any conventional processor, including a reduced instruction set computing (RISC) processor, a complex instruction set computing (CISC) processor, or a combination thereof. Optionally, the processor can be a special-purpose device such as an ASIC.

[0084] Terminal 101 can communicate with software deployment server 149 via network interface 129. Exemplarily, network interface 129 is a hardware network interface, such as a network interface card (NIC). Network 127 can be an external network, such as the Internet, or an internal network, such as Ethernet or a virtual private network (VPN). Optionally, network 127 can also be a wireless network, such as a WiFi network or a cellular network.

[0085] Hard disk drive interface 131 is coupled to system bus 105. Hardware driver interface is connected to hard disk drive 133. System memory 135 is coupled to system bus 105. Data running in system memory 135 may include the operating system (OS) 137, applications 143, and schedules of terminal 101.

[0086] An operating system consists of the Shell 139 and the kernel 141. The Shell 139 is an interface between the user and the operating system kernel. The shell is the outermost layer of the operating system. The shell manages the interaction between the user and the operating system: waiting for user input, interpreting user input for the operating system, and processing various operating system outputs.

[0087] Kernel 141 consists of the parts of the operating system used to manage memory, files, peripherals, and system resources. Kernel 141 interacts directly with the hardware. The operating system kernel typically runs processes and provides inter-process communication, CPU time-slice management, interrupts, memory management, I / O management, and so on.

[0088] For example, when terminal 101 is an in-vehicle terminal, application 143 includes programs related to controlling vehicle driving, such as programs managing the interaction between the autonomous vehicle and obstacles on the road, programs controlling the autonomous vehicle's route or speed, and programs controlling the interaction between the autonomous vehicle and other autonomous vehicles on the road. In one embodiment, when application 143 needs to be executed, terminal 101 can download application 143 from software deployment server 149. In one embodiment, when terminal 101 downloads application 143 from software deployment server 149, terminal 101 may also download a schedule corresponding to application 143 from software deployment server 149.

[0089] Sensor 153 is associated with terminal 101. Sensor 153 is used to detect the environment around terminal 101. For example, sensor 153 can detect animals, cars, obstacles, and pedestrian crossings, etc. Furthermore, sensor 153 can also detect the environment around the aforementioned animals, cars, obstacles, and pedestrian crossings, such as the environment around the animals, for example, other animals around the animals, weather conditions, ambient light levels, etc. Optionally, if terminal 101 is located on an autonomous vehicle, the sensor can be a radar system, etc.

[0090] The above describes the application scenarios of the error detection method provided in the embodiments of this application. The following will describe in detail the execution process of the error detection method.

[0091] Please refer to Figure 2 , Figure 2 This is a flowchart illustrating an error detection method 200 provided in an embodiment of this application. Figure 2 As shown, the error detection method 200 includes the following steps.

[0092] Step 201: Obtain the first scheduling table of the first task. The first scheduling table includes a first test mode. The first test mode is used to detect errors in the target logic circuit. The target logic circuit is a logic circuit used to execute the first task. The first task is used to be executed within the target fault detection time interval (FDTI).

[0093] In this embodiment, during normal operation of the terminal, the terminal can periodically execute the error detection method 200, for example, every 30 milliseconds or 50 milliseconds, to ensure that errors that have occurred can be detected in a timely manner.

[0094] In one possible embodiment, the first task can be a task that needs to run within the target FDTI in the terminal, such as a process or thread that needs to run within the target FDTI in the terminal. The terminal can determine the first task by retrieving it from a task queue, where tasks are tasks that are ready to be executed but have not yet been executed (or tasks in a ready state). The terminal can determine the first task by obtaining its identifier (ID), or by determining the first task based on the data structure corresponding to the first task, such as by determining which thread the first task is based on its thread ID. For example, if the first task is a process, it could be a vehicle video inspection process, a vehicle speed calculation process, a radar detection process, a vehicle anti-lock braking system process, or a tire pressure monitoring process, etc.

[0095] In one possible implementation, in a nondeterministic scheduling scenario, the scheduler does not predict the tasks to be executed in the next FDTI. It only becomes aware of which task to execute next in real time after entering the FDTI. Therefore, a priority preemption method is set for SBIST tasks. In the FDTI, before the execution of each ordinary task (non-SBIST task), the corresponding STL subset (including at least one test mode) will be executed uninterruptedly. In this scenario, the scheduler can be aware of the tasks to be executed in the current FDTI in real time, and thus be aware of the first task.

[0096] In one possible implementation, in a deterministic scheduling scenario, the scheduler can predict the tasks that need to be executed within the next FDTI. To ensure deterministic scheduling, most tasks need to statically determine the worst-case execution time (WCET) to determine the priority order. Therefore, in this scenario, SBIST tasks are not suitable for defaulting to high priority, but should be adapted to the scheduling algorithm and arranged deterministically. In this scenario, the scheduler can perceive the tasks that need to be executed within the FDTI before the current FDTI, and thus perceive the first task.

[0097] In this embodiment, each runnable task in the terminal can have a corresponding scheduling table. These scheduling tables can be pre-installed in the terminal or generated by the terminal based on the machine instruction code of the task. Therefore, the terminal can determine the first scheduling table corresponding to the first task from multiple scheduling tables. For example, if the first task is a process, the terminal can determine the first scheduling table corresponding to it based on the process ID.

[0098] The scheduling table corresponding to the first task may include at least one test mode (e.g., the first test mode and the second test mode mentioned in the embodiments of this application), which corresponds to the machine instruction code of the first task and is used to detect errors in the target logic circuit. The correspondence between the at least one test mode and the machine instruction code of the first task means that, based on the at least one test mode, error detection of the target logic circuit on which the machine instruction code of the first task depends can be achieved.

[0099] In simple terms, when a terminal executes machine instruction code, it relies on the logic circuits within the terminal; that is, it executes machine instruction code based on the logic circuits. Therefore, given that at least one test mode corresponds to the machine instruction code of the first task, the logic circuits used by the terminal when executing the machine instruction code of the first task can all be used to detect errors based on that at least one test mode.

[0100] It is understandable that if an error occurs in the logic circuitry required for the first task during its execution on the terminal, this error could pose a security risk. Therefore, executing a test mode based on the scheduling table corresponding to the first task can detect errors in the required logic circuitry, thus preventing security risks. For other logic circuits, since the terminal is not currently executing any tasks and therefore does not require their use, errors in these circuits will not pose a security risk.

[0101] In one possible embodiment, at least one test mode in the first scheduling table is determined based on a first mapping relationship and at least one instruction type. The first mapping relationship includes a mapping relationship between instruction types and test modes. The at least one instruction type is determined based on a second mapping relationship and a set of machine instruction codes for the target task. The second mapping relationship includes a mapping relationship between machine instruction codes and instruction types. The set of machine instruction codes includes multiple machine instruction codes. For example, the first test mode can be determined based on the aforementioned first mapping relationship and at least one instruction type.

[0102] Reference Figure 3 In the preprocessing stage: the system can scan the tasks during operation, and generate a corresponding schedule table for each task (each schedule table includes at least one test mode). During the STL scheduling analysis, the HL scheduler analyzes the SBIST test sequence in the current period based on the task queue information, FDTI time, and the schedule table of each task generated in the preprocessing stage. During the STL scheduling generation, the analysis results are processed by the generator to generate a set of STL test modes to be scheduled. During the LL scheduling process, the STL test set passed by HL is scheduled and run at the highest privilege level through LL scheduling.

[0103] Step 202: Detect whether the first test mode has been executed within the target FDTI.

[0104] In one possible embodiment, after obtaining the first schedule table of the first task, it can be detected whether the first test mode has been executed within the target FDTI.

[0105] In this embodiment, there may be overlap between test mode sets corresponding to different tasks within the same FDTI (i.e., the union of the two sets is not empty). To avoid repeated execution of test modes within an FDTI cycle, the executed test modes within the FDTI are analyzed to generate a reasonable scheduling set.

[0106] In one possible embodiment, before executing the test mode included in the first schedule, it is necessary to check whether the test mode included in the first schedule has been executed in the current FDTI cycle. If it has been executed, the execution of the test mode can be skipped directly. If it has not been executed, the test mode can be executed.

[0107] The following describes how to detect whether the first test mode has been executed within the target FDTI;

[0108] In one possible embodiment, a first identifier can be used to indicate whether the first test mode has been executed within the target FDTI. During FDTI initialization, the first identifier can indicate that the first test mode has not been executed within the target FDTI, while after the first test mode is executed for the first time in the FDTI, the first identifier can be modified to indicate that the first test mode has been executed within the target FDTI.

[0109] For example, before performing the first task, it can be determined that the first test mode has not been executed in the target FDTI based on the detection that the first identifier corresponding to the first test mode indicates that the first test mode has not been executed in the target FDTI.

[0110] For example, the first identifier can be represented by a bitmask (e.g., the bitmask can be STLMask). For instance, when the bit corresponding to the first test mode in the mask is 1, it indicates that the first test mode has been executed in the current FDTI period; when the bit corresponding to the first test mode in the mask is 0, it indicates that the first test mode has not been executed in the current FDTI period. During FDTI initialization, the first identifier STLMask is set to 0, and a timer is enabled with a timer period of FDTI. Each time the timer is triggered, the first identifier is reset to 0, and the timer is reset. For example, before executing the first task, it can be determined that the first test mode has not been executed within the target FDTI based on the detection that the first identifier STLMask corresponding to the first test mode is 0.

[0111] In addition, a second identifier can be used to indicate whether the first test mode needs to be executed. The first test mode is executed in the target FDTI only when the second identifier indicates that the first test mode needs to be executed. The second identifier is associated with the first identifier. The second identifier will only indicate that the first test mode needs to be executed when the first identifier indicates that the first test mode has not been executed in the target FDTI. When the first identifier indicates that the first test mode has been executed in the target FDTI, the second identifier indicates that the first test mode does not need to be executed.

[0112] For example, before executing the first task, it can be determined that the first test mode needs to be executed based on the detection that the second identifier indicates that the first test mode needs to be executed.

[0113] For example, refer to Figure 4 The second identifier can be represented by a bitmask (for example, the bitmask can be STLNeedExcuteMask). When the bit STLNeedExcuteMask corresponding to the first test mode in the mask is 1, it means that the first test mode still needs to be executed in the current FDTI cycle. When the bit STLNeedExcuteMask corresponding to the first test mode in the mask is 0, it means that the first test mode does not need to be executed in the current FDTI cycle.

[0114] During FDTI initialization, the second identifier STLNeedExcuteMask is set to 0, and a timer is enabled with a timer period of FDTI. Each time the timer is triggered, the second identifier STLNeedExcuteMask is reset to 0, and the timer is reset. For example, before executing the first task, it can be determined that the first test mode needs to be executed based on the detection that the second identifier STLNeedExcuteMask corresponding to the first test mode is 1.

[0115] Step 203: If it is detected that the first test mode has not been executed in the target FDTI, then according to the first scheduling table, the first test mode is executed in the target FDTI to detect errors in the target logic circuit.

[0116] In this embodiment, if it is detected that the first test mode has not been executed within the target FDTI, the first test mode can be executed within the target FDTI according to the first scheduling table. If it is detected that the first test mode has been executed within the target FDTI, the execution of the first test mode is skipped within the target FDTI. That is, the first test mode will only be executed when it is the first time it needs to be executed within the target FDTI, and if the first test mode has already been executed within the target FDTI, it will not be executed again within the target FDTI.

[0117] In one possible embodiment, when the first test mode is to be executed for the first time in the target FDTI, the first test mode can be executed. If a second task (different from the first task) also needs to be executed in the FDTI, a second scheduling table for the second task can be obtained. The second scheduling table also includes the first test mode. Then, during task scheduling, the execution of the first test mode can be skipped in the target FDTI based on the fact that the first test mode has been executed in the target FDTI, so that the first test mode is executed only once in the FDTI and is not executed repeatedly.

[0118] In one possible embodiment, after executing the first test mode within the target FDTI, the first identifier can be modified such that it indicates the first test mode has been executed within the target FDTI. Similarly, after executing the first test mode within the target FDTI, the second identifier can be modified such that it indicates the first test mode does not need to be executed. For example, based on the second identifier indicating the first test mode does not need to be executed, the execution of the first test mode can be skipped within the target FDTI, thereby ensuring the first test mode is executed only once within the FDTI and is not executed repeatedly.

[0119] For example, refer to Figure 5 In nondeterministic scheduling scenarios, the scheduler cannot predict the tasks to be executed within the next FDTI. It only becomes aware of the next task upon entering the FDTI. Therefore, a priority preemption mechanism is implemented for SBIST tasks. Within the FDTI, each regular task (non-SBIST task) executes its corresponding STL subset (including at least one test mode) uninterruptedly before execution. In this scenario, the scheduler can perceive the tasks to be executed within the current FDTI in real time, thus identifying the tasks. The scheduler schedules a task in the ready state from the task queue, obtains its taskID, and finds the corresponding STL subset (test mode set) based on the taskID. For each test mode in the STL subset, the STLMask is used to determine whether the test mode has been executed within the current FDTI period. If the test has already been executed, proceed to the next round of checks. If it has not been executed, set the corresponding bit in `STLNeedExcuteMask` to 1, execute the test mode, and set the bits in `STLMask` and `STLNeedExcuteMask` corresponding to the executed test modes to "executed" and "not required," respectively. This process continues until all test modes have been traversed. After the SBIST task of the currently scheduled task has been completed, the scheduled task can continue to be executed. Other tasks in the task queue are then executed sequentially.

[0120] Reference Figure 6 The horizontal axis represents time, and the vertical axis represents task priority. Each colored square represents a CPU time slice occupied by a task in the current time. One FDTI cycle begins at the origin and ends at the dashed line. Within this cycle, when tasks 1, 2, and 3 are scheduled by the scheduler, the corresponding SBSIT task will run first. The SBSIT task runs the set of STL test patterns associated with the task. The SBSIT task has a higher priority, and the test sequence cannot be interrupted. During the FDTI scheduling time, the test pattern subsets of each task are guaranteed to be unique. For example, before executing task 3, the test pattern subset corresponding to task 3 can be executed (excluding test patterns in the test pattern subset corresponding to task 2).

[0121] For example, refer to Figure 7 In deterministic scheduling scenarios, the scheduler can predict the tasks to be executed within the next FDTI. To ensure deterministic scheduling, most tasks need to statically determine their worst-case execution time (WCET) to determine their priority. Therefore, in this scenario, SBIST tasks are not suitable for default high priority; instead, they should be adapted to the scheduling algorithm and arranged deterministically. In this scenario, the scheduler can detect tasks to be executed within the current FDTI before the current FDTI. The scheduler can schedule a task in the ready state from the task queue. If the task is a normal task, it will be executed. Specifically, the scheduler can obtain the task ID, find the corresponding STL set (set of test modes) based on the task ID, and determine whether the current FDTI has timed out. If it has not timed out, for each test mode in the STL subset, it can determine whether the test mode has been executed within the current FDTI period based on the STLMask. If it has been executed, the next round of judgment is performed until all test modes have been traversed. If not executed, set the corresponding bit in STLNeedExcuteMask to 1. If a timeout occurs, reset all bits of STLmask to 0. If the scheduled task is an SBIST task, execute the SBIST test sequence according to STLNeedExcuteMask, and set the corresponding bit in STLNeedExcuteMask to 0 and the corresponding bit in STLmask to 1 after execution.

[0122] In the embodiments of this application, reference is made to Figure 9The test patterns in the SBIST task can be divided into three states: (not executed, not required), (not executed, required), and (executed, not required). The initial state is (not executed, not required). After passing through the analyzer, the test pattern state remains in its original state or (not executed, required). After the test pattern is executed, the state of (not executed, required) is changed to (executed, not required).

[0123] As shown in the table below, compared with the prior art SBIST scheduling, the SBIST test sequence running time in the present invention is shortened by about 75%.

[0124] STL execution time 4.205ms 1.005ms

[0125] This application provides an error detection method, comprising: obtaining a first scheduling table for a first task, the first scheduling table including a first test mode, the first test mode being used to detect errors in a target logic circuit, the target logic circuit being a logic circuit used to execute the first task, the first task being used to be executed within a target fault detection time interval (FDTI); detecting whether the first test mode has been executed within the target FDTI; if it is detected that the first test mode has not been executed within the target FDTI, then according to the first scheduling table, executing the first test mode within the target FDTI to detect errors in the target logic circuit. The first test mode is only executed when it is the first time it needs to be executed within the target FDTI, and if the first test mode has already been executed within the target FDTI, it will not be executed again within the target FDTI. This ensures that the same test mode is executed only once within the FDTI, and is not repeatedly executed, reducing the load of the test modes in the STL on the processor, reducing the time spent by the processor in detecting errors, and thus improving the processor's efficiency.

[0126] exist Figures 1a to 9 Based on the corresponding embodiments, in order to better implement the above-described solutions of the embodiments of this application, related equipment for implementing the above solutions is also provided below. For details, please refer to... Figure 10 , Figure 10This is a schematic diagram of the structure of a terminal 1000 provided in an embodiment of this application. The terminal 1000 includes a processing unit 1001 and an acquisition unit 1002. The acquisition unit 1002 is used to acquire a first scheduling table for a first task. The first scheduling table includes a first test mode. The first test mode is used to detect errors in a target logic circuit. The target logic circuit is a logic circuit used to execute the first task. The first task is used to be executed within a target fault detection time interval (FDTI). The processing unit 1001 is used to detect whether the first test mode has been executed within the target FDTI.

[0127] If it is detected that the first test mode has not been executed within the target FDTI, then the first test mode is executed within the target FDTI to detect errors in the target logic circuit.

[0128] In some possible implementations, the processing unit 1001 is further configured to skip the execution of the first test mode within the target FDTI if it is detected that the first test mode has been executed within the target FDTI.

[0129] In some possible implementations, the acquisition unit 1002 is further configured to acquire a second schedule table for the second task after executing the first test mode within the target FDTI, the second schedule table including the first test mode, the target logic circuit being a logic circuit for executing the second task, the second task being executed within the target fault detection time interval FDTI;

[0130] The processing unit 1001 is also configured to skip the execution of the first test mode within the target FDTI if the first test mode has been executed within the target FDTI.

[0131] In some possible implementations, the acquisition unit 1002 is further configured to acquire a first identifier corresponding to the first test mode, the first identifier being used to indicate whether the first test mode has been executed within the target FDTI.

[0132] In some possible implementations, the processing unit 1001 is further configured to detect that a first identifier corresponding to the first test mode indicates that the first test mode has not been executed within the target FDTI;

[0133] After the first test mode is executed within the target FDTI, the first identifier is modified so that the first identifier indicates that the first test mode has been executed within the target FDTI.

[0134] In some possible implementations, the processing unit 1001 is further configured to, after detecting that the first test mode has not been executed within the target FDTI, obtain a second identifier corresponding to the first test mode, the second identifier being used to indicate whether the first test mode needs to be executed;

[0135] Before executing the first test mode within the target FDTI, the second identifier is detected indicating that the first test mode needs to be executed.

[0136] In some possible implementations, the processing unit 1001 is further configured to modify the second identifier after executing the first test mode within the target FDTI, such that the second identifier indicates that the first test mode does not need to be executed.

[0137] In some possible implementations, the target task includes a process or a thread.

[0138] In this embodiment, the first test mode is executed only when it is the first time it needs to be executed in the target FDTI. If the first test mode has already been executed in the target FDTI, it will not be executed again in the target FDTI. This ensures that the same test mode is executed only once in the FDTI and will not be executed repeatedly. This reduces the load of the test modes in STL on the processor, reduces the time spent by the processor to detect errors, and thus improves the processor's working efficiency.

[0139] The following describes a terminal device provided in an embodiment of this application. The terminal device can be... Figure 11 For information recommendation devices, please refer to [link / reference]. Figure 11 , Figure 11 This is a schematic diagram of a terminal device provided in an embodiment of this application. The terminal device 1100 can specifically be a virtual reality (VR) device, a mobile phone, a tablet, a laptop computer, a smart wearable device, etc., and is not limited thereto. Specifically, the terminal device 1100 includes: a receiver 1101, a transmitter 1102, a processor 1103, and a memory 1104 (wherein the number of processors 1103 in the terminal device 1100 can be one or more). Figure 11 (Taking a processor as an example), processor 1103 may include application processor 11031 and communication processor 11032. In some embodiments of this application, receiver 1101, transmitter 1102, processor 1103 and memory 1104 may be connected via bus or other means.

[0140] Memory 1104 may include read-only memory and random access memory, and provides instructions and data to processor 1103. A portion of memory 1104 may also include non-volatile random access memory (NVRAM). Memory 1104 stores processor and operation instructions, executable modules, or data structures, or subsets thereof, or extended sets thereof, wherein the operation instructions may include various operation instructions for implementing various operations.

[0141] Processor 1103 controls the operation of the terminal device. In specific applications, the various components of the terminal device are coupled together through a bus system, which may include not only the data bus, but also power buses, control buses, and status signal buses. However, for clarity, all buses are referred to as the bus system in the diagram.

[0142] The methods disclosed in the embodiments of this application can be applied to or implemented by the processor 1103. The processor 1103 can be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method can be completed by the integrated logic circuitry in the hardware of the processor 1103 or by instructions in software form. The processor 1103 can be a general-purpose processor, a digital signal processor (DSP), a microprocessor, or a microcontroller, and may further include an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The processor 1103 can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly embodied in the execution of a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software module can reside in a mature storage medium in the art, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, or registers. This storage medium is located in memory 1104. Processor 1103 reads the information in memory 1104 and, in conjunction with its hardware, completes the steps of the above method. Specifically, processor 1103 can read the information in memory 1104 and, in conjunction with its hardware, complete the data processing-related steps 201 to 203 in the above embodiments.

[0143] Receiver 1101 can be used to receive input digital or character information, and to generate signal inputs related to the settings and function control of the terminal device. Transmitter 1102 can be used to output digital or character information through the first interface; transmitter 1102 can also be used to send instructions to the disk group through the first interface to modify the data in the disk group.

[0144] This application also provides a computer program product that, when run on a computer, causes the computer to perform the functions described in the above embodiments. Figure 2 The steps of the error detection method described in the corresponding embodiment.

[0145] This application also provides a computer-readable storage medium storing a program for performing signal processing, which, when run on a computer, causes the computer to execute the steps of the image processing method as described in the foregoing embodiments.

[0146] The image display device provided in this application embodiment can specifically be a chip, which includes a processing unit and a communication unit. The processing unit can be, for example, a processor, and the communication unit can be, for example, an input / output interface, pins, or circuits. The processing unit can execute computer execution instructions stored in the storage unit to cause the chip in the execution device to execute the data processing method described in the above embodiments, or to cause the chip in the training device to execute the data processing method described in the above embodiments. Optionally, the storage unit is a storage unit within the chip, such as a register or cache. Alternatively, the storage unit can be a storage unit located outside the chip within the wireless access device, such as a read-only memory (ROM) or other types of static storage devices capable of storing static information and instructions, such as random access memory (RAM).

[0147] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0148] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection between apparatuses or units through some interfaces, and may be electrical, mechanical, or other forms.

[0149] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0150] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0151] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory, random access memory, magnetic disks, or optical disks.

Claims

1. An error detection method, characterized in that, include: Obtain a first schedule table for a first task, the first schedule table including a first test mode, the first test mode being used to detect errors in a target logic circuit, the target logic circuit being a logic circuit used to execute the first task, the first task being used to be executed within a target fault detection time interval (FDTI). Detect whether the first test mode has been executed within the target FDTI; If it is detected that the first test mode has not been executed in the target FDTI, then the first test mode is executed in the target FDTI according to the first scheduling table; Obtain a second scheduling table for the second task, the second scheduling table including the first test mode, the target logic circuit being a logic circuit for executing the second task, the second task being executed within the target fault detection time interval (FDTI); Since the first test mode has been executed within the target FDTI, the execution of the first test mode is skipped within the target FDTI.

2. The error detection method according to claim 1, characterized in that, The method further includes: If it is detected that the first test mode has been executed within the target FDTI, then the execution of the first test mode is skipped within the target FDTI.

3. The error detection method according to claim 1 or 2, characterized in that, After executing the first test mode within the target FDTI, the method further includes: Obtain a second scheduling table for the second task, the second scheduling table including the first test mode, the target logic circuit being a logic circuit for executing the second task, the second task being executed within the target fault detection time interval (FDTI); Since the first test mode has been executed within the target FDTI, the execution of the first test mode is skipped within the target FDTI.

4. The error detection method according to any one of claims 1 to 2, characterized in that, The detection of whether the first test mode has been executed within the target FDTI includes: Obtain the first identifier corresponding to the first test mode, the first identifier being used to indicate whether the first test mode has been executed within the target FDTI.

5. The error detection method according to claim 4, characterized in that, The detection that the first test mode has not been executed within the target FDTI includes: The detection of the first identifier corresponding to the first test mode indicates that the first test mode has not been executed within the target FDTI; After executing the first test mode within the target FDTI, the method further includes: Modify the first identifier so that it indicates that the first test mode was executed within the target FDTI.

6. The error detection method according to any one of claims 1 to 2, characterized in that, After detecting that the first test mode has not been executed within the target FDTI, the method further includes: Obtain the second identifier corresponding to the first test mode, the second identifier being used to indicate whether the first test mode needs to be executed; Before executing the first test mode within the target FDTI, the method further includes: The second identifier indicates that the first test mode needs to be executed.

7. The error detection method according to claim 6, characterized in that, After executing the first test mode within the target FDTI, the method further includes: Modify the second identifier so that it indicates the first test mode does not need to be executed.

8. The error detection method according to any one of claims 1 to 2, characterized in that, The target task includes a process or a thread.

9. A terminal, characterized in that, Includes a processor; the processor is used for: Obtain a first schedule table for a first task, the first schedule table including a first test mode, the first test mode being used to detect errors in a target logic circuit, the target logic circuit being a logic circuit used to execute the first task, the first task being used to be executed within a target fault detection time interval (FDTI). Detect whether the first test mode has been executed within the target FDTI; If it is detected that the first test mode has not been executed within the target FDTI, then the first test mode is executed within the target FDTI; The processor is also used for: Obtain a second scheduling table for the second task, the second scheduling table including the first test mode, the target logic circuit being a logic circuit for executing the second task, the second task being executed within the target fault detection time interval (FDTI); Since the first test mode has been executed within the target FDTI, the execution of the first test mode is skipped within the target FDTI.

10. The terminal according to claim 9, characterized in that, The processor is also used for: If it is detected that the first test mode has been executed within the target FDTI, then the execution of the first test mode is skipped within the target FDTI.

11. The terminal according to claim 9 or 10, characterized in that, The processor is also used for: After executing the first test mode within the target FDTI, a second schedule table for the second task is obtained. The second schedule table includes the first test mode. The target logic circuit is a logic circuit for executing the second task, which is used to be executed within the target fault detection time interval FDTI. Since the first test mode has been executed within the target FDTI, the execution of the first test mode is skipped within the target FDTI.

12. The terminal according to any one of claims 9 to 10, characterized in that, The processor is specifically used for: Obtain the first identifier corresponding to the first test mode, the first identifier being used to indicate whether the first test mode has been executed within the target FDTI.

13. The terminal according to claim 12, characterized in that, The processor is specifically used for: The detection of the first identifier corresponding to the first test mode indicates that the first test mode has not been executed within the target FDTI; After the first test mode is executed within the target FDTI, the first identifier is modified so that the first identifier indicates that the first test mode has been executed within the target FDTI.

14. The terminal according to any one of claims 9 to 10, characterized in that, The processor is also used for: After detecting that the first test mode has not been executed within the target FDTI, the second identifier corresponding to the first test mode is obtained. The second identifier is used to indicate whether the first test mode needs to be executed. Before executing the first test mode within the target FDTI, the second identifier is detected indicating that the first test mode needs to be executed.

15. The terminal according to claim 14, characterized in that, The processor is also used for: After the first test mode is executed within the target FDTI, the second identifier is modified so that the second identifier indicates that the first test mode does not need to be executed.

16. The terminal according to any one of claims 9 to 10, characterized in that, The target task includes a process or a thread.

17. A computer-readable storage medium, characterized in that, It includes computer-readable instructions that, when executed on a computer, cause the computer to perform the method as described in any one of claims 1 to 8.

18. A computer program product, characterized in that, Includes computer-readable instructions, which, when executed on a computer, cause the computer to perform the method as described in any one of claims 1 to 8.

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