Function verification method and device, electronic equipment and storage medium

Abstract

The present disclosure relates to a function verification method and device, electronic equipment and computer readable storage medium, and relates to the technical field of semiconductor production and manufacturing, and can be applied to the function verification scene of a chip to be designed. The method comprises: obtaining an initial design circuit corresponding to a chip to be designed; determining all test counter values contained in the chip to be designed based on the initial design circuit; randomly selecting a specified number of target test counter values from all test counter values; and performing function verification on the initial design circuit of the chip to be designed based on the target test counter values to obtain a function verification result. The present disclosure can perform function verification on the chip to be designed by compressing part of the target test counter values obtained by the internal counter, thereby greatly reducing the read-write scan times, reducing the function simulation and verification time, and improving the work efficiency.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing technology, and more specifically, to a functional verification method, a functional verification apparatus, an electronic device, and a computer-readable storage medium. Background Technology

[0002] Dynamic Random Access Memory (DRAM) requires automated testing methods for functional verification during the design process. DRAM functional verification includes verification of the Memory Build-In-Self Test (MBIST) function; "built-in" means that the test vectors for the memory are not generated by external testing equipment, but are automatically generated by the built-in memory test logic, and the results are compared.

[0003] The MBIST function requires reading and writing to all rows and columns of DRAM to detect bad pixels. Due to the large addressing range of DRAM and the slow read and write speed, the whole chip level simulation time is inevitably long and the simulation file is particularly large.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this disclosure is to provide a functional verification method, a functional verification device, an electronic device, and a computer-readable storage medium, thereby overcoming, to at least a certain extent, the problem that due to the large addressing range and slow read / write speed of DRAM, scanning all row and column addresses of DRAM results in very slow simulation speed and a large memory space occupied by simulation files.

[0006] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part by practice of the invention.

[0007] According to a first aspect of this disclosure, a functional verification method is provided, comprising: obtaining an initial design circuit corresponding to a chip to be designed; determining all test count values ​​contained in the chip to be designed based on the initial design circuit; randomly selecting a specified number of target test count values ​​from all the test count values; and performing functional verification on the initial design circuit of the chip to be designed based on the target test count values ​​to obtain a functional verification result.

[0008] In one exemplary embodiment of this disclosure, obtaining the initial design circuit corresponding to the chip to be designed includes: obtaining the functional specification file corresponding to the chip to be designed, and generating the initial design circuit according to the functional specification file.

[0009] In one exemplary embodiment of this disclosure, the step of performing functional verification on the initial design circuit of the chip to be designed based on the target test count value to obtain a functional verification result includes: generating a circuit simulation netlist based on the initial design circuit; performing functional verification on the initial design circuit according to the circuit simulation netlist and the target test count value to obtain a circuit verification result; and using the initial design circuit whose circuit verification result is passed as the target design circuit.

[0010] In one exemplary embodiment of this disclosure, the step of performing functional verification on the initial design circuit based on the circuit simulation netlist and the target test count value to obtain a circuit verification result includes: generating simulation detection data based on the target test count value, the simulation detection data including a simulation detection input waveform, each target test count value corresponding to a random verification address in the initial design circuit; performing functional simulation verification on the random verification address in the initial design circuit based on the simulation detection input waveform and the circuit simulation netlist to obtain a simulation verification waveform; and determining the circuit verification result of the initial design circuit based on the simulation verification waveform.

[0011] In one exemplary embodiment of this disclosure, determining all test count values ​​contained in the chip to be designed based on the initial design circuit includes: determining all address types corresponding to the chip to be designed based on the initial design circuit; each address type corresponds to at least one binary counter circuit; determining an addressing interval corresponding to each address type, the addressing interval being associated with the counting range of the binary counter circuit; and determining all test count values ​​contained in each addressing address type in the chip to be designed based on the addressing interval corresponding to each addressing address type.

[0012] In one exemplary embodiment of this disclosure, randomly selecting a specified number of target test counts from all the test counts includes: determining a first preset number of header test addresses and tail test addresses based on each addressing address type; determining a random reference address corresponding to each addressing address type; determining a second preset number of random test addresses corresponding to each addressing interval based on the random reference addresses; and determining the target test count value corresponding to each addressing address type based on the obtained header test address, tail test address, and random test address.

[0013] In one exemplary embodiment of this disclosure, determining a first preset number of header test addresses and tail test addresses based on each of the addressing address types includes: obtaining the start address and end address in the addressing interval corresponding to each of the addressing address types; determining the first preset number of consecutive header test addresses based on the start address; and determining the first preset number of consecutive tail test addresses based on the end address.

[0014] In one exemplary embodiment of this disclosure, determining the random reference address corresponding to each of the addressing address types includes: obtaining the current system time; determining a time value to be identified based on the addressing range of the addressing address type and the current system time; converting the time value to be identified into a corresponding address conversion value; and determining the random reference address based on the address conversion value.

[0015] In one exemplary embodiment of this disclosure, the time value to be identified includes a minute time value, a second time value, and a millisecond time value; the step of converting the time value to be identified into a corresponding address conversion value includes: determining the parity of the value at each time digit in the minute time value, the second time value, and the millisecond time value; determining the correspondence between each time digit and the address conversion value; if the value at the time digit is odd, then configuring the address conversion value corresponding to the time digit as a first value; if the value at the time digit is even, then configuring the address conversion value corresponding to the time digit as a second value.

[0016] In one exemplary embodiment of this disclosure, converting the time value to be identified into a corresponding address conversion value includes: determining the original time value or the padding time value corresponding to each time bit in the time value to be identified; the padding time value is generated based on at least one bit of the original time value; determining the address conversion value according to the parity of each original time value and the padding time value; if the original time value or the padding time value is odd, then configuring the corresponding address conversion value as a first value; if the original time value or the padding time value is even, then configuring the corresponding address conversion value as a second value.

[0017] In one exemplary embodiment of this disclosure, determining the original time value or the padding time value corresponding to each time bit in the time value to be identified includes: determining the original time bit and the padding time bit corresponding to the time value to be identified; taking the time value at each original time bit as the corresponding original time value; taking the original time bit associated with each padding time bit as the corresponding associated time bit; obtaining the associated time value at each associated time bit; and determining the padding time value at the corresponding padding time bit based on each associated time value.

[0018] In one exemplary embodiment of this disclosure, the address type includes a segmented address type; determining a first preset number of header test addresses and tail test addresses based on each address type includes: segmenting the address type to be segmented to obtain segmented address addresses; and determining the corresponding header test address, tail test address, and random test address according to each segmented address.

[0019] In one exemplary embodiment of this disclosure, the address type includes any one or more combinations of row address, column address, bank address, and bank group address.

[0020] In one exemplary embodiment of this disclosure, the method further includes: if the functional verification result is passed, then performing a coverage verification process on the target design circuit to obtain a corresponding coverage verification result; if the coverage verification result is passed, then performing a regression verification process to obtain a corresponding regression verification result; if the regression verification result is passed, then performing a termination verification process to obtain a corresponding termination verification result; wherein the coverage verification process, the regression verification process, and the termination verification process all include a functional verification process for the initial design circuit.

[0021] In one exemplary embodiment of this disclosure, the method further includes: if the functional verification result is unsuccessful, updating the initial design circuit; and re-performing the functional verification on the chip to be designed based on the updated initial design circuit.

[0022] In one exemplary embodiment of this disclosure, the verification process for the target design circuit includes a coverage verification process, a regression verification process, and a termination verification process; the method further includes: if the verification result of each verification process for the target design circuit is a pass, then a chip manufacturing process is executed; if the verification result of any of the verification processes is a fail, then the target design circuit is updated; and based on the updated target design circuit, all verification processes are re-executed on the chip to be designed.

[0023] According to a second aspect of this disclosure, a functional verification apparatus is provided, comprising: a circuit acquisition module for acquiring an initial design circuit corresponding to a chip to be designed; an initial count value determination module for determining all test count values ​​contained in the chip to be designed based on the initial design circuit; a target count value determination module for randomly selecting a specified number of target test count values ​​from all the test count values; and a functional verification module for performing functional verification on the initial design circuit of the chip to be designed based on the target test count values ​​to obtain a functional verification result.

[0024] In one exemplary embodiment of this disclosure, the circuit acquisition module includes a circuit acquisition unit, used to acquire the functional specification file corresponding to the chip to be designed, and generate an initial design circuit based on the functional specification file.

[0025] In one exemplary embodiment of this disclosure, the functional verification module includes a target circuit determination unit, configured to generate a circuit simulation netlist based on the initial design circuit; perform functional verification on the initial design circuit according to the circuit simulation netlist and the target test count value to obtain a circuit verification result; and use the initial design circuit whose circuit verification result is passed as the target design circuit.

[0026] In one exemplary embodiment of this disclosure, the target circuit determination unit includes a circuit verification subunit, configured to generate simulation test data based on the target test count value, the simulation test data including a simulation test input waveform, each target test count value corresponding to a random verification address in the initial design circuit; perform functional simulation verification on the random verification address in the initial design circuit based on the simulation test input waveform and the circuit simulation netlist to obtain a simulation verification waveform; and determine the circuit verification result of the initial design circuit based on the simulation verification waveform.

[0027] In one exemplary embodiment of this disclosure, the initial count value determination module includes an initial count value determination unit, configured to determine all address types corresponding to the chip to be designed based on the initial design circuit; each address type corresponds to at least one binary counter circuit; determine the addressing interval corresponding to each address type, the addressing interval being associated with the counting range of the binary counter circuit; and determine all test count values ​​contained in each addressing address type in the chip to be designed according to the addressing interval corresponding to each addressing address type.

[0028] In one exemplary embodiment of this disclosure, the target count value determination module includes a target count value determination unit, configured to determine a first preset number of header test addresses and tail test addresses based on each addressing address type; determine a random reference address corresponding to each addressing address type; determine a second preset number of random test addresses from each addressing interval based on the random reference addresses; and determine the target test count value corresponding to each addressing address type based on the obtained header test address, tail test address, and random test address.

[0029] In one exemplary embodiment of this disclosure, the target count value determination unit includes a start and end address determination unit, configured to obtain the start address and end address in the addressing interval corresponding to each addressing address type; determine a first preset number of consecutive start test addresses based on the start address; and determine a first preset number of consecutive end test addresses based on the end address.

[0030] In one exemplary embodiment of this disclosure, the target count value determination unit includes a random address determination unit, used to obtain the current system time; determine a time value to be identified based on the addressing range of the addressing address type and the current system time; convert the time value to be identified into a corresponding address conversion value; and determine the random reference address based on the address conversion value.

[0031] In one exemplary embodiment of this disclosure, the time value to be identified includes a minute time value, a second time value, and a millisecond time value; the random address determination unit includes a first address conversion subunit, configured to determine the parity of the value at each time bit in the minute time value, the second time value, and the millisecond time value; determine the correspondence between each time bit and the address conversion value; if the value at the time bit is odd, then the address conversion value corresponding to the time bit is configured as a first value; if the value at the time bit is even, then the address conversion value corresponding to the time bit is configured as a second value.

[0032] In one exemplary embodiment of this disclosure, the random address determination unit includes a second address conversion subunit, configured to determine the original time value or the padding time value corresponding to each time bit in the time value to be identified; the padding time value is generated based on at least one bit of the original time value; the address conversion value is determined according to the parity of each original time value and the padding time value; if the original time value or the padding time value is odd, the corresponding address conversion value is configured as a first value; if the original time value or the padding time value is even, the corresponding address conversion value is configured as a second value.

[0033] In one exemplary embodiment of this disclosure, the second address translation subunit is configured to perform: determining the original time bit and the padding time bit corresponding to the time value to be identified; taking the time value on each of the original time bits as the corresponding original time value; taking the original time bit associated with each of the padding time bits as the corresponding associated time bit; obtaining the associated time value on each of the associated time bits; and determining the padding time value on the corresponding padding time bit based on each of the associated time values.

[0034] In one exemplary embodiment of this disclosure, the target count value determination unit includes a segmented address determination unit, which is used to segment the address type to be segmented to obtain a segmented address; and to determine the corresponding header test address, the tail test address and the random test address according to each segmented address.

[0035] In one exemplary embodiment of this disclosure, the functional verification device further includes a circuit verification module, configured to: if the functional verification result is passed, perform a coverage verification process on the target design circuit to obtain a corresponding coverage verification result; if the coverage verification result is passed, perform a regression verification process to obtain a corresponding regression verification result; if the regression verification result is passed, perform a termination verification process to obtain a corresponding termination verification result; wherein the coverage verification process, the regression verification process, and the termination verification process all include a functional verification process for the initial design circuit.

[0036] In one exemplary embodiment of this disclosure, the functional verification device further includes a first circuit update module, configured to update the initial design circuit if the functional verification result is a failure; and to re-perform functional verification on the chip to be designed based on the updated initial design circuit.

[0037] In one exemplary embodiment of this disclosure, the verification process for the target design circuit includes a coverage verification process, a regression verification process, and a termination verification process; the functional verification device further includes a second circuit update module, configured to execute a chip manufacturing process if the verification result of each verification process for the target design circuit is a pass; update the target design circuit if the verification result of any of the verification processes is a fail; and re-execute all verification processes on the chip to be designed based on the updated target design circuit.

[0038] According to a third aspect of this disclosure, an electronic device is provided, comprising: a processor; and a memory storing computer-readable instructions that, when executed by the processor, implement the functional verification method according to any one of the preceding claims.

[0039] According to a fourth aspect of this disclosure, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the functional verification method according to any one of the preceding claims.

[0040] The technical solution provided in this disclosure may include the following beneficial effects:

[0041] The functional verification method in the exemplary embodiments of this disclosure, on the one hand, determines a specified number of target test counts from all test counts in the initial design circuit. Each test count corresponds to a random verification address. Functional verification is performed on the initial design circuit of the chip to be designed based on the target test counts. The functional verification process requires switching based on the counter circuit, thus reducing the number of counter toggles during functional verification. On the other hand, since the functional verification of the initial design circuit of the chip to be designed is based on a specified number of target test counts, it is not necessary to test all test counts. This significantly reduces the number of read / write scans, reduces the time for functional simulation and verification, improves work efficiency, and accelerates the verification process.

[0042] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0043] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort. In the drawings:

[0044] Figure 1 A flowchart illustrating a functional verification method according to an exemplary embodiment of the present disclosure is shown schematically;

[0045] Figure 2 An overall flowchart illustrating functional verification of DRAM according to an exemplary embodiment of the present disclosure is shown schematically.

[0046] Figure 3 This schematically illustrates an example diagram of an uncompressed counter in an initial design circuit of the prior art;

[0047] Figure 4 An example diagram illustrating a partially compressed counter of an initial design circuit according to an exemplary embodiment of the present disclosure is shown.

[0048] Figure 5 An example diagram illustrating the determination of a specified number of test addresses according to an exemplary embodiment of the present disclosure is shown.

[0049] Figure 6 An example diagram illustrating the determination of a random reference address according to an exemplary embodiment of the present disclosure is shown;

[0050] Figure 7A block diagram of a test system according to an exemplary embodiment of the present disclosure is shown schematically;

[0051] Figure 8 A block diagram of a functional verification apparatus according to an exemplary embodiment of the present disclosure is shown schematically;

[0052] Figure 9 A block diagram of an electronic device according to an exemplary embodiment of the present disclosure is shown schematically;

[0053] Figure 10 The illustration shows a schematic diagram of a computer-readable storage medium according to an exemplary embodiment of the present disclosure. Detailed Implementation

[0054] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted.

[0055] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced without one or more of the specific details described, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known structures, methods, apparatuses, implementations, materials, or operations are not shown or described in detail to avoid obscuring various aspects of this disclosure.

[0056] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in software, or in one or more software-hardened modules, or in different network and / or processor devices and / or microcontroller devices.

[0057] In MBIST testing, test vectors can be generated based on internal logic. The corresponding modules can operate on the internal high-speed functional clock along with the memory under test, eliminating the need for the test vectors to be shifted in by the machine's slow clock, thus saving significant testing time. Furthermore, comparative verification is also handled internally by the logic itself; the test machine only needs to collect the test results, further reducing testing time. The trade-off is that the built-in self-test logic consumes a large area and lacks the flexibility to freely configure or modify test vectors.

[0058] The MBIST test for DRAM can be entered through the configuration of the mode register, which automatically generates the command. With the help of the compression circuit, data can be written into the array. After the data is compressed and compared through the compression read operation, the address of the storage bank can be remembered for erroneous data and repaired.

[0059] As can be seen from the above process, the MBIST operation requires an operation time of at least seconds. For a DRAM verification environment with a simulation accuracy of picoseconds, the simulation time is extremely long. Furthermore, according to the internal sequence of MBIST, all row and column addresses of DRAM are read and written, and a self-refresh operation is also added to prevent data loss, which will make the simulation speed even slower. At the same time, the waveform file occupies a particularly large amount of memory space, which is simply unacceptable and difficult to implement for Whole Chip Level simulation.

[0060] Based on this, in this example embodiment, a functional verification method is first provided. The functional verification method of this disclosure can be implemented using a server or using a terminal device. The terminal described in this disclosure may include mobile terminals such as mobile phones, tablets, laptops, handheld computers, and personal digital assistants (PDAs), as well as fixed terminals such as desktop computers. Figure 1 A schematic diagram illustrating a functional verification method flow according to some embodiments of the present disclosure is provided. (Reference) Figure 1 The functional verification method may include the following steps:

[0061] Step S110: Obtain the initial design circuit corresponding to the chip to be designed.

[0062] In one exemplary embodiment of this disclosure, the chip to be designed may be a chip awaiting simulation processing for chip structure design. The initial design circuit may be a simulation circuit used when simulating the chip to be designed.

[0063] Before performing functional verification on the chip to be designed, the initial design circuit corresponding to the chip to be designed can be obtained first, so as to generate the corresponding circuit simulation netlist based on the initial design circuit, and then perform functional verification on the chip to be designed based on the circuit simulation netlist.

[0064] Step S120: Determine all test count values ​​contained in the chip to be designed based on the initial design circuit.

[0065] In one exemplary embodiment of this disclosure, all test count values ​​may be the count values ​​of all test counters used when simulating the chip to be designed.

[0066] After obtaining the initial design circuit, all test count values ​​contained in the chip to be designed can be determined based on the initial design circuit. All test count values ​​in the chip to be designed can be determined according to the addressing range of the address corresponding to the chip. The address can be any combination of one or more address types, such as row address, column address, memory bank address, or memory bank group address. Each addressing range of the chip to be designed can correspond to a count value; therefore, all test count values ​​contained in the chip to be designed can be determined.

[0067] Step S130: Randomly select a specified number of target test counts from all test counts.

[0068] In one exemplary embodiment of this disclosure, the specified quantity can be a pre-specified quantity. The target test count value can be a subset of all test count values ​​selected from all test count values. Simulating the chip under design based on the target test count value can achieve the same effect as simulating the chip under design based on all test count values.

[0069] Because the functional verification of a chip design involves reading and writing to the addresses corresponding to all test counts, and also requires refresh operations to prevent data loss, the entire simulation process is very slow and consumes a large amount of memory. Therefore, during the functional verification of a chip design, based on the functional protocol defined in the operating standard and the chip's internal functional implementation scheme, a partial compression of counter values ​​can be used to select a specified number of target test counts for verification. This significantly reduces the number of read and write scans, greatly reduces the time for MBIST functional simulation and verification, and improves the verification process.

[0070] Step S140: Perform functional verification on the initial design circuit of the chip to be designed based on the target test count value, and obtain the functional verification result.

[0071] In one exemplary embodiment of this disclosure, functional verification can be a verification process in electronic design automation (EDA) to verify whether a digital circuit conforms to predetermined functional specifications. The functional verification result can be the verification result obtained by simulating the chip to be designed.

[0072] After determining a specified number of target test counts, the initial design circuit of the chip to be designed can be functionally verified. After the functional verification is completed, the functional verification result of the chip to be designed can be determined.

[0073] According to the functional verification method in this example embodiment, on the one hand, a specified number of target test counts are determined from all test counts in the initial design circuit. Each test count corresponds to a random verification address. Functional verification is performed on the initial design circuit of the chip to be designed based on the target test counts. The functional verification process can use a counter circuit to jump based on the random verification address, without using a counter to count each address. Therefore, the number of counter toggles can be reduced during the functional verification process. On the other hand, since the functional verification of the initial design circuit of the chip to be designed is based on a specified number of target test counts, it is not necessary to test all test counts. This can significantly reduce the number of read / write scans, reduce the time for functional simulation and verification, improve work efficiency, and accelerate the verification process.

[0074] The functional verification method in this example embodiment will be further explained below.

[0075] refer to Figure 2 , Figure 2 This diagram schematically illustrates the overall flowchart of functional verification of DRAM according to an exemplary embodiment of the present disclosure. After obtaining the initial design circuit corresponding to the chip to be designed, a target test count value corresponding to the chip to be designed can be determined based on the initial design circuit. Functional verification is then performed on the initial design circuit of the chip to be designed based on the target test count value. Initial design circuits that pass the functional verification are determined as the target design circuit. Initial design circuits that fail the functional verification are updated, and functional verification is re-performed on the chip to be designed using the updated initial design circuit. The process of performing functional verification on the initial design circuit to determine the target design circuit can be performed based on steps S201 to S207.

[0076] After obtaining the target design circuit, verification processes such as coverage verification, regression verification, and termination verification can be performed on the target design circuit through steps S208 to S210. If the verification result of each verification process for the target design circuit is passed, the chip manufacturing process is executed in step S211; otherwise, the target design circuit will be updated, and all verification processes will be re-executed on the chip to be designed based on the updated target design circuit. The above execution steps complete the entire functional verification process of the chip to be designed.

[0077] As will be readily understood by those skilled in the art, the MBIST function is only one aspect of the functional verification of chip design circuits. Other tests involving traversing memory cells can also employ the functional verification method proposed in this disclosure. This embodiment uses the MBIST function as an example to illustrate the invention, as detailed below.

[0078] In one exemplary embodiment of this disclosure, for step S110, obtaining the initial design circuit corresponding to the chip to be designed can be performed by the following steps: obtaining the functional specification file corresponding to the chip to be designed, and generating the initial design circuit according to the functional specification file.

[0079] The functional specification document can be a predefined functional verification specification document. The initial design circuit can be a simulation design circuit used for functional verification of the chip under design.

[0080] In step S201, the functional protocol specification is defined. For the functional verification process of the chip to be designed, the functional protocol specification can be defined in advance, generating a corresponding functional specification file. In step S202, the initial design circuit is determined according to the protocol. By obtaining the predefined functional specification file, an initial design circuit for functional verification of the chip to be designed can be designed based on the functional specification file. After obtaining the initial design circuit, functional verification can be performed based on the target test count value determined from the initial design circuit, thereby reducing the number of verification steps and improving verification efficiency.

[0081] In one exemplary embodiment of this disclosure, step S140, which involves functionally verifying the initial design circuit of the chip to be designed based on the target test count value to obtain the functional verification result, can be performed through the following steps: generating a circuit simulation netlist based on the initial design circuit; performing functional verification on the initial design circuit according to the circuit simulation netlist and the target test count value to obtain the circuit verification result; and using the initial design circuit whose circuit verification result is passed as the target design circuit.

[0082] The circuit simulation netlist can be a digital simulation netlist used to simulate the initial circuit design. Verification processing can be the specific process of functionally verifying the chip under design. The circuit verification result can be the result obtained from the simulation verification of the initial circuit design of the chip under design.

[0083] Continue to refer to Figure 2In step S203, a circuit simulation netlist is generated. After generating the initial design circuit, a circuit simulation netlist can be generated based on the initial design circuit. In step S204, the simulation stimulus input is verified. The process of verifying the simulation stimulus input includes a functional verification process based on the target test count value. Specifically, it includes: verifying the initial design circuit based on the circuit simulation netlist and the target test count value determined from the initial design circuit. For example, the simulation stimulus input data can be verified based on the initial design circuit. After the initial design circuit verifies the simulation stimulus input based on the target test count value and the circuit simulation netlist, a corresponding output waveform file can be generated, i.e., the corresponding circuit verification result is obtained. Through the above steps, an initial design circuit that conforms to the functional protocol specification can be determined.

[0084] In one exemplary embodiment of this disclosure, for step S140, after obtaining the initial design circuit, functional verification processing can be performed on the initial design circuit according to the circuit simulation netlist and target test count values ​​to obtain circuit verification results. Specifically, this includes: generating simulation test data based on the target test count values, the simulation test data including simulation test input waveforms, each target test count value corresponding to a random verification address in the initial design circuit; performing functional simulation verification on the random verification addresses in the initial design circuit according to the simulation test input waveforms and the circuit simulation netlist to obtain simulation verification waveforms; and determining the circuit verification results of the initial design circuit based on the simulation verification waveforms.

[0085] The simulation test data can be the test data used to check whether the initial circuit passes circuit verification. The simulation test input waveform can be the ideal waveform used for simulation testing. The simulation verification waveform can be the output waveform obtained after simulating the simulation test waveform based on the initial circuit design. The circuit verification result can be the result obtained after performing circuit verification processing on the initial circuit design.

[0086] Continue to refer to Figure 2 In step S205, computer simulation generates waveform files. Simulation test data is generated based on the target test count values. For each target test count value determined from the initial design circuit, each target test count value corresponds to a random verification address in the initial design circuit. The simulation test data used for functional verification of the initial design circuit may include simulation test input waveforms represented in an ideal waveform state.

[0087] In step S206, the circuit function is checked to ensure it conforms to the protocol specifications based on the simulation test input waveform. Functional simulation verification is performed on the random verification addresses in the initial design circuit based on the simulation test input waveform and the circuit simulation netlist, resulting in a simulation verification waveform (i.e., the output waveform). This waveform is used to determine the circuit verification result of the initial design circuit. Typically, the simulation test waveform of the initial circuit may contain errors or be attenuated. The degree of error or attenuation in the simulation test waveform can be used to determine the circuit verification result of the initial circuit, including whether the verification passed or failed.

[0088] After obtaining the circuit verification results, the initial design circuit that passes the verification can be used as the target design circuit, which is the circuit that completes functional verification. If the circuit verification results fail, the circuit design is revised in step S207. For example, the circuit can be redesigned based on the functional specification document to determine the initial design circuit.

[0089] The subsequent verification process for the target design circuit also includes the functional verification process of compressed count values ​​as described in this embodiment. That is, the target design circuit also needs to perform multiple verification processes, such as the chip coverage verification process, regression verification process, and termination verification process. Only after the target design circuit passes the above verification processes can it be considered to have completed all the verification processes for the chip design, including functional verification, before chip production.

[0090] In one exemplary embodiment of this disclosure, step S102, determining all test count values ​​contained in the chip to be designed based on the initial design circuit, includes: determining all address types corresponding to the chip to be designed based on the initial design circuit; each address type corresponds to at least one binary counter circuit; determining the addressing interval corresponding to each address type, the addressing interval being associated with the counting range of the binary counter circuit; and determining all test count values ​​contained in each addressing address type in the chip to be designed based on the addressing interval corresponding to each addressing address type.

[0091] The address type can be the specific type of address contained in the chip being designed. A counter can be a basic logic component in a digital system; based on the carry mechanism, counters can be divided into binary counters and non-binary counters. A binary counter circuit can be a circuit that counts according to the rules of binary number arithmetic. The addressing range can be the processor's ability to address memory.

[0092] After determining the initial design circuit, all address types corresponding to the chip to be designed can be determined based on the initial design circuit. In one exemplary embodiment of this disclosure, the address types include any one or more combinations of row address, column address, bank address, and bank group address.

[0093] Here, the row address can be the row address that the processor can access during memory addressing. The column address range can be the column address that the processor can access during memory addressing. The bank address can be the address corresponding to the memory cell number in the memory. The bank group address can be the address corresponding to the group of memory cells in the memory.

[0094] For the chip under design, all address types corresponding to the chip can be determined based on the initial design circuit. Address types can be any combination of one or more of various address types, such as row address, column address, memory bank address, and memory bank group address. Each address type of the chip under design corresponds to at least one binary counter circuit, which can be used to represent the address range of different address types. Since each address type in the design circuit of the chip under design can be segmented based on the address length and testing requirements, if a certain address type requires segmentation, it can be designated as a segmented address type, and this segmented address type can correspond to multiple counters; if another address type does not require segmentation, this non-segmented address type can correspond to one counter.

[0095] Since different address types may correspond to different addressing ranges, the addressing interval (i.e., addressing range) corresponding to each address type can be determined first. The addressing interval is associated with the counting range of the binary counter circuit. In this embodiment, the counting range of the binary counter circuit can be used to represent the addressing interval for each address type. Specifically, an address within an addressing interval can be represented by a unique value from the binary counter circuit. After determining the addressing interval corresponding to each address type, since an address within an addressing interval can be represented by a unique value from the binary counter circuit, all test count values ​​contained in each addressing address type in the chip under design can be determined based on the addressing interval corresponding to each addressing address type.

[0096] refer to Figure 3 , Figure 3 An example diagram of an uncompressed counter in an initial design circuit of the prior art is shown schematically. Figure 3This includes multiple address types, such as row address (RA), column address (CA), and memory bank address (BA), memory bank group address (GA), etc. For example, the address range corresponding to RA[7:0] can be 0 to 255, and the address range corresponding to BA[2:0] can be 0 to 7. Meanwhile, binary counter circuits with row address values ​​ranging from 0 to 255 can include RA[7:0], CA[5:0], RA[12:8], etc.; binary counter circuits with column address values ​​ranging from 0 to 7 can include BA[2:0], RA[15:13], etc. After determining the address ranges corresponding to different address types, all test count values ​​contained in each address type in the chip under design can be determined separately.

[0097] If the chip under design is to be functionally verified based on all the test counts determined above, then each test count needs to be read and written separately for read and write testing. A refresh operation must also be added to prevent data loss, which would significantly slow down the simulation process. For example, based on... Figure 3 The test count value in the simulation is processed, and the calculation process of the number of times the counter flips is as follows: Number of flips = [(256x64x4+4x1024x2)x32+(256x64x8+4x1024x2)x32]x8x2=103087603712.

[0098] When using all test count values ​​for functional verification, it is necessary to toggle all test count values, which slows down the simulation speed. To solve the above problem, the initial circuit design is modified as follows: Figure 1 During the functional verification shown, after determining all the test count values ​​corresponding to the initial design circuit, as follows: Figure 3 As shown, it can be seen from Figure 3 A subset of test counts is selected from all test counts to be used in the simulation process, such as... Figure 4 The target test count value shown is used to perform functional verification of the initial design circuit based on the target test count value. Furthermore, the initial design circuit that passes the functional verification is used as the target design circuit, and the target design circuit is then subjected to... Figure 2 The coverage verification process, regression verification process, and termination verification process are all included in the functional verification process based on the target test count value. Therefore, the number of read and write scans can be greatly reduced, the time for MBIST functional simulation and verification can be reduced, and work efficiency can be improved.

[0099] In one exemplary embodiment of this disclosure, from Figure 3 Randomly select from all the test count values ​​shown, such as Figure 4The specific processing procedure for the specified number of target test counts shown is as follows: determine a first preset number of header test addresses and tail test addresses based on each address type; determine the random reference address corresponding to each address type; determine a second preset number of random test addresses from each addressing interval based on the random reference addresses; and determine the target test count value corresponding to each address type based on the obtained header test address, tail test address, and random test address.

[0100] The first preset quantity can be a pre-configured specific numerical quantity used to define the number of header and tail test addresses determined from each addressing address type. The header test address can be a test address located at the beginning of a row or column address. The tail test address can be a test address located at the end of a row or column address. The random reference address can be a reference address determined at any position other than the beginning and end positions of the initial design circuit; the random reference address can be used to determine the random test address. The second preset quantity can be a pre-configured specific numerical quantity used to define the number of determined random test addresses. The second preset quantity can be the same as or different from the first preset quantity. The random test address can be a test address determined at the middle position of a row / column address in the initial design circuit.

[0101] Based on historical functional verification experience, the counter in the initial circuit design is prone to problems when toggling between its maximum and minimum values. Therefore, the partially compressed algorithm performs normal toggling of the start and end positions of the binary counter circuit corresponding to each address type. To further improve coverage, a random reference address can be determined at the middle position of the counter. This random reference address can be determined based on a random number. A second preset number of random test addresses are then selected based on the determined random reference address.

[0102] After determining the addressing range corresponding to each addressing address type, a portion of test addresses can be selected based on the addressing range to determine the target test count value. During DRAM manufacturing, due to various reasons such as manufacturing processes, memory cells at the chip edges are more prone to defects than memory cells in the middle. Therefore, when selecting test addresses, a first preset number of header test addresses and tail test addresses can be determined first. For example, in this embodiment, the first preset number can be set to 3, i.e., 3 header test addresses and 3 tail test addresses are determined.

[0103] After determining the head and tail test addresses, to expand test coverage, a random reference address can be selected from the middle position. Based on this random reference address, a second preset number of random test addresses can be determined; this second preset number could be 3, 4, 5, etc. Then, the target test count value is determined based on the determined head and tail test addresses and the random test addresses.

[0104] In one exemplary embodiment of this disclosure, determining a first preset number of header test addresses and tail test addresses based on each address type includes: obtaining the start address and end address in the addressing interval corresponding to each address type; determining a first preset number of consecutive header test addresses based on the start address; and determining a first preset number of consecutive tail test addresses based on the end address.

[0105] The start address can be the address corresponding to the beginning of a row or column address. The end address can be the address corresponding to the end of a row or column address.

[0106] When determining the head and tail test addresses, the start and end addresses of the counter can be determined first. For example, the start address could be 0, and the end address could be max. Since edge memory cells are more prone to bad pixels than middle memory cells, when determining the head and tail test addresses, a first preset number of consecutive head test addresses can be determined based on the start address, and a first preset number of consecutive tail test addresses can be determined based on the end address. For example, the test count value for the head test address can be represented as 0, 1, 2; and the test count value for the tail test address can be represented as max-2, max-1, max.

[0107] Through the above processing steps, the target test count value corresponding to the initial design circuit can be determined, for reference. Figure 4 , Figure 4 An example diagram illustrating a partially compressed counter of an initial design circuit according to an exemplary embodiment of the present disclosure is shown. Figure 4 The value in the middle is the target test count value obtained after partial compression of the counter. It can be seen that the target test count value contains a preset number of consecutive head test addresses, tail test addresses and random test addresses in the middle, which greatly reduces the counter value that needs to be flipped.

[0108] Furthermore, after determining the random reference addresses, a second preset number of random test addresses can be determined based on these addresses. In practice, if a row contains a bad pixel, the two adjacent rows are also highly likely to contain bad pixels. Therefore, within a small segment, three consecutive numbers can be selected to simulate this situation. That is, if the row at the random reference address (random) contains a bad pixel, then the two adjacent rows, random-1 and random+1, are also highly likely to contain bad pixels. Therefore, after determining the random reference addresses, the address preceding and following the stacked reference address can be used together as the random test addresses.

[0109] Use based on Figure 4 Once the target test count value is determined, the counter toggles by number = [(9x9x4+9x9x2)x9+(9x9x8+9x9x2)x9]x8x2 = 186624. Compared to the scheme of toggling all test count values ​​in the chip under design, the processing efficiency is increased by 550,000 times.

[0110] refer to Figure 5 , Figure 5 An example diagram illustrating the determination of a specified number of test addresses according to an exemplary embodiment of the present disclosure is shown. Figure 5 In this method, 0, 1, 2, random-1, random, random+1, max-2, max-1, max are used as target test count values ​​for jumps. Since the random value is different in each simulation, increasing the number of simulations can cover more cases. This is especially useful for counters with a large number of bits, saving simulation time and effectively improving the efficiency of verification work.

[0111] In one exemplary embodiment of this disclosure, determining the random reference address corresponding to each addressing address type includes: obtaining the current system time; determining the time value to be identified based on the addressing range of the addressing address type and the current system time; converting the time value to be identified into the corresponding address conversion value; and determining the random reference address based on the address conversion value.

[0112] The current system time can be the processor's current date and time, for example, it can be composed of date, hour, minute, second, millisecond, etc. The time portion to be identified can be the numerical value of the time to be identified; for example, a portion of the current system time can be used as the time portion to be identified, or the minute, second, and millisecond values ​​can be combined as the time portion to be identified. The time value to be identified can be the specific time value corresponding to the time portion to be identified. The address translation value can be the value used to convert the time value to be identified into a value representing a binary address.

[0113] Since there is a time interval between each simulation, a random number of corresponding bits is generated using the current system time to determine the random reference address. For example, the current system time is obtained, and the time value to be identified for each addressing address type is determined from the current system time. The time value to be identified can be determined based on the time portion to be identified. This embodiment increases coverage by adding randomization. The randomization mechanism ensures that the random numbers obtained in each simulation are evenly distributed within the range of 0 to 255, thereby ensuring that all cases are covered in multiple simulations.

[0114] In one exemplary embodiment of this disclosure, the time value to be identified includes a minute time value, a second time value, and a millisecond time value; converting the time value to be identified into a corresponding address conversion value includes: determining the parity of the value at each time bit in the minute time value, second time value, and millisecond time value; determining the correspondence between each time bit and the address conversion value; if the value at the time bit is odd, then configuring the address conversion value corresponding to the time bit as a first value; if the value at the time bit is even, then configuring the address conversion value corresponding to the time bit as a second value.

[0115] The minute time value can be the minute time value in the time value to be identified. The second time value can be the second time value in the time value to be identified. The millisecond time value can be the millisecond time value in the time value to be identified. A time bit can be the position of one or more specific numerical values ​​that make up the time value to be identified. The first value can be the first address value used to replace the time value in a certain bit; for example, the address value can be represented in binary, so the first value can be 1. The second value can be the second address value used to replace the time value in a certain bit; the second value can be 0.

[0116] For example, when the counter range corresponding to the addressing interval of a certain addressing address type is 0 to 255, the time value to be identified can be determined as the time value corresponding to the minutes, seconds and milliseconds to generate an 8-bit random number.

[0117] refer to Figure 6 , Figure 6 An example diagram illustrating the determination of a random reference address according to an exemplary embodiment of the present disclosure is shown. Figure 6 In the current system time, the values ​​for minutes (min), seconds (s), and milliseconds (ms) are 12:34:0153. These three time values ​​can be used together as the time value to be identified. After determining the time value to be identified, it can be converted to obtain the corresponding address conversion value, and then the random reference address can be determined based on the address conversion value.

[0118] It will be readily apparent to those skilled in the art that, in some other exemplary embodiments, values ​​in other time digits of the current system time can also be used as the time value to be identified. For example, values ​​in the seconds and milliseconds time digits can be used as the time value to be identified; or, for example, values ​​in multiple time digits such as hours, seconds, and milliseconds can be used together as the time value to be identified; or, for example, values ​​in multiple time digits such as hours, minutes, and milliseconds can be used together as the time value to be identified. All of the above solutions fall within the protection scope of this disclosure.

[0119] After determining the time value to be identified, the parity of the value in each time bit of the time value can be determined. Then, address translation is performed based on the parity of the time bit values ​​to generate the corresponding address translation value. For example, continue to refer to... Figure 6 When the value of a certain time bit is odd, the address translation value can be configured as the first value; when the value of a certain time bit is even, the address translation value can be configured as the second value. The random reference address is then determined based on the resulting address translation value. For example... Figure 6 The hourly time includes two time bits, 1 and 2. The value of the first time bit is 1, which is odd, and the corresponding data conversion value is set to 1. The value of the first time bit is 2, which is even, and the corresponding data conversion value is set to 0. All data conversion values ​​are determined sequentially based on the other time bits, and the random reference address 10101111 is determined accordingly.

[0120] In one exemplary embodiment of this disclosure, converting a time value to be identified into a corresponding address conversion value includes: determining the original time value or the padding time value corresponding to each time bit in the time value to be identified; generating the padding time value based on at least one original time value; determining the address conversion value according to the parity of each original time value and the padding time value; if the original time value or the padding time value is odd, configuring the corresponding address conversion value as a first value; if the original time value or the padding time value is even, configuring the corresponding address conversion value as a second value.

[0121] The original time value can be a time value determined directly from a specific time position of the time value to be identified. The padding time value can be a time value generated from one or more original time values.

[0122] During the address translation value determination process, there may be insufficient time value bits. In this case, the existing time value in the time bits of the time value to be identified can be used as the original time value, and a corresponding padding time value can be generated based on the original time value. For example, when the time value to be identified is determined based on the minute, second, and millisecond time bits of the current system time, since an 8-bit random number needs to be generated, the highest bit of the ms part does not have a corresponding value. In this case, the highest bit of the ms will become the padding time bit, and the corresponding padding time value needs to be generated based on the original time value. After determining the padding time value, the corresponding address translation value can be generated according to the parity of the original time value and the padding time value.

[0123] In one exemplary embodiment of this disclosure, determining the original time value or the padding time value corresponding to each time bit in the time value to be identified includes: determining the original time bit and the padding time bit corresponding to the time value to be identified; taking the time value at each original time bit as the corresponding original time value; taking the original time bit associated with each padding time bit as the corresponding associated time bit; obtaining the associated time value at each associated time bit; and determining the padding time value at the corresponding padding time bit based on each associated time value.

[0124] The original time bit can be the time value position corresponding to the current system time directly used for address value conversion. The padding time bit can be the value position of the time value generated by padding calculation based on one or more original time bits. The associated time bit can be an original time bit that is associated with the padding time bit. The associated time value can be the specific time value on the associated time bit.

[0125] refer to Figure 6 When determining an 8-bit random number to generate a random reference address, the most significant bit of `ms` can be used as the padding time bit, and the other time bits can be used as the original time bits. The original time values ​​can be directly obtained from the original time bits, for example, the original time values ​​are 1, 2, 3, 4, 1, 5, 3. Since the most significant bit of `ms` does not have a corresponding time value, the time value corresponding to the most significant bit of `ms` can be determined based on the original time values. For example, the original time bits associated with the padding time bits can be determined as associated time bits. For instance, the associated time bits corresponding to the padding time value bits include the most significant bit of `s` and the least significant bit of `ms`.

[0126] Therefore, the padding time value can be obtained by adding the least significant bit of s to the least significant bit of ms. For example, the time value of the most significant bit of ms can be 4 + 3 = 7. After determining the original time value and the padding time value, an address conversion can be performed based on the obtained time value to obtain the address conversion value. For example, if the current system time is 12 minutes 34 seconds 153 milliseconds, the corresponding random reference address (binary random number) is 10101111, and the counter count value random = 175 can be obtained.

[0127] In one exemplary embodiment of this disclosure, the address type includes a segmented address type; determining a first preset number of header test addresses and tail test addresses based on each address type includes: segmenting the address type to be segmented to obtain segmented address; and determining the corresponding header test address, tail test address, and random test address for each segmented address.

[0128] The address type to be segmented can be an address type waiting to be segmented. The segmented address can be an address obtained after segmenting the addressing range corresponding to the address type to be segmented.

[0129] For various addressing address types, since some addressing address types correspond to large addressing ranges, in order to reduce the propagation speed consumption of counter toggling and improve testing efficiency, this type of addressing address can be divided into a segmented addressing address type and segmented to obtain segmented addressing addresses. Subsequent functional verification processing is then performed based on the obtained segmented addressing addresses to improve the propagation speed of binary counter circuit toggling. For example, in the above addressing address types, the addressing range of the row address is large. The row address can be used as the segmented addressing address type, and the row address can be segmented to obtain multiple different segmented addressing addresses, including RA[7:0], RA[12:8], RA[15:13], etc.

[0130] After obtaining the segmented addressing addresses, a first preset number of header test addresses and tail test addresses, as well as a second preset number of random test addresses, can be further determined from each segmented addressing address. Specifically, the header test address, tail test address, and random test address are determined from each segmented addressing address. The method for determining the segmented addressing addresses is the same as the address determination method described above, and will not be repeated here.

[0131] In one exemplary embodiment of this disclosure, if the functional verification result is unsuccessful, the initial design circuit is updated; the functional verification of the chip to be designed is then re-performed based on the updated initial design circuit.

[0132] After determining the target test count value, functional verification of the chip under design can be performed based on the target test count value. For details, please refer to [link / reference]. Figure 7 , Figure 7 A block diagram of a test system according to an exemplary embodiment of the present disclosure is illustrated. The chip test sequence may include multiple chips to be designed. The MBIST function is run sequentially on each chip to be designed in the chip test sequence. For each chip to be designed, the MBIST function can be performed based on a digital simulation netlist of DRAM and a target test count value. Functional verification processing can be performed using the target test count value obtained after acceleration using a compression algorithm for the counter portion. The generated simulation waveform file is used as the simulation output result, and the correctness of the initial design circuit is determined by observing the simulation results.

[0133] Continue to refer to Figure 2 In step S206, the circuit function is checked against the simulation waveform to see if it conforms to the protocol specifications. If the circuit function does not conform to the protocol specifications, the functional verification result of the chip under design is considered to be unsuccessful. If the functional verification result is unsuccessful, in step S207, the circuit design is modified, that is, the initial design circuit is updated to obtain the updated initial design circuit. Then, the functional verification of the chip under design is performed again based on the updated initial design circuit.

[0134] In one exemplary embodiment of this disclosure, if the functional verification result is passed, a coverage verification process is executed on the target design circuit to obtain the corresponding coverage verification result; if the coverage verification result is passed, a regression verification process is executed to obtain the corresponding regression verification result; if the regression verification result is passed, a termination verification process is executed to obtain the corresponding termination verification result; wherein, the coverage verification process, the regression verification process, and the termination verification process all include a functional verification process for the initial design circuit.

[0135] The coverage verification process can be a randomized verification process for the chip under design to improve its test coverage. The coverage verification result can be the verification result obtained by performing coverage verification on the chip under design. The regression verification process can be the specific process of performing regression verification on the chip under design. The regression verification result can be the verification result obtained after performing the regression verification process on the chip under design. The verification termination process can be the verification process before starting the chip manufacturing process for the chip under design. The verification termination result can be the verification result obtained after performing the verification termination process on the chip under design.

[0136] Continue to refer to Figure 2After determining the target test count value, a coverage verification process for the chip under design can be executed based on the target test count value. In step S208, randomized verification improves coverage. Because the coverage verification process uses the selected target test count value and employs a randomized verification method, the verification coverage can be effectively improved, thus enhancing the verification effect. After the coverage verification process for the chip under design is completed, the corresponding coverage verification result is obtained. If the coverage verification result is passed, the regression verification process and the final verification process for the chip under design are then performed to obtain the corresponding regression verification result and the final verification result, which are then used to proceed with subsequent processing.

[0137] In one exemplary embodiment of this disclosure, the verification process for the target design circuit includes a coverage verification process, a regression verification process, and a termination verification process. If the verification result of each verification process for the target design circuit is a pass, then the chip manufacturing process is executed. If the verification result of any verification process is a fail, then the target design circuit is updated. Based on the updated target design circuit, all verification processes for the chip to be designed are re-executed.

[0138] Among them, chip manufacturing process can be the specific operational process for chip trial production. For example, chip manufacturing process can include tape-out process, which can refer to manufacturing chips through a series of process steps like an assembly line.

[0139] Continue to refer to Figure 2 In step S209, the regression verification function is successful. If the regression verification result is successful, the subsequent verification termination process proceeds; if the regression verification result is unsuccessful, the process returns to determine whether the initial design circuit conforms to the functional protocol specification. In step S210, the verification termination function is successful. If the verification termination result is successful, the subsequent processing process proceeds; if the verification termination result is unsuccessful, the process returns to determine whether the initial design circuit conforms to the functional protocol specification.

[0140] In the overall process of DRAM functional verification, the early stage mainly involves functional backscrambling and randomization verification. Compression algorithms shorten simulation time and can quickly check whether the circuit design meets the functional protocol specifications. Simultaneously, different random numbers are obtained from simulations at different time points to check various scenarios. In the middle stage of the project, regression verification is performed to periodically check functionality and prevent MBIST functional errors caused by other changes to the circuit, ensuring consistent functional correctness. Finally, a final verification is conducted midway through the project to ensure functional correctness before chip fabrication.

[0141] The regression verification process for the chip under design described above includes a functional verification process for the initial design circuit; similarly, the final verification process also includes a functional verification process for the initial design circuit. Since both the regression and final verification processes involve functional verification of the initial design circuit, which is based on the target test counter, this significantly reduces the number of read / write scans, the time required for MBIST functional simulation and verification, improves work efficiency, and accelerates the verification process.

[0142] Continue to refer to Figure 2 If all the above functional verification results pass, then in step S211, the chip manufacturing process is triggered. That is, if both the regression verification result and the end verification result pass, then the subsequent chip manufacturing process, i.e., the tape-out process, continues.

[0143] If any of the verification processes—coverage verification, regression verification, and termination verification—fail, it can be further determined whether the initial design circuit does not conform to the functional protocol specification. If it does not, the circuit design of the initial design circuit can be updated; then, the verification process for the chip to be designed can be carried out based on the updated initial design circuit.

[0144] In summary, the functional verification method disclosed herein involves: obtaining the initial design circuit corresponding to the chip to be designed; determining all test count values ​​contained in the chip to be designed based on the initial design circuit; randomly selecting a specified number of target test count values ​​from all test count values; and performing functional verification on the initial design circuit of the chip to be designed based on the target test count values ​​to obtain the functional verification result. On one hand, determining a specified number of target test count values ​​from all test count values ​​in the initial design circuit, with each test count value corresponding to a random verification address, and performing functional verification on the initial design circuit of the chip to be designed based on the target test count values, requires switching based on a counter circuit. Therefore, this reduces the number of counter toggles during functional verification. On the other hand, since the functional verification of the initial design circuit of the chip to be designed is based on a specified number of target test count values, it is not necessary to test all test count values, which can significantly reduce the number of read / write scans, reduce the time for functional simulation and verification, improve work efficiency, and accelerate the verification process. On the other hand, since edge cells of a chip are prone to dead pixels, multiple consecutive head and tail test addresses are determined based on the edge cells. The middle positions of the chip are less prone to dead pixels, and random test addresses can be determined using a random method. This can simulate the situation where a real MBIST test scan detects dead pixel locations, thus expanding the functional verification coverage. Furthermore, since the coverage verification process, regression verification process, and termination verification process all include functional verification procedures based on the target test count value, verification time can be significantly reduced and work efficiency improved in various verification processes.

[0145] It should be noted that although the steps of the method in this invention are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0146] Furthermore, in this example embodiment, a functional verification device is also provided. (See reference...) Figure 8 The functional verification device 800 may include: a circuit acquisition module 810, an initial count value determination module 820, a target count value determination module 830, and a functional verification module 840.

[0147] Specifically, the circuit acquisition module 810 is used to acquire the initial design circuit corresponding to the chip to be designed; the initial count value determination module 820 is used to determine all test count values ​​contained in the chip to be designed based on the initial design circuit; the target count value determination module 830 is used to randomly select a specified number of target test count values ​​from all test count values; and the functional verification module 840 is used to perform functional verification on the initial design circuit of the chip to be designed based on the target test count values ​​to obtain the functional verification result.

[0148] In one exemplary embodiment of this disclosure, the circuit acquisition module 810 includes a circuit acquisition unit, used to acquire the functional specification file corresponding to the chip to be designed, and generate an initial design circuit based on the functional specification file.

[0149] In one exemplary embodiment of this disclosure, the functional verification module 840 includes a target circuit determination unit, which is used to generate a circuit simulation netlist based on the initial design circuit; perform functional verification on the initial design circuit according to the circuit simulation netlist and the target test count value to obtain the circuit verification result; and use the initial design circuit whose circuit verification result is passed as the target design circuit.

[0150] In one exemplary embodiment of this disclosure, the target circuit determination unit includes a circuit verification subunit, which is used to generate simulation test data based on target test count values. The simulation test data includes simulation test input waveforms, and each target test count value corresponds to a random verification address in the initial design circuit. Based on the simulation test input waveforms and the circuit simulation netlist, functional simulation verification is performed on the random verification addresses in the initial design circuit to obtain simulation verification waveforms. The circuit verification result of the initial design circuit is determined based on the simulation verification waveforms.

[0151] In one exemplary embodiment of this disclosure, the initial count value determination module 820 includes an initial count value determination unit, used to determine all addressing address types corresponding to the chip to be designed based on the initial design circuit; each addressing address type corresponds to at least one binary counter circuit; determine the addressing interval corresponding to each addressing address type, the addressing interval being associated with the counting range of the binary counter circuit; and determine all test count values ​​contained in each addressing address type in the chip to be designed according to the addressing interval corresponding to each addressing address type.

[0152] In one exemplary embodiment of this disclosure, the target count value determination module 830 includes a target count value determination unit, configured to determine a first preset number of header test addresses and tail test addresses based on each addressing address type; determine a random reference address corresponding to each addressing address type; determine a second preset number of random test addresses from each addressing interval based on the random reference addresses; and determine a target test count value corresponding to each addressing address type based on the obtained header test addresses, tail test addresses, and random test addresses.

[0153] In one exemplary embodiment of this disclosure, the target count value determination unit includes a start and end address determination unit, used to obtain the start address and end address in the addressing interval corresponding to each addressing address type; determine a first preset number of consecutive start test addresses based on the start address; and determine a first preset number of consecutive end test addresses based on the end address.

[0154] In one exemplary embodiment of this disclosure, the target count value determination unit includes a random address determination unit, used to obtain the current system time; determine the time value to be identified based on the addressing range of the addressing address type and the current system time; convert the time value to be identified into the corresponding address conversion value; and determine a random reference address based on the address conversion value.

[0155] In one exemplary embodiment of this disclosure, the time values ​​to be identified include minute time values, second time values, and millisecond time values; the random address determination unit includes a first address conversion subunit, used to determine the parity of the value at each time bit in the minute time value, second time value, and millisecond time value; determine the correspondence between each time bit and the address conversion value; if the value at the time bit is odd, then the address conversion value corresponding to the time bit is configured as a first value; if the value at the time bit is even, then the address conversion value corresponding to the time bit is configured as a second value.

[0156] In one exemplary embodiment of this disclosure, the random address determination unit includes a second address conversion subunit, used to determine the original time value or the padding time value corresponding to each time bit in the time value to be identified; the padding time value is generated based on at least one original time value; the address conversion value is determined according to the parity of each original time value and the padding time value; if the original time value or the padding time value is odd, the corresponding address conversion value is configured as a first value; if the original time value or the padding time value is even, the corresponding address conversion value is configured as a second value.

[0157] In one exemplary embodiment of this disclosure, the second address translation subunit is configured to perform: determining the original time bit and the padding time bit corresponding to the time value to be identified; taking the time value on each original time bit as the corresponding original time value; taking the original time bit associated with each padding time bit as the corresponding associated time bit; obtaining the associated time value on each associated time bit; and determining the padding time value on the corresponding padding time bit based on each associated time value.

[0158] In one exemplary embodiment of this disclosure, the target count value determination unit includes a segmented address determination unit, which is used to segment the address type to be segmented to obtain segmented address; and to determine the corresponding header test address, tail test address and random test address according to each segmented address.

[0159] In one exemplary embodiment of this disclosure, the functional verification device 800 further includes a circuit verification module, configured to: if the functional verification result is passed, perform a coverage verification process on the target design circuit to obtain a corresponding coverage verification result; if the coverage verification result is passed, perform a regression verification process to obtain a corresponding regression verification result; if the regression verification result is passed, perform a termination verification process to obtain a corresponding termination verification result; wherein the coverage verification process, the regression verification process, and the termination verification process all include a functional verification process for the initial design circuit.

[0160] In one exemplary embodiment of this disclosure, the functional verification device 800 further includes a first circuit update module, used to update the initial design circuit if the functional verification result is a failure; and to re-perform functional verification on the chip to be designed based on the updated initial design circuit.

[0161] In one exemplary embodiment of this disclosure, the verification process for the target design circuit includes a coverage verification process, a regression verification process, and a termination verification process; the functional verification device 800 further includes a second circuit update module, which is used to execute a chip manufacturing process if the verification result of each verification process for the target design circuit is a pass; if the verification result of any verification process is a fail, the target design circuit is updated; and the entire verification process is re-executed on the chip to be designed based on the updated target design circuit.

[0162] The specific details of the virtual modules of each functional verification device mentioned above have been described in detail in the corresponding functional verification methods, so they will not be repeated here.

[0163] It should be noted that although several modules or units of the functional verification device have been mentioned in the detailed description above, this division is not mandatory. In fact, according to embodiments of this disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0164] Furthermore, in an exemplary embodiment of this disclosure, an electronic device capable of implementing the above-described method is also provided.

[0165] Those skilled in the art will understand that various aspects of the present invention can be implemented as systems, methods, or program products. Therefore, various aspects of the present invention can be specifically implemented as entirely hardware embodiments, entirely software embodiments (including firmware, microcode, etc.), or embodiments combining hardware and software aspects, collectively referred to herein as “circuit,” “module,” or “system.”

[0166] The following is for reference. Figure 9 To describe an electronic device 900 according to such an embodiment of the present disclosure. Figure 9 The electronic device 900 shown is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments disclosed herein.

[0167] like Figure 9 As shown, the electronic device 900 is presented in the form of a general-purpose computing device. The components of the electronic device 900 may include, but are not limited to: at least one processing unit 910, at least one storage unit 920, a bus 930 connecting different system components (including storage unit 920 and processing unit 910), and a display unit 940.

[0168] The storage unit stores program code that can be executed by the processing unit 910, causing the processing unit 910 to perform the steps described in the "Exemplary Methods" section above, according to various exemplary embodiments of this disclosure.

[0169] Storage unit 920 may include readable media in the form of volatile storage units, such as random access memory (RAM) 921 and / or cache memory 922, and may further include read-only memory (ROM) 923.

[0170] Storage unit 920 may include a program / utility 924 having a set (at least one) program module 925, such program module 925 including but not limited to: operating system, one or more application programs, other program modules and program data, each or some combination of these examples may include an implementation of a network environment.

[0171] Bus 930 can represent one or more of several bus structures, including a memory cell bus or memory cell controller, a peripheral bus, a graphics acceleration port, a processing unit, or a local bus using any of the various bus structures.

[0172] Electronic device 900 can also communicate with one or more external devices 970 (e.g., keyboard, pointing device, Bluetooth device, etc.), and with one or more devices that enable a user to interact with electronic device 900, and / or with any device that enables electronic device 900 to communicate with one or more other computing devices (e.g., router, modem, etc.). This communication can be performed via input / output (I / O) interface 950. Furthermore, electronic device 900 can also communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN), and / or public networks, such as the Internet) via network adapter 960. As shown, network adapter 960 communicates with other modules of electronic device 900 via bus 930. It should be understood that, although not shown in the figures, other hardware and / or software modules can be used in conjunction with electronic device 900, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0173] From the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solutions according to the embodiments of this disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, terminal device, or network device, etc.) to execute the methods according to the embodiments of this disclosure.

[0174] In exemplary embodiments of this disclosure, a computer-readable storage medium is also provided, on which a program product capable of implementing the methods described above is stored. In some possible embodiments, various aspects of the invention may also be implemented as a program product comprising program code that, when the program product is run on a terminal device, causes the terminal device to perform the steps of the various exemplary embodiments of the invention described in the "Exemplary Methods" section above.

[0175] refer to Figure 10As shown, a program product 1000 for implementing the above-described method according to an embodiment of the present invention is described. It may employ a portable compact disc read-only memory (CD-ROM) and include program code, and may run on a terminal device, such as a personal computer. However, the program product of the present invention is not limited thereto. In this document, the readable storage medium may be any tangible medium containing or storing a program that may be used by or in conjunction with an instruction execution system, apparatus, or device.

[0176] The program product may employ any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: an electrical connection having one or more wires, a portable disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0177] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, carrying readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A readable signal medium may also be any readable medium other than a readable storage medium, capable of sending, propagating, or transmitting programs for use by or in conjunction with an instruction execution system, apparatus, or device.

[0178] The program code contained on the readable medium may be transmitted using any suitable medium, including but not limited to wireless, wired, optical fiber, RF, etc., or any suitable combination thereof.

[0179] Program code for performing the operations of this invention can be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java and C++, and conventional procedural programming languages ​​such as C or similar languages. The program code can execute entirely on the user's computing device, partially on the user's device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0180] Furthermore, the above figures are merely illustrative of the processes included in the method according to exemplary embodiments of the present invention, and are not intended to be limiting. It is readily understood that the processes shown in the above figures do not indicate or limit the temporal order of these processes. Additionally, it is readily understood that these processes may be executed synchronously or asynchronously, for example, in multiple modules.

[0181] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0182] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A functional verification method applied to a memory, characterized in that, include: Obtain the initial design circuit corresponding to the chip to be designed; Based on the initial design circuit, determine all test count values ​​contained in the chip to be designed; Randomly select a specified number of target test counts from all the test counts; Based on the target test count value, the initial design circuit of the chip to be designed is functionally verified to obtain the functional verification result; The process of determining all test count values ​​contained in the chip to be designed based on the initial design circuit includes: Based on the initial design circuit, all address types corresponding to the chip to be designed are determined, and each address type corresponds to at least one binary counter circuit. Determine the addressing range corresponding to each of the addressing address types, wherein the addressing range is associated with the counting range of the binary counter circuit; Based on the addressing range corresponding to each addressing address type, determine all test count values ​​contained in each addressing address type in the chip to be designed; The step of randomly selecting a specified number of target test counts from all the test counts includes: A first preset number of header test addresses and tail test addresses are determined based on each of the addressing address types; Determine the random reference address corresponding to each of the addressing address types; Based on the random reference address, a second preset number of random test addresses are determined for each of the addressing intervals; Based on the obtained head test address, tail test address and random test address, determine the target test count value corresponding to each addressing address type; The step of determining a first preset number of header test addresses and tail test addresses based on each of the addressing address types includes: Obtain the initial and end addresses of the addressing range corresponding to each of the addressing address types; Based on the initial address, determine a first preset number of consecutive header test addresses; A first preset number of consecutive tail test addresses are determined based on the end address.

2. The method according to claim 1, characterized in that, The step of obtaining the initial design circuit corresponding to the chip to be designed includes: Obtain the functional specification file corresponding to the chip to be designed, and generate the initial design circuit based on the functional specification file.

3. The method according to claim 1, characterized in that, The functional verification of the initial design circuit of the chip to be designed based on the target test count value, to obtain the functional verification result, includes: A circuit simulation netlist is generated based on the initial circuit design. Based on the circuit simulation netlist and the target test count, the initial design circuit is functionally verified to obtain the circuit verification results; The initial design circuit that passes the circuit verification is used as the target design circuit.

4. The method according to claim 3, characterized in that, The step of performing functional verification on the initial design circuit based on the circuit simulation netlist and the target test count value to obtain circuit verification results includes: Simulation test data is generated based on the target test count value. The simulation test data includes simulation test input waveforms. Each target test count value corresponds to a random verification address in the initial design circuit. Based on the simulation detection input waveform and the circuit simulation netlist, the random verification address in the initial design circuit is functionally simulated and verified to obtain the simulation verification waveform. The circuit verification results of the initial design circuit are determined based on the simulation verification waveforms.

5. The method according to claim 1, characterized in that, Determining the random reference address corresponding to each of the addressing address types includes: Get the current system time; The time value to be identified is determined based on the addressing range of the addressing address type and the current system time; The time value to be identified is converted into the corresponding address conversion value, and the random reference address is determined based on the address conversion value.

6. The method according to claim 5, characterized in that, The time value to be identified includes minute time values, second time values, and millisecond time values; the step of converting the time value to be identified into the corresponding address conversion value includes: Determine the parity of the value at each time digit in the minute time value, the second time value, and the millisecond time value, respectively; Determine the correspondence between each of the time bits and the address conversion value; If the value in the time bit is odd, then the address conversion value corresponding to the time bit is configured to the first value; If the value in the time bit is even, then the address conversion value corresponding to the time bit is configured to the second value.

7. The method according to claim 5, characterized in that, The step of converting the time value to be identified into the corresponding address conversion value includes: Determine the original time value or the padded time value corresponding to each time bit in the time value to be identified; the padded time value is generated based on at least one bit of the original time value. The address conversion value is determined based on the parity of each original time value and the padded time value; If the original time value or the padding time value is odd, then the corresponding address conversion value is configured to the first value; If the original time value or the padding time value is even, then the corresponding address conversion value is configured to the second value.

8. The method according to claim 7, characterized in that, Determining the original time value or padding time value corresponding to each time bit in the time value to be identified includes: Determine the original time bit and the padded time bit corresponding to the time value to be identified; The time value at each of the original time bits is taken as the corresponding original time value; The original time bit associated with each of the aforementioned time padding bits is taken as the corresponding associated time bit; Obtain the associated time value at each associated time bit, and determine the corresponding padding time value at the padding time bit based on each associated time value.

9. The method according to any one of claims 1-8, characterized in that, The addressing address type includes the addressing address type to be segmented; the step of determining a first preset number of header test addresses and tail test addresses based on each of the addressing address types includes: The address type to be segmented is segmented to obtain a segmented address; The corresponding head test address, tail test address, and random test address are determined based on each segmented address.

10. The method according to claim 1, characterized in that, The addressing address type includes any one or more combinations of row address, column address, memory bank address, and memory bank group address.

11. The method according to claim 3, characterized in that, The method further includes: If the functional verification result is passed, then the coverage verification process is performed on the target design circuit to obtain the corresponding coverage verification result; If the coverage verification result is passed, then the regression verification process is executed to obtain the corresponding regression verification result; If the regression verification result is passed, the verification process ends and the corresponding verification end result is obtained. The coverage verification process, the regression verification process, and the termination verification process all include a functional verification process for the initial design circuit.

12. The method according to claim 3, characterized in that, The method further includes: If the functional verification result is unsuccessful, then the initial design circuit is updated; The functional verification of the chip under design was re-performed based on the updated initial design circuit.

13. The method according to claim 11, characterized in that, The verification process for the target design circuit includes a coverage verification process, a regression verification process, and a final verification process; the method further includes: If the verification result of each verification process for the target circuit design is a pass, then the chip manufacturing process is executed; If the verification result of any of the verification processes is a failure, then the target design circuit is updated; The entire verification process is re-executed for the chip under design based on the updated target design circuit.

14. An electronic device, characterized in that, include: processor; as well as A memory storing computer-readable instructions that, when executed by the processor, implement the functional verification method according to any one of claims 1 to 13.

15. A computer-readable storage medium having a computer program stored thereon, the computer program, when executed by a processor, implementing the functional verification method according to any one of claims 1 to 13.

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