Memory read / write verification method

Abstract

This invention discloses a memory read / write verification method. First, a margin verification is performed on all memory I / Os based on input data, and the read data corresponding to each I / O is obtained based on the verification results. This allows for determining whether to perform a write operation on the I / O corresponding to the read data. Then, a write operation is performed on the I / Os that require a write operation. Finally, after the write operation is completed, a margin verification is performed again to determine whether the corresponding I / O was successfully written based on the verification results. This avoids duplicate writes and improves verification efficiency.

Description

Technical Field

[0001] This invention relates to the field of electronic technology, and in particular to a memory read / write verification method and a computer-readable storage medium. Background Technology

[0002] In related technologies, each time data is written to a memory, it is necessary to verify whether the actual value written is equal to the input value and whether the read current meets a certain margin. In other words, verification is required every time data is written. Existing read and write verification methods require the entire system to perform Margin 0 verification or Margin 1 verification separately. When a write failure occurs, it needs to be rewritten. In other words, regardless of whether the original write was successful, it needs to be rewritten. This not only increases system consumption but also easily leads to overwrite phenomenon. Summary of the Invention

[0003] The present invention aims to at least partially solve one of the technical problems in the aforementioned technologies. Therefore, one objective of the present invention is to provide a memory read / write verification method that avoids repeated writes, thereby improving verification efficiency.

[0004] A second objective of this invention is to provide a computer-readable storage medium.

[0005] To achieve the above objectives, a memory read / write verification method is proposed in the first aspect of the present invention, comprising the following steps: performing margin verification on all I / Os of the memory based on input data, and obtaining the read data corresponding to each I / O based on the verification results, so as to determine whether to perform a write operation on the I / O corresponding to the read data based on the read data; performing a write operation on the I / O that needs to be written; and performing margin verification again after the write operation is completed, so as to determine whether the corresponding I / O has been successfully written based on the verification results.

[0006] According to the memory read / write verification method proposed in this embodiment of the invention, firstly, margin verification is performed on all I / Os of the memory based on the input data, and the read data corresponding to each I / O is obtained based on the verification results, so as to determine whether to perform a write operation on the I / O corresponding to the read data; then, the write operation is performed on the I / O that needs to be written; finally, after the write operation is completed, margin verification is performed again, so as to determine whether the corresponding I / O has been successfully written based on the verification results; thereby, duplicate writing can be avoided, thereby improving verification efficiency.

[0007] In addition, the memory read / write verification method proposed above according to embodiments of the present invention may also have the following additional technical features:

[0008] Optionally, margin verification is performed on all memory I / Os based on the input data, including: when the input data is 0, Margin 0 verification is performed on the I / Os corresponding to the input data of 0, and when the input data is 1, Margin 1 verification is performed on the I / Os corresponding to the input data of 1.

[0009] Based on the above technical means, all IOs can choose to perform Margin 0 verification or Margin 1 verification according to the corresponding input data, thereby reducing system consumption and further improving verification efficiency.

[0010] Optionally, the IO corresponding to the input data being 0 is subjected to Margin 0 verification, including: comparing the current of the IO corresponding to the input data being 0 with Margin 0, where Margin 0 represents the margin that needs to be satisfied when writing 0.

[0011] Optionally, a Margin 1 verification is performed on the IO corresponding to the input data being 1, including: comparing the current of the IO corresponding to the input data being 1 with the Margin 1, where Margin 1 represents the margin that needs to be satisfied when writing 1.

[0012] Optionally, the read data corresponding to each IO can be obtained based on the verification results, including: if the current of the IO corresponding to the input data is 0 is less than Margin 0, then the corresponding read data is 0; otherwise, the corresponding read data is 1.

[0013] Optionally, if the current of the IO corresponding to the input data is 1 is greater than Margin 1, then the corresponding read data is 1; otherwise, the corresponding read data is 0.

[0014] Optionally, determining whether to perform a write operation on the IO corresponding to the read data based on the read data includes: determining whether the read data is equal to the corresponding input data; if so, the IO corresponding to the read data does not perform a write operation; if not, the IO corresponding to the read data performs a write operation.

[0015] Optionally, the write success of the corresponding IO can be determined based on the verification result, including: if the current of the IO corresponding to the input data is 0 is less than Margin 0, then the corresponding read data is 0, and the write is considered successful; otherwise, the write fails. If the current of the IO corresponding to the input data is 1 is greater than Margin 1, then the corresponding read data is 1, and the write is considered successful; otherwise, the write fails.

[0016] Optionally, if the verification result indicates that the corresponding IO write has failed, then continue to perform write operations on the IOs that need to be written, repeating the iteration until it is determined that all IO writes have been successful.

[0017] To achieve the above objectives, a second aspect of the present invention provides a computer-readable storage medium storing a memory read / write verification program thereon, which, when executed by a processor, implements the memory read / write verification method as described above.

[0018] According to embodiments of the present invention, a computer-readable storage medium stores a memory read / write verification program so that when the processor executes the memory read / write verification program, it can implement the memory read / write verification method as described above, thereby avoiding repeated writing and improving verification efficiency. Attached Figure Description

[0019] Figure 1 A flowchart illustrating the existing memory read / write verification method;

[0020] Figure 2 The diagram shows the read / write circuit corresponding to the existing memory read / write verification method, where (a) is the read circuit diagram and (b) is the write circuit diagram.

[0021] Figure 3 This is a flowchart illustrating a memory read / write verification method according to an embodiment of the present invention.

[0022] Figure 4 This is a flowchart illustrating a memory read / write verification method according to an embodiment of the present invention.

[0023] Figure 5 The present invention provides a schematic diagram of a read / write circuit corresponding to a memory read / write verification method according to an embodiment of the present invention, wherein (a) is a schematic diagram of the read circuit and (b) is a schematic diagram of the write circuit. Detailed Implementation

[0024] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0025] In related technologies, such as Figure 1 As shown, the existing verification read-in diagram shows that when Verify 0, M0_EN is enabled and M1_EN is disabled, and DOUT reads data; when Verify 1, M0_EN is disabled and M1_EN is enabled, and DOUT reads data. The write driver diagram shows that when WE is enabled, a write operation is performed. When DIN=0, W1_EN is disabled and W0_EN is enabled, performing a write 0 operation; when DIN=1, W1_EN is enabled and W0_EN is disabled, performing a write 1 operation. The corresponding flowchart is shown below. Figure 2As shown, the first write operation is performed; then, M1_EN is enabled, and all IOs perform Verify 1 operation to read the cell data at the specified address. If the specified DOUT is different from the IO with DIN=1, the write operation fails, and data writing continues until a certain condition is met. If the specified DOUT is the same as the IO with DIN=1, the write operation succeeds. Finally, M0_EN is enabled, and all IOs perform Verify 0 to read the cell data at the specified address. If the specified DOUT is different from the IO with DIN=0, the write operation fails, and data writing continues until a certain condition is met. If the specified DOUT is the same as the IO with DIN=0, the write operation succeeds. Therefore, the existing read / write verification method requires the following steps: Write -> Verify1 (0) -> Verify0 (1). Each verification is performed by all IOs, that is, Verify 0 is the entire system verifying whether the address to be written with 0 is written with 0, and Verify 1 is the entire system verifying whether the address to be written with 1 is written with 1. This kind of discrete operation significantly increases system consumption; and if a write operation fails once, at least one additional Verify operation is required if disturbines are to be written, which also increases system consumption; furthermore, if a write operation fails once, it needs to be rewritten, and this rewriting is also system-level, meaning that regardless of whether the original write was successful or not, it needs to be rewritten; this operation may result in overwrite.

[0026] To address the aforementioned problems, this invention proposes a memory read / write verification method that implements the following steps: Write -> Verify. The Verify process involves simultaneous Verify 0 and Verify 1 operations; the specific Verify 0 or Verify 1 operation depends on the input data. This simultaneous Verify structure reduces system overhead and increases Verify efficiency. Furthermore, it enables writing to cells that have successfully been written to, only writing to cells that have failed Verification. Each time a write operation is completed, the current address is verified, with the specific Verify operation implemented according to DIN. Therefore, this invention avoids overwrite phenomena and does not require additional Verification steps.

[0027] To better understand the above technical solutions, exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the invention to those skilled in the art.

[0028] To better understand the above technical solutions, the following will provide a detailed explanation of the technical solutions in conjunction with the accompanying drawings and specific implementation methods.

[0029] The memory read / write verification method of the present invention will now be described with reference to the accompanying drawings.

[0030] Specifically, Figure 3 This is a flowchart illustrating a memory read / write verification method provided in an embodiment of this application. Figure 3 As shown, the memory read / write verification method includes the following steps:

[0031] Step 101: Perform margin verification on all memory I / Os based on the input data, and obtain the read data corresponding to each I / O based on the verification results, so as to determine whether to perform a write operation on the I / O corresponding to the read data.

[0032] In other words, a margin verification is performed before a write operation to avoid rewriting previously successfully written IO.

[0033] It should be noted that the verification results can be used to determine whether the corresponding IO was successfully written. The determination method can be manual or determined by a specific device. This invention does not impose any specific limitations on this.

[0034] As one embodiment, margin verification is performed on all memory I / Os based on the input data, including: when the input data is 0, Margin 0 verification is performed on the I / Os corresponding to the input data of 0; when the input data is 1, Margin 1 verification is performed on the I / Os corresponding to the input data of 1.

[0035] In other words, during the verification process, each IO can perform either Margin 0 verification or Margin 1 verification based on the input data. That is to say, each IO performs either Margin 0 verification or Margin 1 verification as needed, thereby enabling all IOs to be verified simultaneously.

[0036] As an example, performing Margin 0 verification on the IO corresponding to input data 0 includes: comparing the current of the IO corresponding to input data 0 with Margin 0, where Margin 0 represents the margin that needs to be satisfied when writing 0.

[0037] As an example, the read data corresponding to each IO is obtained according to the verification result, including: if the current of the IO corresponding to the input data is 0 is less than Margin 0, then the corresponding read data is 0; otherwise, the corresponding read data is 1.

[0038] In other words, if the input data is 0 and the corresponding read data is 0, it means the write was successful; if the input data is 0 and the corresponding read data is 1, it means the write failed.

[0039] As an example, performing Margin 1 verification on the IO corresponding to input data 1 includes: comparing the current of the IO corresponding to input data 1 with Margin 1, where Margin 1 represents the margin that needs to be satisfied when writing 1.

[0040] As one example, obtaining the read data corresponding to each IO based on the verification results also includes:

[0041] If the current of the IO corresponding to the input data is 1 is greater than Margin 1, then the corresponding read data is 1; otherwise, the corresponding read data is 0.

[0042] In other words, if the input data is 1 and the corresponding read data is 1, it means the write was successful; if the input data is 1 and the corresponding read data is 0, it means the write failed.

[0043] As one example, determining whether to perform a write operation on the IO corresponding to the read data based on the read data includes: determining whether the read data is equal to the corresponding input data; if so, the IO corresponding to the read data does not perform a write operation; if not, the IO corresponding to the read data performs a write operation.

[0044] It should be noted that if the read data is equal to the corresponding input data, it means that the write was successful. Therefore, the corresponding IO does not need to perform a write operation again. In this case, it is only necessary to re-perform the write operation for the IO that failed to write.

[0045] Step 102: Perform a write operation on the IO that needs to be written.

[0046] It should be noted that the IO that needs to perform a write operation refers to the IO that has been judged to have failed to write.

[0047] Step 103: After the write operation is completed, perform margin verification again to determine whether the corresponding IO was successfully written based on the verification result.

[0048] It should be noted that the determination of whether the corresponding IO is successfully written is based on the verification results, including: when the current of the IO corresponding to the input data is 0 is less than Margin 0, the corresponding read data is 0, and the write is considered successful; otherwise, the write fails. When the current of the IO corresponding to the input data is 1 is greater than Margin 1, the corresponding read data is 1, and the write is considered successful; otherwise, the write fails.

[0049] As an example, such as Figure 4As shown, if the verification result indicates that the corresponding IO write has failed, the write operation will continue to be performed on the IOs that need to be written, and the process will be repeated until all IOs are determined to have been successfully written.

[0050] In other words, step 1 involves verifying once to read the DOUT of each IO at the specified address; step 2 involves checking if DIN = DOUT, then the IO does not perform a write operation, otherwise the IO performs a write operation; step 3 involves verifying again, and if the IO that writes 0 satisfies Margin 0 and the IO that writes 1 satisfies Margin 1, then all IOs are successfully written; otherwise, step 2 is returned to repeat the write operation for the IOs that failed to write.

[0051] In other words, the Verify step 1 of this process prevents the IO with DIN=DOUT from performing write operations, thus preventing overwrite and reducing system consumption; each Verify operation involves each IO performing the corresponding Verify 0 or Verify 1 operation based on DIN, simplifying the system's write and Verify process.

[0052] As a specific embodiment, Figure 5 This is a schematic diagram of a read / write circuit corresponding to a memory read / write verification method according to an embodiment of the present invention, wherein, as shown... Figure 5 As shown in (a), the Verify structure includes a first NOT gate, a first AND gate, a first verification unit, a second verification unit, and a second AND gate;

[0053] The first NOT gate is used to perform a NOT operation on the input data DIN;

[0054] The first input of the first AND gate receives the input data after the NOT operation, the second input of the first AND gate receives the verification enable signal Verify_EN, and the output of the first AND gate is connected to the first verification unit Margin 0 so as to send the write 0 verification enable signal M0_EN to the first verification unit Margin 0.

[0055] The first input of the second AND gate receives the input data DIN, the second input of the second AND gate receives the verification enable signal Verify_EN, and the output of the second AND gate is connected to the second verification unit Margin 1 so as to send the write 1 verification enable signal M1_EN to the second verification unit Margin 1.

[0056] The first verification unit Margin 0 is connected to the second verification unit Margin 1 so that all I / Os of the memory can be verified based on the input data DIN, and the read data DOUT corresponding to each I / O can be obtained based on the verification results.

[0057] It should be noted that the Verify structure also includes a storage unit and a sampling module. The storage unit is used to store data, and the sampling unit is used to sample and read out the data DOUT.

[0058] In other words, by using the above structure, Verify_EN is enabled when verification is required. When DIN=0, Margin0 verification is performed; when DIN=1, Margin 1 verification is performed. This allows each IO to be verified by either Margin 0 or Margin 1 based on DIN, meaning all IOs can be verified simultaneously. The entire system can perform Verify 0 and Verify 1 verifications simultaneously, thereby reducing system consumption and increasing Verify efficiency.

[0059] Among them, such as Figure 5 As shown in (b), the write driver structure includes a second NOT gate, a third AND gate, a third NOT gate, a fourth AND gate, and a write driver unit;

[0060] The second NOT gate is used to perform a NOT operation on the read data DOUT;

[0061] The first input of the third AND gate receives the write enable signal WE, the second input of the third AND gate receives the input data DIN, the third input of the third AND gate receives the read data after the NOT operation, and the output of the third AND gate is connected to the write driver unit so as to send the write 1 enable signal W1_EN to the write driver unit and write 1 according to the write 1 enable signal.

[0062] The third NOT gate is used to perform NOT operation on the input data DIN;

[0063] The first input of the fourth AND gate receives the write enable signal WE, the second input of the fourth AND gate receives the input data after the NOT operation, the third input of the fourth AND gate receives the read data DOUT, and the output of the fourth AND gate is connected to the write driver unit so as to send the write 0 enable signal W0_EN to the write driver unit and write 0 according to the write 0 enable signal.

[0064] In other words, with the above structure, when performing a write operation, for example, when DIN=1, no write operation is needed when DOUT=1, and a write operation of 1 is performed only when DOUT=0; when DIN=0, a write operation of 0 is performed when DOUT=1, and no write operation is needed when DOUT=0. This structure will not perform a write operation when the input DIN is equal to the DOUT of the last Verify, which can prevent overwrite and reduce system consumption.

[0065] In summary, the memory read / write verification method proposed in this embodiment of the invention first performs margin verification on all memory I / Os based on input data, and obtains the read data corresponding to each I / O based on the verification results, so as to determine whether to perform a write operation on the I / O corresponding to the read data; then, the write operation is performed on the I / O that needs to be written; finally, after the write operation is completed, margin verification is performed again, so as to determine whether the corresponding I / O has been successfully written based on the verification results; thereby, duplicate writing can be avoided, thereby improving verification efficiency.

[0066] In addition, embodiments of the present invention also propose a computer-readable storage medium storing a memory read / write verification program thereon, which, when executed by a processor, implements the memory read / write verification method as described above.

[0067] According to embodiments of the present invention, a computer-readable storage medium stores a memory read / write verification program so that when the processor executes the memory read / write verification program, it can implement the memory read / write verification method as described above, thereby avoiding repeated writing and improving verification efficiency.

[0068] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0069] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0070] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0071] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0072] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. The illustrative expressions of the above terms in this specification should not be construed as necessarily referring to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0073] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A method for verifying memory read / write operations, characterized in that, The method includes: Based on the input data, all memory I / Os are checked for margin, and the read data corresponding to each I / O is obtained based on the check results, so as to determine whether to perform a write operation on the I / O corresponding to the read data. Perform write operations on I / O operations that require write operations; After the write operation is completed, a margin verification is performed again to determine whether the corresponding IO was successfully written based on the verification result. This includes performing margin verification on all memory I / O based on the input data, including: When the input data is 0, the IO corresponding to the input data is 0 is validated with Margin 0; when the input data is 1, the IO corresponding to the input data is 1 is validated with Margin 1. The process of determining whether to perform a write operation on the IO corresponding to the read data based on the read data includes: Determine whether the read data is equal to the corresponding input data. If yes, the IO corresponding to the read data will not perform a write operation; otherwise, the IO corresponding to the read data will perform a write operation. The read structure used in margin verification includes a first NOT gate, a first AND gate, a first verification unit, a second verification unit, and a second AND gate. The first NOT gate is used to perform NOT operation on the input data; The first input of the first AND gate receives the input data after the NOT operation, the second input of the first AND gate receives the verification enable signal, and the output of the first AND gate is connected to the first verification unit so as to send a write 0 verification enable signal to the first verification unit. The first input terminal of the second AND gate receives input data, the second input terminal of the second AND gate receives a verification enable signal, and the output terminal of the second AND gate is connected to the second verification unit so as to send a write-1 verification enable signal to the second verification unit. The first verification unit is connected to the second verification unit so that all I / Os of the memory can be verified based on the input data, and the read data corresponding to each I / O can be obtained based on the verification results.

2. The memory read / write verification method according to claim 1, characterized in that, Margin 0 validation is performed on the I / O operations corresponding to input data of 0, including: The current of the IO corresponding to an input data of 0 is compared with Margin 0, where Margin 0 represents the margin required to write 0.

3. The memory read / write verification method according to claim 2, characterized in that, Margin 1 validation is performed on the IO corresponding to input data of 1, including: The current of the IO corresponding to the input data of 1 is compared with Margin 1, where Margin 1 represents the margin that needs to be satisfied when writing 1.

4. The memory read / write verification method according to claim 3, characterized in that, Based on the verification results, obtain the read data corresponding to each IO, including: If the current of the IO corresponding to the input data is 0 is less than Margin 0, then the corresponding read data is 0; otherwise, the corresponding read data is 1.

5. The memory read / write verification method according to claim 4, characterized in that, Based on the verification results, the read data corresponding to each IO is obtained, including: If the current of the IO corresponding to the input data is 1 is greater than Margin 1, then the corresponding read data is 1; otherwise, the corresponding read data is 0.

6. The memory read / write verification method according to claim 5, characterized in that, Based on the verification results, determine whether the corresponding IO was successfully written, including: If the current of the IO corresponding to the input data is 0 is less than Margin 0, then the corresponding read data is 0, and the write is considered successful; otherwise, the write fails. If the current of the IO corresponding to the input data is 1 is greater than Margin 1, then the corresponding read data is 1, and the write is considered successful; otherwise, the write fails.

7. The memory read / write verification method according to claim 1, characterized in that, If the verification results indicate that the corresponding IO write has failed, continue to perform write operations on the IOs that need to be written, repeating the iteration until all IO writes are determined to be successful.

8. A computer-readable storage medium, characterized in that, It stores a memory read / write verification program, which, when executed by the processor, implements the memory read / write verification method as described in any one of claims 1-7.

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