A 10T SRAM circuit for implementing iterative or computational operations in memory
By designing a 10T SRAM circuit, the memory performance bottleneck in the traditional von Neumann architecture was solved, enabling iterative computation in memory, improving computation speed and efficiency, and expanding application scenarios.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- ANHUI UNIV
- Filing Date
- 2022-09-15
- Publication Date
- 2026-07-17
AI Technical Summary
In the traditional von Neumann architecture, the speed of memory and processor is mismatched, causing memory performance to become a bottleneck in computer performance, especially in fields with large computational demands such as machine learning and image recognition, where there is a lack of circuit structures for iterative or computational operations in memory.
Design a 10T SRAM circuit, using a 10T SRAM cell as the basic unit, including an upper part, a middle part and a lower part, each composed of specific transistors. The middle part is used as a switch to realize the function of storing data in multiple rows or for calculation and cell storage. Data can be stored in both the upper and lower parts.
It improves computing speed and efficiency, reduces energy consumption during data transmission, expands application scenarios, and has a simple structure, enabling high-speed iterative or computational processing.
Smart Images
Figure CN115472196B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit technology, and more particularly to a 10TSRAM (10T Static Random Access Memory) circuit that implements iterative or computational operations in memory. Background Technology
[0002] With the rapid development of artificial intelligence, applications such as machine learning and edge computing have seen rapid growth, placing higher demands on computing speed. However, the traditional von Neumann architecture separates the processor's computing units from its memory. Data is read from memory during processing and written back after processing. Due to the rapid advancements of Moore's Law, memory speed has become out of sync with processor speed. Memory access speed lags significantly behind processor processing speed, making memory performance a major bottleneck in overall computer performance, particularly evident in computationally intensive fields like machine learning and image recognition.
[0003] To overcome the drawbacks of traditional von Neumann architectures, computing in memory (CIM) has become a hot topic. CIM eliminates the need to transfer data to the processor, performing calculations directly in memory. This significantly reduces energy consumption for data access during computation, while improving both computational speed and energy efficiency. Iterative OR calculations have important applications in the Advanced Encryption Standard (AES), but current technologies lack circuit structures specifically designed for iterative OR calculations in memory. Summary of the Invention
[0004] The purpose of this invention is to provide a 10T SRAM circuit that implements iterative OR calculations in memory. This circuit can not only perform OR calculations on multiple rows of data, but also enable data to be stored in both the upper and lower parts of a single cell, thus breaking the spatial limitations on computation.
[0005] The objective of this invention is achieved through the following technical solution:
[0006] A 10T SRAM circuit for implementing iterative or computational operations in memory, wherein the circuit uses 10T SRAM cells as the basic unit and sets up n rows and n columns of memory cells, wherein:
[0007] Each 10T SRAM cell comprises an upper half, a middle half, and a lower half. PMOS transistors M1 and M2, and NMOS transistors M3 and M4 constitute the upper half; NMOS transistors M5 and M6 constitute the middle half; and PMOS transistors M7 and M8, and NMOS transistors M9 and M10 constitute the lower half. The upper and lower halves are stored as two 4T SRAM cells, and the middle half is used as a switch.
[0008] One end of PMOS transistor M1 is connected to power supply VDD, and the other end is connected to one end of NMOS transistors M3 and M5 to form storage node Q1, and they are connected to the gate of PMOS transistor M2; one end of PMOS transistor M2 is connected to power supply VDD, and the other end is connected to one end of NMOS transistors M4 and M6 to form storage node QB1, and they are connected to the gate of PMOS transistor M1.
[0009] The other end of NMOS transistor M3 is connected to bit line N_BL, and the other end of NMOS transistor M4 is connected to bit line N_BLB. The gates of NMOS transistors M3 and M4 are connected to word line N_WL. The gate of NMOS transistor M5 is connected to control signal CON_L, and the other end is connected together with one end of NMOS transistor M9 and PMOS transistor M7 to form memory node Q2. This point is connected to the gate of NMOS transistor M10.
[0010] The gate of NMOS transistor M6 is connected to the control signal CON_R, and the other end is connected together with one end of NMOS transistor M10 and one end of PMOS transistor M8 to form storage node QB2. This point is connected to the gate of NMOS transistor M9. The other end of PMOS transistor M7 is connected to bit line P_BL; the other end of PMOS transistor M8 is connected to bit line P_BLB; the gates of PMOS transistors M7 and M8 are connected to word line P_WL; the other end of NMOS transistor M9 is connected to the control signal CON_B; and the other end of NMOS transistor M10 is grounded to VSS.
[0011] For a memory cell with n rows and n columns, looking at each row, in the upper part: the upper access transistor of the 10T SRAM cell in the same row is connected to the same word line N_WL; in the lower part: the data access transistor of the 10T SRAM cell in the same row is connected to the same word line P_WL; the lower end of the NMOS transistor M9 in the same row is connected to CON_B, the gate of the NMOS transistor M5 is connected to CON_L, and the gate of the NMOS transistor M6 is connected to CON_R.
[0012] Looking at each column, in the upper part: the left side is connected to bit line N_BL, and the right side is connected to bit line N_BLB; in the lower part: the left side is connected to bit line P_BL, and the right side is connected to bit line P_BLB.
[0013] As can be seen from the technical solution provided by the present invention, the circuit can not only realize the calculation of multiple rows of data, but also realize the function of storing data in both the upper and lower parts of a single unit, thus making its application scenarios more extensive; moreover, the circuit structure is simple, which can effectively improve the efficiency and speed of operation and reduce the energy consumed in the transmission process. Attached Figure Description
[0014] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0015] Figure 1 A schematic diagram of a 10T SRAM circuit structure for implementing iterative or computational operations in memory, provided in an embodiment of the present invention;
[0016] Figure 2 This is a schematic diagram of the structure of each 10T SRAM cell according to an embodiment of the present invention;
[0017] Figure 3 This is a schematic diagram of the circuit described in an embodiment of the present invention during the 6T read / write operation phase;
[0018] Figure 4 This is a diagram showing the read / write structure of the circuit in dual 4T mode according to an embodiment of the present invention;
[0019] Figure 5 The diagram shows the computational structure and timing of the circuit in dual 4T mode according to the embodiments of the present invention. Detailed Implementation
[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments, and do not constitute a limitation of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present invention.
[0021] like Figure 1The diagram shown is a schematic of a 10T SRAM circuit structure for implementing iterative computation in memory according to an embodiment of the present invention. The circuit uses a 10T SRAM cell as the basic unit and sets up n rows and n columns of memory cells, wherein:
[0022] like Figure 2 The diagram shown is a structural schematic of each 10T SRAM cell according to an embodiment of the present invention. Each 10T SRAM cell includes an upper part, a middle part, and a lower part. PMOS transistors M1 and M2, and NMOS transistors M3 and M4 constitute the upper part; NMOS transistors M5 and M6 constitute the middle part; PMOS transistors M7 and M8, and NMOS transistors M9 and M10 constitute the lower part. The upper and lower parts are used as two 4T SRAM cells for storage, and the middle part is used as a switch.
[0023] One end of PMOS transistor M1 is connected to power supply VDD, and the other end is connected to one end of NMOS transistors M3 and M5 to form storage node Q1, and they are connected to the gate of PMOS transistor M2; one end of PMOS transistor M2 is connected to power supply VDD, and the other end is connected to one end of NMOS transistors M4 and M6 to form storage node QB1, and they are connected to the gate of PMOS transistor M1.
[0024] The other end of NMOS transistor M3 is connected to bit line N_BL, and the other end of NMOS transistor M4 is connected to bit line N_BLB. The gates of NMOS transistors M3 and M4 are connected to word line N_WL. The gate of NMOS transistor M5 is connected to control signal CON_L (control signal for the gate of transistor M5, which can turn Q1 and Q2 on or off). The other end is connected together with one end of NMOS transistor M9 and PMOS transistor M7 as storage node Q2, and this point is connected to the gate of NMOS transistor M10.
[0025] The gate of NMOS transistor M6 is connected to the control signal CON_R (the control signal for the gate of transistor M6, which can turn Q1 and Q2 on or off). The other end is connected to one end of NMOS transistor M10 and one end of PMOS transistor M8 to form storage node QB2, and this point is connected to the gate of NMOS transistor M9. The other end of PMOS transistor M7 is connected to bit line P_BL; the other end of PMOS transistor M8 is connected to bit line P_BLB; the gates of PMOS transistors M7 and M8 are connected to word line P_WL; the other end of NMOS transistor M9 is connected to the control signal CON_B (the control signal for the source of transistor M9, which can ground or float the source of M9); the other end of NMOS transistor M10 is grounded to VSS.
[0026] For a memory cell with n rows and n columns, looking at each row, in the upper part: the upper access transistor of the 10T SRAM cell in the same row is connected to the same word line N_WL; in the lower part: the data access transistor of the 10T SRAM cell in the same row is connected to the same word line P_WL; the lower end of the NMOS transistor M9 in the same row is connected to CON_B, the gate of the NMOS transistor M5 is connected to CON_L, and the gate of the NMOS transistor M6 is connected to CON_R.
[0027] Looking at each column, in the upper part: the left side is connected to bit line N_BL (the bit line on the left side of the upper half, used for read and write operations), and the right side is connected to bit line N_BLB (the bit line on the right side of the upper half, used for read and write operations); in the lower part: the left side is connected to bit line P_BL (the bit line on the left side of the lower half, used for read and write operations), and the right side is connected to bit line P_BLB (the bit line on the right side of the lower half, used for read and write operations).
[0028] Based on the structure of the circuit, such as Figure 3 The diagram shown is a schematic of the circuit described in this embodiment of the invention during the 6T read / write operation phase:
[0029] During a read operation: CON_L = 1, CON_R = 1, CON_B = 0, N_WL = 1; enable the upper half NMOS transistors M3 and M4, P_WL = 1, and disable the lower half NMOS transistors M7 and M8; bit lines N_BL and N_BLB are precharged to low level.
[0030] If the voltage of the left storage node Q is "1" and the voltage of the right storage node QB is "0", then the bit line N_BL is charged through the NMOS transistor M4 to complete the read "1" operation; if the voltage of the left storage node Q is "0" and the voltage of the right storage node QB is "1", then the bit line N_BL remains low and completes the read "0" operation.
[0031] During a write operation: In the middle section, CON_L = 1, CON_R = 1, CON_B = 0; P_WL = 0, enabling the lower half PMOS transistors M7 and M8; N_WL = 0, disabling the upper half NMOS transistors M3 and M4; bit lines P_BL and P_BLB are precharged to high level.
[0032] To write a "1", the row write module ROW_WIRTE sets bit line P_BL=1 and bit line P_BLB=0. Memory node Q will be charged through bit line P_BL, and memory node QB will be discharged to bit line P_BLB through PMOS transistor M8, thus completing the write "1" operation. To write a "0", the row write module ROW_WIRTE sets bit line P_BL=0 and bit line P_BLB=1. Memory node Q will be discharged through bit line P_BL, and bit line P_BLB will be discharged to memory node QB through NMOS transistor M8, thus completing the write "0" operation.
[0033] Based on the structure of the circuit, such as Figure 4 The diagram shown is a read / write structure diagram of the circuit in dual 4T mode according to an embodiment of the present invention, focusing on the read / write process of the upper 4T part:
[0034] During a read operation, the middle part CON_L = 0, CON_R = 0, CON_B = 0; bit lines N_BL and N_BLB are precharged to low level.
[0035] If the voltage of the left storage node Q is "1" and the voltage of the right storage node QB is "0", then the bit line N_BL is charged through the NMOS transistor M3 to complete the read "1" operation; if the voltage of the left storage node Q is "0" and the voltage of the right storage node QB is "1", then the bit line N_BL remains low and completes the read "0" operation.
[0036] During a write operation, the middle part CON_L = 0, CON_R = 0, CON_B = 0; bit lines N_BL and N_BLB are precharged to low level.
[0037] To write a "1", the row write module ROW_WIRTE sets bit line N_BL to high and bit line N_BLB to low. Memory node Q charges through bit line N_BL, and memory node QB discharges through NMOS transistor M4 to bit line N_BLB, thus completing the write "1" operation. To write a "0", the row write module ROW_WIRTE sets bit line N_BL to low and bit line N_BLB to high. Memory node Q discharges through bit line N_BL, and bit line N_BLB discharges through NMOS transistor M4 to memory node QB, thus completing the write "0" operation.
[0038] The read / write process for the lower 4T is similar to that for the upper 4T, and will not be described in detail here.
[0039] Based on the structure of the circuit, such as Figure 5 The diagram shown is the computational structure and timing diagram of the circuit in dual 4T mode according to an embodiment of the present invention. In operation mode:
[0040] Before performing calculations, the circuit is in a dual 4T mode structure, with CON_L=0, CON_R=0, and CON_B=0 in the middle part; the data to be written is written to the two storage nodes Q1 and Q2 respectively through the bit lines of the upper and lower parts; the specific writing method can be referred to the read and write section in the dual 4T mode.
[0041] When the operation signal is enabled, CON_L will jump from 0 to 1 within a very short period of time, turning on storage nodes Q1 and Q2. CON_B is floating during the period when CON_L = 1 and is not grounded. Therefore, there is no path from storage node Q1 to Q2 and then to ground, so the operation is performed in the 10T SRAM cell.
[0042] When Q1=0, Q2=0 and Q1=1, Q2=1, since the data stored in the upper and lower nodes is the same, when performing calculations, the left side of the 10T SRAM cell is turned on and off, and no potential difference is formed, so the data does not change.
[0043] When Q1 = 1 and Q2 = 0, the upper ends of the upper PMOS transistors M1 and M2 are connected to the power supply VDD. At this time, Q1 is affected by VDD and is called a strong "1". At this time, the path from Q2 to ground VSS is closed and is called a weak "0". Therefore, when CON_L = 1 and CON_B is floating, both the upper and lower terminals are on. Since the potential of Q1 is higher than that of Q2, the charge will be shared after the terminals are turned on, making the voltage levels of Q1 and Q2 equal. As there is a continuous charge flowing from VDD to Q2, and Q2 is connected to the gate of NMOS transistor M10, as the voltage of Q2 increases, the gate voltage of NMOS transistor M10 will increase. When the gate voltage of NMOS transistor M10 is higher than the transistor's turn-on voltage, NMOS transistor M10 turns on, pulling down the voltage of QB2. QB2 controls the gate of NMOS transistor M9. As the voltage of QB2 decreases, the gate voltage of NMOS transistor M9 will be less than the transistor's turn-on voltage, and NMOS transistor M9 will turn off, causing the charge accumulation at point Q2 to increase further. Under this mutually reinforcing change, the state of Q2 will eventually flip, becoming a weak "1".
[0044] When Q1 = 0 and Q2 = 1, the previous analysis leads to the conclusion that Q1 is a weak "0" and Q2 is a weak "1".
[0045] When CON_B is floating, CON_L = 1 and conducts vertically. Due to charge sharing, the level of Q1 will increase slightly, but only slightly, and will not change the state of Q1.
[0046] Analyzing the operations within the unit again, we can see that whether Q1 = 1 and Q2 = 0 or Q1 = 0 and Q2 = 1, weak "1" or weak "0" will appear after the operation. After the 4T operation in the upper part, some charge will accumulate in Q1. Similarly, in the lower part, Q2 will lose some charge due to charge sharing.
[0047] To further enhance the stability of the storage unit, this embodiment employs a dynamic compensation method to address this issue. Specifically:
[0048] The N_BL and N_BLB bit lines are precharged using a low level, while the P_BL and P_BLB bit lines are precharged using a high level.
[0049] After the operation, for a very short period, the access transistors N_WL=1 and P_WL=0 in both the upper and lower sections are turned on, i.e., NMOS transistors M3 and M4, and PMOS transistors M7 and M8 are turned on. This allows the charge accumulated in Q1 to be released through the NMOS transistor M3. Similarly, Q2 experiences a further increase in potential due to the inflow of current into the bit line P_BL, thus stabilizing and storing the processed data. At this point, the input data and the result are stored separately in the upper and lower 4T structures, achieving high-speed iterative OR operation. Figure 5 The entire calculation process can be seen quite clearly.
[0050] It is worth noting that the contents not described in detail in the embodiments of the present invention belong to the prior art known to those skilled in the art.
[0051] In summary, the circuit structure provided by this invention is simple, using a 10T SRAM unit as the basic unit. It can calculate the result of a single OR operation in the travel dimension within one cycle, and the result of N XOR operations in the travel dimension within N cycles. Compared with the traditional von Neumann architecture, which performs calculations in memory and in the processor, this circuit can reduce the energy consumption during data transmission and improve the speed and efficiency of computation. Compared with the traditional 6T SRAM structure, this circuit can also work as dual 4T SRAM, greatly increasing the storage capacity.
[0052] The above description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims. The information disclosed in the background section is intended only to enhance the understanding of the overall background technology of the present invention and should not be construed as an admission or implication in any way that such information constitutes prior art known to those skilled in the art.
Claims
1. A 10T SRAM circuit for implementing iterative or computational operations in memory, characterized in that, The circuit uses a 10TSRAM cell as the basic unit to set up an n-row n-column memory cell, wherein: Each 10T SRAM cell comprises an upper half, a middle half, and a lower half. PMOS transistors M1 and M2, and NMOS transistors M3 and M4 constitute the upper half; NMOS transistors M5 and M6 constitute the middle half; and PMOS transistors M7 and M8, and NMOS transistors M9 and M10 constitute the lower half. The upper and lower halves are stored as two 4T SRAM cells, and the middle half is used as a switch. One end of PMOS transistor M1 is connected to power supply VDD, and the other end is connected to one end of NMOS transistors M3 and M5 to form storage node Q1, and they are connected to the gate of PMOS transistor M2; one end of PMOS transistor M2 is connected to power supply VDD, and the other end is connected to one end of NMOS transistors M4 and M6 to form storage node QB1, and they are connected to the gate of PMOS transistor M1. The other end of NMOS transistor M3 is connected to bit line N_BL, and the other end of NMOS transistor M4 is connected to bit line N_BLB. The gates of NMOS transistors M3 and M4 are connected to word line N_WL. The gate of NMOS transistor M5 is connected to control signal CON_L, and the other end is connected together with one end of NMOS transistor M9 and PMOS transistor M7 to form memory node Q2. This point is connected to the gate of NMOS transistor M10. The gate of NMOS transistor M6 is connected to the control signal CON_R, and the other end is connected together with one end of NMOS transistor M10 and one end of PMOS transistor M8 to form storage node QB2. This point is connected to the gate of NMOS transistor M9. The other end of PMOS transistor M7 is connected to bit line P_BL; the other end of PMOS transistor M8 is connected to bit line P_BLB; the gates of PMOS transistors M7 and M8 are connected to word line P_WL; the other end of NMOS transistor M9 is connected to the control signal CON_B; and the other end of NMOS transistor M10 is grounded to VSS. For a memory cell with n rows and n columns, looking at each row, in the upper part: the upper access transistor of the 10T SRAM cell in the same row is connected to the same word line N_WL; in the lower part: the data access transistor of the 10T SRAM cell in the same row is connected to the same word line P_WL; the lower end of the NMOS transistor M9 in the same row is connected to CON_B, the gate of the NMOS transistor M5 is connected to CON_L, and the gate of the NMOS transistor M6 is connected to CON_R. Looking at each column, in the upper part: the left side is connected to bit line N_BL, and the right side is connected to bit line N_BLB; in the lower part: the left side is connected to bit line P_BL, and the right side is connected to bit line P_BLB. Based on the structure of the circuit, during the 6T read / write operation phase: During a read operation: CON_L=1, CON_R=1, CON_B=0, N_WL=1 in the middle section; enable the upper half NMOS transistors M3 and M4, P_WL=1, and disable the lower half PMOS transistors M7 and M8; bit lines N_BL and N_BLB are precharged to low level. If the voltage of the left storage node Q is "1" and the voltage of the right storage node QB is "0", then the bit line N_BL is charged through the NMOS transistor M3 to complete the read "1" operation; if the voltage of the left storage node Q is "0" and the voltage of the right storage node QB is "1", then the bit line N_BL remains low and completes the read "0" operation. During a write operation: CON_L=1, CON_R=1, CON_B=0 in the middle part; word line P_WL=0, enabling the lower half PMOS transistors M7 and M8, N_WL=0, disabling the upper half NMOS transistors M3 and M4 access transistors; bit lines P_BL and P_BLB are precharged to high level; To perform a write "1" operation, the row write module ROW_WIRTE sets bit line P_BL=1 and bit line P_BLB=0. Memory node Q will be charged through bit line P_BL, and memory node QB will be discharged to bit line P_BLB through PMOS transistor M8, thus completing the write "1" operation. To perform a write "0" operation, the row write module ROW_WIRTE sets bit line P_BL=0 and bit line P_BLB=1. Memory node Q will be discharged through bit line P_BL, and bit line P_BLB will be discharged to memory node QB through PMOS transistor M8, thus completing the write "0" operation.
2. The 10T SRAM circuit for implementing iterative or computational operations in memory according to claim 1, characterized in that, Based on the structure of the circuit, during the dual 4T read / write phase: Regarding the read / write process of the 4T section above: During a read operation, the middle part CON_L=0, CON_R=0, CON_B=0; bit lines N_BL and N_BLB are precharged to low level; If the voltage of the left storage node Q is "1" and the voltage of the right storage node QB is "0", then the bit line N_BL is charged through the NMOS transistor M3 to complete the read "1" operation; if the voltage of the left storage node Q is "0" and the voltage of the right storage node QB is "1", then the bit line N_BL remains low and completes the read "0" operation. During a write operation, the middle part CON_L=0, CON_R=0, CON_B=0; bit lines N_BL and N_BLB are precharged to low level; To perform a write "1" operation, the row write module ROW_WIRTE sets bit line N_BL to high and bit line N_BLB to low. Memory node Q will charge through bit line N_BL, and memory node QB will discharge through NMOS transistor M4 to bit line N_BLB, thus completing the write "1" operation. To perform a write "0" operation, the row write module ROW_WIRTE sets bit line N_BL to low and bit line N_BLB to high. Memory node Q will discharge through bit line N_BL, and bit line N_BLB will discharge through NMOS transistor M4 to memory node QB, thus completing the write "0" operation.
3. The 10T SRAM circuit for implementing iterative or computational operations in memory according to claim 1, characterized in that, Based on the structure of the circuit, the circuit operates in the following way: Before the calculation, the circuit is in a dual 4T mode structure, with CON_L=0, CON_R=0, and CON_B=0 in the middle part; the data to be written is written to the two storage nodes Q1 and Q2 respectively through the bit lines of the upper and lower parts. When the operation signal is enabled, the control signal CON_L will jump from 0 to 1, turning on storage nodes Q1 and Q2. CON_B is floating during the period when CON_L=1 and is not grounded. Therefore, there is no path from storage node Q1 to Q2 and then to ground, so the operation is performed in the 10T SRAM cell. When Q1=0, Q2=0 and Q1=1, Q2=1, since the data stored in the upper and lower nodes is the same, when performing calculations, the left side of the 10TSRAM cell is turned on and off, and no potential difference is formed, so the data does not change. When Q1=1 and Q2=0, the upper ends of the PMOS transistors M1 and M2 are connected to the power supply VDD. At this time, Q1 is affected by VDD and is called a strong "1". The path from Q2 to ground VSS is closed and is called a weak "0". Therefore, when CON_L=1 and CON_B is floating, both transistors are conducting. Since the potential at Q1 is higher than that at Q2, the charge will be shared after conduction, making the voltage levels of Q1 and Q2 equal. Because there is a continuous charge flowing from VDD to Q2, and Q2 is connected to the gate of NMOS transistor M10, as... The increase in the voltage of Q2 will increase the gate voltage of NMOS transistor M10. When the gate voltage of NMOS transistor M10 is higher than the transistor's turn-on voltage, NMOS transistor M10 turns on, which will pull down the voltage of QB2. QB2 controls the gate of NMOS transistor M9. As the voltage of QB2 decreases, the gate voltage of NMOS transistor M9 will be less than the transistor's turn-on voltage, and NMOS transistor M9 will turn off, causing the charge accumulation at point Q2 to increase further, eventually causing the state of Q2 to flip and become a weak "1". When Q1=0 and Q2=1, we conclude that Q1 is a weak "0" and Q2 is a weak "1". When CON_B is floating, CON_L=1 conducts both vertically and horizontally. Due to charge sharing, the level of Q1 will increase slightly, but only slightly, and will not change the state of Q1. Whether Q1=1 and Q2=0 or Q1=0 and Q2=1, weak "1" or weak "0" will appear after the operation. After the 4T operation in the upper part, some charge will accumulate in Q1. Similarly, in the lower part, Q2 will lose some charge due to charge sharing. To further enhance the stability of the storage cells, a dynamic compensation method is adopted to solve this problem. Specifically: The N_BL and N_BLB bit lines are precharged using a low level, while the P_BL and P_BLB bit lines are precharged using a high level. After the operation, the access transistors N_WL=1 and P_WL=0 are turned on in both the upper and lower parts, that is, NMOS transistors M3 and M4, and PMOS transistors M7 and M8 are turned on. In this way, the charge accumulated in Q1 will be released through the access transistor NMOS transistor M3. Similarly, Q2 will have its potential further increased by the current flowing into the bit line P_BL, so as to stabilize and save the data after the operation. At this time, the input data and the result of the operation are stored in the upper and lower 4T structures respectively, realizing the function of high-speed iterative OR operation.