Memory chip and operating method

Abstract

The application discloses a storage chip and an operating method. The storage chip comprises a first pin, a first input buffer, and a first switch, and / or a second pin, a level conversion buffer, and a second switch. Through time-sharing work of the first input buffer and the first switch, normal work signals can be transmitted from the first pin to a first transmission end in a first time period, and first external high-voltage signals can be transmitted from the first pin to a second transmission end in a second time period. Thus, the first external high-voltage signals can be used for test work without increasing the number of pins.

Description

Technical Field

[0001] This application relates to the field of storage technology, specifically to a storage chip and its operating method. Background Technology

[0002] The memory chip requires a corresponding high voltage to complete the test. The high voltage used in this test can only be the internal high voltage of the memory chip. There is no way to introduce an external high voltage to complete the test without increasing the number of pins on the memory chip. Summary of the Invention

[0003] This application provides a memory chip and its operating method to solve the technical problem that it is impossible to use external high voltage for testing without increasing the number of pins.

[0004] In a first aspect, this application provides a memory chip, which includes a first pin, a first input buffer, a first switch and / or a second pin, a level shifting buffer, and a second switch. The input terminal of the first input buffer is connected to the first pin, the control terminal of the first input buffer is connected to a first control terminal, and the output terminal of the first input buffer is connected to a first transmission terminal. The first input buffer operates in a first time period. The input terminal of the first switch is connected to the first pin, the control terminal of the first switch is connected to a first enable terminal, and the output terminal of the first switch is connected to a second transmission terminal. The first switch operates in a second time period. And / or, the input terminal of the level shifting buffer is connected to the second pin, the control terminal of the level shifting buffer is connected to a second control terminal, and the output terminal of the level shifting buffer is connected to a third transmission terminal. The level shifting buffer operates in the first time period. The input terminal of the second switch is connected to the second pin, the control terminal of the second switch is connected to a second enable terminal, and the output terminal of the second switch is connected to a fourth transmission terminal. The second switch operates in the second time period, and the second time period and the first time period do not overlap in timing.

[0005] In some embodiments, the memory chip further includes a third pin, a third input buffer, and a first data selector and / or a fourth pin, a fourth input buffer, and a second data selector, wherein the input of the third input buffer is connected to the third pin; the first input of the first data selector is connected to the output of the first input buffer, the second input of the first data selector is connected to the output of the third input buffer, the selection terminal of the first data selector is connected to the test control terminal, and the output of the first data selector is connected to the fifth transmission terminal; and / or, the input of the fourth input buffer is connected to the fourth pin; the first input of the second data selector is connected to the output of the level shifting buffer, the second input of the second data selector is connected to the output of the fourth input buffer, the selection terminal of the second data selector is connected to the test control terminal, and the output of the second data selector is connected to the sixth transmission terminal.

[0006] In some embodiments, the first or second data selector includes an inverter, a first transistor, a second transistor, a third transistor, and a fourth transistor. The input of the inverter is connected to a test control terminal. The first terminal of the first transistor is connected to the output of the third or fourth input buffer, the control terminal of the first transistor is connected to the output of the inverter, and the second terminal of the first transistor is connected to the fifth or sixth transmission terminal. The first transistor is a P-channel transistor. The first terminal of the second transistor is connected to the first terminal of the first transistor, the control terminal of the second transistor is connected to the input of the inverter, and the second terminal of the second transistor is connected to the second terminal of the first transistor. The second transistor is an N-channel transistor. The first terminal of the third transistor is connected to the first pin, the control terminal of the third transistor is connected to the control terminal of the second transistor, and the second terminal of the third transistor is connected to the second terminal of the second transistor. The third transistor is a P-channel transistor. The first terminal of the fourth transistor is connected to the first terminal of the third transistor, the control terminal of the fourth transistor is connected to the output of the inverter, and the second terminal of the fourth transistor is connected to the second terminal of the third transistor. The fourth transistor is an N-channel transistor.

[0007] Secondly, this application provides an operation method for a memory chip in at least one of the above embodiments, the operation method comprising: configuring a first control terminal for transmitting a first control signal; the first control signal controlling a first input buffer to be in a non-working state during a second time period; a first external high-voltage signal being transmitted sequentially to a second transmission terminal via a first pin and a first switch during the second time period; and / or configuring a second control terminal for transmitting a second control signal; the second control signal controlling a level conversion buffer to be in a non-working state during the second time period; and a second external high-voltage signal being transmitted sequentially to a fourth transmission terminal via a second pin and a second switch during the second time period.

[0008] In some embodiments, the operation method further includes: configuring a first enable terminal for transmitting a first enable signal; the first enable signal controlling a first switch to be in an off state during a first time period; a chip select signal being transmitted sequentially to a first transmission terminal via a first pin and a first input buffer during the first time period; and / or configuring a second enable terminal for transmitting a second enable signal; the second enable signal controlling a second switch to be in an off state during the first time period; and a clock signal being transmitted sequentially to a third transmission terminal via a second pin and a level conversion buffer during the first time period.

[0009] In some embodiments, the operation method further includes: configuring the third pin and the fourth pin of the memory chip to transmit a first external signal and a second external signal respectively; configuring a high-potential duration of at least one of the first external signal and the second external signal as a first time period; and configuring a low-potential duration of at least one of the first external signal and the second external signal as a second time period.

[0010] In some embodiments, the operation method further includes: configuring a test control terminal inside the memory chip for transmitting a test control signal; the test control signal controlling the first data selector to output a chip select signal to one of the fifth or sixth transmission terminals during the second time period, and / or the test control signal controlling the second data selector to output a clock signal to the other of the fifth or sixth transmission terminals during the second time period.

[0011] In some embodiments, the operation method further includes: configuring the third pin and the fourth pin of the memory chip to transmit a write protection signal and a hold signal respectively in the first time period; the third input buffer outputs the write protection signal in the first time period, and / or the fourth input buffer outputs the hold signal in the first time period.

[0012] In some embodiments, the operation method further includes: configuring the low-level duration of the test control signal as a first time period; and configuring the high-level duration of the test control signal as a second time period.

[0013] In some embodiments, the operation method further includes: during the second time period, the output potential of the first input buffer is consistent with the control potential of the first input buffer; during the second time period, the output potential of the level shifting buffer is opposite to the control potential of the level shifting buffer.

[0014] Thirdly, this application provides an operating method for a memory chip, the operating method comprising: configuring the memory chip to include a first pin and a third pin, wherein the first pin is used to receive a first signal in a working mode, and the third pin is used to receive a third signal in a working mode; providing a first external high voltage signal to the memory chip via the first pin in a test mode; and providing the first signal to the memory chip via the third pin in the test mode.

[0015] In some embodiments, the operation method further includes: configuring the memory chip to include a second pin and a fourth pin, wherein the second pin is used to receive a second signal in the operating mode and the fourth pin is used to receive a fourth signal in the operating mode; providing a second external high-voltage signal to the memory chip via the second pin in the test mode; and providing the second signal to the memory chip via the fourth pin in the test mode.

[0016] The memory chip and operating method provided in this application, through the time-division operation of the first input buffer and the first switch, can transmit a normal working signal from the first pin to the first transmission terminal in the first time period, and can also transmit a first external high voltage signal from the first pin to the second transmission terminal in the second time period. In this way, the first external high voltage signal can be used for testing without increasing the number of pins.

[0017] Furthermore, by using the level conversion buffer and the time-division operation of the second switch, it is possible to transmit a normal working signal from the second pin to the third transmission terminal in the first time period, and also to transmit a second external high-voltage signal from the second pin to the fourth transmission terminal in the second time period. This not only enables the use of a second external high-voltage signal for testing without increasing the number of pins, but also provides a variety of external high-voltage signals required for testing.

[0018] Furthermore, compared to using internal high voltage for testing, using external high voltage signals for testing allows for more flexible and convenient adjustment of the required test potential to meet the different testing needs of different signal products, thus expanding the scope of testing applicability. Attached Figure Description

[0019] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0020] Figure 1 This is a top view of a memory chip in related technologies.

[0021] Figure 2 for Figure 1 The diagram shows the structure of the memory chip.

[0022] Figure 3 for Figure 2 The diagram shows the testing process for the memory chip.

[0023] Figure 4 This is a schematic diagram of a memory chip provided in an embodiment of this application.

[0024] Figure 5 for Figure 4 The diagram shows the first type of test process for the memory chip.

[0025] Figure 6 for Figure 4 The diagram shows the second testing process for the memory chip.

[0026] Figure 7 for Figure 4 The diagram shows the third testing process for the memory chip.

[0027] Figure 8This is a schematic diagram of another structure of the memory chip provided in an embodiment of this application.

[0028] Figure 9 for Figure 8 The diagram shows the structure of the data selector in the memory chip.

[0029] Figure 10 for Figure 8 The diagram shows the first type of test process for the memory chip.

[0030] Figure 11 for Figure 8 The diagram shows the second testing process for the memory chip.

[0031] Figure 12 for Figure 8 The diagram shows the third testing process for the memory chip. Detailed Implementation

[0032] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0033] Figure 1 This is a top view of a memory chip in the related technology. The memory chip has a first pin ( / CS PAD), a pin DO (IO1), a pin / WP (IO2), a pin GND, a pin VCC, a pin / HOLD ( / RESET or IO3), a second pin (CLKPAD), and a pin DI (IO0). Due to the need to minimize the area, each pin has its own function, and no extra undefined pins are configured.

[0034] Figure 2 for Figure 1 The diagram shows a partial structural schematic of the memory chip. The first pin ( / CS PAD) of the memory chip is connected to the input terminal of the first input buffer 100 via a pad. The output terminal of the first input buffer 100 outputs a delayed signal CSb. The second pin (CLK PAD) of the memory chip is connected to the input terminal of the second input buffer 200 via a pad. The output terminal of the second input buffer 200 outputs a delayed signal CLKb.

[0035] Figure 3 for Figure 2 The diagram shows the testing process for the memory chip, which includes the following stages:

[0036] Phase 1 T1: Apply a low-level chip select signal / CS to the first pin ( / CS PAD), apply a clock signal CLK to the second pin (CLK PAD), set the test control signal TESTMODE to a low level, apply the signal SI to the pin (DIPAD) to load the test start command (ENTER CMD), and at this time, use the first internal high voltage IHV1 to start the test process.

[0037] Phase 2 T2: Apply a low-level chip select signal / CS to the first pin ( / CS PAD), apply a clock signal CLK to the second pin (CLK PAD), switch the test control signal TESTMODE from low to high, apply the signal SI to the pin (DI PAD) to load the test command (TEST CMD), and at this time, the second internal high voltage IHV2 is used to execute the test process.

[0038] Phase 3 T3: Apply a low-level chip select signal / CS to the first pin ( / CS PAD), apply a clock signal CLK to the second pin (CLK PAD), switch the test control signal TESTMODE from high to low, apply the signal SI to the pin (DI PAD) to load the test end command (EXIT CMD), and at this time, use the first internal high voltage IHV1 to end the test process.

[0039] In summary, in the relevant technologies, memory chips require corresponding high voltage to complete the testing process. The high voltage in this testing process can only be the internal high voltage of the memory chip, and the hardware that provides the internal high voltage requires additional space on the memory chip. There is no way to introduce external high voltage to complete the testing without increasing the number of pins on the memory chip.

[0040] In view of the aforementioned technical problem that it is impossible to use external high voltage for testing without increasing the number of pins, this embodiment provides a memory chip. Please refer to [link to relevant documentation]. Figures 4 to 12 ,like Figure 4 As shown, the memory chip includes a first pin ( / CS PAD), a first input buffer 100, and a first switch 300. The input terminal of the first input buffer 100 is connected to the first pin ( / CS PAD), the control terminal of the first input buffer 100 is connected to a first control terminal, and the output terminal of the first input buffer 100 is connected to a first transmission terminal. The first input buffer 100 operates in a first time period. The input terminal of the first switch 300 is connected to the first pin ( / CS PAD), the control terminal of the first switch 300 is connected to a first enable terminal, and the output terminal of the first switch 300 is connected to a second transmission terminal. The first switch 300 operates in a second time period, and the second time period does not overlap with the first time period in timing.

[0041] It is understood that the memory chip provided in this embodiment, through the time-division operation of the first input buffer 100 and the first switch 300, can transmit a normal working signal from the first pin ( / CS PAD) to the first transmission terminal in the first time period, and can also transmit the first external high voltage signal EHV1 from the first pin ( / CS PAD) to the second transmission terminal in the second time period. In this way, the first external high voltage signal EHV1 can be used for testing without increasing the number of pins.

[0042] It should be noted that the operation of the first input buffer 100 in the first time period indicates that during this period, the output signal of the first input buffer 100 follows the input signal, meaning the first input buffer 100 is in a buffered state. The operation of the first switch 300 in the second time period indicates that during this period, the first switch 300 is in a conducting state, not an off state. The time-division multiplexing of the operation of the first input buffer 100 and the first switch 300 indicates that the buffered state of the first input buffer 100 and the conducting state of the first switch 300 are located in two non-overlapping time periods.

[0043] Among them, the buffer in the above-mentioned buffer state can buffer the input signal and output it.

[0044] It should be noted that the first control terminal is used to transmit the first control signal DIS_CSb. When the first control signal DIS_CSb is at a low level, the waveform of the chip select signal / CS connected to the first pin ( / CS PAD) is the same as the waveform of the signal CSb at the first transmission terminal. The phase of the signal CSb can lag behind the phase of the chip select signal / CS, or the phase of the chip select signal / CS can be the same as the phase of the signal CSb. For example, when the first control signal DIS_CSb is at a high level, the output potential of the first input buffer 100 is clamped at a high level. In this way, when the first external high voltage signal EHV1 is applied to the first pin ( / CS PAD) in the second time period, the first external high voltage signal EHV1 applied to the first pin ( / CS PAD) can be prevented from appearing at the output terminal of the first input buffer 100.

[0045] The first enable terminal is used to transmit the first enable signal EN_EXTHV. When the first enable signal EN_EXTHV is high, the first switch 300 is turned on, and the first external high-voltage signal EHV1 applied to the first pin ( / CS PAD) is transmitted to the second transmission terminal via the first switch 300 for chip testing. When the first enable signal EN_EXTHV is low, the first switch 300 is turned off. In this state, the signal CSb follows the waveform of the chip select signal / CS applied to the first pin ( / CS PAD). The chip select signal / CS applied to the first pin ( / CS PAD) is transmitted to the first transmission terminal via the first input buffer 100 for normal chip operation.

[0046] In one embodiment, the first control terminal can be the same as the first enable terminal as the same terminal. In this case, the first control signal DIS_CSb and the first enable signal EN_EXTHV are also the same and can be used selectively. This can reduce the number of signal transmission lines required and simplify the control logic.

[0047] It should be noted that this also enables electrical interlocking between the first input buffer 100 and the first switch 300, improving operational reliability.

[0048] In one embodiment, the memory chip may further include a second pin (CLK PAD), a level shifting buffer 400, and a second switch 500. The input terminal of the level shifting buffer 400 is connected to the second pin (CLK PAD), the control terminal of the level shifting buffer 400 is connected to a second control terminal, and the output terminal of the level shifting buffer 400 is connected to a third transmission terminal. The level shifting buffer 400 operates in a first time period. The input terminal of the second switch 500 is connected to the second pin (CLK PAD), the control terminal of the second switch 500 is connected to a second enable terminal, and the output terminal of the second switch 500 is connected to a fourth transmission terminal. The second switch 500 operates in a second time period. The first and second time periods do not overlap in timing.

[0049] It is understood that the memory chip provided in this embodiment, through the time-division operation of the level conversion buffer 400 and the second switch 500, can transmit a normal working signal from the second pin (CLK PAD) to the third transmission terminal in the first time period, and can also transmit the second external high voltage signal EHV2 from the second pin (CLK PAD) to the fourth transmission terminal in the second time period. This not only enables testing using the second external high voltage signal EHV2 without increasing the number of pins, but also provides a variety of external high voltage signals required for testing.

[0050] Furthermore, compared to using internal high voltage for testing, using external high voltage signals for testing allows for more flexible and convenient adjustment of the required test potential to meet the different testing needs of different signal products, thus expanding the scope of testing applicability.

[0051] It should be noted that the second control terminal is used to transmit the second control signal DIS_CLK. When the second control signal DIS_CLK is at a low level, the waveform of the clock signal CLK connected to the second pin (CLK PAD) is the same as the waveform of the signal CLKb at the third transmission terminal. The phase of the clock signal CLK can lag behind the phase of the signal CLKb, or the phase of the clock signal CLK can be the same as the phase of the signal CLKb. When the second control signal DIS_CLK is at a high level, the output potential of the level shifting buffer 400 is clamped to a low level. For example, the potential of the signal CLKb is low at this time. In this way, when the second external high voltage signal EHV2 is applied to the second pin (CLK PAD) in the second time period, the second external high voltage signal EHV2 applied to the second pin (CLK PAD) can be prevented from appearing at the output terminal of the level shifting buffer 400.

[0052] The second enable terminal is used to transmit a second enable signal. When the second enable signal is high, the second switch 500 is turned on, and the second external high-voltage signal EHV2 applied to the second pin (CLK PAD) is transmitted to the fourth transmission terminal via the second switch 500 for chip testing. When the second enable signal is low, the second switch 500 is turned off. In this state, the signal CLKb follows the waveform of the clock signal CLK applied to the second pin (CLK PAD). The clock signal CLK applied to the second pin (CLK PAD) is transmitted to the third transmission terminal via the level shifting buffer 400 for normal chip operation.

[0053] In one embodiment, the second control terminal can also be the same as the second enable terminal as the same terminal. In this case, the second control signal DIS_CLK and the second enable signal are also the same and can be used selectively. This can further reduce the number of signal transmission lines required and further simplify the control logic.

[0054] It should be noted that this also enables electrical interlocking between the level conversion buffer 400 and the second switch 500, improving operational reliability.

[0055] In one embodiment, the first enable terminal and the second enable terminal are the same and can be used as the same enable terminal. In this case, the first enable signal EN_EXTHV and the second enable signal are also the same and can be used selectively. This can further reduce the number of signal transmission lines required and further simplify the control logic.

[0056] In one embodiment, such as Figure 8 As shown, the memory chip also includes a third pin ( / WP PAD), a third input buffer 600, and a first data selector 800. The input terminal of the third input buffer 600 is connected to the third pin ( / WP PAD). The first input terminal of the first data selector 800 is connected to the output terminal of the first input buffer 100, the second input terminal of the first data selector 800 is connected to the output terminal of the third input buffer 600, the selection terminal of the first data selector 800 is connected to the test control terminal, and the output terminal of the first data selector 800 is connected to the fifth transmission terminal.

[0057] It should be noted that the test control terminal is used to transmit the test control signal TESTMODE. When the test control signal TESTMODE is high, the output of the first data selector 800 is connected to the output of the third input buffer 600, and the chip select signal / CS is applied to the third pin ( / WP PAD, i.e., the / WP pin replaces the / CS pin). Therefore, the signal CSb received by the fifth transmission terminal is the chip select signal / CS transmitted sequentially through the third input buffer 600 and the first data selector 800. In other words, in this state, the first external high-voltage signal EHV1 is transmitted sequentially through the first pin ( / CS PAD) and the first switch 300 to the second transmission terminal. This simultaneously satisfies the memory chip's requirements for the first external high-voltage signal EHV1 and the chip select signal / CS. When the test control signal TESTMODE is low, the memory chip's test process ends.

[0058] In one implementation, such as Figure 8 As shown, the memory chip also includes a fourth pin ( / HOLD PAD), a fourth input buffer 700, and a second data selector 900. The input terminal of the fourth input buffer 700 is connected to the fourth pin ( / HOLD PAD). The first input terminal of the second data selector 900 is connected to the output terminal of the level shifting buffer 400, the second input terminal of the second data selector 900 is connected to the output terminal of the fourth input buffer 700, the selection terminal of the second data selector 900 is connected to the test control terminal, and the output terminal of the second data selector 900 is connected to the sixth transmission terminal.

[0059] It should be noted that when the test control signal TESTMODE is high, the output of the second data selector 900 is connected to the output of the fourth input buffer 700, and the clock signal CLK is applied to the fourth pin ( / HOLD PAD, i.e., the / HOLD pin replaces the / CLK pin to provide the clock signal for the chip). Therefore, the signal CLK received by the sixth transmission terminal is the clock signal CLK transmitted sequentially through the fourth input buffer 700 and the second data selector 900. In other words, in this state, the second external high-voltage signal EHV2 is transmitted sequentially through the second pin (CLK PAD) and the second switch 500 to the fourth transmission terminal, thus simultaneously satisfying the memory chip's requirements for both the second external high-voltage signal EHV2 and the clock signal CLK. When the test control signal TESTMODE is low, the testing process of the memory chip ends.

[0060] In one implementation, such as Figure 9 As shown, the first data selector 800 or the second data selector 900 includes an inverter INV1, a first transistor M1, a second transistor M2, a third transistor M3, and a fourth transistor M4. The input terminal of the inverter INV1 is connected to the test control terminal. The first terminal of the first transistor M1 is connected to the output terminal of the third input buffer 600 or the output terminal of the fourth input buffer 700. The control terminal of the first transistor M1 is connected to the output terminal of the inverter INV1. The second terminal of the first transistor M1 is connected to the fifth or sixth transmission terminal. The first transistor M1 is a P-channel transistor. The first terminal of the second transistor M2 is connected to the first terminal of the first transistor M1. The control terminal of the second transistor M2 is connected to the input terminal of the inverter INV1. The second terminal of the second transistor M2 is connected to the second terminal of the first transistor M1. The second transistor M2 is an N-channel transistor. The first terminal of the third transistor M3 is connected to the first pin ( / CS PAD). The control terminal of the third transistor M3 is connected to the control terminal of the second transistor M2. The second terminal of the third transistor M3 is connected to the second terminal of the second transistor M2. The third transistor M3 is a P-channel transistor. The first terminal of the fourth transistor M4 is connected to the first terminal of the third transistor M3. The control terminal of the fourth transistor M4 is connected to the output terminal of the inverter INV1. The second terminal of the fourth transistor M4 is connected to the second terminal of the third transistor M3. The fourth transistor M4 is an N-channel transistor.

[0061] It should be noted that the first electrode can be either the drain or the source, and the second electrode can be either the drain or the source; alternatively, the first electrode can be either the collector or the emitter, and the second electrode can be either the collector or the emitter. The control electrode can be either the gate or the base.

[0062] In one embodiment, this embodiment provides an operation method for the memory chip in at least one of the above embodiments, the operation method including the following steps:

[0063] Configure the first control terminal to receive the first control signal DIS_CSb.

[0064] The first control signal DIS_CSb controls the first input buffer 100 to be in a non-working state during the second time period.

[0065] The first external high-voltage signal EHV1 is transmitted sequentially to the second transmission terminal via the first pin ( / CS PAD) and the first switch 300 during the second time period.

[0066] It is understood that the operation method provided in this embodiment, through the time-division operation of the first input buffer 100 and the first switch 300, can transmit the normal operation signal from the first pin ( / CS PAD) to the first transmission terminal in the first time period, and can also transmit the first external high voltage signal EHV1 from the first pin ( / CS PAD) to the second transmission terminal in the second time period. In this way, the first external high voltage signal EHV1 can be used for testing without increasing the number of pins.

[0067] In one embodiment, the method of operation further includes the following steps:

[0068] Configure the second control terminal to receive the second control signal DIS_CLK.

[0069] The second control signal DIS_CLK controls the level conversion buffer 400 to be in a non-operating state during the second time period.

[0070] The second external high-voltage signal EHV2 is transmitted sequentially to the fourth transmission terminal via the second pin (CLK PAD) and the second switch 500 during the second time period.

[0071] It is understood that the operation method provided in this embodiment, through the time-division operation of the level conversion buffer 400 and the second switch 500, can transmit a normal working signal from the second pin (CLK PAD) to the third transmission terminal (i.e., the level conversion buffer 400 is in a buffered state) in the first time period, and can also transmit the second external high voltage signal EHV2 from the second pin (CLK PAD) to the fourth transmission terminal (i.e., the second switch 500 is in a conducting state) in the second time period. This not only enables testing using the second external high voltage signal EHV2 without increasing the number of pins, but also provides various external high voltage signals required for testing.

[0072] Furthermore, compared to using internal high voltage for testing, using external high voltage signals for testing allows for more flexible and convenient adjustment of the required test potential to meet the different testing needs of different signal products, thus expanding the scope of testing applicability. At the same time, it eliminates the need to install excessive charge pumps inside the memory chip to increase the voltage, saving memory chip area.

[0073] It should be noted that the non-working state refers to a state in which the output potential of the first input buffer 100 is clamped at a high potential and there is no output chip select signal / CS; or, it can also refer to a state in which the output potential of the level shifting buffer 400 is clamped at a low potential and there is no output clock signal CLK.

[0074] It should be noted that the time-division operation of the level conversion buffer 400 and the second switch 500 is used to illustrate that the buffer state of the level conversion buffer 400 and the conduction state of the second switch 500 are located in two non-overlapping time periods.

[0075] In one embodiment, the operation method further includes: configuring a first enable terminal to receive a first enable signal EN_EXTHV. The first enable signal EN_EXTHV controls the first switch 300 to be in an off state during a first time period. The chip select signal / CS is transmitted sequentially to the first transmission terminal via the first pin ( / CS PAD) and the first input buffer 100 during the first time period.

[0076] It should be noted that, under normal operating conditions of the memory chip, the chip select signal / CS applied to the first pin ( / CS PAD) is transmitted to the first transmission terminal to ensure the normal operation of the memory chip.

[0077] In one embodiment, the operation method further includes: configuring a first enable terminal to transmit a first enable signal EN_EXTHV. The first enable signal EN_EXTHV controls the second switch 500 to be in an off state during a first time period. The clock signal CLK is transmitted sequentially to a third transmission terminal via a second pin (CLK PAD) and a level shifting buffer 400 during the first time period.

[0078] It should be noted that, under normal operating conditions of the memory chip, the clock signal CLK applied to the second pin (CLK PAD) is transmitted to the third transmission terminal to ensure the normal operation of the memory chip.

[0079] In one embodiment, such as Figures 4 to 7As shown, the operation method further includes: configuring the third pin ( / WP PAD) and the fourth pin ( / HOLD PAD) of the memory chip to transmit a first external signal and a second external signal, respectively. The high-potential duration of at least one of the first external signal and the second external signal is configured as a first time period. The low-potential duration of at least one of the first external signal and the second external signal is configured as a second time period.

[0080] In one embodiment, the first external signal and the second external signal can be two different external signals, or the first external signal and the second external signal can both use the same external signal. This external signal can be a square wave signal with a low level.

[0081] In one embodiment, the first external signal can be an adjusted write-protect signal / WP, meaning that the write-protect signal / WP is constructed to have a low potential duration during the second time period. The second external signal can be an adjusted hold signal / HOLD, meaning that the hold signal / HOLD is also constructed to have a low potential duration during the second time period.

[0082] It should be noted that the first and second time periods can be defined by the duration of the low potential of at least one of the write protection signal / WP and the hold signal / HOLD. This allows for the reuse of the write protection signal / WP and the hold signal / HOLD, and also allows for precise limitation of the usage time of the external high voltage signal during the test.

[0083] Figure 5 for Figure 4 The diagram shows the first type of testing process for the memory chip, which includes the following stages:

[0084] Phase 1 T1: Apply a low-level chip select signal / CS to the first pin ( / CS PAD), apply a clock signal CLK to the second pin (CLK PAD) for transmission, set the test control signal TESTMODE to a low level, apply the signal SI to the pin (DIPAD) to load the test start command (ENTER CMD), and use the internal high voltage IHV0 to start the test process.

[0085] Phase 2 T2: First, apply a low-level chip select signal / CS to the first pin ( / CS PAD), apply a clock signal CLK to the second pin (CLK PAD), switch the test control signal TESTMODE from low to high, apply the signal SI to the pin (DI PAD) to load the test command (TEST CMD), and at this time, the second internal high voltage IHV2 is used to execute the test process.

[0086] Next, the write protection signal / WP switches from a high level to a low level, and a first external high-voltage signal EHV1 is applied to the first pin ( / CS PAD). The first external high-voltage signal EHV1 is transmitted sequentially through the first pin ( / CS PAD) and the first switch 300 to the second transmission terminal. At this time, the test can use the first external high-voltage signal EHV1 from the second transmission terminal. The first external high-voltage signal EHV1 applied to the first pin ( / CS PAD) is removed when the write protection signal / WP switches from a low level to a high level.

[0087] Phase 3 T3: Apply a low-level chip select signal / CS to the first pin ( / CS PAD), apply a clock signal CLK to the second pin (CLK PAD), apply a signal SI to the pin (DI PAD) to load the test end instruction (EXITCMD), and switch the test control signal TESTMODE from a high level to a low level. At this time, the second internal high voltage IHV2 and internal high voltage IHV0 are used to end the test process.

[0088] Understandably, this method allows for the introduction of a first external high voltage to complete the test without increasing the number of pins on the memory chip. The low-level duration of the write-protect signal / WP can be used to limit the usage time of the first external high voltage signal EHV1 during the test. Furthermore, since EHV1 is an external voltage signal, its potential can be adjusted more flexibly to meet different test requirements.

[0089] Figure 6 for Figure 4 The diagram shows a second testing process for the memory chip, which includes the following stages:

[0090] Phase 1 T1: Apply a low-level chip select signal / CS to the first pin ( / CS PAD), apply a clock signal CLK to the second pin (CLK PAD), set the test control signal TESTMODE to a low level, apply the signal SI to the pin (DIPAD) to load the test start command (ENTER CMD), and use the internal high voltage IHV0 to start the test process.

[0091] Phase 2 T2: First, apply a low-level chip select signal / CS to the first pin ( / CS PAD), apply a clock signal CLK to the second pin (CLK PAD), switch the test control signal TESTMODE from low to high, apply the signal SI to the pin (DI PAD) to load the test command (TEST CMD), and at this time, the second internal high voltage IHV2 is used to execute the test process.

[0092] Next, while holding the signal / HOLD from high to low, apply a second external high-voltage signal EHV2 to the second pin (CLK PAD). The second external high-voltage signal EHV2 is transmitted sequentially through the second pin (CLK PAD) and the second switch 500 to the fourth transmission terminal. At this point, the test can use the second external high-voltage signal EHV2 from the fourth transmission terminal. Continue this process until the holding signal / HOLD switches from low to high, then remove the second external high-voltage signal EHV2 applied to the second pin (CLK PAD).

[0093] Phase 3 T3: Apply a low-level chip select signal / CS to the first pin ( / CS PAD), apply a clock signal CLK to the second pin (CLK PAD), apply a signal SI to the pin (DI PAD) to load the test end command (EXIT CMD), and switch the test control signal TESTMODE from high to low. At this time, the second internal high voltage IHV2 and internal high voltage IHV0 are used to end the test process.

[0094] Understandably, this method allows for the introduction of a second external high voltage to complete the test without increasing the number of pins on the memory chip. The duration of the low level of the hold signal / HOLD can be used to limit the usage time of the second external high voltage signal EHV2 during the test. Furthermore, since EHV2 is an external voltage signal, its potential can be adjusted more flexibly to meet different test requirements.

[0095] Figure 7 for Figure 4 The diagram shows the third testing process for the memory chip, which includes the following stages:

[0096] Phase 1 T1: Apply a low-level chip select signal / CS to the first pin ( / CS PAD), apply a clock signal CLK to the second pin (CLK PAD), set the test control signal TESTMODE to a low level, apply the signal SI to the pin (DIPAD) to load the test start command (ENTER CMD), and use the internal high voltage IHV0 to start the test process.

[0097] Phase 2 T2: First, apply a low-level chip select signal / CS to the first pin ( / CS PAD), apply a clock signal CLK to the second pin (CLK PAD), switch the test control signal TESTMODE from low to high, apply the signal SI to the pin (DI PAD) to load the test command (TEST CMD), and at this time, the second internal high voltage IHV2 is used to execute the test process.

[0098] Next, both the write protection signal / WP and the hold signal / HOLD switch from high to low potential. A first external high-voltage signal EHV1 is applied to the first pin ( / CS PAD). The first external high-voltage signal EHV1 is transmitted sequentially through the first pin ( / CS PAD) and the first switch 300 to the second transmission terminal. A second external high-voltage signal EHV2 is applied to the second pin (CLK PAD). The second external high-voltage signal EHV2 is transmitted sequentially through the second pin (CLK PAD) and the second switch 500 to the fourth transmission terminal. At this point, the test can simultaneously use the first external high-voltage signal EHV1 from the second transmission terminal and the second external high-voltage signal EHV2 from the fourth transmission terminal. This continues until both the write protection signal / WP and the hold signal / HOLD switch from low to high potential, at which point the first external high-voltage signal EHV1 applied to the first pin ( / CS PAD) and the second external high-voltage signal EHV2 applied to the second pin (CLK PAD) are removed.

[0099] Phase 3 T3: Apply a low-level chip select signal / CS to the first pin ( / CS PAD), apply a clock signal CLK to the second pin (CLK PAD), apply a signal SI to the pin (DI PAD) to load the test end instruction (EXITCMD), and switch the test control signal TESTMODE from high to low. At this time, the second internal high voltage IHV2 and internal high voltage IHV0 are used to end the test process.

[0100] Understandably, this method allows for the introduction of a first external high-voltage signal EHV1 and a second external high-voltage signal EHV2 to complete the test without increasing the number of pins on the memory chip. The low-level durations of the write-protect signal / WP and the hold signal / HOLD can be used to define the usage time of the first external high-voltage signal EHV1 and the second external high-voltage signal EHV2 during the test, respectively. Furthermore, since both the first external high-voltage signal EHV1 and the second external high-voltage signal EHV2 are external voltage signals, their potentials can be adjusted more flexibly to meet different testing requirements.

[0101] In one embodiment, such as Figures 8 to 12 As shown, the operation method further includes: configuring the internal test control terminal of the memory chip to transmit the test control signal TESTMODE. During the second time period, the test control signal TESTMODE controls the first data selector 800 to output the chip select signal / CS to the fifth transmission terminal, and / or, during the second time period, the test control signal TESTMODE controls the second data selector 900 to output the clock signal CLK to the sixth transmission terminal.

[0102] It should be noted that in this embodiment, when the second transmission terminal and / or the fourth transmission terminal provide the first external high-voltage signal EHV1 and / or the second external high-voltage signal EHV2, the chip select signal / CS is applied to the third pin ( / WP PAD) and transmitted to the fifth transmission terminal to provide the chip select signal / CS for the memory chip; alternatively, the clock signal CLK can be applied to the fourth pin ( / HOLDPAD) and transmitted to the sixth transmission terminal to provide the clock signal CLK for the memory chip. In other words, even if at least one of the original first pin ( / CS PAD) or second pin (CLK PAD) is used to access the external high-voltage signal, the memory chip will not lose the chip select signal / CS and / or the clock signal CLK.

[0103] In one embodiment, the operation method further includes: configuring the third pin ( / WP PAD) and the fourth pin ( / HOLD PAD) of the memory chip to receive the write protection signal / WP and the hold signal / HOLD respectively during a first time period. During the first time period, the third input buffer 600 outputs the write protection signal WPb1, and / or, the fourth input buffer 700 outputs the hold signal HOLDb1 during the first time period.

[0104] It should be noted that during the first period when no external high-voltage signal is required for testing, the third pin ( / WP PAD) and the fourth pin ( / HOLD PAD) can provide the corresponding write protection signal / WP and hold signal / HOLD to the memory chip under normal operating conditions. This allows the third pin ( / WP PAD) and the fourth pin ( / HOLD PAD) to be multiplexed in different periods, thereby enabling the introduction of an external high-voltage signal for testing the memory chip without increasing the number of pins on the memory chip.

[0105] In one embodiment, such as Figures 10 to 12 As shown, the operation method further includes: configuring the low-level duration of the test control signal TESTMODE as the first time period; and configuring the high-level duration of the test control signal TESTMODE as the second time period.

[0106] It should be noted that the low-level duration of the test control signal TESTMODE in this embodiment can also be used to clearly limit the usage time of the external high-voltage signal during the test, enriching the limitation scheme for the usage time of the external high-voltage signal during the test, so as to be able to adapt to more test environments.

[0107] Figure 10 for Figure 8 The diagram shows the first type of testing process for the memory chip, which includes the following stages:

[0108] Phase 1 T1: Apply a low-level chip select signal / CS to the first pin ( / CS PAD), apply a clock signal CLK to the second pin (CLK PAD), set the test control signal TESTMODE to a low level, apply the signal SI to the pin (DIPAD) to load the test start command (ENTER CMD), and use the internal high voltage IHV0 to start the test process.

[0109] Phase 2 T2: Apply clock signal CLK to the second pin (CLK PAD), switch test control signal TESTMODE from low to high potential, apply signal SI to the pin (DI PAD) to load test command (TEST CMD), apply first external high voltage signal EHV1 to the first pin ( / CS PAD), and transmit the first external high voltage signal EHV1 sequentially through the first pin ( / CSPAD) and the first switch 300 to the second transmission terminal. At this time, the first external high voltage signal EHV1 is used to execute the test process.

[0110] At the same time, the chip select signal / CS is applied to the third pin ( / WP PAD). The chip select signal / CS is transmitted sequentially through the third pin ( / WPPAD), the third input buffer 600, and the first data selector 800 to the fifth transmission terminal, providing the memory chip with the chip select signal / CS that may be needed.

[0111] In the third stage T3: the clock signal CLK is applied to the second pin (CLK PAD), and the signal SI is applied to the pin (DIPAD) to load the test end command (EXIT CMD). The test control signal TESTMODE switches from high potential to low potential. At this time, the first external high voltage signal EHV1 and the internal high voltage IHV0 are used to end the test process.

[0112] Understandably, this method can introduce a first external high voltage to complete the test without increasing the number of pins on the memory chip, while at the same time providing the memory chip with the necessary chip select signal / CS through the path from the third pin ( / WP PAD) to the fifth transmission terminal.

[0113] Figure 11 for Figure 8 The diagram shows a second testing process for the memory chip, which includes the following stages:

[0114] Phase 1 T1: Apply a low-level chip select signal / CS to the first pin ( / CS PAD), apply a clock signal CLK to the second pin (CLK PAD), set the test control signal TESTMODE to a low level, apply the signal SI to the pin (DIPAD) to load the test start command (ENTER CMD), and use the internal high voltage IHV0 to start the test process.

[0115] Phase 2 T2: Apply clock signal CLK to the second pin (CLK PAD), switch test control signal TESTMODE from low to high potential, apply signal SI to the pin (DI PAD) to load test command (TEST CMD), apply first external high voltage signal EHV1 to the first pin ( / CS PAD), and transmit the first external high voltage signal EHV1 sequentially through the first pin ( / CSPAD) and the first switch 300 to the second transmission terminal. At this time, the first external high voltage signal EHV1 is used to execute the test process.

[0116] At the same time, the chip select signal / CS is applied to the fourth pin ( / HOLD PAD). The chip select signal / CS is transmitted sequentially through the fourth pin ( / HOLD PAD), the fourth input buffer 700, and the second data selector 900 to the sixth transmission terminal, providing the memory chip with the chip select signal / CS that may be needed.

[0117] In the third stage T3: the clock signal CLK is applied to the second pin (CLK PAD), and the signal SI is applied to the pin (DIPAD) to load the test end command (EXIT CMD). The test control signal TESTMODE switches from high potential to low potential. At this time, the first external high voltage signal EHV1 and the internal high voltage IHV0 are used to end the test process.

[0118] Understandably, this method can introduce a first external high voltage to complete the test without increasing the number of pins on the memory chip, while at the same time providing the memory chip with the chip select signal / CS that may be needed through the path from the fourth pin ( / HOLD PAD) to the sixth transmission terminal.

[0119] Figure 12 for Figure 8 The diagram shows the third testing process for the memory chip, which includes the following stages:

[0120] Phase 1 T1: Apply a low-level chip select signal / CS to the first pin ( / CS PAD), apply a clock signal CLK to the second pin (CLK PAD), set the test control signal TESTMODE to a low level, apply the signal SI to the pin (DIPAD) to load the test start command (ENTER CMD), and use the internal high voltage IHV0 to start the test process.

[0121] Phase 2 T2: The test control signal TESTMODE switches from low to high potential, and the signal SI is applied to the pin (DI PAD) to load the test command (TEST CMD). The first external high voltage signal EHV1 is applied to the first pin ( / CS PAD). The first external high voltage signal EHV1 is transmitted to the second transmission terminal sequentially through the first pin ( / CS PAD) and the first switch 300. At the same time, the second external high voltage signal EHV2 is applied to the second pin (CLK PAD). The second external high voltage signal EHV2 is transmitted to the fourth transmission terminal sequentially through the second pin (CLK PAD) and the second switch 500. At this time, the first external high voltage signal EHV1 and the second external high voltage signal EHV2 are used simultaneously to execute the test process.

[0122] Simultaneously, a chip select signal / CS is applied to the third pin ( / WP PAD). The chip select signal / CS is transmitted sequentially through the third pin ( / WPPAD), the third input buffer 600, and the first data selector 800 to the fifth transmission terminal, providing the memory chip with the chip select signal / CS that may be needed. A clock signal CLK is applied to the fourth pin ( / HOLD PAD). The clock signal CLK is transmitted sequentially through the fourth pin ( / HOLD PAD), the fourth input buffer 700, and the second data selector 900 to the sixth transmission terminal, providing the memory chip with the clock signal CLK that may be needed.

[0123] Phase 3 T3: Apply signal SI to pin (DI PAD) to load test end command (EXIT CMD). Test control signal TESTMODE switches from high potential to low potential. At this time, the first external high voltage signal EHV1, the second external high voltage signal EHV2, and the internal high voltage IHV0 are used to end the test process.

[0124] Understandably, this operation method can introduce the first external high-voltage signal EHV1 and the second external high-voltage signal EHV2 to complete the test without increasing the number of pins on the memory chip. At the same time, it can provide the memory chip with the chip select signal / CS and the clock signal CLK that may be needed through the path from the third pin ( / WP PAD) to the fifth transmission terminal and the path from the fourth pin ( / HOLD PAD) to the sixth transmission terminal.

[0125] In other embodiments, such as Figure 8-12 As shown, when one pin of the memory chip is used as the input terminal of an external high voltage, the other pin of the memory chip replaces the function of that pin, and is not limited to using the / WP pin to replace the / CS pin and / or the / HOLD pin to replace the CLK pin.

[0126] In one embodiment, this embodiment provides a method for operating a memory chip, the method comprising: configuring the memory chip to include a first pin and a third pin, wherein the first pin is used to receive a first signal in a working mode, and the third pin is used to receive a third signal in a working mode; providing a first external high voltage signal to the memory chip via the first pin in a test mode; and providing the first signal to the memory chip via the third pin in the test mode.

[0127] It should be noted that, in this embodiment, the first pin can be... Figure 8 The / CS pin ( / CSPAD) or CLK pin (CLK PAD) shown in the diagram can have the third pin in this state. Figure 8 The / WP pin ( / WP PAD) or / HOLD pin ( / HOLD PAD) shown. For example, when the first pin is the / CS pin, the first signal can be the chip select signal / CS, and the third pin can be either the / WP pin or the / HOLD pin; when the first pin is the CLK pin, the first signal is the clock signal CLK, and the third pin can also be either the / WP pin or the / HOLD pin.

[0128] It is understood that this embodiment can introduce a first external high-voltage signal EHV1 to complete the test without increasing the number of pins on the memory chip, while also providing the memory chip with the chip select signal / CS or clock signal CLK that may be required.

[0129] In one embodiment, the operation method further includes: configuring the memory chip to include a second pin and a fourth pin, wherein the second pin is used to receive a second signal in the operating mode and the fourth pin is used to receive a fourth signal in the operating mode; providing a second external high-voltage signal to the memory chip via the second pin in the test mode; and providing the second signal to the memory chip via the fourth pin in the test mode.

[0130] It should be noted that, in this embodiment, the first pin is... Figure 8 The / CS pin shown ( / CS PAD) has the following characteristics: the first signal is the chip select signal / CS, and the third pin is... Figure 8 When the / WP pin ( / WP PAD) is shown, the third signal is the write-protect signal / WP, and the second pin is... Figure 8 The CLK pin shown (CLK PAD) has the following characteristics: the second signal is the clock signal CLK, and the fourth pin is... Figure 8 The / HOLD pin shown ( / HOLD PAD) has a fourth signal, which is the hold signal / HOLD.

[0131] Alternatively, the first pin is Figure 8The / CS pin shown ( / CS PAD) has the following characteristics: the first signal is the chip select signal / CS, and the third pin is... Figure 8 When the / HOLD pin ( / HOLD PAD) is shown, the third signal is the hold signal / HOLD, and the second pin is... Figure 8 The CLK pin shown (CLK PAD) has the following characteristics: the second signal is the clock signal CLK, and the fourth pin is... Figure 8 The fourth signal on the / WP pin ( / WP PAD) shown is the write-protect signal / WP.

[0132] Alternatively, the first pin is Figure 8 The CLK pin shown (CLK PAD) has the following characteristics: the first signal is the clock signal CLK, and the third pin is... Figure 8 When the / WP pin ( / WP PAD) is shown, the third signal is the write-protect signal / WP, and the second pin is... Figure 8 The / CS pin shown ( / CS PAD) has a second signal, which is the chip select signal / CS, and a fourth pin... Figure 8 The / HOLD pin shown ( / HOLD PAD) has a fourth signal, which is the hold signal / HOLD.

[0133] Alternatively, the first pin is Figure 8 The CLK pin shown (CLK PAD) has the following characteristics: the first signal is the clock signal CLK, and the third pin is... Figure 8 When the / HOLD pin ( / HOLD PAD) is shown, the third signal is the hold signal / HOLD, and the second pin is... Figure 8 The / CS pin shown in the diagram ( / CS PAD) has a second signal that is the chip select signal / CS, and a fourth pin that is... Figure 8 The fourth signal on the / WP pin ( / WP PAD) shown is the write-protect signal / WP.

[0134] It is understood that this embodiment can introduce a first external high-voltage signal EHV1 and a second external high-voltage signal EHV2 to complete the test without increasing the number of pins of the memory chip, while also providing the memory chip with the chip select signal / CS and clock signal CLK that may be needed.

[0135] It should be noted that the aforementioned memory chip can be NOR Flash, and specifically, NOR Flash can be serial communication flash memory.

[0136] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0137] The foregoing has provided a detailed description of the memory chip and operating method provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A memory chip, characterized in that, include: First pin; A first input buffer, wherein the input terminal of the first input buffer is connected to the first pin, the control terminal of the first input buffer is connected to the first control terminal, the output terminal of the first input buffer is connected to the first transmission terminal, and the first input buffer operates in a first time period; as well as A first switch, wherein the input terminal of the first switch is connected to the first pin, the control terminal of the first switch is connected to the first enable terminal, and the output terminal of the first switch is connected to the second transmission terminal, and the first switch operates in a second time period; and / or, The second pin; A level shifting buffer, wherein the input terminal of the level shifting buffer is connected to the second pin, the control terminal of the level shifting buffer is connected to the second control terminal, and the output terminal of the level shifting buffer is connected to the third transmission terminal, and the level shifting buffer operates during the first time period; as well as A second switch is provided, wherein the input terminal of the second switch is connected to the second pin, the control terminal of the second switch is connected to the second enable terminal, and the output terminal of the second switch is connected to the fourth transmission terminal. The second switch operates during the second time period, and the second time period does not overlap with the first time period in terms of timing.

2. The memory chip according to claim 1, characterized in that, The memory chip also includes: Third pin; The third input buffer, wherein the input terminal of the third input buffer is connected to the third pin; A first data selector, wherein a first input terminal of the first data selector is connected to the output terminal of the first input buffer, a second input terminal of the first data selector is connected to the output terminal of the third input buffer, a selection terminal of the first data selector is connected to a test control terminal, and an output terminal of the first data selector is connected to a fifth transmission terminal; and / or Fourth pin; A fourth input buffer, wherein the input terminal of the fourth input buffer is connected to the fourth pin; The second data selector has its first input connected to the output of the level shifting buffer, its second input connected to the output of the fourth input buffer, its selection terminal connected to the test control terminal, and its output connected to the sixth transmission terminal.

3. The memory chip according to claim 2, characterized in that, The first data selector or the second data selector includes: An inverter, the input terminal of which is connected to the test control terminal; The first transistor has its first terminal connected to the output terminal of the third input buffer or the output terminal of the fourth input buffer, its control terminal connected to the output terminal of the inverter, and its second terminal connected to the fifth transmission terminal or the sixth transmission terminal. The first transistor is a P-channel transistor. The second transistor has its first terminal connected to the first terminal of the first transistor, its control terminal connected to the input terminal of the inverter, and its second terminal connected to the second terminal of the first transistor. The second transistor is an N-channel transistor. A third transistor, wherein its first terminal is connected to the first pin, its control terminal is connected to the control terminal of the second transistor, and its second terminal is connected to the second terminal of the second transistor; the third transistor is a P-channel transistor; and The fourth transistor has its first terminal connected to the first terminal of the third transistor, its control terminal connected to the output terminal of the inverter, and its second terminal connected to the second terminal of the third transistor. The fourth transistor is an N-channel transistor.

4. A method for operating a memory chip as described in any one of claims 1-3, characterized in that, The operation method includes: Configure the first control terminal to receive the first control signal; The first control signal controls the first input buffer to be in a non-working state during the second time period; The first external high-voltage signal is transmitted sequentially through the first pin and the first switch to the second transmission terminal during the second time period; And / or, Configure a second control terminal to receive a second control signal; The second control signal controls the level shifting buffer to be in a non-operating state during the second time period; The second external high-voltage signal is transmitted sequentially to the fourth transmission terminal via the second pin and the second switch during the second time period.

5. The operating method according to claim 4, characterized in that, The operation method further includes: Configure the first enable terminal to receive the first enable signal; The first enable signal controls the first switch to be in the off state during the first time period; The chip select signal is transmitted sequentially through the first pin and the first input buffer to the first transmission terminal during the first time period; And / or, Configure a second enable terminal to receive a second enable signal; The second enable signal controls the second switch to be in the off state during the first time period; The clock signal is transmitted sequentially through the second pin and the level conversion buffer to the third transmission terminal during the first time period.

6. The operating method according to claim 4, characterized in that, The operation method further includes: The third and fourth pins of the memory chip are configured to receive a first external signal and a second external signal, respectively. The high-potential duration of at least one of the first external signal and the second external signal is configured as the first time period; Configure the low potential duration of at least one of the first external signal and the second external signal as the second time period.

7. The operating method according to claim 4, characterized in that, The operation method further includes: The internal test control terminal of the memory chip is configured to receive test control signals; The test control signal controls the first data selector to output a chip select signal to the fifth transmission terminal during the second time period, and / or the test control signal controls the second data selector to output a clock signal to the sixth transmission terminal during the second time period.

8. The operating method according to claim 7, characterized in that, The operation method further includes: The third and fourth pins of the memory chip are configured to receive write protection signals and hold signals respectively during the first time period; During the first time period, the third input buffer outputs a write protection signal, and / or, during the first time period, the fourth input buffer outputs a hold signal.

9. The operating method according to claim 7, characterized in that, The operation method further includes: Configure the low-level duration of the test control signal to be the first time period; Configure the high-level duration of the test control signal as the second time period.

10. The operating method according to claim 4, characterized in that, The operation method further includes: During the second time period, the output potential of the first input buffer is the same as the control potential of the first input buffer. During the second time period, the output potential of the level shifting buffer is opposite to the control potential of the level shifting buffer.

11. A method for operating a memory chip, characterized in that, include: The memory chip is configured to include a first pin, a second pin, and a third pin. The first pin is used to receive a first signal in the operating mode, the third pin is used to receive a third signal in the operating mode, and the second pin is used to receive a second signal in the operating mode. In test mode, a first external high-voltage signal is provided to the memory chip via the first pin; In the test mode, the first signal is provided to the memory chip via the third pin; In the first time period, a normal operation signal is transmitted from the first pin to the first transmission terminal. In the second time period, a first external high voltage signal is transmitted from the first pin to the second transmission terminal. In the first time period, a normal operation signal is transmitted from the second pin to the third transmission terminal. In the second time period, a second external high voltage signal is transmitted from the second pin to the fourth transmission terminal.

12. The operating method according to claim 11, characterized in that, The operation method further includes: The memory chip is configured to include a fourth pin, which is used in the operating mode to receive a fourth signal; In the test mode, the second external high-voltage signal is provided to the memory chip via the second pin; In the test mode, the second signal is provided to the memory chip via the fourth pin.

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