Method of manufacturing a semiconductor structure

Abstract

Embodiments of the present disclosure relate to methods of forming trench and conductive pillar features using dielectric and metal mask layers. In particular, embodiments of the present disclosure provide a hard mask stack including a first dielectric mask layer, a second dielectric mask layer, and a metal mask layer, where the first and second dielectric mask layers have a high etch selectivity.

Description

Technical Field

[0001] This disclosure relates to a method for manufacturing semiconductor structures. Background Technology

[0002] The semiconductor industry has experienced sustained rapid growth due to the ever-increasing integration density of various electronic components. In most cases, this increase in integration density comes from the iterative reduction of the minimum feature size, thereby allowing more components to be integrated into a given wafer area.

[0003] During integrated circuit manufacturing, a pattern is first formed in a photoresist layer using a lithography process. This pattern is then transferred to a hard mask layer via one or more etching processes, and subsequently formed in a target layer beneath the hard mask layer. However, as integrated circuits continue to shrink in size, the features transferred to the hard mask layer can break down during subsequent etching processes, leading to defects or low-quality features in the target layer.

[0004] Therefore, there is a need to improve hard mask layers and their associated patterning methods. Summary of the Invention

[0005] Some embodiments disclosed herein provide a method for fabricating a semiconductor structure. The method includes depositing a first hard mask layer over a dielectric layer, depositing a second hard mask layer over the first hard mask layer, wherein the second hard mask layer includes a metallic material, depositing a third hard mask layer over the second hard mask layer, wherein the third hard mask layer and the first hard mask layer have etch selectivity relative to each other, forming a first pattern through the third hard mask layer and the second hard mask layer, forming a second pattern through the first hard mask layer and the dielectric layer, using the third hard mask layer as an etch stop, and transferring the first pattern from the third hard mask layer and the second hard mask layer through the first hard mask layer to the dielectric layer.

[0006] Some embodiments disclosed herein provide a method for fabricating a semiconductor structure. The method includes depositing a hard mask stack, wherein the hard mask stack includes a first hard mask layer, a second hard mask layer disposed on the first hard mask layer, and a third hard mask layer disposed on the second hard mask layer, wherein the third hard mask layer comprises a nitride, and forming a plurality of mandrels on the hard mask stack, forming spacer mandrels on the sidewalls of the plurality of mandrels, wherein the spacer mandrels comprise oxide, removing the plurality of mandrels, and using the spacer mandrels as etch masks to etch the third hard mask layer.

[0007] Some embodiments disclosed herein provide a method for fabricating a semiconductor structure. The method includes depositing a first hard mask layer on a target layer, depositing a second hard mask layer on the first hard mask layer, wherein the second hard mask layer comprises a metal-containing material, depositing a third hard mask layer on the second hard mask layer, wherein the third hard mask layer is an oxygen-free layer, forming a first pattern thereon through the third hard mask layer and the second hard mask layer, and forming a second pattern through the first hard mask layer, wherein the second pattern overlaps with the first pattern, and the third hard mask layer serves as an etch stop during patterning of the first hard mask layer. Attached Figure Description

[0008] The state of this disclosure is in relation to the accompanying documents. Figure 1 The best way to understand this text is by referring to the detailed description below. Note that, according to industry standards, the features are not drawn to scale. In practice, the dimensions of the features can be arbitrarily increased or decreased for clarity of explanation.

[0009] Figure 1 This is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0010] Figures 2 to 7 , Figures 8A to 8B , Figures 9A to 9B , Figures 10A to 10B , Figures 11A to 11B , Figures 12A to 12B ,and Figures 13 to 15 The semiconductor device at various manufacturing stages according to this disclosure is illustrated schematically.

[0011] [Symbol Explanation]

[0012] 100: Method

[0013] 102~128: Operation

[0014] 200: Semiconductor devices

[0015] 202:Substrate

[0016] 204: Etching stop layer

[0017] 206: Dielectric layer

[0018] 206L: Wiring opening

[0019] 206V: Opening of conductive post

[0020] 208: First hard mask layer

[0021] 208L: Wiring opening

[0022] 208V: Opening of conductive post

[0023] 210: Second hard mask layer

[0024] 210L: Open

[0025] 210m: Shielding strip

[0026] 212: Third hard mask layer

[0027] 212L: Open

[0028] 212m: Masking strip

[0029] 214: Core layer

[0030] 214m: mandrel

[0031] 214o: Opening

[0032] 215: Triple-layer photoresist

[0033] 216: Spacer layer

[0034] 216L: Open

[0035] 216m: Spacing mandrel

[0036] 217: Triple-layer photoresist

[0037] 218: Bottom Layer

[0038] 218V: Opening of conductive post

[0039] 220: Intermediate Layer

[0040] 220V: Opening of conductive post

[0041] 222: Upper layer

[0042] 222V: Opening of conductive post

[0043] 226: Electrical conductivity characteristics

[0044] 226L: Conductive wire

[0045] 226V: Conductive conductive column

[0046] 230: Dielectric layer

[0047] 232L: Conductive wire

[0048] 232V: Conductive post

[0049] 240: Bottom layer

[0050] 242: Intermediate Layer

[0051] 244: Upper layer

[0052] 244m: mandrel

[0053] 244o: Opening

[0054] P1~2: Pitch

[0055] W1~9: Width Detailed Implementation

[0056] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature above or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not, in itself, indicate any relationship between the various embodiments and / or configurations discussed.

[0057] Furthermore, for the convenience of describing the relationship between one element or feature as illustrated in the figures and another element(s) or feature(s), spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” and the like are used herein. Spatial relative terms are intended to cover different orientations of the device during use or operation, other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted similarly accordingly.

[0058] The embodiments disclosed herein relate to methods for forming trench and conductive via features using dielectric layers and metal masking layers. Specifically, the embodiments disclosed herein provide a hard mask stack including two dielectric masking layers and a metal-containing masking layer between the two dielectric masking layers, wherein the two dielectric masking layers are selected from different materials that have high etch selectivity relative to each other.

[0059] Figure 1 This is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. In particular, method 100 relates to a process for patterning a dielectric layer and forming trenches and conductive pillars in the dielectric layer to provide conductive features. Figures 2 to 7 , Figures 8A to 8B , Figures 9A to 9B , Figures 10A to 10B , Figures 11A to 11B , Figures 12A to 12B ,and Figures 13 to 15 The semiconductor device 200 at various manufacturing stages according to method 100 is illustrated schematically. Figures 2 to 7 , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A ,and Figures 13 to 15 This is a schematic cross-sectional view of the semiconductor device 200. Figure 8B , Figure 9B , Figure 10B , Figure 11B ,and Figure 12B This is a schematic top view of the semiconductor device 200.

[0060] Method 100 involves patterning trenches and conductive pillar openings in a dielectric material layer, and forming trench and conductive pillar conductive structures in the dielectric material layer. Method 100 can be used to perform damascene processes, such as dual damascene processes. In some embodiments, the trench and conductive pillar conductive structures may be part of a metallization structure or interconnect structure of a semiconductor device. The trench and conductive pillar conductive structures may be formed of metal. For example, conductive lines formed using the techniques described herein can be used to form conductive interconnects as part of a back end of line (BEOL) process.

[0061] In some embodiments, the semiconductor device 200 is treated as part of a larger wafer. For example... Figure 2 As shown, the semiconductor device 200 includes a substrate 202. In some embodiments, the substrate 202 includes various features formed thereon and therein. For example, the substrate 202 may include active devices, interconnect structures, and the like.

[0062] Substrate 202 may include a semiconductor material such as silicon, doped or undoped, or an active layer of a semiconductor-on-insulator (SOI) substrate. Substrate 202 may include other semiconductor materials such as germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used. Devices (not shown), such as transistors (e.g., planar transistors, field-effect transistors (FETs), FinFETs, horizontal gate all-around (HGAA) FETs, vertical gate all-around (VGAA) FETs), and other suitable devices, other types of transistors, diodes, capacitors, resistors, etc., may be formed in the semiconductor material and / or on its active surface in substrate 202. Interconnect structures such as interlayer dielectric layers, etch stop layers, and IMD layers may also be included in the substrate 202.

[0063] The semiconductor device 200 may include an etch-stop layer 204 and a dielectric layer 206 formed over a substrate 202. According to the method 100 described herein, conductive features such as conductive lines and conductive pillars are to be formed in the dielectric layer 206.

[0064] In some embodiments, the etch stop layer 204 may be a dielectric material with etch selectivity relative to the dielectric layer 206 and acts as an etch stop layer when the dielectric layer 206 is etched. The material and process used to form the etch stop layer 204 may depend on the material of the dielectric layer 206. In some embodiments, the etch stop layer 204 may be formed of SiN, SiON, SiCON, SiC, SiOC, SiCN, SiO, other dielectrics, the like, or combinations thereof. The etch stop layer 204 may be formed by plasma enhanced chemical vapor deposition (PECVD), low-pressure CVD (LPCVD), plasma vapor deposition (PVD), atomic layer deposition (ALD), or the like. Other materials and processes may be used.

[0065] In some embodiments, dielectric layer 206 is an IMD (inter-metal dielectric) layer. In some embodiments, dielectric layer 206 may be formed above an inter-layer dielectric (ILD) layer formed on the source / drain region or gate of a transistor (e.g., FinFET), and may be a dielectric layer in an interconnect structure or a dielectric layer used in other types of metallization structures.

[0066] In some embodiments, dielectric layer 206 comprises one or more layers of dielectric material, for example, one or more layers of low-k dielectric material. Dielectric layer 206 may be silicon oxide, undoped silicate glass, doped silicon oxide, such as borosilicate glass (BPSG), fluorosilicate glass (FSG), phosphosilicate glass (PSG), borosilicate glass (BSG), polymer materials, and / or other suitable dielectric materials. Dielectric layer 206 may be formed by PECVD, low-LPCVD, PVD, or other suitable deposition processes. In some embodiments, dielectric layer 206 may comprise silicon oxide formed using a tetraethoxysilane (TEOS) precursor in a PECVD process.

[0067] In some embodiments, the etch stop layer 204 may be omitted, and the dielectric layer 206 may be in solid contact with the substrate 202. In other embodiments, any number of intervening layers may be provided between the dielectric layer 206 and the substrate 202. Such intervening layers may include an IMD layer or a dielectric layer, and may have contact sockets, conductive lines, and / or conductive pillars formed therein, or may include one or more intervening layers, such as additional etch stop layers, adhesion layers, and combinations thereof, and the like.

[0068] Method 100 can be used to pattern the dielectric layer 206 to form trenches and conductive pillar openings. Figures 2 to 15 In the example shown, trench and conductive pillar patterns are formed in dielectric layer 206 using two lithography processes. A first lithography process forms a first pattern having trench openings or wiring openings. A second lithography process forms a second pattern having conductive pillar openings aligned with the trench openings in the first pattern. The trench openings and conductive pillar openings are patterned and then transferred to dielectric layer 206 using a stack of hard masking layers. In some embodiments, the stack of hard masking layers includes a metal-containing hard masking layer sandwiched between two dielectric hard masking layers with different etch characteristics. In some embodiments, the hard masking stack includes a first hard masking layer 208, a second hard masking layer 210 formed on the first hard masking layer 208, and a third hard masking layer 212 formed on the second hard masking layer 210. The first hard masking layer 208 and the third hard masking layer 212 are dielectric masks with high etch selectivity relative to each other, and the second hard masking layer 210 is a metal-containing mask. In some embodiments, the first hard masking layer 208 contains oxygen but not nitrogen, while the third masking layer 212 does not contain oxygen.

[0069] In operation 102 of method 100, a first hard mask layer 208 is deposited on dielectric layer 206, such as Figure 2 As shown in the diagram. The first hard mask layer 208 may be formed of a material including oxide materials (e.g., silicon oxide, titanium oxide, silicon carbide, or similar materials, or combinations thereof). In some embodiments, when the dielectric layer 206 includes a low-k material, the first hard mask layer 208 may be formed of silicon oxide. The first hard mask layer 208 may include more than one layer and includes more than one material. In some embodiments, the first hard mask layer 208 is formed of a nitrogen-free material.

[0070] The first hard mask layer 208 can be formed using processes such as CVD, ALD, or similar methods. In some embodiments, the first hard mask layer 208 has a thickness between about 100 angstroms and about 300 angstroms. In other embodiments, the first hard mask layer 208 may have another thickness suitable for the critical dimensions of features to be patterned in the dielectric layer 206 and the first hard mask layer 208.

[0071] In operation 104 of method 100, a second hard mask layer 210 is formed above the first hard mask layer 208, such as Figure 2 As shown in the diagram. In subsequent processing steps, a pattern is formed on the second hard mask layer 210 using the patterning techniques described herein. As described below, the second hard mask layer 210 serves as an etching mask for etching the first hard mask layer 208 and transferring the pattern of the second hard mask layer 210 to the first hard mask layer 208. The second hard mask layer 210 may be formed of a material containing one or more metals, such as tungsten, titanium nitride, titanium, tungsten carbide, titanium oxide, tantalum nitride, tantalum, or combinations thereof.

[0072] The second hard mask layer 210 may be formed by processes such as CVD, ALD, or similar. Other processes and materials may be used. In some embodiments, the second hard mask layer 210 has a thickness between about 100 angstroms and about 300 angstroms. In other embodiments, the second hard mask layer 210 may have another thickness suitable for the critical dimensions of features to be patterned in the dielectric layer 206, the first hard mask layer 208, or the second hard mask layer 210.

[0073] In operation 106 of method 100, the third hard mask layer 212 is formed above the second hard mask layer 210, as follows: Figure 2As shown in the diagram. In subsequent processing steps, the third hard mask layer 212 serves as an etch stop during the etching of the first hard mask layer 208 and dielectric layer 206; therefore, the third hard mask layer 212 comprises a material having etch selectivity relative to the first hard mask layer 208 and dielectric layer 206. In some embodiments, the third hard mask layer 212 is oxygen-free. For example, the third hard mask layer 212 may be a nitrogen-containing dielectric material, such as silicon nitride (SiN), silicon carbonitride (SiCN), or other nitrogen-containing materials. The third hard mask layer 212 may be formed using processes such as CVD, ALD, or similar methods.

[0074] In some embodiments, the third hard mask layer 212 has a thickness between about 100 angstroms and about 300 angstroms. In other embodiments, the third hard mask layer 212 may have another thickness suitable for the critical dimensions of features patterned in the dielectric layer 206, the first hard mask layer 208, the second hard mask layer 210, or the third hard mask layer 212.

[0075] In operation 108 of method 100, the mandrel layer 214 is formed on the third hard mask layer 212, as follows: Figure 2 As shown in the diagram. As described below, the mandrel layer 214 can be patterned to form a mandrel, serving as a base for subsequent spacer patterns in a self-aligned double patterning (SADP) process. In the SADP process, the mandrel layer 214 is removed from the third hard mask layer 212, thus exhibiting high etch selectivity relative to the third hard mask layer 212.

[0076] The mandrel layer 214 may comprise one or more layers and comprise more than one material. In some embodiments, the mandrel layer 214 may be a carbon material layer, such as a carbon layer deposited using a CVD process, a spin-on carbon material, or a layer of other types of carbon material. In some embodiments, the mandrel layer 214 comprises amorphous silicon formed by CVD, PVD, PECVD, or other suitable deposition methods. In some embodiments, the mandrel layer 214 comprises tin oxide. For example, the mandrel layer 214 may comprise an atomic ratio of tin to oxygen of about 1:2 (e.g., SnO2). The mandrel layer 214 may be deposited using any suitable process (such as ALD, CVD, PVD, or similar). In some embodiments, Sn(CH3)4 and O2 are used as precursors during deposition, and the deposition may be performed at a temperature of about 1°C to about 200°C and a pressure of about 1 Torr to about 10 Torr.

[0077] In some embodiments, the mandrel layer 214 has a thickness between about 200 angstroms and about 500 angstroms. In other embodiments, the mandrel layer 214 may have another thickness suitable for the critical dimensions of features to be patterned in the dielectric layer 206, the first hard mask layer 208, the second hard mask layer 210, the third hard mask layer 212, or the mandrel layer 214.

[0078] In operation 110 of method 100, the mandrel layer 214 is patterned to form a plurality of mandrels 214m, such as Figure 3 As shown in the diagram. The mandrel 214m is defined by the remainder of the mandrel layer 214. In some embodiments, the mandrel 214m may be a plurality of parallel strips formed along the y-direction and having a pitch P1 along the x-direction. In some embodiments, the pitch P1 is the minimum pitch achievable using a lithography process. The mandrel 214m may be formed by depositing and patterning a photoresist structure over the mandrel layer 214.

[0079] like Figure 2 As shown, three layers of photoresist 215 are formed on the mandrel layer 214. The three layers of photoresist 215 include a bottom layer 240, an intermediate layer 242 above the bottom layer 240, and an upper layer 244 above the intermediate layer 242. The upper layer 244 may be formed of photoresist. In some embodiments, the intermediate layer 242 may comprise an inorganic material, such as silicon nitride, silicon oxynitride, silicon oxide, or the like. The bottom layer 240 may be a bottom anti-reflective coating (BARC) layer. The intermediate layer 242 has high etch selectivity relative to the upper layer 244 and the bottom layer 240. The layers of photoresist 215 may be deposited sequentially as a blanket, for example, by spin coating. Although three layers of photoresist 215 have been discussed herein, other types of photoresist, such as single-layer or double-layer photoresist, may also be used. The type of photoresist used may depend on the lithography process used to pattern the mandrel layer 214.

[0080] A lithography process is performed to pattern the upper layer 244 using a first pattern having a plurality of parallel lines with a pitch of P1. The patterned upper layer 244 is then used as an etch mask for patterning the intermediate layer 242. The patterned intermediate layer 242 is then used as an etch mask for patterning the bottom layer 240, and subsequently, the patterned bottom layer 240 is used to pattern the mandrel layer 214, forming a mandrel 214m separated from the opening 214o, as shown. Figure 3 As shown in the figure. It has been observed that using a three-layer photoresist to etch the target layer (e.g., the mandrel layer 214) improves the clarity of the fine-pitch pattern formed in the target layer.

[0081] After performing a lithography process, a pattern comprising a plurality of mandrels 244m separated by openings 244o is formed in the upper layer 244. The pattern of the upper layer 244 is then transferred to the intermediate layer 242 in an etching process. In some embodiments, an anisotropic etching process is used such that the openings 244o in the upper layer 244 extend through the intermediate layer 242 at substantially the same size. Optionally, a trimming process may be performed to increase the size of the openings 244o in the intermediate layer 242. In some embodiments, the trimming process may be an anisotropic plasma etching process with a process gas including O2, CO2, N2 / H2, H2, the like, combinations thereof, or any other gas suitable for trimming the intermediate layer 242. The trimming process may increase the width W1 of the openings 244o and decrease the width W2 of the mandrels 244m. An anisotropic etching process can be performed to transfer the pattern of the intermediate layer 242 to the bottom layer 240, thereby causing the opening 244o to extend through the bottom layer 240.

[0082] Next, an anisotropic etching process is used to transfer the pattern of the bottom layer 240 to the mandrel layer 214, so that the opening 244o in the bottom layer 240 extends through the mandrel layer 214. For example... Figure 3 As shown, after operation 110, the mandrel layer 214 has a pattern comprising a mandrel 214m of width W4, separated by an opening 214o of width W3. In some embodiments, the width W4 may be 20 nm or less. In some embodiments, a trimming process may be performed on the intermediate layer 242 to achieve a desired ratio of width W4 to width W3, thereby uniformly spacing subsequently defined spacer wirings. In other embodiments, the intermediate layer 242 is initially patterned to have the desired width W4 to width W3 ratio, and the trimming process may be omitted.

[0083] The mandrel layer 214 can be etched using any suitable etching process, such as a dry etching process. In some embodiments, when the mandrel layer 214 is formed of tin oxide, a hydrogen-containing etchant containing hydrogen as a reactive component can be used as the etchant. For example, the etchant may include hydrogen (H2) or hydrogen in combination with HBr, NH3, or the like as an active etchant. In some embodiments, the etchant may include other process gases, such as Ar, N2, or combinations thereof, as a carrier gas. In some embodiments, when the mandrel layer 214 comprises tin oxide, the mandrel layer 214 is etched using H2 plasma. In other embodiments, different reactants, such as chlorine (Cl2), may be used to etch the mandrel layer 214. In some embodiments, for example, when the mandrel layer 214 is formed of amorphous silicon, the mandrel layer 214 may be etched using a reactive ion etch (RIE) process, wherein the etching process gas includes fluorine in the form of CHF3, CF4, CH2F2, SF3, the like, or combinations thereof. Additional process gases, such as Ar, N2, O2, and similar substances or combinations thereof, may be used.

[0084] The third hard mask layer 212 beneath the mandrel layer 214 serves as an etch stop layer during the patterning of the mandrel layer 214. The third hard mask layer 212 can be used as an etch stop layer because the material of the mandrel layer 214 can be patterned with a chemical etchant (e.g., a hydrogen-containing gas), which does not significantly etch the third hard mask layer 212, which includes SiN or SiCN.

[0085] In operation 112, the spacer layer 216 (e.g., on the patterned mandrel layer 214) is... Figure 4 As shown), and the spacer mandrel 216m is then formed above the mandrel 214m and along the sidewall, as shown. Figure 5 As shown in the diagram. In some embodiments, spacer layer 216 may be deposited on all exposed surfaces, including the exposed surface of the third hard mask layer 212 in opening 214o and the top surface of mandrel 214m. The material of spacer layer 216 is selected to have high etch selectivity with respect to the third hard mask layer 212 and mandrel 214m. For example, spacer layer 216 may comprise oxides such as SiO or TiO.

[0086] The spacer layer 216 can be deposited using any suitable process (such as ALD, CVD, or similar). In some embodiments, the deposition process of the spacer layer 216 is conformal, such that the thickness of the spacer layer 216 on the sidewall of the mandrel 214m is substantially equal to the thickness of the spacer layer 216 on the top surface of the mandrel 214m and the bottom surface of the opening 214o.

[0087] The spacer layer 216 is patterned to remove the lateral portions of the spacer layer 216, while leaving the spacer mandrel 216m on the sidewall of the mandrel 214m, as shown. Figure 5 As shown in the diagram, the spacer layer 216 is etched to expose portions of the mandrel 214m and the third hard mask layer 212. Patterning the spacer layer 216 may include a dry etching process that selectively etches the spacer layer 216 at a higher speed than etching the mandrel 214m and the third hard mask layer 212. Because the spacer layer 216 comprises an oxide material, an etchant with a high etch rate used for etching oxide materials can be used to etch the spacer layer 216. Examples of etchants for etching the spacer layer 216 may include CF4, CHF3, or other fluorine-containing gases. The dry etching process may be anisotropic, such as a RIE process.

[0088] In operation 114, mandrel 214m is removed to form a groove pattern, wherein spacer mandrel 216m is separated from opening 216L, as shown. Figure 6 As shown in the diagram. The mandrel 214m is removed using an etching process. Because the mandrel 214m has relative etch selectivity to the spacer mandrel 216m, the mandrel 214m can be removed without removing the spacer mandrel 216m. The etched mandrel 214m exposes an underlying third hard mask layer 212, which can act as an etch stop layer. In some embodiments, the etched mandrel 214m can reduce the height of the spacer mandrel 216m without removing it. The removal of the mandrel 214m can be performed using a dry etching process similar to the process for patterning the mandrel 214m described in operation 110. For example, a dry etching process can selectively remove the mandrel 214m using a hydrogen-containing reactive gas while leaving the spacer mandrel 216m intact. However, the chemical composition of the etchant used to remove the mandrel 214m may be the same as or different from the chemical composition of the etchant used to pattern the mandrel 214m.

[0089] After some or all of the mandrel 214m is removed, the spacer mandrel 216m may have a pitch P2. In some embodiments, the pitch P2 may be less than about 30 nm. In embodiments employing the SADP process described above, the pitch P2 may be half of the minimum pitch achievable by a lithography process. In some embodiments, the pattern defined by the spacer mandrel 216m is the negative terminal of the subsequently formed conductive wire. For example, the opening 216L corresponds to the pattern of the subsequently formed conductive wire. The width of each of the spacer mandrels 216m is W6, and the width of each of the openings 216L is W5. The sum of the widths W5 and W6 is equal to the pitch P2. In some embodiments, the width W6 may be in the range of about 40% to about 60% of the pitch P2. A width W6 less than 40% of the pitch P2 may not produce a spacer mandrel that is sufficiently robust for subsequent processing, while a width W6 greater than 60% of the pitch P2 may produce a thin conductive wire, thereby increasing the resistance of the conductive wire.

[0090] In some embodiments, operations 112 and 114 may be omitted, and the mandrel 214m formed in operation 110 may be used directly as an etching mask and transferred to the third hard mask layer 212 as described below.

[0091] In operation 116, the pattern spaced between the centroids 216m is transferred to the third hard mask layer 212 and the second hard mask layer 210, as follows: Figure 7 As shown in the figure, the opening 216L of the separation spacer mandrel 216m extends through the third hard mask layer 212 and the second hard mask layer 210, forming openings 212L / 210L and mask strips 212m / 210m, and exposing a portion of the first hard mask layer 208.

[0092] The pattern of the spacer core layer 214 is first transferred to the third hard mask layer 212 during a suitable etching process. For example... Figure 7 As shown, after operation 116, a plurality of mask strips 212m are formed in the third hard mask layer 212. Mask strips 212m, separated by openings 212L, are formed therein through the third hard mask layer 212. Openings 212L have approximately the same size as openings 216L. The etching process may be anisotropic, such that openings 216L, spaced between the mandrels 216m, extend through the third hard mask layer 212, and openings 212L and openings 216L in the third hard mask layer 212 have substantially the same size.

[0093] The etching process for etching the third hard mask layer 212 may include a wet etching process, a dry etching process, or a combination thereof. Because the third hard mask layer 212 comprises an oxygen-free material and the spacer mandrel 216m comprises an oxide, the spacer mandrel 216m can be used as an etching mask and the second hard mask layer 210 as an etching stop layer, selectively etching the third hard mask layer 212 using an oxidant. In some embodiments, an oxygen (O2) plasma can be used to etch the third hard mask layer 212. In other embodiments, a plasma etching process is used to etch the third hard mask layer 212, the plasma etching process including one or more process gases, such as CF4, NF3, other suitable gases, or combinations thereof.

[0094] After etching the third hard mask layer 212, a portion of the spacer mandrel 216m may be retained. In some embodiments, the remaining portion of the spacer mandrel 216m may be removed using a suitable etching process, for example, a wet etching process called BOE (buffered oxide etching) using a solution of hydrofluoric acid (HF) and ammonium fluoride (NH4F). In other embodiments, the remaining portion of the spacer mandrel 216m may be removed using a dry etching process using an etchant comprising CF4 and H2.

[0095] After removing the spacer mandrel 216m, the pattern in the third hard mask layer 212 is transferred to the second hard mask layer 210 using a suitable etching process. The etching process can be anisotropic, allowing openings in the third hard mask layer 212 to extend through the second hard mask layer 210 at substantially the same size. Figure 7 As shown, after operation 116, a plurality of masking strips 210m are formed in the second hard masking layer 210. Adjacent masking strips 210m are separated by openings 210L. Openings 210L have approximately the same size as openings 212L.

[0096] In some embodiments, the second hard mask layer 210, including the metallic material, can be etched using plasma processes such as inductively coupled plasma (ICP), parallel plate plasma, ion beam etching (IBE), or reactive ion beam etching (RIBE). In some embodiments, the second hard mask layer 210 is etched using plasma etching with fluorine-containing gases (such as CF4 and / or CHF3), carbon-containing gases (such as CH4), and chlorine-containing gases (such as Cl2).

[0097] like Figure 7As shown, after operation 116, the pitch of the masking strips 212m / 210m and the openings 212L / 210L is pitch P2. The width of the masking strips 212m / 210m is approximately equal to the width W6, and the width of the openings 212L / 210L is approximately equal to the width W5.

[0098] In operation 118, three layers of photoresist 217 are disposed above the patterned hard mask layers 212, 210, and 208, and a conductive pillar pattern is formed in the three layers of photoresist 217, such as... Figures 8A to 8B and Figures 9A to 9B As shown in the figure. The three-layer photoresist 217 can be similar to the three-layer photoresist 215 described above.

[0099] In some embodiments, the three-layer photoresist 217 may be selectively chosen to suit extreme ultraviolet (EUV) lithography. The photoresist 217 may include a bottom layer 218 formed over a first hard mask layer 208 and between openings 212L / 210L in patterned hard mask layers 210 and 212; an intermediate layer 220 formed over the bottom layer 218; and an upper layer 222 formed over the intermediate layer 220. The upper layer 222 is a photoresist layer. In other embodiments, one or both of the bottom layer 218 and the intermediate layer 220 may be omitted to form a bilayer photoresist structure or a monolayer photoresist structure.

[0100] The bottom layer 218 may be a material such as spin-on-carbon (SOC), silicon carbide (SiOC), silicon, silicon oxynitride, titanium oxide, silicon oxide, silicon nitride, polymers, or combinations thereof. The bottom layer 218 contains a patternable material and / or a material tuned to provide anti-reflective properties. The bottom layer 218 may be formed by a spin coating process, such that the bottom layer 218 fills the openings 210L / 212L. The bottom layer 218 may have a thickness between approximately 50 angstroms and approximately 300 angstroms.

[0101] Intermediate layer 220 may have a composition that provides anti-reflective properties and / or hard masking properties for lithography processes. In one embodiment, intermediate layer 220 includes a silicon-containing layer, such as a silicon hard masking material. Intermediate layer 220 may include a silicon-containing inorganic polymer. In other embodiments, intermediate layer 220 includes a siloxane polymer, such as a polymer having an O-Si-O-Si backbone. The silicon ratio of intermediate layer 220 may be selected to control the etching rate. In other embodiments, intermediate layer 220 may include silicon oxide, such as spin-on glass (SOG), silicon nitride, silicon oxynitride, polycrystalline silicon, a metal-containing organic polymer material (the organic polymer material contains metals such as titanium, titanium nitride, aluminum, and / or tantalum), and / or other suitable materials. Intermediate layer 220 may be omitted when there is good adhesion between bottom layer 218 and top layer 222. Intermediate layer 220 may have a thickness between about 50 angstroms and about 300 angstroms.

[0102] The upper layer 222 may be a positive or negative photoresist layer. In some embodiments, the upper layer 222 is made of polymethyl methacrylate (PMMA), polymethyl glutarimide (PMGI), phenolic resin (DNQ / Novolac), or SU-8. In one embodiment, the upper layer 222 may have a thickness between about 200 angstroms and about 500 angstroms.

[0103] In operation 118 of method 100, such as Figures 8A to 8B As shown, the upper layer 222 is patterned using a lithography process. In some embodiments, the upper layer 222 can be patterned using an extreme ultraviolet (EUV) lithography process, which uses extreme ultraviolet radiation or soft X-rays, i.e., radiation with wavelengths less than 130 nm, and has become one of the lithography methods used to form smaller semiconductor devices.

[0104] The upper layer 222 is patterned with a second pattern including one or more conductive post openings 222v. The openings 222v expose the intermediate layer 220 (if present) or the bottom layer 218 (if the intermediate layer 220 is absent). Figure 8B As shown, the conductive post opening 222v may have a width W7 along the x-direction and a width W8 along the y-direction. The width W8 may be the same as or different from the width W7. The conductive post opening 222v in... Figure 8B The opening is shown as a rectangle. However, the conductive post opening 222v can have other shapes, such as circular, elliptical, or square.

[0105] Subsequently, the patterned upper layer 222 is used as an etch mask for the patterned intermediate layer 220. The patterned intermediate layer 220 is then used as an etch mask for the patterned bottom layer 218, and the patterned bottom layer 218 is then used to pattern the first hard mask layer 208, as... Figure 9Aand Figure 9B As shown in the image.

[0106] In some embodiments, an anisotropic etching process is used such that an opening 222v in the upper layer 222 extends through the intermediate layer 220 to form a conductive pillar opening 220v. The conductive pillar openings 222v and 220v are substantially the same size. An etching process can be performed to transfer the pattern of the intermediate layer 220 to the bottom layer 218 to form a conductive pillar opening 218v in the bottom layer 218. The conductive pillar opening 218v may have a width W9 at the level of the third hard mask layer 212. Figure 9A As shown, due to the high aspect ratio of the conductive pillar opening 218v, the conductive pillar opening 218v can shrink along the z-direction, resulting in the width W9 at the third hard mask layer 212 being smaller than the width W7. The difference between the width W9 and the width W7 can be referred to as "process shrinkage".

[0107] The conductive post opening 222v is positioned to align with one of the openings 212L / 210L, such that an opening can be formed at the bottom of the respective opening 212L / 210L through the first hard masking layer 208. To align the conductive post opening 222v with the target opening 212L / 210L, the width W7 of the conductive post opening 222v is selected to be equal to or greater than the width W5, thereby providing tolerance for coverage errors and tolerance for the aforementioned process shrinkage. In some embodiments, the width W7 may be greater than the width W5, with a tolerance ranging from about 3 nm to about 50% of the pitch P2. When the tolerance is less than about 3 nm, the conductive post opening 222v may not be able to align with the target opening 212L / 210L due to coverage errors. When the tolerance is greater than about 50% of the pitch P2, the conductive post opening 222v may connect to two adjacent wiring openings 212L / 210L, resulting in a short circuit in the resulting conductive features.

[0108] In some embodiments, the minimum dimension of width W7 is half of the minimum pitch achievable by the lithography process for patterning the upper layer 222. As described above, the pitch of the mask strips 212m / 210m and the openings 212L / 210L is pitch P2, which can be half of the minimum pitch achievable by the lithography process. The width W5 of the openings 212L / 210L can be between 40% and 60% of the pitch P2. When the pitch of the openings 212L / 210L is half of the minimum pitch achievable by the lithography process, the width W7 of the conductive post opening 222v is within the range between pitch P2 and the sum of pitch P2 and process shrinkage.

[0109] like Figures 9A to 9BAs shown, after patterning the three layers of photoresist 217, a conductive pillar opening 218v is formed through the bottom layer 218 and exposes a portion of the first hard mask layer 208. Because the width W7 is selected to allow the width W9 of the conductive pillar opening 218v at the third hard mask layer 212 level to be greater than the width W5 of the opening 212L / 210L, a portion of the third hard mask layer 212 is exposed on one or both sides of the conductive pillar opening 218v.

[0110] In operation 120, such as Figures 10A to 10B and Figures 11A to 11B As shown, the conductive pillar pattern formed in the three-layer photoresist 217 is transferred to the dielectric layer 206 through one or more etching processes. The bottom layer 218 serves as an etching mask to progressively transfer the pattern of the bottom layer 218 to the first hard mask layer 208 and the dielectric layer 206, which is the target layer for forming the conductive pillar openings 208v and 206v. An etching stop layer 204 is exposed at the bottom of the conductive pillar opening 206v. Figure 10B As shown, the conductive post openings 208v / 206v have a width equal to the width W5 along the x-direction. The conductive post openings 208v / 206v have a width equal to the width W8 along the y-direction.

[0111] The first hard mask layer 208 and dielectric layer 206 can be etched in the same process or in separate processes. In some embodiments, plasma or RIE anisotropic etching can be used to form the conductive pillar openings 208v / 206v to achieve relatively uniform dimensions. In some embodiments, a RIE process can be used, which uses an etchant with a high etching rate against oxides. Example etchants may include CF4, CHF3, or other fluorine-containing gases. In other embodiments, the first hard mask layer 208 and dielectric layer 206 can be etched using any suitable etching process, for example, a wet etching process called BOE (buffered oxide etching) using a solution of hydrofluoric acid (HF) and ammonium fluoride (NH4F). In other embodiments, the first hard mask layer 208 and dielectric layer 206 can be removed using a dry etching process containing an etchant containing CF4 and H2.

[0112] Because the third hard mask layer 212 is an oxygen-free layer, the etching chemistry used to etch the oxygen-containing first hard mask layer 208 and dielectric layer 206 etches the third hard mask layer 212 very slowly. As a result, the exposed third hard mask layer 212 acts as an etching mask, protecting the underlying second hard mask layer 210 during the etching process to form the conductive pillar openings 208V / 206V.

[0113] In current hard mask stacking techniques, both the first and third hard mask layers comprise oxide-based dielectric materials typically formed from the same material. This is because spacer cores are conventionally formed of silicon nitride for ease of fabrication, and the third hard mask layer needs to be oxide-based to achieve etch selectivity between the spacer core and the third hard mask layer. As the critical size decreases, to address coverage tolerances and / or lithography limitations, the openings of the conductive pillars formed in the photoresist layer are wider than the trench openings, resulting in the exposure of a portion of the third hard mask layer after the patterned conductive pillar openings. The exposed third mask layer will be etched at the same rate as the first hard mask layer and the dielectric layer, leading to damage or loss of the second hard mask layer or the metal-containing hard mask layer, which can cause the conductive lines with conductive pillars to collapse. By selecting materials with high etch selectivity for the first hard mask layer 208 and the third hard mask layer 212, the embodiments disclosed herein enable a reduction in pitch without damaging the conductive lines.

[0114] During the etching of the first hard mask layer 208 and the dielectric layer 206, the intermediate layer 220 is consumed. After forming the conductive pillar openings 208V / 206V, an ashing process can be performed to remove the bottom layer 218 of the three-layer photoresist 217, thereby exposing the wiring openings 212L / 210L, as shown. Figures 11A to 11B As shown in the image.

[0115] In operation 122 of method 100, the patterns with openings 212L / 210L in the third hard mask layer 212 and the second hard mask layer 210 are transferred to a portion of the first hard mask layer 208 and the dielectric layer 206, such as Figures 12A to 12B As shown in the diagram. In operation 122, the first hard mask layer 208 and the dielectric layer 206 may be etched in the same process or using separate processes. In some embodiments, plasma or RIE anisotropic etching may be used to form wiring openings 208L in the first hard mask layer 208 and wiring openings 206L in the dielectric layer 206 to achieve relatively uniform dimensions. In some embodiments, a RIE process may be used, which uses an etchant with a high etching rate against oxides. Example etchants may include CF4, or CHF3, or other fluorine-containing gases. In other embodiments, the first hard mask layer 208 and the dielectric layer 206 may be etched using any suitable etching process, for example, a wet etching process called BOE (buffered oxide etching) using a solution of hydrofluoric acid (HF) and ammonium fluoride (NH4F). In other embodiments, the first hard mask layer 208 and the dielectric layer 206 may be removed using a dry etching process containing an etchant containing CF4 and H2.

[0116] During the formation of wiring openings 208L and 206L, the third hard mask layer 212 and the second hard mask layer 210 serve as etching masks. The third hard mask layer 212 may be consumed or substantially consumed during operation 122. In some embodiments, the etch stop layer 204 exposed by the conductive post opening 206v is also removed, thereby extending the conductive post opening 206v to the underlying layer.

[0117] like Figure 12B As shown, because the shielding strips 210m on both sides of the conductive post openings 208v / 206v maintain structural integrity during the conductive post patterning in operation 120, the wiring openings 210L / 208L / 206L are substantially consistent with other positions at the location where they connect to the conductive post opening 206v.

[0118] In operation 124 of method 100, one or more conductive materials are filled into the wiring openings 210L / 208L / 206L and the conductive post openings 208v / 206v to form conductive wires 226L and conductive posts 226v (collectively referred to as conductive features 226), respectively. Figure 13 As shown in the image.

[0119] The conductive material may include Co, Cu, Ag, Al, TiN, TaN, Ta, Ti, Hf, Zr, Ni, W, Zn, Ca, Au, Mg, Mo, Cr, or the like. The conductive material may be formed by CVD, PVD, electroplating, ALD, or other suitable techniques. In some embodiments, one or more liner layers and / or barrier layers (not shown) may be formed along the sidewalls and bottom surfaces of the wiring openings 210L / 208L / 206L and the conductive post openings 208v / 206v before the conductive material is filled. The liner may include TiO, TiN, TaO, TaN, or the like, and may provide a diffusion barrier layer, an adhesion layer, and / or a seed layer for the conductive wires.

[0120] In operation 126, a planarization process, such as chemical mechanical polishing (CMP), is performed to remove excess conductive material and expose the dielectric layer 206, as follows. Figure 14 As shown in the diagram, conductive lines 226L and conductive pillars 226v are formed within the dielectric layer 206.

[0121] In operation 128, a subsequent layer, such as another dielectric layer 230 having conductive pillars 232v and conductive lines 232L, may be formed thereon, as follows: Figure 15 As shown in the figure. In some embodiments, method 100 can be used to form conductive pillars 232v and conductive lines 232L in dielectric layer 230. Alternatively, depending on the circuit design, interconnect structures or bonding pads can be formed above dielectric layer 206.

[0122] The various embodiments or examples described herein offer several advantages over the prior art. One disclosed embodiment provides a hard mask stack including a first dielectric mask layer, a second dielectric mask layer, and a metal mask layer, wherein the first and second dielectric mask layers have high etch selectivity. By selecting materials with high etch selectivity for the two dielectric layers, the disclosed embodiments enable a reduction in pitch without damaging the conductive lines.

[0123] It should be understood that not all advantages need to be disclosed herein, no particular advantage needs to be used in all embodiments or instances, and other embodiments or instances may provide different advantages.

[0124] Some embodiments disclosed herein provide a method for fabricating a semiconductor structure. The method includes depositing a first hard mask layer over a dielectric layer, depositing a second hard mask layer over the first hard mask layer, wherein the second hard mask layer includes a metallic material, depositing a third hard mask layer over the second hard mask layer, wherein the third hard mask layer and the first hard mask layer have etch selectivity relative to each other, forming a first pattern through the third hard mask layer and the second hard mask layer, forming a second pattern through the first hard mask layer and the dielectric layer, using the third hard mask layer as an etch stop, and transferring the first pattern from the third hard mask layer and the second hard mask layer through the first hard mask layer to the dielectric layer.

[0125] In some embodiments, the third hard mask layer comprises silicon nitride.

[0126] In some embodiments, the first hard mask is a nitrogen-free layer.

[0127] In some embodiments, the first hard mask layer comprises an oxide.

[0128] In some embodiments, the step of forming a first pattern through the third hard mask layer and the second hard mask layer includes the following steps: forming a mandrel layer on the third hard mask layer; patterning the mandrel layer to form a plurality of mandrels; forming a plurality of spacer mandrels on a plurality of sidewalls of the mandrels; removing the mandrels; and using the spacer mandrels as an etch mask and the first hard mask layer as an etch termination to etch the third hard mask and the second hard mask.

[0129] In some embodiments, the spacer core is formed of an oxide material.

[0130] In some embodiments, the central axis layer comprises tin oxide.

[0131] Some embodiments disclosed herein provide a method for fabricating a semiconductor structure. The method includes depositing a hard mask stack, wherein the hard mask stack includes a first hard mask layer, a second hard mask layer disposed on the first hard mask layer, and a third hard mask layer disposed on the second hard mask layer, wherein the third hard mask layer comprises a nitride, and forming a plurality of mandrels on the hard mask stack, forming spacer mandrels on the sidewalls of the plurality of mandrels, wherein the spacer mandrels comprise oxide, removing the plurality of mandrels, and using the spacer mandrels as etch masks to etch the third hard mask layer.

[0132] In some embodiments, the first hard mask layer comprises an oxide, and the second hard mask layer comprises a metal.

[0133] In some embodiments, forming the mandrel includes the steps of: depositing a mandrel layer comprising amorphous silicon, carbon, or tin oxide; and patterning the mandrel layer to form the mandrel on a third hard mask layer.

[0134] In some embodiments, the spacer mandrel comprises silicon oxide or titanium oxide.

[0135] In some embodiments, the method further includes the following steps: forming a conductive pillar pattern over a first hard mask layer and a dielectric layer below the first hard mask layer; and using a third hard mask layer as an etching mask to etch through a portion of the first hard mask layer and the dielectric layer to form a wiring pattern in the dielectric layer.

[0136] In some embodiments, the step of forming the conductive pillar pattern includes the following steps: depositing a photoresist over a third hard mask layer; patterning the photoresist to form a conductive pillar opening through the photoresist, wherein the conductive pillar opening is aligned with a wiring opening between two adjacent mandrels in the third hard mask layer, and at least one of the two adjacent mandrels is exposed through the conductive pillar opening; and using the photoresist as an etch mask to etch through the first hard mask layer.

[0137] In some embodiments, it further includes the step of filling multiple openings in the wiring pattern and the conductive post pattern with a conductive material.

[0138] Some embodiments disclosed herein provide a method for fabricating a semiconductor structure. The method includes depositing a first hard mask layer on a target layer, depositing a second hard mask layer on the first hard mask layer, wherein the second hard mask layer comprises a metal-containing material, depositing a third hard mask layer on the second hard mask layer, wherein the third hard mask layer is an oxygen-free layer, forming a first pattern thereon through the third hard mask layer and the second hard mask layer, and forming a second pattern through the first hard mask layer, wherein the second pattern overlaps with the first pattern, and the third hard mask layer serves as an etch stop during patterning of the first hard mask layer.

[0139] In some embodiments, the third hard mask layer comprises silicon nitride.

[0140] In some embodiments, the first hard mask layer is a nitrogen-free layer.

[0141] In some embodiments, the step of forming the first pattern includes the following steps: forming a plurality of first mandrels on a third hard mask layer; and using the plurality of first mandrels as an etch mask to etch the third hard mask layer.

[0142] In some embodiments, the step of forming a plurality of first mandrels includes the following steps: depositing a mandrel layer on a third hard mask layer; patterning the mandrel layer to form a plurality of second mandrels; and depositing a spacer layer on a plurality of sidewalls of the second mandrels to form the first mandrels.

[0143] In some embodiments, the first mandrel is formed of an oxide material.

[0144] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that this disclosure can be used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same objectives and / or advantages. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that such equivalent constructions can be modified, substituted, and replaced herein without departing from the spirit and scope of this disclosure.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, Includes the following steps, A first hard masking layer is deposited above a dielectric layer; A second hard mask layer is deposited on the first hard mask layer, wherein the second hard mask layer includes a metal-containing material; A third hard mask layer is deposited on top of the second hard mask layer; A first pattern is formed through the third hard mask layer and the second hard mask layer; An etching process is performed to form a second pattern through the first hard mask layer and an upper portion of the dielectric layer, wherein the third hard mask layer and the first hard mask layer have etch selectivity in the etching process, such that the third hard mask layer acts as an etch mask during the etching process to protect the second hard mask layer; and The first pattern is transferred from the third hard mask layer and the second hard mask layer through the first hard mask layer to the dielectric layer.

2. The method according to claim 1, characterized in that, The third hard mask layer contains silicon nitride.

3. The method according to claim 1, characterized in that, The first hard mask is a nitrogen-free layer.

4. The method according to claim 2, characterized in that, The first hard mask layer contains an oxide.

5. The method according to claim 2, characterized in that, The step of forming the first pattern through the third hard mask layer and the second hard mask layer includes the following steps: A mandrel layer is formed on the third hard mask layer; Pattern the mandrel layer to form multiple mandrels; Multiple spacer mandrels are formed on multiple sidewalls of the multiple mandrels; Remove the multiple mandrels; and Using the plurality of spacer mandrels as an etching mask and the first hard mask layer as an etching termination, the third hard mask and the second hard mask are etched.

6. The method according to claim 5, characterized in that, The plurality of spacer cores are formed of an oxide material.

7. The method according to claim 5, characterized in that, The mandrel layer contains tin oxide.

8. A method for manufacturing a semiconductor structure, characterized in that, Includes the following steps: Deposit a hard mask stack, wherein the hard mask stack comprises: First hard mask layer; A second hard mask layer, disposed on the first hard mask layer; and A third hard mask layer is disposed on the second hard mask layer, wherein the third hard mask layer includes a nitride; and Multiple mandrels are formed on this hard mask stack; A plurality of spacer cores are formed on a plurality of sidewalls of the plurality of cores, wherein the plurality of spacer cores comprise an oxide; Remove the multiple mandrels; The third hard mask layer was etched using the plurality of spacer mandrels as an etch mask. A photoresist is deposited above the third hard mask layer; The photoresist is patterned to form a conductive post opening through the photoresist, wherein the conductive post opening is aligned with a wiring opening between two adjacent spacer cores in the third hard mask layer, and at least one of the two adjacent spacer cores is exposed through the conductive post opening. A conductive pillar pattern is formed above the first hard mask layer and a dielectric layer below the first hard mask layer through the conductive pillar opening, wherein the photoresist serves as an etching mask. and An etching process is performed to etch through the first hard mask layer and an upper portion of the dielectric layer to form a wiring pattern in the dielectric layer, wherein the third hard mask layer and the first hard mask layer have an etching selectivity for the etching process, such that the third hard mask layer acts as an etching mask during the etching process to protect the second hard mask layer.

9. The method according to claim 8, characterized in that, The first hard mask layer comprises an oxide, and the second hard mask layer comprises a metal.

10. The method according to claim 8, characterized in that, Forming the plurality of mandrels includes the following steps: The deposition includes a core layer of amorphous silicon, carbon, or tin oxide; and The mandrel layer is patterned to form the plurality of mandrels on the third hard mask layer.

11. The method according to claim 10, characterized in that, The plurality of spacer cores contain silicon oxide or titanium oxide.

12. The method according to claim 8, characterized in that, It further includes filling the wiring pattern and the multiple openings in the conductive post pattern with a conductive material.

13. A method for manufacturing a semiconductor structure, characterized in that, Includes the following steps: A first hard masking layer is deposited on a target layer; A second hard mask layer is deposited on the first hard mask layer, wherein the second hard mask layer comprises a metal-containing material; A third hard masking layer is deposited on the second hard masking layer, wherein the third hard masking layer is an oxygen-free layer; A first pattern is formed thereon through the third hard mask layer and the second hard mask layer; and An etching process is performed to form a second pattern through the first hard mask layer, wherein the second pattern overlaps with the first pattern, wherein the third hard mask layer and the first hard mask layer have an etching selectivity for the etching process, such that the third hard mask layer acts as an etching mask during the etching process to protect the second hard mask layer.

14. The method according to claim 13, characterized in that, The third hard mask layer contains silicon nitride.

15. The method according to claim 14, characterized in that, The first hard mask layer is a nitrogen-free layer.

16. The method according to claim 15, characterized in that, The steps to form the first pattern include the following: Multiple first mandrels are formed on the third hard mask layer; and The third hard mask layer is etched using multiple first mandrels as an etch mask.

17. The method according to claim 16, characterized in that, The steps of forming the plurality of first mandrels include the following steps: A mandrel layer is deposited on the third hard mask layer; Pattern the mandrel layer to form multiple second mandrels; and A spacer layer is deposited on the sidewalls of the plurality of second mandrels to form the plurality of first mandrels.

18. The method according to claim 17, characterized in that, The plurality of first mandrels are formed of an oxide material.

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