A vertical transistor and its fabrication method

Abstract

This invention provides a vertical transistor and its fabrication method. The fabrication method includes the following steps: transferring a graphene film onto a substrate, patterning the graphene film on the substrate, fabricating a two-dimensional oxide layer on the graphene film, and fabricating a metal electrode on the graphene film, the two-dimensional oxide layer, and the substrate to obtain the vertical transistor. The two-dimensional oxide layer comprises a single-layer two-dimensional oxide with different doping ratios or a multilayer two-dimensional oxide with a heterostructure. The vertical transistor of this invention uses the two-dimensional oxide layer as the channel layer. By metal doping the two-dimensional oxide layer or forming a heterostructure two-dimensional oxide layer, the doping metal ratio can be controlled, and the stability of the two-dimensional oxide layer can be improved. This effectively controls the carrier properties of the vertical transistor channel, achieving higher on-state current and on / off ratio.

Description

Technical Field

[0001] This invention relates to the field of vertical transistor technology, and more particularly to a vertical transistor and its fabrication method. Background Technology

[0002] With the advent of the big data era, the technological development of information technology has placed higher demands on chip performance. The miniaturization and large-scale integration of transistors are important development trends and technical challenges.

[0003] Traditional field-effect transistors (FETs) have a planar geometry, including a channel region connecting the source and drain, and a gate electrostatically coupled to the channel through an oxide dielectric layer. Traditional FETs rely on the electrostatic switching of channel carriers by the gate electric field, where the channel current is always perpendicular to the gate electric field. In contrast, a novel geometry of vertical transistors features a sandwich structure of source / semiconductor / drain, where the carrier transport direction is parallel to the gate electric field direction. The channel length depends on the semiconductor thin film thickness rather than lithographic resolution, typically exhibiting ultra-short channel lengths. This results in superior characteristics such as high speed, low power consumption, and flexible operation, opening up a new field for unique device physics and transistor design. Currently, two different operating mechanisms have been developed for vertical transistors: thermionic vertical transistors with semiconductor channels and tunneling vertical transistors. Various semiconductors conforming to this vertical transistor geometry have been reported, including transition metal chalcogenides, silicon and germanium, thin-film oxide reporters, and organic semiconductors. Among these advancements, the unique structure and electronic properties of atomically thin two-dimensional layered materials have led to the development of novel vertical transistor electronic switch designs that promise to reach the physical limit of the shortest channel. Electrode materials for vertical transistors include metal electrodes, graphene, and carbon nanotubes. Graphene's adjustable work function and partial electrostatic transparency make it suitable as an active contact in van der Waals heterostructures, serving as either a semiconductor or insulating layer. This approach utilizes two-dimensional semiconductor materials as channel materials and graphene as source materials to create a new generation of vertical transistors. However, while common two-dimensional layered semiconductor materials offer many advantages, their controllable doping is challenging, and they suffer from poor stability, hindering their application in vertical transistor channel materials.

[0004] Therefore, existing technologies still need to be improved and developed. Summary of the Invention

[0005] In view of the shortcomings of the prior art, the purpose of this invention is to provide a vertical transistor and its fabrication method to solve the problems of poor stability and difficulty in controllable doping of existing two-dimensional layered semiconductor materials for vertical transistors.

[0006] The technical solution of the present invention is as follows:

[0007] A method for fabricating a vertical transistor includes the following steps:

[0008] A graphene film is transferred onto a substrate, and the graphene film is patterned on the substrate; wherein the substrate includes a silicon substrate gate electrode and a gate dielectric layer disposed on the silicon substrate gate electrode;

[0009] A two-dimensional oxide layer is prepared on the graphene film;

[0010] Metal electrodes are fabricated on the graphene film, the two-dimensional oxide layer, and the substrate to obtain the vertical transistor;

[0011] The two-dimensional oxide layer includes single-layer two-dimensional oxides with different doping ratios or multi-layer two-dimensional oxides with heterostructures.

[0012] In a further embodiment of the present invention, the step of transferring the graphene film onto a substrate and patterning the graphene film on the substrate includes:

[0013] The graphene film is transferred onto the substrate, and photoresist is sequentially spin-coated, exposed, developed, and etched with oxygen plasma to remove the photoresist, thereby obtaining a patterned graphene film.

[0014] In a further embodiment of the present invention, the step of preparing a two-dimensional oxide layer on the graphene film includes:

[0015] A two-dimensional oxide layer was prepared by printing liquid metal onto the graphene film.

[0016] The metal doping ratio of two-dimensional oxides can be controlled by adjusting the composition of liquid metal, or by alternately printing liquid metals with different compositions to obtain multilayer two-dimensional oxides with heterostructures.

[0017] In a further embodiment of the present invention, the doping metal of the monolayer two-dimensional oxides with different doping ratios is one of Ga, Zn or Sn.

[0018] In a further embodiment of the present invention, the heterostructure of the multilayer two-dimensional oxide is an alternating stacked structure of two or more of In2O3, Ga2O3, and ZnO.

[0019] A further feature of the present invention is that the thickness of the single-layer two-dimensional oxide is 0.6-4 nanometers.

[0020] In a further embodiment of the present invention, the step of fabricating a metal electrode on the graphene film, the two-dimensional oxide layer, and the substrate to obtain the vertical transistor includes:

[0021] Metal electrodes are fabricated on the graphene film, the two-dimensional oxide layer, and the substrate using electron beam lithography and thermal evaporation; wherein the metal electrodes comprise:

[0022] The source electrode is disposed on the graphene film;

[0023] The drain electrode is disposed on the two-dimensional oxide layer and the gate dielectric layer.

[0024] In a further embodiment of the present invention, the metal electrode material is titanium (Ti) and gold (Au).

[0025] In a further embodiment of the present invention, the silicon substrate gate electrode is a heavily doped silicon wafer.

[0026] A vertical transistor, fabricated using the vertical transistor fabrication method described in this invention, comprises:

[0027] Silicon substrate gate electrode;

[0028] A gate dielectric layer is disposed on the gate electrode of the silicon substrate;

[0029] A graphene film is disposed on the gate dielectric layer;

[0030] The source electrode is disposed on the graphene film;

[0031] A two-dimensional oxide layer is disposed on the graphene film;

[0032] A drain electrode is disposed on the two-dimensional oxide layer and the gate dielectric layer;

[0033] The two-dimensional oxide layer includes single-layer two-dimensional oxides with different doping ratios or multi-layer two-dimensional oxides with heterostructures.

[0034] This invention provides a vertical transistor and its fabrication method. The fabrication method includes the steps of: transferring a graphene film onto a substrate and patterning the graphene film on the substrate; wherein the substrate includes a silicon substrate gate electrode and a gate dielectric layer disposed on the silicon substrate gate electrode; fabricating a two-dimensional oxide layer on the graphene film; and fabricating a metal electrode on the graphene, the two-dimensional oxide layer, and the substrate to obtain the vertical transistor; wherein the two-dimensional oxide layer includes a single-layer two-dimensional oxide with different doping ratios or a multilayer two-dimensional oxide with a heterostructure. The vertical transistor of this invention uses the two-dimensional oxide layer as the channel layer. By metal doping the two-dimensional oxide layer or forming a heterostructure two-dimensional oxide layer, the doping metal ratio can be controlled, and the stability of the two-dimensional oxide layer can be improved, thereby effectively controlling the channel carrier properties of the vertical transistor and achieving higher on-state current and on-off ratio. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0036] Figure 1 This is a flowchart of a preferred embodiment of a method for fabricating a vertical transistor according to the present invention.

[0037] Figure 2 This is a schematic diagram of the single-layer two-dimensional oxide before synthesis in this invention.

[0038] Figure 3 This is a schematic diagram of the synthesis of a single-layer two-dimensional oxide in this invention.

[0039] Figure 4 This is a schematic diagram illustrating the synthesis of heterostructured multilayer two-dimensional oxides in this invention.

[0040] Figure 5 This is a schematic diagram of the heterostructure multilayer two-dimensional oxide in this invention.

[0041] Figure 6 This is a schematic diagram of the vertical transistor structure in this invention.

[0042] Figure 7 This is a comparison of the transfer characteristic curves of vertical transistors based on In2O3 and Zn-doped In2O3 in this invention.

[0043] Figure 8 This is a comparison of the transfer characteristic curves of the vertical transistors based on ZnO and In2O3 / ZnO heterostructures in this invention.

[0044] The labels in the attached figure are as follows: 1. Gate electrode on silicon substrate; 2. Gate dielectric layer; 3. Graphene film; 4. Two-dimensional oxide layer; 5. Drain electrode; 6. Source electrode. Detailed Implementation

[0045] This invention provides a vertical transistor and its fabrication method. To make the objectives, technical solutions, and effects of this invention clearer and more explicit, the invention will be further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0046] In the implementation methods and claims, unless otherwise specified in the text, the terms "a," "an," "the," and "the" may also include plural forms. If the embodiments of the present invention involve descriptions of "first," "second," etc., such descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features.

[0047] It should be further understood that the term "comprising" as used in this specification means the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It should be understood that when we say an element is "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may be intermediate elements. Furthermore, "connected" or "coupled" as used herein can include wireless connections or wireless coupling. The term "and / or" as used herein includes all or any unit and all combinations of one or more associated listed items.

[0048] It will be understood by those skilled in the art that, unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It should also be understood that terms such as those defined in general dictionaries should be understood to have the same meaning as in the context of the prior art, and should not be interpreted in an idealized or overly formal sense unless specifically defined as herein.

[0049] Furthermore, the technical solutions of the various embodiments can be combined with each other, but only if they are feasible for those skilled in the art. If the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.

[0050] The inventors discovered that while common two-dimensional layered semiconductor materials have many advantages, they also have disadvantages such as difficulty in controllable doping and poor stability, which are not conducive to their application in vertical transistor channel materials.

[0051] To address the aforementioned technical problems, this invention provides a vertical transistor and its fabrication method, such as... Figure 1 As shown, it includes the following steps:

[0052] S100: Transfer the graphene film onto a substrate and pattern the graphene film on the substrate;

[0053] S200: A two-dimensional oxide layer is prepared on the graphene film;

[0054] S300: Prepare metal electrodes on the graphene film, the two-dimensional oxide layer, and the substrate to obtain the vertical transistor.

[0055] This embodiment uses a two-dimensional oxide layer prepared by metal doping and heterostructure as the channel layer, employing a source / two-dimensional oxide layer / drain structure. On one hand, the band structure of the two-dimensional oxide and the carrier concentration can be controlled by adjusting the metal ratio in the liquid metal alloy, i.e., controlling the metal doping ratio in the two-dimensional metal oxide. On the other hand, alternating printing of liquid metals with different compositions facilitates the preparation of heterostructured two-dimensional oxides, thereby improving the performance of the vertical transistor and enhancing transistor performance indicators such as mobility, on / off ratio, threshold voltage, and on-state current.

[0056] Specifically, the two-dimensional oxide is prepared by liquid metal printing (LMP). A thin film of self-oxide (with a minimum thickness of <1 nm) forms on the surface of the liquid metal. This is a natural two-dimensional oxide material, and the composition of the two-dimensional oxide is related to the composition of the liquid metal. Based on the properties of the liquid metal (either elemental liquid metal or liquid metal alloy), the surface of elemental liquid metal generally forms binary oxides, such as zinc oxide (ZnO), indium oxide (In₂O₃), and tin oxide (SnO₂) (which can be considered as doped oxides with a doping concentration of 0), and doped ternary oxides, such as indium tin oxide (ITO) and indium zinc oxide (IZO). That is, changing the composition of the liquid metal alloy can control the doping ratio in the two-dimensional oxide, thereby controlling the band structure and carrier concentration of the two-dimensional metal oxide. Furthermore, the heterostructure of the two-dimensional oxide can control the interaction and carrier properties between adjacent oxide layers, thereby improving transistor performance indicators such as mobility, on / off ratio, threshold voltage, and on-state current of vertical transistors, while simultaneously improving the stability of the two-dimensional oxide. Furthermore, quantum confinement can be achieved by controlling the thickness of two-dimensional oxides. When the particle size reaches the nanometer scale, the electronic energy levels near the Fermi level split from a continuous state into discrete energy levels, thereby changing the magnetic, optical, acoustic, thermal, electrical, and superconducting properties of the material.

[0057] In some embodiments, a heavily doped silicon substrate is selected as the gate electrode of the vertical transistor, wherein SiO2 is used as the gate dielectric layer with a thickness of 100 nm. Of course, other materials with high dielectric constants, such as hafnium oxide (HfO2) or silicon carbide (Si3N4), can also be used, and are not limited thereto. In this embodiment, a p-type heavily doped silicon wafer with a doping concentration of 10⁻⁶ is selected as the Si substrate. 16 / cm 3 The thickness is 500μm.

[0058] In some embodiments, the steps of transferring the graphene film onto a substrate and patterning the graphene film on the substrate include: preparing the graphene film using chemical vapor deposition; sequentially spin-coating photoresist onto the substrate; exposing and developing the substrate; transferring the graphene film using a wet method; and removing the photoresist to obtain the patterned graphene film. It should be noted that the width of the graphene film is smaller than the width of the gate dielectric layer.

[0059] In some embodiments, the step of preparing a two-dimensional oxide layer on the graphene film includes: preparing a two-dimensional oxide layer on the graphene film using liquid metal printing; adjusting the proportion of doped metals in the liquid metal to control the metal doping ratio in the two-dimensional oxide, thereby preparing two-dimensional oxide layers with different metal doping ratios. In this embodiment, doped two-dimensional oxides are formed by doping indium oxide (In2O3) with different proportions of zinc (Zn) (0-5%). Of course, elements such as Ga and Sn can also be used, and are not limited here. Alternatively, heterogeneous multilayer two-dimensional oxides can be prepared by alternating printing of liquid metals with different compositions. For example, the heterogeneous multilayer two-dimensional oxides can be formed by alternating stacking structures of two or more of In2O3, Ga2O3, ZnO, and SnO2, and are not limited here. In addition, it should be noted that the width of the two-dimensional oxide layer is smaller than that of the graphene film.

[0060] like Figures 2-4 As shown, each liquid metal printing produces a two-dimensional oxide layer. The thickness of different single-layer oxides is obtained by controlling the time the liquid metal is exposed to air. That is, the longer the exposure time in air, the thicker the oxide layer. The thickness of a single-layer oxide is generally 0.6-4 nm. Figure 2 In this process, before the liquid metal comes into contact with the surface of the printing material, a thin film of self-oxide is formed on the surface of the liquid metal. The thickness of the single-layer oxide is controlled by controlling the time the liquid metal is exposed to air. Figure 3 In this process, when the liquid metal comes into contact with and leaves the surface of the printing material, the two-dimensional oxide peels off from the liquid metal, forming a single layer of two-dimensional oxide. Figure 4 In this process, a heterogeneous structure of alternating stacks of two-dimensional oxides is fabricated by printing liquid metals of different compositions alternately.

[0061] like Figure 5 As shown, in some embodiments, a heterostructure In2O3 / ZnO of alternating stacked two-dimensional oxides is prepared by alternating printing of liquid metal composed of elemental indium (In) and elemental zinc (Zn). Of course, various heterostructures can also be selected, not limited to ABAB… type stacks, but also ABCABC…, ABCDABCD…, or ABA, ABCBA, ABCDCBA, etc., which are not limited here.

[0062] In some embodiments, a metal electrode is fabricated on the graphene film, the two-dimensional oxide layer, and the gate dielectric layer to obtain the vertical transistor. This process includes the following steps: spin-coating photoresist onto the graphene film, the two-dimensional oxide layer, and the gate dielectric layer, followed by annealing; pre-patterning the electrode using an electron beam; developing the electrode using a developer; depositing a source electrode on the graphene film using thermal evaporation; depositing a drain electrode on the two-dimensional oxide layer and the gate dielectric layer; and finally dissolving the photoresist to obtain the vertical transistor. In this embodiment, titanium (Ti) and gold (Au) are selected as the metal electrode materials. Of course, other suitable metal materials can also be used, and this is not limited to these methods.

[0063] In some embodiments, a vertical transistor is also provided, wherein it is fabricated using the vertical transistor fabrication method described in this invention. For example... Figure 6 As shown, the vertical transistor includes a silicon substrate gate electrode 1, a gate dielectric layer 2 disposed on the silicon substrate gate electrode 1, a graphene film 3 disposed on the gate dielectric layer 2, a two-dimensional oxide layer 4 disposed on the graphene film 3, a drain electrode 5 disposed on the two-dimensional oxide layer 4 and the gate dielectric layer 2, and a source electrode 6 disposed on the graphene film 3. The two-dimensional oxide layer 4 includes single-layer two-dimensional oxides with different doping ratios or multilayer two-dimensional oxides with heterostructures.

[0064] In the vertical transistor provided in this embodiment, the two-dimensional oxide layer 4 serves as the channel layer, the graphene film 3 serves as the active contact of the two-dimensional oxide, the source electrode 6 is fabricated on the graphene film 3, and the drain electrode 5 is fabricated on the two-dimensional oxide layer 4 and the gate dielectric layer 2. The vertical transistor presents a source / two-dimensional oxide layer / drain structure. By controlling the metal doping ratio of the two-dimensional oxide layer or using a heterostructure of multilayer two-dimensional oxide, not only can the stability of the two-dimensional oxide layer be improved, but also the channel carrier properties of the transistor can be effectively controlled to achieve higher on-state current and on-off ratio.

[0065] The following specific embodiments further illustrate a vertical transistor and its fabrication method according to the present invention:

[0066] Example 1

[0067] Vertical transistors based on Zn-doped In2O3:

[0068] 1. Prepare a SiO2 / Si substrate. The SiO2 substrate should be 100 nm thick, and the Si substrate should be a p-type heavily doped silicon wafer with a doping concentration of 10%. 16 / cm 3 The thickness is 500μm.

[0069] 2. Transfer and pattern graphene. The specific steps are as follows: support graphene with polymethyl methacrylate (PMMA) to form a sandwich structure of PMMA / graphene / copper foil. Then, etch the graphene in ferric chloride (FeCl3) solution to remove the copper foil, obtaining PMMA / graphene. Transfer it to a SiO2 / Si substrate, remove PMMA, and then spin-coat photoresist, expose, develop, and etch with oxygen plasma to remove the photoresist, thus obtaining patterned graphene.

[0070] 3. Preparation of two-dimensional oxide layer: In / Zn alloy with a certain zinc doping ratio (0%-5%) of liquid metal is printed on graphene to obtain a single layer of metal-doped two-dimensional oxide with a thickness of 0.6nm-4nm.

[0071] 4. Fabrication of Source and Drain Electrodes: Source and drain electrodes were fabricated on graphene and two-dimensional oxide layers respectively using electron beam lithography and thermal evaporation. The specific steps were as follows: PMMA200K and PMMA950K were sequentially deposited on graphene and two-dimensional oxide layers using spin coating. Each layer was annealed at 180°C for 15 minutes. Electrode patterns were pre-fabricated using an electron beam, with electrode widths of 5μm, 10μm, and 20μm. The developing solution used was 75% isopropanol and 25% methyl isobutyl ketone (MIBK). After development, thermal evaporation was performed under vacuum at 10°C. -4 Under these conditions, 5 nm of titanium (Ti) and 50 nm of gold (Au) were deposited sequentially at a rate of 0.01 nm / s. After deposition, the devices were lifted off by immersing them in acetone for 90 minutes.

[0072] In this embodiment, a Zn-doped In2O3 two-dimensional oxide is used as the channel layer, and a graphene film is used as the active contact of the Zn-doped In2O3 two-dimensional oxide. The source electrode is prepared on the graphene film, and the drain electrode is prepared on the Zn-doped In2O3 two-dimensional oxide and SiO2, thereby obtaining a vertical transistor based on the Zn-doped In2O3 two-dimensional oxide. Figure 7 The graph shows a comparison of the transfer characteristic curves of vertical transistors based on In2O3 and Zn-doped In2O3, as shown in the figure. Figure 7 As shown, curve a is the transfer characteristic curve of the vertical transistor based on Zn-doped In2O3, while curve b is the transfer characteristic curve of the vertical transistor based on In2O3. It can be clearly seen that the vertical transistor based on Zn-doped In2O3 has a higher (about an order of magnitude) on-state current and on-state ratio compared with the vertical transistor based on In2O3.

[0073] Example 2

[0074] Vertical transistors based on In2O3 / ZnO heterostructures:

[0075] 1. Prepare a SiO2 / Si substrate. The SiO2 substrate should be 100 nm thick, and the Si substrate should be a p-type heavily doped silicon wafer with a doping concentration of 10%. 16 / cm 3 The thickness is 500μm.

[0076] 2. Transfer and pattern graphene. The specific steps are as follows: support graphene with polymethyl methacrylate (PMMA) to form a sandwich structure of PMMA / graphene / copper foil. Then, etch the graphene in ferric chloride (FeCl3) solution to remove the copper foil, obtaining PMMA / graphene. Transfer it to a SiO2 / Si substrate, remove PMMA, and then spin-coat photoresist, expose, develop, and etch with oxygen plasma to remove the photoresist, thus obtaining patterned graphene.

[0077] 3. Preparation of two-dimensional oxide layers: Liquid metals, namely elemental In and elemental Zn, were alternately printed on graphene to obtain a heterostructure of In2O3 / ZnO two-dimensional oxides.

[0078] 4. Fabrication of Source and Drain Electrodes: Source and drain electrodes were fabricated on graphene and two-dimensional oxide layers respectively using electron beam lithography and thermal evaporation. The specific steps were as follows: PMMA200K and PMMA950K were sequentially deposited on graphene and two-dimensional oxide layers using spin coating. Each layer was annealed at 180°C for 15 minutes. Electrode patterns were pre-fabricated using an electron beam, with electrode widths of 5μm, 10μm, and 20μm. The developing solution used was 75% isopropanol and 25% methyl isobutyl ketone (MIBK). After development, thermal evaporation was performed under vacuum at 10°C. -4 Under these conditions, 5 nm of titanium (Ti) and 50 nm of gold (Au) were deposited sequentially at a rate of 0.01 nm / s. After deposition, the devices were lifted off by immersing them in acetone for 90 minutes.

[0079] In this embodiment, a two-dimensional oxide with an In2O3 / ZnO heterostructure is used as the channel layer, and a graphene film is used as the active contact of the two-dimensional oxide with an In2O3 / ZnO heterostructure. The source electrode is prepared on the graphene film, and the drain electrode is prepared on the two-dimensional oxide with an In2O3 / ZnO heterostructure and SiO2, thereby obtaining a vertical transistor based on a two-dimensional oxide with an In2O3 / ZnO heterostructure. Figure 8 The graph shows a comparison of the transfer characteristic curves of vertical transistors based on ZnO and In2O3 / ZnO heterostructures, as shown below. Figure 8As shown, curve c is the transfer characteristic curve of the vertical transistor based on the In2O3 / ZnO heterostructure, while curve d is the transfer characteristic curve of the vertical transistor based on ZnO. It can be clearly seen that the vertical transistor based on the In2O3 / ZnO heterostructure has an order of magnitude higher on-state current and switching ratio compared with the vertical transistor based on ZnO.

[0080] In summary, the present invention provides a vertical transistor and its fabrication method, wherein the fabrication method includes the steps of: transferring a graphene film onto a substrate and patterning the graphene film on the substrate; wherein the substrate includes a silicon substrate gate electrode and a gate dielectric layer disposed on the silicon substrate gate; fabricating a two-dimensional oxide layer on the graphene film; and fabricating a metal electrode on the graphene, the two-dimensional oxide layer, and the substrate to obtain the vertical transistor; wherein the two-dimensional oxide layer includes a single-layer two-dimensional oxide or a multilayer two-dimensional oxide with a heterostructure, with different doping ratios. The vertical transistor of the present invention uses a two-dimensional oxide layer as the channel layer, the graphene film as the active contact of the two-dimensional oxide layer, a source electrode fabricated on the graphene film, and a drain electrode fabricated on the two-dimensional oxide layer and the gate dielectric layer to obtain the vertical transistor. By metal doping the two-dimensional oxide layer or forming a heterostructure two-dimensional oxide layer, the doping metal ratio can be controlled, and the stability of the two-dimensional oxide layer can be improved, thereby effectively controlling the channel carrier properties of the vertical transistor and achieving higher on-state current and on-off ratio.

[0081] It should be understood that the application of the present invention is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. A method for fabricating a vertical transistor, characterized in that, Including the following steps: A graphene film is transferred onto a substrate, and the graphene film is patterned on the substrate; wherein the substrate includes a silicon substrate gate electrode and a gate dielectric layer disposed on the silicon substrate gate electrode; A two-dimensional oxide layer is prepared on the graphene film; Metal electrodes are fabricated on the graphene film, the two-dimensional oxide layer, and the substrate to obtain the vertical transistor; The two-dimensional oxide layer includes single-layer two-dimensional oxides with different doping ratios or multi-layer two-dimensional oxides with heterostructures. The steps for preparing a two-dimensional oxide layer on the graphene film include: printing a two-dimensional oxide layer on the graphene film using liquid metal; adjusting the metal doping ratio of the two-dimensional oxide by adjusting the composition of the liquid metal or preparing a multilayer two-dimensional oxide with a heterogeneous structure by alternating printing liquid metals of different compositions.

2. The method for fabricating a vertical transistor according to claim 1, characterized in that, The step of transferring the graphene film onto a substrate and patterning the graphene film on the substrate includes: The graphene film is transferred onto the substrate, and photoresist is sequentially spin-coated, exposed, developed, and etched with oxygen plasma to remove the photoresist, thereby obtaining a patterned graphene film.

3. The method for fabricating a vertical transistor according to claim 1, characterized in that, The doping metal of the monolayer two-dimensional oxides with different doping ratios is one of Ga, Zn or Sn.

4. The method for fabricating a vertical transistor according to claim 1, characterized in that, The heterostructured multilayer two-dimensional oxide is an alternating stacked structure of two or more of In2O3, Ga2O3, and ZnO.

5. The method for fabricating a vertical transistor according to claim 1, characterized in that, The thickness of the single-layer two-dimensional oxide is 0.6-4 nanometers.

6. The method for fabricating a vertical transistor according to claim 1, characterized in that, The step of fabricating a metal electrode on the graphene film, the two-dimensional oxide layer, and the substrate to obtain the vertical transistor includes: Metal electrodes are fabricated on the graphene film, the two-dimensional oxide layer, and the substrate using electron beam lithography and thermal evaporation; wherein the metal electrodes comprise: The source electrode is disposed on the graphene film; The drain electrode is disposed on the two-dimensional oxide layer and the gate dielectric layer.

7. The method for fabricating a vertical transistor according to claim 6, characterized in that, The metal electrode materials are titanium (Ti) and gold (Au).

8. The method for fabricating a vertical transistor according to claim 1, characterized in that, The gate electrode of the silicon substrate is a heavily doped silicon wafer.

9. A vertical transistor, characterized in that, The vertical transistor is prepared by the method described in any one of claims 1-8, comprising: Silicon substrate gate electrode; A gate dielectric layer is disposed on the gate electrode of the silicon substrate; A graphene film is disposed on the gate dielectric layer; The source electrode is disposed on the graphene film; A two-dimensional oxide layer is disposed on the graphene film; A drain electrode is disposed on the two-dimensional oxide layer and the gate dielectric layer; The two-dimensional oxide layer includes single-layer two-dimensional oxides with different doping ratios or multi-layer two-dimensional oxides with heterostructures.

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