Semiconductor devices and their fabrication methods

Abstract

This disclosure provides a semiconductor device and a method for fabricating the same. The method includes: providing a semiconductor structure; wherein the semiconductor structure includes a substrate, the substrate includes a peripheral circuit region, a conductive structure is formed on the peripheral circuit region, and a dielectric layer covering the conductive structure; forming a contact hole penetrating the dielectric layer and extending into the peripheral circuit region; wherein the contact hole and the conductive structure are arranged side by side; performing a first cleaning on the contact hole using a first cleaning agent; wherein the pH value of the first cleaning agent is greater than or equal to 4 and less than 7; after the first cleaning, forming a protective layer covering the sidewalls of the contact hole; after forming the protective layer, filling the contact hole to form a conductive contact plug; wherein the conductive contact plug is electrically connected to the substrate.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for fabricating the same. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a common storage device characterized by high integration, fast read / write speeds, and low cost, making it widely used in various consumer electronics products such as computers, mobile phones, and set-top boxes. DRAM consists of a memory array area and a peripheral circuit area. The memory array area stores data, while the peripheral circuit area is electrically connected to it to control the storage and retrieval of data. As semiconductor structures become increasingly miniaturized and integrated, the spacing between conductive lines and contact plugs within the peripheral circuit area is continuously decreasing, thus increasing the risk of short circuits. Summary of the Invention

[0003] According to a first aspect of this disclosure, a method for fabricating a semiconductor device is provided, comprising:

[0004] A semiconductor structure is provided; wherein the semiconductor structure includes a substrate, the substrate includes a peripheral circuit region, a conductive structure is formed on the peripheral circuit region, and a dielectric layer covering the conductive structure;

[0005] A contact hole is formed that penetrates the dielectric layer and extends into the peripheral circuit area; wherein the contact hole is arranged side by side with the conductive structure;

[0006] The contact hole is first cleaned using a first cleaning agent; wherein the pH value of the first cleaning agent is greater than or equal to 4 and less than 7;

[0007] After the first cleaning, a protective layer is formed covering the sidewalls of the contact hole;

[0008] After the protective layer is formed, the contact hole is filled to form a conductive contact plug; wherein the conductive contact plug is electrically connected to the substrate.

[0009] In some embodiments, the first cleaning agent comprises hydrofluoric acid, sulfuric acid, hydrogen peroxide, and water, wherein the volume fraction of hydrofluoric acid is 0.02% to 0.04%, the volume fraction of sulfuric acid is 3% to 7%, the volume fraction of hydrogen peroxide is 10% to 15%, and the volume fraction of water is 77.96% to 86.98%.

[0010] In some embodiments, the protective layer forming the sidewalls of the contact hole includes:

[0011] A protective material layer is formed covering the sidewalls and bottom of the contact hole;

[0012] Remove the protective material layer covering the bottom of the contact hole to form a protective layer covering the sidewall of the contact hole.

[0013] In some embodiments, the preparation method further includes:

[0014] When removing the protective material layer covering the bottom of the contact hole, the substrate inside the contact hole is etched to flatten the substrate inside the contact hole.

[0015] In some embodiments, forming a protective material layer covering the sidewalls and bottom of the contact hole includes:

[0016] A protective material layer covering the sidewalls and bottom of the contact hole is formed using an atomic layer deposition process; wherein the thickness of the protective material layer covering the bottom of the contact hole is less than the thickness of the protective material layer covering the sidewalls of the contact hole.

[0017] In some embodiments, after forming the protective layer, the preparation method further includes:

[0018] The contact hole is then cleaned a second time.

[0019] In some embodiments, the second cleaning of the contact hole includes:

[0020] The contact hole is cleaned using a first cleaning agent; wherein the pH value of the first cleaning agent is greater than or equal to 4 and less than 7.

[0021] The contact hole is cleaned in a second step and a third step using a second cleaning agent; wherein the second cleaning agent includes hydrofluoric acid.

[0022] In some embodiments, the substrate comprises a silicon-based semiconductor;

[0023] The process of filling the contact hole to form a conductive contact plug includes:

[0024] A first metallic material is deposited at the bottom of the contact hole;

[0025] The substrate after the first metal material is deposited is subjected to heat treatment; wherein the first metal material and the substrate react to form a metal silicide layer.

[0026] In some embodiments, the method for filling the contact hole to form a conductive contact plug further includes:

[0027] A metal nitride layer is formed covering the protective layer and the metal silicide layer;

[0028] A second metal material is filled into the contact hole after the metal nitride layer is formed to form a metal layer.

[0029] In some embodiments, the protective layer is made of one or more of silicon nitride and silicon oxynitride.

[0030] According to a second aspect of this disclosure, a semiconductor device is provided, the semiconductor device comprising:

[0031] A substrate, the substrate including a peripheral circuit region, the peripheral circuit region having a conductive structure;

[0032] A dielectric layer that covers the peripheral circuit area of ​​the substrate and the conductive structure;

[0033] A conductive contact plug extends through the dielectric layer and into the substrate, wherein the conductive contact plug and the conductive structure are arranged side by side.

[0034] A protective layer covers the sidewalls of the conductive contact plug.

[0035] In some embodiments, the dielectric layer includes a first sub-dielectric layer and a second sub-dielectric layer stacked sequentially, wherein the first sub-dielectric layer is located on the side of the second sub-dielectric layer that is relatively far away from the substrate;

[0036] The conductive contact plug includes a first segment located within the first sub-dielectric layer and a second segment located within the second sub-dielectric layer, wherein the radial dimension of the first segment is greater than or equal to the radial dimension of the second segment.

[0037] In some embodiments, the protective layer is made of one or more of silicon nitride and silicon oxynitride.

[0038] In some embodiments, the conductive contact plug includes:

[0039] A metal layer that penetrates the dielectric layer and extends into the substrate;

[0040] A metal nitride layer covers the sidewalls and bottom of the metal layer;

[0041] A metal silicide layer covers the bottom of the metal nitride layer.

[0042] In some embodiments, the substrate further includes a memory array region, the memory array region including a plurality of active regions arranged in an array, the active regions including a source, a channel and a drain;

[0043] The semiconductor device further includes:

[0044] A word line extends along a first direction, the word line passes through a plurality of active regions arranged side by side along the first direction, and is coupled to the channel of the active regions, the first direction being parallel to the plane of the substrate;

[0045] Bit lines extend along a second direction, the bit lines are located on the substrate and contact the drains of a plurality of active regions arranged in parallel along the second direction, the second direction being parallel to the plane of the substrate and intersecting the first direction;

[0046] A capacitive contact plug is located on the substrate, and the capacitive contact plug is in contact with the source electrode of the active region;

[0047] A first isolation layer is located between the bit line and the substrate;

[0048] The second isolation layer is located between the bit line and the capacitor contact plug.

[0049] In the semiconductor device fabrication method provided in this disclosure, a protective layer is formed on the sidewall of the contact hole before depositing conductive material in the contact hole. Therefore, when the contact hole position shifts and the sidewall of the contact hole exposes the conductive structure, the protective layer covers the sidewall of the contact hole, which can isolate the conductive structure from the conductive contact plug subsequently formed in the contact hole, greatly reducing the probability of short circuit between the conductive structure and the conductive contact plug, and helping to improve the performance and yield of the device.

[0050] Furthermore, in this embodiment, when the sidewalls of the contact hole are cleaned with a first cleaning agent (i.e., a weak acid cleaning agent) with a pH value greater than or equal to 4 and less than 7, very little side-cutting occurs on the sidewalls of the contact hole. Therefore, "boob" formation is virtually eliminated within the contact hole, resulting in a better contact hole profile and relatively straight sidewalls. After the protective layer is formed, the sidewalls of the protective layer are also relatively straight, which facilitates the filling of conductive material within the contact hole, reduces the probability of air gaps appearing within the conductive contact plug, and improves the morphology of the conductive contact plug. This, in turn, reduces the Rc (Resistor Capacitor) delay of the device, making the current conduction of the conductive contact plug more stable. Moreover, the straight conductive contact plug also reduces the probability of short circuits between the conductive contact plug and the conductive structure, which is beneficial for improving the performance of the device.

[0051] Furthermore, since contact holes generally do not have a "belly" and their sidewalls are relatively straight, the critical dimension (CD) of the contact hole can be increased. This increases the overlay window for the photolithography process, the window for the etching process, and reduces the difficulty of forming the contact hole. Attached Figure Description

[0052] Figures 1a to 1dThis is a schematic flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of the present disclosure.

[0053] Figure 2 A partial topographic view of a semiconductor device provided in an embodiment of this disclosure;

[0054] Figure 3 This is a partial structural schematic diagram of a semiconductor device provided in an embodiment of the present disclosure;

[0055] Figure 4 A partial topographic view of another semiconductor device provided in an embodiment of this disclosure;

[0056] Figure 5 This is a schematic flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of the present disclosure.

[0057] Figures 6a to 6j This is a schematic diagram of the structure of another semiconductor device provided in the present disclosure during the fabrication process;

[0058] Figure 7 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this disclosure. Detailed Implementation

[0059] The technical solution of this disclosure will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0060] In the description of this disclosure, it should be understood that the terms “length,” “width,” “depth,” “upper,” “lower,” “outer,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0061] In DRAM, a 1T1C structure, typically consisting of a transistor and a capacitor, serves as the memory cell. Voltage signals on the word lines control the transistor to turn on or off, thereby reading data from the capacitor via the bit lines or writing data to the capacitor for storage. Peripheral circuitry can be coupled to the bit lines and word lines to control the memory cell. For example, the peripheral circuitry may include write circuitry, read circuitry, control logic, input / output circuitry, row address decoders, column address decoders, etc.

[0062] Figures 1a to 1d This is a schematic diagram of the structure of a semiconductor device during its fabrication process, provided as an embodiment of the present disclosure. Figure 1a This is a top view schematic diagram of the semiconductor device during its fabrication process. Figures 1b to 1d This is a schematic cross-sectional view of the semiconductor device. (For example...) Figure 1a and Figure 1b As shown, a semiconductor structure is provided, which includes a substrate 100, the substrate 100 including a memory array region and a peripheral circuit region.

[0063] In some embodiments, the substrate 100 of the storage array region includes a shallow trench isolation structure 120 (STI) and a plurality of active regions 110 (AA), the plurality of active regions 110 being arranged in an array, and the shallow trench isolation structure 120 being located between adjacent active regions 110 to isolate adjacent active regions 110.

[0064] For example, each active region 110 may include one or two transistors. In this embodiment, each active region 110 includes two transistors arranged side by side, with their drains in contact and connected to the same bit line 120. The source of the first transistor is connected to a capacitor, and the source of the second transistor is connected to another capacitor.

[0065] like Figure 1a As shown, the semiconductor device also includes a word line 130 that passes through the active region 110, extends along the X direction, and is coupled to the channel of a plurality of transistors arranged side-by-side along the X direction. A bit line 120 is located on the substrate 100, extends along the Y direction, and contacts the drain of a plurality of transistors arranged side-by-side along the Y direction.

[0066] The semiconductor device also includes multiple capacitive contact plugs, the bottom of which contacts the source of the transistor, and the top of which is used to mount a capacitor.

[0067] In some embodiments, different concentrations and types of doped ions may be implanted into the substrate 100 of the peripheral circuit region as needed to form transistors, or well regions, deep well regions, etc. of other devices, thereby forming peripheral devices.

[0068] The substrate 100 of the peripheral circuit may also include a shallow trench isolation structure 120 to isolate adjacent devices.

[0069] See Figure 1b A conductive structure 200 is formed on the peripheral circuit region. For example, the conductive structure forms part of a gate structure (PG), which can be used to form transistors in the peripheral circuit, as well as various devices formed from transistors (e.g., inverters). The gate structure also includes a gate dielectric layer disposed between the conductive structure 200 and the substrate 100 to isolate the conductive structure 200 and the substrate 100.

[0070] In some embodiments, the substrate 100 of the peripheral circuit area further includes a shallow trench isolation structure 120 to isolate adjacent devices.

[0071] See also Figure 1b A dielectric layer 300 is formed that covers the peripheral circuit area and the conductive structure 200, and a contact hole 400 is formed that penetrates the dielectric layer 300 and extends to the peripheral circuit area. The contact hole 400 and the conductive structure 200 are arranged side by side.

[0072] For example, the dielectric layer 300 includes a first sub-dielectric layer 310 and a second sub-dielectric layer 320 stacked sequentially, wherein the first sub-dielectric layer 310 is located on the side of the second sub-dielectric layer 320 that is relatively away from the substrate 100. For example, the first sub-dielectric layer 310 is made of silicon nitride, and the second sub-dielectric layer 320 is made of silicon oxide.

[0073] Figure 1b The storage array area in the middle is Figure 1a The diagram shows a cross-sectional view of the storage array area along line AA. Figure 1b As shown, the capacitor contact plug 150 is covered with an insulating layer 160 formed in the previous process. This insulating layer 160 affects the contact between the capacitor contact plug 150 and the capacitor, therefore, the insulating layer 160 needs to be removed.

[0074] For example, the insulating layer 160 is made of silicon nitride, and the dielectric layer 300 is made of both silicon nitride and silicon oxide. Therefore, when the insulating layer 160 is removed, the dielectric layer 300 is also etched.

[0075] See Figure 1c When the insulating layer 160 covering the capacitor contact plug 150 is removed, the contact hole 400 in the peripheral circuit area is etched a second time, resulting in an increase in the diameter of the contact hole 400. This increase in diameter is difficult to control within a certain range and can easily lead to a reduction in the distance between the contact hole 400 and the conductive structure 200.

[0076] See Figure 1d The contact hole 400 is filled to form a conductive contact plug (Periphery Contact, PC) 500.

[0077] As semiconductor device dimensions continue to shrink, the spacing between conductive structures and contact holes is constantly decreasing, leading to increasingly stringent requirements for overlay accuracy. During photolithography, asymmetrical mask structures or light source asymmetry can affect the positional accuracy of contact holes, easily causing them to shift. This results in the sidewalls of the contact holes exposing adjacent conductive structures. When conductive material is filled into the contact holes to form conductive plugs, these plugs can short-circuit with the conductive structures, causing device failure and reducing production yield. Figure 2 This is a partial topographic diagram of a semiconductor device provided in an embodiment of the present disclosure, such as... Figure 2As shown, at the location indicated by the black arrow, the conductive structure 200 and the conductive contact plug 500 come into contact, causing a short circuit between the conductive structure 200 and the conductive contact plug 500.

[0078] Figure 3 This is a partial structural schematic diagram of a semiconductor device provided in an embodiment of the present disclosure. Figure 4 This is a partial topographic diagram of another semiconductor structure provided in an embodiment of this disclosure. For example... Figure 3 and Figure 4 As shown, in some embodiments, after dry etching to form the contact hole 400, when the contact hole 400 is wet-washed, the cleaning agent will consume the silicon oxide layer (second sub-dielectric layer 320) on the sidewall of the contact hole 400. The sidewall of the contact hole 400 is scooped out by about 5nm to 7nm, forming a "belly" with a large radial dimension. Subsequently, after the conductive material is deposited, an obvious air gap 540 is formed at the "belly" position, which is not conducive to the filling of the conductive material and the stability of the current, resulting in a decrease in memory performance.

[0079] Therefore, this disclosure provides a method for fabricating a semiconductor device. Figure 5 This is a schematic flowchart of a method for fabricating a semiconductor device according to an embodiment of the present disclosure, as shown below. Figure 5 As shown, the preparation method includes:

[0080] S100: Provides a semiconductor structure; wherein the semiconductor structure includes a substrate, the substrate includes a peripheral circuit region, a conductive structure is formed on the peripheral circuit region, and a dielectric layer covering the conductive structure;

[0081] S200: A contact hole is formed that penetrates the dielectric layer and extends into the substrate of the peripheral circuit area; wherein the contact hole is arranged side by side with the conductive structure;

[0082] S300: The contact hole is cleaned for the first time using a first cleaning agent; wherein the pH value of the first cleaning agent is greater than or equal to 4 and less than 7;

[0083] S400: After the first cleaning, a protective layer is formed covering the sidewalls of the contact hole;

[0084] S500: After forming the protective layer, the contact holes are filled to form conductive contact plugs; wherein the conductive contact plugs are electrically connected to the substrate.

[0085] Figures 6a to 6j This is a schematic diagram illustrating the fabrication process of another semiconductor device provided in this disclosure. The following is in conjunction with… Figures 6a to 6j This disclosure introduces a method for fabricating a semiconductor device according to embodiments.

[0086] See Figure 6aStep S100 is performed to provide a semiconductor structure, which includes a substrate, a memory array region and a peripheral circuit region, a conductive structure 200 formed on the peripheral circuit region, and a dielectric layer 300 covering the conductive structure 200.

[0087] For example, the substrate 100 may be made of silicon, germanium, silicon-germanium semiconductor or silicon carbide, or silicon-on-insulator (SOI) or germanium-on-insulator (GOI), or other materials such as gallium arsenide or other group III or V compounds.

[0088] In some embodiments, doped ions may be implanted into the substrate 100 of the peripheral circuit area as needed to form the source and drain of a transistor, or to form the well region, deep well region, etc. of other devices.

[0089] For example, the substrate 100 of the peripheral circuit area may also include a shallow trench isolation structure 120 for electrically isolating adjacent devices.

[0090] like Figure 6a As shown, a gate dielectric layer is also provided between the conductive structure 200 in the peripheral circuit area and the substrate 100, and the conductive structure 200 and the gate dielectric layer constitute a gate structure.

[0091] For example, the conductive structure 200 may include a polysilicon layer 210, a metal nitride layer 220, and a metal layer 230 stacked sequentially from bottom to top. The polysilicon layer 210 may include doped polysilicon, the metal nitride layer 220 may be made of materials including, but not limited to, titanium nitride, tungsten nitride, and tantalum nitride, and the metal layer 230 may be made of materials including, but not limited to, tungsten, copper, aluminum, and cobalt.

[0092] It should be understood that in other embodiments, the conductive structure 200 may also be a conductive structure connected to the P-type doped region or N-type doped region of the PN junction.

[0093] In some embodiments, the semiconductor structure further includes an isolation structure 600 covering the sidewalls of the conductive structure 200. For example, the isolation structure 600 includes a first nitride layer 610, an oxide layer 620, and a second nitride layer 630 sequentially stacked on the sidewalls of the conductive structure 200 to form a non-non-polar structure. For example, the first nitride layer is made of silicon nitride, the oxide layer is made of silicon oxide, and the second nitride layer is made of silicon nitride.

[0094] For example, the first nitride layer 610 may also cover the top of the conductive structure 200.

[0095] For example, the second nitride layer 630 may also cover the surface of the substrate 100 of the peripheral circuit area.

[0096] In some embodiments, the dielectric layer 300 includes a first sub-dielectric layer 310 and a second sub-dielectric layer 320 stacked sequentially, wherein the first sub-dielectric layer 310 is located on the side of the second sub-dielectric layer 320 that is relatively far from the substrate 100. For example... Figure 6a As shown, the second sub-dielectric layer 320 covers the conductive structure 200, that is, the top of the second sub-dielectric layer 320 is higher than the top of the conductive structure 200.

[0097] For example, the second sub-dielectric layer 320 also covers the isolation structure 600, with the top of the second sub-dielectric layer 320 higher than the top of the isolation structure 600.

[0098] For example, the first sub-dielectric layer 310 is made of silicon nitride, and the second sub-dielectric layer 320 is made of silicon oxide.

[0099] See Figures 6a to 6e Step S200 is executed to form a contact hole 400 that penetrates the dielectric layer 300 and extends into the substrate 100 of the peripheral circuit area.

[0100] For example, a dry etching process can be used to form the contact hole 400.

[0101] In some embodiments, there are multiple contact holes 400, including a first contact hole 410 and a second contact hole 420, which are respectively disposed on both sides of the conductive structure 200. When the apertures of the first contact hole 400 and the second contact hole 420 are small, due to limitations in the photolithography process, the first contact hole 400 and the second contact hole 420 cannot be formed in one exposure. Therefore, the first contact hole 400 and the second contact hole 420 can be formed separately.

[0102] like Figure 6a As shown, a first mask layer 710 covering the dielectric layer 300 is formed, a first photoresist layer 810 covering the first mask layer 710 is formed, and the first photoresist layer 810 is exposed and developed to form a first via 811 in the first photoresist layer 810.

[0103] like Figure 6b As shown, the first mask layer 710 is etched through the first via 811, and the dielectric layer 300 is etched based on the first mask layer 710 to form a first contact hole 410 that penetrates the dielectric layer 300 and extends into the substrate 100 of the peripheral circuit area. After the first contact hole 410 is formed, the first mask layer 710 is removed.

[0104] In some embodiments, the first mask layer 710 includes a first spin-coated hard mask layer 711 and a first silicon oxynitride layer 712 stacked sequentially, wherein the first spin-coated hard mask layer 711 is located between the dielectric layer 300 and the first silicon oxynitride layer 712.

[0105] like Figure 6c As shown, a second mask layer 720 is formed to cover the dielectric layer 300 and fill the first contact hole 410, a second photoresist layer 820 is formed to cover the second mask layer 720, and the second photoresist layer 820 is exposed and developed to form a second through hole 821 in the second photoresist layer 820.

[0106] like Figure 6d As shown, the second mask layer 720 is etched through the second via 821, and the dielectric layer 300 is etched based on the second mask layer 720 to form a second contact hole 420 that penetrates the dielectric layer 300 and extends into the substrate 100 of the peripheral circuit area. After forming the second contact hole 420, the second mask layer 720 is removed.

[0107] In some embodiments, the second mask layer 720 includes a second spin-coated hard mask layer 721 and a second silicon oxynitride layer 722 stacked sequentially, wherein the second spin-coated hard mask layer 721 is located between the dielectric layer 300 and the second silicon oxynitride layer 722.

[0108] In this embodiment, the first contact hole 410 is formed first through a set of photolithography and etching processes, and then the second contact hole 420 is formed through another set of photolithography and etching processes. Compared with forming the first contact hole 410 and the second contact hole 420 simultaneously, the method of forming the first contact hole 410 and the second contact hole 420 separately in this embodiment results in higher dimensional and positional accuracy of the contact hole 400.

[0109] In other embodiments, after forming a mask layer covering the dielectric layer and a photoresist layer covering the mask layer, a first mask is used to expose the photoresist layer for the first via area, and a second mask is used to expose the photoresist layer for the area to form the second via area. After development, the first via 811 and the second via 821 are formed in the photoresist layer. Then, the mask layer is etched based on the first via 811 and the second via 821, and the dielectric layer 300 is etched based on the mask layer to simultaneously form the first contact hole 410 and the second contact hole 420 in the dielectric layer 300.

[0110] After the contact hole 400 is formed, step S300 is performed to clean the contact hole 400 for the first time.

[0111] It should be understood that dry etching is typically used to form contact holes 400 with high aspect ratios. During dry etching, a polymer film layer is formed on the sidewalls of the contact hole 400 to reduce lateral etching and enhance the directionality of etching, thereby achieving good control over the aperture (i.e., critical dimension) of the contact hole 400. In addition, particle contamination can also form within the contact hole 400 during dry etching.

[0112] In this embodiment, the contact hole 400 is cleaned for the first time, mainly to remove the polymer and particles remaining after dry etching, forming a relatively smooth surface, which is conducive to the deposition of a protective layer in subsequent processes.

[0113] In some embodiments, the contact hole 400 is first cleaned using a first cleaning agent. The pH value of the first cleaning agent is typically greater than or equal to 4 and less than 7, that is, the first cleaning agent is a weak acid cleaning agent. Through the reaction of the weak acid with the polymer and particles, the polymer on the sidewalls and the particles inside the contact hole 400 are removed.

[0114] In some embodiments, the first cleaning agent comprises hydrofluoric acid (HF), sulfuric acid (H2SO4), hydrogen peroxide (H2O2), and water (H2O), wherein the volume fraction of hydrofluoric acid is 0.02% to 0.04%, the volume fraction of sulfuric acid is 3% to 7%, the volume fraction of hydrogen peroxide is 10% to 15%, and the volume fraction of water is 77.96% to 86.98%.

[0115] For example, the volume fractions of hydrofluoric acid (HF), sulfuric acid (H2SO4), hydrogen peroxide (H2O2), and water (H2O) in the first cleaning agent may be 0.03%, 5%, 12%, and 82.97%, respectively.

[0116] In some embodiments, the initial cleaning time for the contact hole using the first cleaning agent is 50 to 70 seconds, for example, 60 seconds. Sulfuric acid and hydrogen peroxide can react with the polymer, degrading the polymer and thereby removing the polymer from the sidewalls of the contact hole 400.

[0117] Because it contains 0.03% (300ppm) HF, a chemical reaction can occur: 6HF + SiO2 → H2SiF6 + 2H2O. Since the content of HF is very small, the consumption of oxides on the sidewall is minimal. During the cleaning process, HF can remove the tiny protrusions on the sidewall of the contact hole 400, reduce the roughness of the sidewall, make the sidewall smooth, which is conducive to the deposition of a protective layer, and the morphology and structure of the deposited protective layer are better.

[0118] See Figure 6e and Figure 6f Step S400 is executed to form a protective layer 900 covering the sidewall of the contact hole 400.

[0119] like Figure 6e As shown, a protective material layer 910 is formed covering the sidewalls and bottom of the contact hole 400. For example, the material of the protective material layer 910 may include, but is not limited to, insulating materials such as silicon nitride and silicon oxynitride.

[0120] like Figure 6fAs shown, the protective material layer covering the bottom of the contact hole 400 is removed to form a protective layer 900 covering the sidewalls of the contact hole 400. In this step, after removing the protective material layer at the bottom of the contact hole 400, the substrate 100 is exposed so that the conductive contact plug subsequently formed can be electrically connected to the substrate 100.

[0121] In some embodiments, atomic layer deposition (ALD) may be used to form a protective material layer 910 covering the sidewalls and bottom of the contact hole 400.

[0122] Taking silicon nitride deposition as an example, the semiconductor structure is placed on a boat inside a heated furnace tube. The temperature is controlled between 580°C and 720°C (e.g., 600°C), and the heating time is controlled between 110s and 130s (e.g., 120s). Reactive gases (e.g., silane, silane dichloride, silicon tetrachloride, ammonia, etc.) are introduced into the furnace tube. Si and N single-atom films are deposited layer by layer on the sidewalls of the contact hole 400 to form a silicon nitride protective material layer. The protective material layer obtained by atomic layer deposition is uniform and dense, has excellent coverage, and the deposition thickness is controllable.

[0123] For example, the thickness of the protective layer 900 is 2nm to 5nm. The protective layer 900 on the sidewall of the contact hole 400 is deposited uniformly and densely. The film thickness is moderate, and the filling of the contact hole 400 is minimal, resulting in a good deposition effect of the protective layer 900.

[0124] In some embodiments, when forming a protective material layer covering the sidewalls and bottom of the contact hole 400 using an atomic layer deposition process, the direction of the deposited ions can be controlled to reduce the accumulation of ions at the bottom of the contact hole 400. This results in the thickness of the protective material layer covering the bottom of the contact hole 400 being less than the thickness of the protective material layer covering the sidewalls of the contact hole 400, making it easier to remove the bottom protective material layer and reducing the probability of an open circuit between the conductive contact plug and the substrate 100.

[0125] In some embodiments, a dry etching process may be used to remove the protective material layer at the bottom of the contact hole 400.

[0126] For example, it can be removed using a dry etching process. Figure 1b When the insulating layer 160 on top of the capacitor contact plug 150 is etched, the protective material layer at the bottom of the contact hole 400 is removed. This reduces the number of process steps and shortens the process cycle.

[0127] In some embodiments, when removing the protective material layer covering the bottom of the contact hole 400, the substrate 100 inside the contact hole 400 may also be etched to flatten the substrate 100 inside the contact hole 400.

[0128] like Figure 6g As shown, when the surface of the substrate 100 within the contact hole 400 is relatively rough, the protective material layer 910 can be deposited in the tiny depressions on the rough surface of the substrate 100. In some embodiments, under the same etching conditions, both the protective material layer 910 and the substrate 100 can be etched. Therefore, when removing the protective material layer 910 at the depressions, the tiny protrusions of the substrate 100 can be etched away, resulting in better flatness and a smoother surface of the substrate 100 within the contact hole 400 after etching. Consequently, the contact surface between the subsequently formed conductive contact plug and the substrate 100 is smoother, and the contact resistance is lower.

[0129] In this embodiment, the etching of the protective material layer at the bottom of the contact hole and the formation of the conductive contact plug work together. When removing the protective material layer at the bottom of the contact hole, the substrate inside the contact hole is flattened so that the bottom of the formed conductive contact plug makes good contact with the substrate.

[0130] In some embodiments, before the protective material layer 910 is formed, a first bias power is used to remove the insulating layer 160 on top of the capacitor contact plug 150 using a dry etching process. After the protective material layer 910 is formed, a second bias power is used when removing the insulating layer 160 on top of the capacitor contact plug 150 and the protective material layer 910 at the bottom of the contact hole 400. The second bias power is less than the first bias power to reduce the directionality of the plasma and reduce the bombardment effect of the plasma on the protective material layer 910 at the bottom of the contact hole 400, thereby making the etching morphology at the bottom of the contact hole 400 smoother, that is, the surface of the substrate 100 inside the contact hole 400 smoother, which is conducive to the formation of conductive material.

[0131] In some embodiments, taking silicon nitride as an example as the protective material layer, CHF3 and He can be used as etching gases, the second bias power is 75V, and the etching time is controlled between 9s and 11s (e.g., 10s). In this way, more atoms are dissociated, the concentration of free radicals is better, the silicon nitride at the bottom of the contact hole 400 can be etched away, and a relatively flat bottom morphology can be obtained, while the silicon nitride on the sidewall of the contact hole 400 maintains a good morphology.

[0132] In the semiconductor device fabrication method provided in this disclosure, a protective layer is formed on the sidewall of the contact hole before depositing conductive material in the contact hole. Therefore, when the contact hole position shifts and the sidewall of the contact hole exposes the conductive structure, the protective layer covers the sidewall of the contact hole, which can isolate the conductive structure from the conductive contact plug subsequently formed in the contact hole, greatly reducing the probability of short circuit between the conductive structure and the conductive contact plug, and helping to improve the performance and yield of the device.

[0133] Furthermore, in this embodiment, when the sidewalls of the contact hole are cleaned with a first cleaning agent (i.e., a weak acid cleaning agent) with a pH value greater than or equal to 4 and less than 7, the sidewalls of the contact hole are minimally eroded, or even nonexistent. Therefore, "boob" formation is virtually eliminated within the contact hole, resulting in a better morphology and straighter sidewalls. The relatively straight sidewalls of the contact hole, after the protective layer is formed, also facilitate the filling of conductive material within the contact hole, reducing the probability of air gaps within the conductive contact plug. This leads to a better morphology of the conductive contact plug, thereby reducing the Rc delay of the device and making the current conduction of the conductive contact plug more stable. Moreover, the straight conductive contact plug also reduces the probability of short circuits between the conductive contact plug and the conductive structure, thus improving device performance.

[0134] Furthermore, since contact holes generally do not have a "belly" and their sidewalls are relatively straight, the critical dimension (CD) of the contact hole can be increased. This increases the overlay window for the photolithography process, the window for the etching process, and reduces the difficulty of forming the contact hole.

[0135] In some implementations, after removing the protective material layer at the bottom of the contact hole 400 to form the protective layer 900, the preparation method further includes a second cleaning of the contact hole 400. That is, cleaning the sidewalls of the protective layer 900 and the bottom of the contact hole 400.

[0136] For example, the second cleaning of contact hole 400 includes:

[0137] The first cleaning agent is used to clean the contact hole 400 as the first step;

[0138] The second cleaning agent was used to perform the second and third cleaning steps on the contact hole 400.

[0139] As mentioned above, the protective material layer at the bottom of the contact hole 400 was removed using a dry etching process, leaving polymer and particles on the sidewalls of the protective layer 900. Therefore, a first cleaning agent (weak acid cleaning agent) was first used to remove the polymer and particles from the sidewalls of the protective layer 900.

[0140] Next, the contact hole 400 is cleaned in a second step using a second cleaning agent, which includes diluted hydrofluoric acid (DHF), and the concentration of hydrofluoric acid in the second cleaning agent is greater than the concentration of hydrofluoric acid in the first cleaning agent. For example, DHF can be obtained by mixing a 49% hydrofluoric acid solution with deionized water at a volume ratio of 1:2 to 1:500.

[0141] Here, the second step of cleaning the contact hole 400 can be performed using the CLN procedure in the Certas device. For example, the cleaning time for the second step is 25 to 35 seconds, such as 30 seconds.

[0142] Finally, the contact hole 400 is cleaned in the third step using a second cleaning agent for 15 to 25 seconds, for example, 20 seconds.

[0143] In this embodiment, when the second cleaning agent is used to perform the second and third cleaning steps on the contact hole 400, the main reaction that occurs is: 6HF + SiO2 → H2SiF6 + 2H2O, which removes the residual silicon oxide in the contact hole 400, so that the conductive contact plug formed subsequently has good contact with the substrate 100, thereby having good current conduction capability.

[0144] See Figures 6h to 6j The contact hole 400 is filled to form a conductive contact plug 500, wherein the conductive contact plug 500 is electrically connected to the substrate 100. In some embodiments, the conductive contact plug 500 includes a metal silicide layer 510, a metal nitride layer 520, and a metal layer 530.

[0145] like Figure 6j As shown, a metal silicide layer 510 is formed at the bottom of the contact hole 400, and the metal silicide layer 510 is electrically connected to the substrate 100. In some embodiments, the metal silicide layer 510 can be deposited directly at the bottom of the contact hole 400.

[0146] In other embodiments, the substrate 100 includes a silicon-based semiconductor, and a first metal material can be deposited at the bottom of the contact hole 400. The semiconductor structure after the first metal material is deposited is heat-treated so that the first metal material and the silicon-based semiconductor substrate 100 react to generate a metal silicide layer 510.

[0147] For example, cobalt (Co) can be deposited at the bottom of the contact hole 400. Heating the semiconductor structure causes a chemical reaction at the bottom of the contact hole 400: Co + 2Si → CoSi2. The metal silicide layer 510 (e.g., CoSi2) can reduce the Rc delay of the device.

[0148] In some embodiments, the top of the metal silicide layer 510 is below the surface of the substrate 100.

[0149] In some embodiments, the material of the metal silicide layer 510 includes cobalt silicide, titanium silicide, molybdenum silicide, tungsten silicide, etc.

[0150] like Figure 6i As shown, a metal nitride layer 520 is formed covering the protective layer 900 and the metal silicide layer 510. For example, the material of the metal nitride layer 520 may include, but is not limited to, titanium nitride, tungsten nitride, tantalum nitride, etc.

[0151] In some embodiments, the metal nitride forming the metal nitride layer 520 also covers the surface of the dielectric layer.

[0152] like Figure 6j As shown, a second metal material is filled into the contact hole 400 after the metal silicide layer 510 and the metal nitride layer 520 are formed to form a metal layer 530. For example, the material of the metal layer 530 includes, but is not limited to, tungsten, aluminum, copper, titanium, cobalt, molybdenum, etc.

[0153] In some embodiments, the second metallic material further covers the metal nitride on the surface of the substrate 100.

[0154] In some embodiments, after depositing the second metal material, the metal nitride and the second metal material on the surface of the substrate 100 are removed to form a metal nitride layer 520 and a metal layer 530 located within the contact hole 400.

[0155] In the semiconductor device fabrication method provided in this disclosure, a protective layer is formed on the sidewall of the contact hole before depositing conductive material in the contact hole. Therefore, when the contact hole position shifts and the sidewall of the contact hole exposes the conductive structure, the protective layer covers the sidewall of the contact hole, which can isolate the conductive structure from the conductive contact plug subsequently formed in the contact hole, greatly reducing the probability of short circuit between the conductive structure and the conductive contact plug, and helping to improve the performance and yield of the device.

[0156] Furthermore, in this embodiment, when the sidewalls of the contact hole are cleaned with a first cleaning agent (i.e., a weak acid cleaning agent) with a pH value greater than or equal to 4 and less than 7, very little side-cutting occurs on the sidewalls of the contact hole. Therefore, "boob" formation is virtually eliminated within the contact hole, resulting in a better contact hole profile and relatively straight sidewalls. After the protective layer is formed, the sidewalls of the protective layer are also relatively straight, which facilitates the filling of conductive material within the contact hole, reduces the probability of air gaps appearing within the conductive contact plug, and improves the morphology of the conductive contact plug. This, in turn, reduces the Rc (Resistor Capacitor) delay of the device, making the current conduction of the conductive contact plug more stable. Moreover, the straight conductive contact plug also reduces the probability of short circuits between the conductive contact plug and the conductive structure, which is beneficial for improving the performance of the device.

[0157] This disclosure also provides a semiconductor structure. Figure 7 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this disclosure, such as... Figure 7 As shown, the semiconductor device includes:

[0158] The substrate 100 includes a peripheral circuit region, on which a conductive structure 200 is provided;

[0159] The dielectric layer 300 covers the peripheral circuit area and conductive structure 200 of the substrate 100;

[0160] The conductive contact plug 500 penetrates the dielectric layer 300 and extends into the substrate 100 of the peripheral circuit area. The conductive contact plug 500 and the conductive structure 200 are arranged side by side.

[0161] The protective layer 900 covers the sidewall of the conductive contact plug 500.

[0162] In this embodiment, a protective layer 900 is provided on the sidewall of the conductive contact plug 500, which can isolate the conductive contact plug 500 and the conductive structure 200, greatly reducing the probability of short circuit between the conductive contact plug 500 and the conductive structure 200, and helping to improve the performance and yield of the device.

[0163] In some implementations, the dielectric layer 300 includes a first sub-dielectric layer 310 and a second sub-dielectric layer 320, the first sub-dielectric layer 310 being located on the side of the second sub-dielectric layer 320 that is relatively far from the substrate 100, and the conductive contact plug including a first segment located in the first sub-dielectric layer 310 and a second segment located in the second sub-dielectric layer 320, wherein the radial dimension of the first segment is greater than or equal to the radial dimension of the second segment.

[0164] In other words, along the direction from top to bottom, the radial dimension of the conductive contact plug 500 penetrating the dielectric layer is substantially equal or gradually decreases. The conductive contact plug 500 has a good morphology, thereby enabling it to have good current conduction capability.

[0165] For example, the first sub-dielectric layer 310 is made of silicon nitride, and the second sub-dielectric layer 320 is made of silicon oxide.

[0166] In some embodiments, the thickness of the protective layer 900 ranges from 2 nm to 5 nm. If the protective layer 900 is too thin, the isolation effect on the conductive structure 200 and the conductive contact plug 500 will be weakened; if it is too thick, it will occupy more space, causing the radial dimension of the conductive contact plug 500 to decrease. In this embodiment, the thickness of the protective layer 900 is 2 nm to 5 nm, which is more suitable and can achieve a better isolation effect.

[0167] In some embodiments, the protective layer 900 is made of one or more of silicon nitride and silicon oxynitride.

[0168] In some embodiments, the conductive contact plug 500 includes a metal layer 530, a metal nitride layer 520, and a metal silicide layer 510, wherein the metal layer 530 penetrates the dielectric layer 300 and extends into the substrate 100, the metal nitride layer 520 covers the sidewalls and bottom of the metal layer 530, and the metal silicide layer 510 covers the bottom of the metal nitride layer 520.

[0169] The semiconductor device provided in this embodiment is fabricated using the above-described semiconductor device fabrication method. Therefore, when the conductive contact plug 500 is formed by directly depositing a metal silicide layer 510, the bottom of the conductive contact plug 500 (i.e., the contact surface between the conductive contact plug 500 and the substrate 100) is flat, and the conductive contact plug 500 has good current conduction performance. When the metal silicide layer 510 is formed by depositing a first metal material and heat treatment, the bottom of the metal nitride layer 520 (the contact surface between the metal nitride layer 520 and the metal silicide layer 510) is flat, and the conductive contact plug 500 has good current conduction performance.

[0170] In some embodiments, such as Figure 1a and Figure 1b As shown, the substrate 100 also includes a memory array region, which includes a plurality of active regions 110 arranged in an array, and the active regions 110 include a source, a channel and a drain.

[0171] The semiconductor device also includes:

[0172] Word line 130 extends along a first direction, passes through a plurality of active regions 110 arranged in parallel along the first direction, and is coupled to the channel of the active regions 110. The first direction is parallel to the plane where the substrate 100 is located.

[0173] Bit line 120 extends along a second direction, is located on substrate 100, and contacts the drain of a plurality of active regions 110 arranged in parallel along the second direction. The second direction is parallel to the plane of substrate 100 and intersects with the first direction.

[0174] Capacitor contact plug 150 is located on substrate 100 and is in contact with the source of active region 110.

[0175] The first isolation layer 170 is located between the bit line 120 and the substrate 100;

[0176] The second isolation layer 180 is located between bit line 120 and capacitor contact plug 150.

[0177] Furthermore, the semiconductor device also includes a capacitor (not shown) located on the side of the capacitor contact plug 150 that is relatively away from the substrate 100, that is, on top of the capacitor contact plug 150.

[0178] For example, the first direction and the second direction are perpendicular, with the first direction being the X direction and the second direction being the Y direction. In other embodiments, the first direction and the second direction may intersect but not be perpendicular.

[0179] The above embodiments are merely illustrative of the principles and effects of this disclosure and are not intended to limit this disclosure. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this disclosure. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this disclosure should still be covered by the claims of this disclosure.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: A semiconductor structure is provided; wherein the semiconductor structure includes a substrate, the substrate includes a peripheral circuit region, a conductive structure is formed on the peripheral circuit region, and a dielectric layer covering the conductive structure; A contact hole is formed that penetrates the dielectric layer and extends into the peripheral circuit area; wherein the contact hole is arranged side by side with the conductive structure; The contact hole is first cleaned using a first cleaning agent; wherein the pH value of the first cleaning agent is greater than or equal to 4 and less than 7; After the first cleaning, a protective layer is formed covering the sidewalls of the contact hole; After the protective layer is formed, the contact hole is filled to form a conductive contact plug; wherein the conductive contact plug is electrically connected to the substrate; The first cleaning agent comprises hydrofluoric acid, sulfuric acid, hydrogen peroxide and water, wherein the volume fraction of hydrofluoric acid is 0.02% to 0.04%, the volume fraction of sulfuric acid is 3% to 7%, the volume fraction of hydrogen peroxide is 10% to 15%, and the volume fraction of water is 77.96% to 86.98%. The protective layer forming the sidewalls of the contact hole includes: A protective material layer is formed covering the sidewalls and bottom of the contact hole; Remove the protective material layer covering the bottom of the contact hole to form a protective layer covering the sidewall of the contact hole; The protective material layer forming the sidewalls and bottom of the contact hole includes: A protective material layer covering the sidewalls and bottom of the contact hole is formed using an atomic layer deposition process; wherein the thickness of the protective material layer covering the bottom of the contact hole is less than the thickness of the protective material layer covering the sidewalls of the contact hole.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The preparation method further includes: When removing the protective material layer covering the bottom of the contact hole, the substrate inside the contact hole is etched to flatten the substrate inside the contact hole.

3. The method for fabricating a semiconductor device according to claim 1, characterized in that, After forming the protective layer, the preparation method further includes: The contact hole is then cleaned a second time.

4. The method for fabricating a semiconductor device according to claim 3, characterized in that, The second cleaning of the contact hole includes: The contact hole is cleaned using a first cleaning agent; wherein the pH value of the first cleaning agent is greater than or equal to 4 and less than 7. The contact hole is cleaned in a second step and a third step using a second cleaning agent; wherein the second cleaning agent includes hydrofluoric acid.

5. The method for fabricating a semiconductor device according to claim 1, characterized in that, The substrate includes a silicon-based semiconductor; The process of filling the contact hole to form a conductive contact plug includes: A first metallic material is deposited at the bottom of the contact hole; The substrate after the first metal material is deposited is subjected to heat treatment; wherein the first metal material and the substrate react to form a metal silicide layer.

6. The method for fabricating a semiconductor device according to claim 5, characterized in that, The method for preparing a conductive contact plug by filling the contact hole further includes: A metal nitride layer is formed covering the protective layer and the metal silicide layer; A second metal material is filled into the contact hole after the metal nitride layer is formed to form a metal layer.

7. The method for fabricating a semiconductor device according to claim 1, characterized in that, The protective layer is made of one or more of silicon nitride and silicon oxynitride.

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