Semiconductor memory device and method of manufacturing the same

Abstract

A semiconductor memory device and a manufacturing method thereof. The semiconductor memory device includes a transistor extending laterally in a direction parallel to a substrate and including an active layer above the substrate, the active layer having a first end portion and a second end portion; bit line contact nodes respectively formed on an upper surface and a lower surface of the first end portion of the active layer; a bit line side ohmic contact extending vertically and connected to the first end portion of the active layer and the bit line contact nodes; a bit line extending in a direction perpendicular to the substrate and connected to the bit line side ohmic contact; and a capacitor connected to the second end portion of the active layer.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0075592, filed on June 10, 2021, the entirety of which is incorporated herein by reference. Technical Field

[0003] Various embodiments of the present invention relate to a semiconductor device, and more specifically, to a memory cell and a semiconductor device including a three-dimensional memory cell. Background Technology

[0004] The integration density of two-dimensional semiconductor memory devices is primarily determined by the area occupied by the memory cells. Therefore, the integration density is mainly influenced by the level of fine patterning technology. While the integration density of two-dimensional semiconductor memory devices continues to improve, progress is limited due to the extremely expensive tools required to fabricate finer patterns. Therefore, three-dimensional (3D) semiconductor memory devices with three-dimensionally arranged memory cells have been proposed. Summary of the Invention

[0005] Various embodiments of the present invention provide highly integrated memory cells and semiconductor memory devices including highly integrated memory cells.

[0006] A semiconductor memory device according to one embodiment of the present invention may include: a transistor, an active layer extending laterally in a direction parallel to a substrate and included above the substrate, the active layer having a first end and a second end; a bit line contact node formed on an upper surface and a lower surface of the first end of the active layer, respectively; a bit line-side ohmic contact extending vertically and connected to the first end of the active layer and the bit line contact node; a bit line extending in a direction perpendicular to the substrate and connected to the bit line-side ohmic contact; and a capacitor connected to the second end of the active layer.

[0007] A semiconductor memory device according to another embodiment of the present invention may include: a transistor, an active layer extending laterally in a direction parallel to a substrate and included above the substrate, the active layer having a first end and a second end; a bit line contact node formed on an upper surface and a lower surface of the first end of the active layer, respectively; a bit line-side ohmic contact extending vertically and connected to the first end of the active layer and the bit line contact node; a bit line extending in a direction perpendicular to the substrate and connected to the bit line-side ohmic contact; a storage contact node formed on an upper surface and a lower surface of the second end of the active layer, respectively; a storage node-side ohmic contact extending vertically and connected to the second end of the active layer and the storage contact node; and a capacitor connected to the storage node-side ohmic contact.

[0008] A method for manufacturing a semiconductor memory device according to another embodiment of the present invention may include: forming a laterally oriented stack including an active layer, the active layer including a first end and a second end; forming a first contact node on an upper surface and a lower surface of the first end of the active layer, respectively; forming a vertically oriented first ohmic contact to cover the first contact node and the first end of the active layer; and forming a first conductive layer connected to the first ohmic contact and vertically oriented in a direction intersecting the active layer. After forming the first conductive layer, the method may include: forming a second contact node on an upper surface and a lower surface of the second end of the active layer, respectively; forming a second ohmic contact, the second ohmic contact being vertically oriented to cover the second contact node and the second end of the active layer; and forming a second conductive layer connected to the second ohmic contact. The first conductive layer may include bit lines, and the second conductive layer may include storage nodes of a capacitor. Before forming the first contact node, the method may further include: forming wires facing each other, the active layer being interposed between the wires.

[0009] In one embodiment, the present invention can increase the height of the bit line-side ohmic contact by using a bit line contact node. Therefore, the contact area between the bit line and the bit line-side ohmic contact can be increased.

[0010] In one embodiment, the present invention can increase the height of the ohmic contact on the storage node side by increasing the storage contact node. Therefore, the contact area between the storage node and the ohmic contact on the storage node side can be increased.

[0011] In one embodiment, the present invention can improve the external resistance in a three-dimensional dynamic random access memory (DRAM). Attached Figure Description

[0012] Figure 1 This is a schematic perspective view showing a memory cell of a semiconductor memory device according to an embodiment of the present invention.

[0013] Figure 2 It is shown Figure 1 A cross-sectional view of a memory cell.

[0014] Figure 3 This is a schematic perspective view illustrating a semiconductor memory device according to another embodiment of the present invention.

[0015] Figure 4 This is a schematic cross-sectional view illustrating a memory cell array of a semiconductor memory device according to another embodiment of the present invention.

[0016] Figure 5 This is a cross-sectional view showing the edge portion of the double-line character.

[0017] Figure 6This is a cross-sectional view showing a semiconductor memory device according to another embodiment of the present invention.

[0018] Figure 7 This is a schematic perspective view illustrating a memory cell according to another embodiment of the present invention.

[0019] Figure 8 It is shown Figure 7 A cross-sectional view of a memory cell.

[0020] Figure 9 This is a schematic perspective view illustrating a semiconductor memory device according to another embodiment of the present invention.

[0021] Figures 10A to 10H This is a diagram illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present invention.

[0022] Figures 11A to 11G This is a diagram illustrating a method for manufacturing a semiconductor memory device according to another embodiment of the present invention.

[0023] Figure 12 This is a schematic cross-sectional view showing a memory cell according to another embodiment of the present invention.

[0024] Figures 13A to 13E This is a diagram illustrating a method for manufacturing a semiconductor memory device according to another embodiment of the present invention.

[0025] Figure 14A and Figure 14B This is a schematic cross-sectional view showing a memory cell according to an embodiment of the present invention.

[0026] Figure 15 This is a schematic perspective view illustrating a memory cell according to another embodiment of the present invention.

[0027] Figure 16 This is a schematic perspective view illustrating a memory cell according to another embodiment of the present invention. Detailed Implementation

[0028] The embodiments described herein will be explained with reference to cross-sectional views, plan views, and block diagrams, which serve as ideal schematic diagrams of the invention. Therefore, the structures in the drawings may be modified according to manufacturing techniques and / or tolerances. The embodiments of the invention are not limited to the specific structures shown in the figures, but include any variations in the structures that may result from the manufacturing process. Furthermore, any regions and shapes shown in the figures are schematic and intended to illustrate specific examples of the regional structures of various elements, and are not intended to limit the scope of the invention.

[0029] In the implementation described below, memory cells are vertically stacked to increase memory cell density and reduce parasitic capacitance.

[0030] Figure 1 This is a schematic perspective view showing a memory cell of a semiconductor memory device according to an embodiment of the present invention. Figure 2 It is shown Figure 1 A cross-sectional view of a memory cell.

[0031] Reference Figure 1 and Figure 2 According to various embodiments of the present invention, the memory cell MC of a 3D semiconductor memory device may include a bit line BL, a transistor TR, and a capacitor CAP. The transistor TR may include an active layer ACT and dual word lines DWL (WL1, WL2). The dual word lines DWL may have a first word line WL1 and a second word line WL2 facing each other, with the active layer ACT interposed between the first word line WL1 and the second word line WL2. The capacitor CAP may include a memory node SN, a dielectric layer DE, and a board node PN.

[0032] The bit line BL can have a cylindrical shape extending in a first direction D1. The active layer ACT can have a strip shape extending in a second direction D2 intersecting the first direction D1. The double word line DWL can have a linear shape extending in a third direction D3 intersecting both the first direction D1 and the second direction D2. The plate node PN of the capacitor CAP can be connected to the plate line PL.

[0033] Bit line BL can be vertically oriented along a first direction D1. Bit line BL can be referred to as a vertically oriented bit line or a cylindrical bit line. Bit line BL can include a conductive material. Bit line BL can include a silicon-based material, a metal-based material, or a combination thereof. Bit line BL can include, for example, silicon, a metal, a metal nitride, a metal silicide, or a combination thereof. Bit line BL can also include, for example, polycrystalline silicon, titanium nitride, tungsten, or a combination thereof. For example, bit line BL can include polycrystalline silicon or titanium nitride (TiN) doped with N-type impurities. Bit line BL can include a TiN / W stack comprising titanium nitride and tungsten on the titanium nitride.

[0034] A bitline BL may include a bitline body BLM and a bitline barrier BLB. The bitline barrier BLB may be disposed on a side of the bitline body BLM. The bitline body BLM may include tungsten, and the bitline barrier BLB may include titanium nitride (TiN). In another embodiment, the bitline barrier BLB may surround a sidewall of the bitline body BLM.

[0035] The dual word line (DWL) can extend along a third direction D3, and the active layer (ACT) can extend along a second direction D2. The active layer (ACT) can be arranged laterally from the bit line (BL) along the second direction D2. The dual word line (DWL) can include a pair of word lines, namely a first word line (WL1) and a second word line (WL2). The first word line (WL1) and the second word line (WL2) can face each other along a first direction D1, with the active layer (ACT) placed between them. A gate dielectric layer (GD) can be formed on the upper and lower surfaces of the active layer (ACT).

[0036] The active layer ACT may comprise a semiconductor material or an oxide semiconductor material. For example, the active layer ACT may comprise silicon, germanium, silicon-germanium, or IGZO (indium gallium zinc oxide). The active layer ACT may comprise polycrystalline silicon or monocrystalline silicon. The active layer ACT may comprise a channel CH, a first source / drain region SR between the channel CH and the bit line BL, and a second source / drain region DR between the channel CH and the capacitor CAP. The channel CH may be defined between the first source / drain region SR and the second source / drain region DR.

[0037] The first source / drain region SR and the second source / drain region DR may be doped with impurities of the same conductivity type. The first source / drain region SR and the second source / drain region DR may be doped with N-type or P-type impurities. The first source / drain region SR and the second source / drain region DR may include at least one impurity selected from arsenic (As), phosphorus (P), boron (B), indium (In), and combinations thereof. A first side of the first source / drain region SR may contact the bit line BL, and a second side of the first source / drain region SR may contact the channel CH. A first side of the second source / drain region DR may contact the memory node SN, and a second side of the second source / drain region DR may contact the channel CH. The second side of the first source / drain region SR and the second source / drain region DR may partially overlap with the side of the first word line WL1 and the side of the second word line WL2. In one embodiment, the lateral length of the channel CH along the second direction D2 may be less than the lateral length of the first source / drain region SR and the second source / drain region DR along the second direction D2. In another embodiment, the lateral length of the channel CH along the second direction D2 can be greater than the lateral length of the first source / drain region SR and the second source / drain region DR along the second direction D2.

[0038] In one embodiment, the transistor TR is a single-cell transistor and may have a double word line (DWL). In the double word line DWL, the first word line WL1 and the second word line WL2 may have the same potential. For example, the first word line WL1 and the second word line WL2 may form a pair, and the same word line drive voltage may be applied to the first word line WL1 and the second word line WL2. As described above, a memory cell MC according to one embodiment of the present invention may have a double word line DWL, wherein the first word line WL1 and the second word line WL2 are adjacent to a channel CH.

[0039] In another embodiment, the first word line WL1 and the second word line WL2 can have different potentials. For example, a word line drive voltage can be applied to the first word line WL1, and a reference (e.g., ground) voltage can be applied to the second word line WL2. The second word line WL2 can be referred to as a back word line or a shielded word line. In another embodiment, a reference (e.g., ground) voltage can be applied to the first word line WL1, and a word line drive voltage can be applied to the second word line WL2.

[0040] In one embodiment, the active layer ACT can be thinner than the first word line WL1 and the second word line WL2. In other words, the vertical thickness of the active layer ACT along the first direction D1 can be less than the vertical thickness of each of the first word lines WL1 and WL2 along the first direction D1. Thus, the thin active layer ACT can be referred to as a thin-body active layer. The thin active layer ACT may include a thin-body channel CH, and the thin-body channel CH may have a thickness of 10 nm or less. In another embodiment, the channel CH may have the same vertical thickness as the first word line WL1 and the second word line WL2.

[0041] In one implementation, the upper and lower surfaces of the active layer ACT can be flat surfaces. That is, the upper and lower surfaces of the active layer ACT can be parallel to each other in the second direction D2.

[0042] The gate dielectric layer (GD) can be formed from, for example, silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicate, high-k material, ferroelectric material, antiferroelectric material, or a combination thereof. The gate dielectric layer (GD) can include, for example, SiO2, Si3N4, HfO2, Al2O3, ZrO2, AlON, HfON, HfSiO, HfSiON, or HfZrO.

[0043] Double word line dual-word line (DWL) materials can include metals, metal mixtures, metal alloys, or semiconductor materials. Double word line DWL materials can include titanium nitride, tungsten, polycrystalline silicon, or combinations thereof. For example, a double word line DWL can include a TiN / W stack in which titanium nitride and tungsten are stacked sequentially. Double word line DWL materials can include N-type work function materials or P-type work function materials. N-type work function materials can have a low work function of 4.5 eV or lower, while P-type work function materials can have a high work function of 4.5 eV or higher.

[0044] In one embodiment, a bit-line side ohmic contact BOC can be formed between the first source / drain region SR and the bit line BL. The bit-line side ohmic contact BOC and the first source / drain region SR can be jointly connected to the bit line contact node BLC. The bit line contact node BLC can be connected to both the upper and lower surfaces of the first source / drain region SR. The bit line contact node BLC can have a dual structure with bit line contact nodes respectively disposed on the upper and lower surfaces of the first source / drain region SR. The bit-line side ohmic contact BOC can be disposed between the bit line contact node BLC and the bit line BL. The height H1 of the bit-line side ohmic contact BOC can be increased by the bit line contact node BLC. The contact area between the bit line BL and the bit-line side ohmic contact BOC can be increased. The contact area between the bit line BL and the first source / drain region SR can also be increased.

[0045] The bit line contact node (BLC) can comprise polysilicon, such as polysilicon doped with N-type impurities. The height H1 of the bit line-side ohmic contact (BOC), i.e., the thickness H1 of the bit line-side ohmic contact BOC in the first direction D1, can be greater than the thickness H2 of the active layer ACT in the first direction D1. The first source / drain region (SR) can be doped with N-type impurities diffused from the bit line contact node (BLC). The bit line-side ohmic contact (BOC) can have a height that completely covers the side surfaces of the bit line contact node (BLC) and the first source / drain region (SR). The bit line contact node (BLC) and the first source / drain region (SR) can form a "horizontally oriented T-shaped structure," which can be formed from a combination of various N-type doped polysilicon materials.

[0046] When the silicon of the bit line contact node BLC and the first source / drain region SR reacts with the metal of the bit line BL, a bit line-side ohmic contact BOC can be formed. The bit line-side ohmic contact BOC may include metal silicide.

[0047] A capacitor CAP can be laterally disposed from the transistor TR along the second direction D2. The capacitor CAP can include a memory node SN extending laterally from the active layer ACT along the second direction D2. The capacitor CAP can also include a dielectric layer DE and a board node PN on the memory node SN. The memory node SN, dielectric layer DE, and board node PN can be arranged laterally along the second direction D2. The memory node SN can have a laterally oriented cylindrical shape. The dielectric layer DE can conformally cover the inner and outer walls of the memory node SN. The board node PN can have a shape consistent with the dielectric layer DE on the inner and outer walls of the memory node SN. The board node PN can be connected to a board line PL. The memory node SN can be electrically connected to a second source / drain region DR.

[0048] The storage node SN can have a three-dimensional structure, and the three-dimensional storage node SN can have a three-dimensional structure oriented laterally along the second direction D2. As an example of a three-dimensional structure, the storage node SN can have a cylindrical shape. In another embodiment, the storage node SN can have a cylindrical or pylinder shape. A pylinder shape refers to a structure that combines a cylindrical shape and a pylinder shape. (See reference...) Figure 2 As shown in the orientation, the upper surface of the storage node SN can be located at the same horizontal level as the upper surface of the first word line WL1. The lowermost surface of the storage node SN can be located at the same horizontal level as the bottom surface of the second word line WL2.

[0049] A board node PN may include an internal node N1 and external nodes N2, N3, and N4. Internal node N1 and external nodes N2, N3, and N4 can be interconnected. Internal node N1 may be located inside the housing of the storage node SN. External nodes N2 and N3 may be located outside the housing of the storage node SN, separated by a dielectric layer DE. External node N4 can interconnect internal node N1 with external nodes N2 and N3. External nodes N2 and N3 may be positioned around the outer wall of the housing of the storage node SN. External node N4 can be used as a board line PL.

[0050] Storage nodes (SN) and board nodes (PN) can include metals, noble metals, metal nitrides, conductive metal oxides, conductive noble metal oxides, metal carbides, metal silicides, or combinations thereof. For example, storage nodes (SN) and board nodes (PN) can include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), titanium nitride / tungsten (TiN / W) stacks, and tungsten nitride / tungsten (WN / W) stacks. Board nodes (PN) can include combinations of metal-based and silicon-based materials. For example, a board node (PN) can be a titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN) stack. In a titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN) stack, silicon germanium can be the gap filler material inside the cylinder that fills the storage node SN above the titanium nitride, titanium nitride (TiN) can be used as the plate node PN of the capacitor CAP, and tungsten nitride can be a material with low resistivity.

[0051] The dielectric layer DE may comprise silicon oxide, silicon nitride, high-k material, or a combination thereof. High-k materials may have a higher dielectric constant than silicon oxide. Silicon oxide (SiO2) may have a dielectric constant of about 3.9, and the dielectric layer DE may comprise a high-k material with a dielectric constant of 4 or greater. High-k materials may have a dielectric constant of about 20 or greater. High-k materials may include, for example, hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanium oxide (SrTiO3). In another embodiment, the dielectric layer DE may be formed from a composite layer comprising two or more layers of the aforementioned high-k materials.

[0052] The dielectric layer DE can be formed of zirconium (Zr)-based oxide. The dielectric layer DE can have a stacked structure including zirconium oxide (ZrO2). The stacked structure including zirconium oxide (ZrO2) can include a ZA (ZrO2 / Al2O3) stack or a ZAZ (ZrO2 / Al2O3 / ZrO2) stack. The ZA stack can have a structure in which aluminum oxide (Al2O3) is stacked on top of zirconium oxide (ZrO2). The ZAZ stack can have a structure in which zirconium oxide (ZrO2), aluminum oxide (Al2O3), and zirconium oxide (ZrO2) are stacked sequentially. The ZA and ZAZ stacks can be referred to as zirconium oxide (ZrO2)-based layers. In another embodiment, the dielectric layer DE can be formed of hafnium (Hf)-based oxide. The dielectric layer DE can have a stacked structure including at least hafnium oxide (HfO2). Stacked structures including hafnium oxide (HfO2) can include HA (HfO2 / Al2O3) stacks or HAH (HfO2 / Al2O3 / HfO2) stacks. HA stacks can have a structure in which aluminum oxide (Al2O3) is stacked on top of hafnium oxide (HfO2). HAH stacks can have a structure in which hafnium oxide (HfO2), aluminum oxide (Al2O3), and hafnium oxide (HfO2) are stacked sequentially. HA stacks and HAH stacks can be referred to as hafnium oxide (HfO2)-based layers. In ZA, ZAZ, HA, and HAH stacks including aluminum oxide (Al2O3), the band gap energy (hereinafter referred to as the band gap) of Al2O3 is generally greater than that of zirconium oxide (ZrO2) and hafnium oxide (HfO2). The dielectric constant of aluminum oxide (Al2O3) is also generally lower than that of zirconium oxide (ZrO2) and hafnium oxide (HfO2). Therefore, the dielectric layer DE can include a stack of a high-k material and a high-bandgap material with a bandgap greater than that of the high-k material. The dielectric layer DE can include silicon oxide (SiO2) as a high-bandgap material other than aluminum oxide (Al2O3). Because the dielectric layer DE includes a high-bandgap material, leakage current can be suppressed. The high-bandgap material can be thinner than the high-k material. In another embodiment, the dielectric layer DE can include a stacked structure in which high-k materials and high-bandgap materials are alternately stacked. For example, the dielectric layer DE can include a ZAZA (ZrO2 / Al2O3 / ZrO2 / Al2O3) stack, a ZAZAZ (ZrO2 / Al2O3 / ZrO2 / Al2O3 / ZrO2) stack, a HAHA (HfO2 / Al2O3 / HfO2 / Al2O3) stack, or a HAHAH (HfO2 / Al2O3 / HfO2 / Al2O3 / HfO2) stack. In the above-mentioned stacked structure, aluminum oxide (Al2O3) can be thinner than zirconium oxide (ZrO2) and hafnium oxide (HfO2).

[0053] In another embodiment, the dielectric layer DE may have a stacked structure, a multilayer structure, or a mixed structure comprising zirconium oxide, hafnium oxide, and aluminum oxide.

[0054] In another embodiment, the dielectric layer DE may include a ferroelectric material or an antiferroelectric material.

[0055] In another embodiment, an interface control layer for improving leakage current can be formed between the storage node SN and the dielectric layer DE. The interface control layer may include titanium oxide (TiO2), niobium oxide, or niobium nitride. The interface control layer may also be formed between the board node PN and the dielectric layer DE.

[0056] Capacitors (CAP) can include metal-insulator-metal (MIM) capacitors. Storage nodes (SN) and board nodes (PN) can include metal-based materials.

[0057] The capacitor CAP can be replaced by other data storage materials. For example, data storage materials can include phase change materials, magnetic tunnel junctions (MTJs), or variable resistance materials.

[0058] Figure 3 This is a schematic perspective view of a semiconductor memory device according to one embodiment of the present invention. Figure 4 yes Figure 3 A cross-sectional view of the vertical memory cell array MCA_C. Figure 5 This is a cross-sectional view showing the edge portion of the double-line character.

[0059] Reference Figures 3 to 5 The semiconductor memory device 100 may include a memory cell array (MCA). Figure 1 Multiple memory cells, composed of memory cells MC, can be arranged on the first to third directions D1, D2, and D3 to form a memory cell array. Figure 3The memory cell array (MCA) can form a three-dimensional memory cell array of memory cells MC, and the three-dimensional memory cell array can include a vertical memory cell array (MCA_C) and a horizontal memory cell array (MCA_R). The vertical memory cell array (MCA_C) refers to an array of memory cells MC arranged vertically in a first direction D1. The horizontal memory cell array (MCA_R) refers to an array of memory cells MC arranged horizontally in a third direction D3. The vertical memory cell array (MCA_C) can be referred to as a column array of memory cells MC, while the horizontal memory cell array (MCA_R) can be referred to as a row array of memory cells MC. Bit lines BL can be vertically oriented to connect to the vertical memory cell array (MCA_C), and double word lines (DWL) can be horizontally oriented to connect to the horizontal memory cell array (MCA_R). Bit lines BL connected to the vertical memory cell array (MCA_C) can be referred to as common bit lines, and vertical memory cell arrays (MCA_C) adjacent to each other along the third direction D3 can be connected to different common bit lines. The double word line DWL connected to the horizontal memory cell array MCA_R can be referred to as the common double word line, and the horizontal memory cell arrays MCA_R adjacent to each other along the first direction D1 can be connected to different common double word lines.

[0060] A memory cell array (MCA) may include multiple memory cells (MCs), and each memory cell (MC) may include a vertically oriented bit line (BL), a laterally oriented active layer (ACT), a double word line (DWL), and a laterally oriented capacitor (CAP). For example, Figure 3 A three-dimensional DRAM memory cell array comprising four memory cells (MCs) is shown.

[0061] Adjacent active layers ACT on the first direction D1 can share a bit line BL. Adjacent active layers ACT on the third direction D3 can share a double word line DWL. Capacitors CAP can be connected to active layers ACT individually. Capacitors CAP can share a board line PL. A single active layer ACT can be thinner than the first word line WL1 and the second word line WL2 of the double word line DWL.

[0062] exist Figure 3 In the illustrated memory cell array (MCA), multiple double word lines (DWLs) can be vertically stacked in a first direction D1. Each DWL can comprise a pair of first word lines WL1 and second word lines WL2. Multiple active layers (ACTs) can be laterally arranged between the first word lines WL1 and second word lines WL2, spaced apart from each other in a third direction D3. The channels (CHs) of the active layers (ACTs) can be located between the first word lines WL1 and second word lines WL2.

[0063] Reference Figure 5Each double letter line (DWL) may have a stepped shape on both sides of its edge portion, and this stepped shape may define a contact portion (CA). Each of the first letter line (WL1) and the second letter line (WL2) may include edge portions on both sides, i.e., contact portions (CA). Each contact portion (CA) may have a stepped shape.

[0064] Multiple word line pads WLP1 and WLP2 can be connected to contact portions CA, respectively. For example, the first word line pad WLP1 can be connected to the high-level dual word line DWL, that is, the contact portion CA of the first word line WL1 and the second word line WL2 at the high-level bit. The second word line pad WLP2 can be connected to the low-level dual word line DWL, that is, the contact portion CA of the first word line WL1 and the second word line WL2 at the low-level bit. The first word line WL1 and the second word line WL2 at the high-level bit can be interconnected through the first word line pad WLP1. The first word line WL1 and the second word line WL2 at the low-level bit can be interconnected through the second word line pad WLP2.

[0065] The semiconductor memory device 100 may further include a substrate PERI, and the substrate PERI may include a peripheral circuit portion. Hereinafter, the substrate PERI will be simply referred to as the peripheral circuit portion PERI. The bit lines BL of the memory cell array MCA may be oriented perpendicularly to the surface of the peripheral circuit portion PERI along a first direction D1, and the double word lines DWL may be oriented parallel to the surface of the peripheral circuit portion PERI along a third direction D3.

[0066] The Peripheral Circuit I (PERI) can be positioned at a lower level than the Memory Cell Array (MCA). This structure is referred to below as a COP (Cell over PERI) structure. The PERI may include at least one control circuit for driving the MCA. The at least one control circuit of the PERI may include an N-channel transistor, a P-channel transistor, a CMOS circuit, or a combination thereof. The at least one control circuit of the PERI may include an address decoder circuit, a read circuit, a write circuit, etc. The at least one control circuit of the PERI may include a planar channel transistor, a concave channel transistor, a buried gate transistor, a FinFET, etc.

[0067] For example, the peripheral circuitry PERI may include sub-word line drivers SWD1 and SWD2 and a sense amplifier SA. The high-level bit's dual word line DWL can be connected to the first sub-word line driver SWD1 via a first word line pad WLP1 and a first metal interconnect MI1. The low-level bit's dual word line DWL can be connected to the second sub-word line driver SWD2 via a second word line pad WLP2 and a second metal interconnect MI2. The bit line BL can be connected to the sense amplifier SA via a third metal interconnect MI3. The third metal interconnect MI3 may have a multilayer metal (MLM) structure including multiple vias and multiple metal lines.

[0068] Figure 6 This is a schematic cross-sectional view illustrating a memory cell array of a semiconductor memory device according to another embodiment of the present invention. Figure 6 A semiconductor memory device 110 with a POC (PERI over Cell) structure is shown. Figure 6 In the middle, "and" can be omitted. Figure 5 Detailed description of the repeating parts.

[0069] Reference Figure 6 The semiconductor memory device 110 may include a memory cell array MCA and a peripheral circuit section PERI'. The peripheral circuit section PERI' may be located at a horizontal position higher than the memory cell array MCA. This structure is referred to below as a POC (PERI over Cell) structure.

[0070] The peripheral circuitry PERI' may include sub-word line drivers SWD1 and SWD2, and a sense amplifier SA. The high-level bit's dual word line DWL can be connected to the first sub-word line driver SWD1 via a first word line pad WLP1 and a first metal interconnect MI1. The low-level bit's dual word line DWL can be connected to the second sub-word line driver SWD2 via a second word line pad WLP2 and a second metal interconnect MI2. The bit line BL can be connected to the sense amplifier SA via a third metal interconnect MI3. The third metal interconnect MI3 may have a multilayer metal structure including multiple vias and multiple metal lines.

[0071] Figure 7 This is a schematic perspective view showing a memory cell of a semiconductor memory device according to another embodiment. Figure 8 yes Figure 7 A cross-sectional view of a semiconductor memory device. Figure 7 and Figure 8 In the middle, "and" can be omitted. Figure 1 and Figure 2 Detailed description of the repeating parts.

[0072] Reference Figure 7 and Figure 8 The memory cell MC10 of the 3D semiconductor memory device may include a bit line BL, a transistor TR, and a capacitor CAP. The transistor TR may include an active layer ACT, a gate dielectric layer GD, and dual word lines DWL (W1, W2). The active layer ACT may include a first source / drain region SR, a second source / drain region DR, and a channel CH between the first source / drain region SR and the second source / drain region DR. The capacitor CAP may include a memory node SN, a dielectric layer DE, and a board node PN. The bit line BL may have a pillar shape extending in a first direction D1. The active layer ACT may have a strip shape extending in a second direction D2 intersecting the first direction D1. The dual word line DWL may have a line shape extending in a third direction D3 intersecting the first direction D1 and the second direction D2. The dual word line DWL may include a first word line WL1 and a second word line WL2. The board node PN of the capacitor CAP may be connected to a board line PL.

[0073] The bit-line side ohmic contact BOC can be formed between the first source / drain region SR and the bit line BL. The bit-line side ohmic contact BOC and the first source / drain region SR can be jointly connected to the bit line contact node BLC. The bit line contact node BLC can be connected to the upper and lower surfaces of the first source / drain region SR, respectively. The bit line contact node BLC can have a dual structure with the bit line contact node BLC respectively disposed on the upper and lower surfaces of the first source / drain region SR. The bit-line side ohmic contact BOC can be located between the bit line contact node BLC and the bit line BL. The height H1 of the bit-line side ohmic contact BOC can be increased by the bit line contact node BLC. The contact area between the bit line BL and the bit-line side ohmic contact BOC can be increased. The contact area between the bit line BL and the first source / drain region SR can also be increased.

[0074] The bit line contact node (BLC) may include polysilicon, such as polysilicon doped with N-type impurities. The height of the bit line-side ohmic contact (BOC), i.e., the thickness H1 of the bit line-side ohmic contact BOC in the first direction D1, may be greater than the thickness H2 of the active layer ACT in the first direction D1. The bit line-side ohmic contact BOC may have a height that completely covers the side surface of the bit line contact node (BLC) and the side surface of the first source / drain region (SR).

[0075] When the silicon of the bit line contact node BLC and the first source / drain region SR reacts with the metal of the bit line BL, a bit line-side ohmic contact BOC can be formed. The bit line-side ohmic contact BOC may include metal silicide.

[0076] A storage node-side ohmic contact SOC can be formed between the second source / drain region DR and the storage node SN. The storage node-side ohmic contact SOC and the second source / drain region DR can be jointly connected to a storage contact node SNC. The storage contact node SNC can be connected to the upper and lower surfaces of the second source / drain region DR, respectively. The storage contact node SNC can have a dual structure with the storage contact node SNC disposed on both the upper and lower surfaces of the second source / drain region DR. The storage node-side ohmic contact SOC can be disposed between the storage contact node SNC and the storage node SN. The height H1 of the storage node-side ohmic contact SOC can be increased by increasing the storage contact node SNC, thereby increasing the contact area between the storage node SN and the storage node-side ohmic contact SOC. The contact area between the storage node SN and the second source / drain region DR can be increased.

[0077] The memory node-side ohmic contact SOC and the bit line-side ohmic contact BOC can have the same height. The memory contact node SNC can include polysilicon, such as polysilicon doped with N-type impurities. The height of the memory node-side ohmic contact SOC, i.e., its thickness H1 in the first direction D1, can be greater than the thickness H2 of the active layer ACT in the first direction D1. The second source / drain region DR can be doped with N-type impurities diffused from the memory contact node SNC. The memory node-side ohmic contact SOC can have a height that completely covers the side surface of the memory contact node SNC and the side surface of the second source / drain region DR.

[0078] When the silicon of the storage contact node (SNC) and the second source / drain region (DR) reacts with metal, a storage node-side ohmic contact (SOC) can be formed. The storage node-side ohmic contact (SOC) can include metal silicides.

[0079] Figure 9 This is a schematic perspective view illustrating a semiconductor memory device according to another embodiment of the present invention. Figure 9 In the middle, "and" can be omitted. Figure 3 and Figure 4 Detailed description of the repeating parts.

[0080] Reference Figure 9 The semiconductor memory device 120 may include a memory cell array MCA10. Figure 7 The memory cell MC10 can be arranged on the first to third directions D1, D2 and D3 to form Figure 9The memory cell array MCA10 can include a three-dimensional array of memory cells MC10, and the three-dimensional memory cell array can include a vertical memory cell array MCA_C and a horizontal memory cell array MCA_R. The vertical memory cell array MCA_C refers to an array of memory cells MC10 arranged vertically in a first direction D1. The horizontal memory cell array MCA_R refers to an array of memory cells MC10 arranged horizontally in a third direction D3. The vertical memory cell array MCA_C can be referred to as a column array of memory cells MC10, and the horizontal memory cell array MCA_R can be referred to as a row array of memory cells MC10. Bit lines BL can be vertically oriented to connect to the vertical memory cell array MCA_C, and double word lines DWL can be horizontally oriented to connect to the horizontal memory cell array MCA_R. The bit lines BL connected to the vertical memory cell array MCA_C can be referred to as common bit lines, and adjacent vertical memory cell arrays MCA_C along the third direction D3 can be connected to different common bit lines respectively. The double word line DWL connected to the horizontal memory cell array MCA_R can be referred to as the common double word line, and the horizontal memory cell arrays MCA_R adjacent to each other along the first direction D1 can be connected to different common double word lines.

[0081] The memory cell array MCA10 may include multiple memory cells MC10, and each memory cell MC10 may include a vertically oriented bit line BL, a horizontally oriented active layer ACT, a double word line DWL, and a horizontally oriented capacitor CAP. Figure 9 A three-dimensional DRAM memory cell array comprising four memory cells MC10 is shown.

[0082] Adjacent active layers ACT on the first direction D1 can be connected to a bit line BL. Adjacent active layers ACT on the third direction D3 can share the same double word line DWL. Capacitors CAP can be individually connected to the active layers ACT. Capacitors CAP can share a board line PL. A single active layer ACT can be thinner than the first word line WL1 and the second word line WL2 of the double word line DWL.

[0083] In the memory cell array MCA10, multiple double word lines (DWLs) can be vertically stacked in a first direction D1. Each double word line (DWL) may include a pair of first word lines (WL1) and second word lines (WL2). Between the first word lines (WL1) and second word lines (WL2), multiple active layers (ACTs) can be arranged laterally, spaced apart from each other, in a third direction D3. The channels (CH) of the active layers (ACTs) may be located between the first word lines (WL1) and second word lines (WL2).

[0084] Similar to Figure 5 As shown, in Figure 9 In the dual word line (DWL) of the memory cell array MCA10, the stepped contact portion can be defined at the edge portions on both sides.

[0085] Similar to Figure 5 and Figure 6 As shown, Figure 9 The semiconductor memory device 120 may include a COP or POC structure.

[0086] The transistors according to the above embodiments can be applied to dual-gate (DG) field-effect transistors, fin field-effect transistors (FinFETs), gate all-around (GAA) field-effect transistors, and multi-bridge thin-channel field-effect transistors.

[0087] Figures 10A to 10H This is a diagram illustrating a method for manufacturing a semiconductor memory device according to various embodiments of the present invention.

[0088] Reference Figure 10A A stack SB can be formed. The stack SB may include intermediate dielectric layers 11 and 15, sacrificial layers 12 and 14, and a semiconductor layer 13. The semiconductor layer 13 may be disposed between the lower intermediate dielectric layer 11 and the upper intermediate dielectric layer 15. The lower sacrificial layer 12 may be disposed between the lower intermediate dielectric layer 11 and the semiconductor layer 13, and the upper sacrificial layer 14 may be disposed between the upper intermediate dielectric layer 15 and the semiconductor layer 13. The intermediate dielectric layers 11 and 15 may include silicon oxide, and the sacrificial layers 12 and 14 may include silicon nitride. The semiconductor layer 13 may include a semiconductor material or an oxide semiconductor material. The semiconductor layer 13 may include monocrystalline silicon, polycrystalline silicon, or IGZO (indium gallium zinc oxide).

[0089] The first opening 16 can be formed by etching the stack SB. The first opening 16 can have a hole shape that passes perpendicularly through the stack SB.

[0090] Multiple semiconductor layers 13 can be formed between sacrificial layers 12 and 14. For example, similar to Figure 3 The active layer ACT shown can have multiple semiconductor layers 13 arranged laterally on the same plane. For example, forming multiple semiconductor layers 13 may include: forming a stack SB, wherein sacrificial layers 12 and 14 are disposed on intermediate dielectric layers 11 and 15, respectively, and a planar semiconductor layer is formed between sacrificial layers 12 and 14; forming multiple device separation vias by etching the stack SB; and forming a pattern of multiple semiconductor layers laterally arranged between sacrificial layers 12 and 14 by trench etching the planar semiconductor layer through the device separation vias.

[0091] like Figure 10BAs shown, the recess 17 can be formed by selectively etching sacrificial layers 12 and 14. A portion of the semiconductor layer 13 can be exposed through the recess 17. An upper recess in the recess 17 can be formed between the semiconductor layer 13 and the upper intermediate dielectric layer 15, and a lower recess in the recess 17 can be formed between the semiconductor layer 13 and the lower intermediate dielectric layer 11. Hereinafter, the portion of the semiconductor layer 13 exposed through the recess 17 is referred to as "first portion P1". The first portion P1 of the semiconductor layer 13 may refer to the portion where the channel CH and the first source / drain region SR are to be formed, as described in the above embodiment. The portion of the semiconductor layer 13 covered by sacrificial layers 12 and 14 is referred to as "second portion P2".

[0092] like Figure 10C As shown, a gate dielectric layer 18 can be formed on the first portion P1 of the semiconductor layer 13. The gate dielectric layer 18 can be selectively formed on the surface of the first portion P1 of the semiconductor layer 13 by an oxidation process. In another embodiment, the gate dielectric layer 18 can be formed by a deposition process, and in this case, the gate dielectric layer 18 can be formed on the surface of the recess 17 and the surface of the first portion P1 of the semiconductor layer 13.

[0093] Next, double word lines 19 can be formed by filling each recess 17 with a conductive material. The double word lines 19 may comprise polysilicon, titanium nitride, tungsten, or a combination thereof. For example, forming double word lines 19 may include: conformally depositing titanium nitride, depositing tungsten on the titanium nitride to fill the recess 17, and etching back the titanium nitride and tungsten. The double word lines 19 may partially fill the recess 17, and thus expose a portion of the gate dielectric layer 18. The double word lines 19 may face each other perpendicularly, with a first portion P1 of the semiconductor layer 13 interposed between them.

[0094] like Figure 10D As shown, a padding layer 20 can be formed that contacts one side of the double letter line 19. The padding layer 20 can be disposed in the groove 17. The padding layer 20 may include silicon oxide or silicon nitride. The padding layer 20 may be disposed in a portion of the groove 17. That is, a blank space (or air gap) may be reserved on one side of the padding layer 20.

[0095] Next, the first end E1 of the first portion P1 can be exposed by etching the portion of the gate dielectric layer 18 exposed through the pad layer 20. Hereinafter, the first end E1 of the first portion P1 will be simply referred to as "first end E1". The first end E1 of the semiconductor layer 13 may include a horizontally flat surface LP and a vertically flat surface VP located between the horizontally flat surface LP. The vertically flat surface VP can be exposed through the first opening 16, and the horizontally flat surface LP can be exposed through a blank space disposed on one side of the pad layer 20.

[0096] like Figure 10E As shown, the first opening 16 can be filled with a conductive layer 21' containing impurities. The conductive layer 21' can be polycrystalline silicon containing N-type impurities such as phosphorus. A portion of the conductive layer 21' can fill the empty space disposed on one side of the pad layer 20. The conductive layer 21' can directly contact the first end E1 of the semiconductor layer 13. The conductive layer 21' can cover the vertically flat surface VP and the horizontally flat surface LP of the first end E1.

[0097] Subsequent heat treatment can be performed to allow impurities to diffuse from the conductive layer 21' into the semiconductor layer 13. Therefore, a first source / drain region 22 can be formed in the first portion P1 of the semiconductor layer 13.

[0098] like Figure 10F As shown, a bit line contact node 23 can be formed by recessing the conductive layer 21'. The bit line contact node 23 can fill the remaining space of the groove 17. The bit line contact node 23 can fill the blank space provided on one side of the pad layer 20. The bit line contact node 23 can be vertically arranged with the first source / drain region 22 inserted therebetween. The bit line contact node 23 can be formed on the upper and lower surfaces of the first source / drain region 22, respectively. The combination of the bit line contact node 23 and the first source / drain region 22 can form a horizontally oriented T-shape. One side of the first source / drain region 22 can be self-aligned to one side of the bit line contact node 23. Therefore, the vertically flat surface VP of the first end E1 can be exposed.

[0099] In one embodiment, the groove 17 may be filled with double letter lines 19, a padding layer 20, and a bit line contact node 23.

[0100] like Figure 10G As shown, a bit-line side ohmic contact 24 can be formed on the bit-line contact node 23 and the first source / drain region 22. The bit-line side ohmic contact 24 may include a metal silicide. For example, the metal silicide can be formed by sequentially depositing a metal layer on the bit-line contact node 23 and the first source / drain region 22 and annealing the metal layer, and unreacted metal layers can be removed. The metal silicide can be formed when the silicon in the bit-line contact node 23 and the first source / drain region 22 reacts with the metal layer. The bit-line side ohmic contact 24 can simultaneously cover one side of the bit-line contact node 23 and one side of the first source / drain region 22.

[0101] like Figure 10H As shown, a bit line BL can be formed to contact the bit line-side ohmic contact 24. The bit line BL can have a cylindrical shape that fills the first opening 16. The bit line BL can include a bit line block 25 and a bit line body 26, and the bit line block 25 can contact the bit line-side ohmic contact 24. The bit line block 25 can include titanium nitride, and the bit line body 26 can include tungsten.

[0102] In another embodiment, the bit line-side ohmic contact 24 can be formed simultaneously with the bit line barrier 25. For example, as the bit line barrier 25, a titanium / titanium nitride (Ti / TiN) stack can be deposited and annealed. In this case, titanium can be silicided to form titanium silicide, which can be used as the bit line-side ohmic contact 24, and the titanium nitride can become the bit line barrier 25.

[0103] Figures 11A to 11G A method for manufacturing a semiconductor memory device according to another embodiment of the present invention is shown. Figures 11A to 11G The method for manufacturing capacitors described herein is based on an embodiment of the present invention and can be used in the formation of... Figure 10H Execute after the bit line BL.

[0104] ]like Figure 11A As shown, the second opening 27 can be formed by etching different portions of the stack SB. The second opening 27 can extend vertically. The second opening 27 can have a hole shape that passes through the aforementioned different portions of the stack SB.

[0105] Next, the sacrificial layers 12 and 14, and the second portion P2 of the semiconductor layer 13, can be selectively recessed through the second opening 27. Therefore, a capacitor opening 28 can be formed between the intermediate dielectric layers 11 and 15. After performing the process of forming the second opening 27 and the capacitor opening 28, the remaining semiconductor layer 13 is simply referred to as the "active layer 13". A double word line 19 can be formed therein, interposed with the active layer 13.

[0106] Next, the sacrificial layers 12 and 14 can be further recessed. Therefore, a blanking space (or air gap) can be provided on one side of the sacrificial layers 12 and 14, and the second end E2 of the active layer 13 can be exposed through the blanking space. Similar to the first end E1, the second end E2 may include a horizontally flat surface and a vertically flat surface located between the horizontally flat surfaces. The vertically flat surface can be exposed through the capacitor opening 28, and the horizontally flat surface can be exposed through the blanking space provided on one side of the sacrificial layers 12 and 14. The remaining sacrificial layers 12 and 14 can cover the side surfaces of the double letter line 19.

[0107] like Figure 11B As shown, a conductive layer 29' including impurities can be formed. The conductive layer 29' can be polycrystalline silicon containing N-type impurities such as phosphorus. A portion of the conductive layer 29' can fill the empty space disposed on one side of the sacrificial layers 12 and 14. The conductive layer 29' can directly contact the second end E2 of the active layer 13. The conductive layer 29' can cover the vertically flat surface and the horizontally flat surface of the second end E2.

[0108] Subsequent heat treatment can be performed to allow impurities to diffuse from the conductive layer 29' into the active layer 13. Therefore, a second source / drain region 30 can be formed at the second end E2 of the active layer 13. The first source / drain region 22 and the second source / drain region 30 can be formed laterally spaced apart from each other in the active layer 13, and a channel CH can be defined between the first source / drain region 22 and the second source / drain region 30.

[0109] like Figure 11C As shown, the conductive layer 29' can be recessed to form a storage contact node 29. The storage contact node 29 can fill the empty space on one side of the sacrificial layers 12 and 14. The storage contact node 29 can be vertically positioned with a second source / drain region 30 inserted therebetween. The storage contact node 29 can be formed on the upper and lower surfaces of the second source / drain region 30, respectively. The combination of the storage contact node 29 and the second source / drain region 30 can form a horizontally oriented T-shape. The vertically flat surface of the second source / drain region 30 can be exposed by self-alignment to one side of the storage contact node 29.

[0110] like Figure 11D As shown, a memory node-side ohmic contact 31 can be formed on the memory contact node 29 and the second source / drain region 30. The memory node-side ohmic contact 31 may include a metal silicide. For example, the metal silicide can be formed by sequentially depositing a metal layer on the memory contact node 29 and the second source / drain region 30 and annealing the metal layer, and unreacted metal layers can be removed. The metal silicide can be formed when the metal layer reacts with the silicon in the memory contact node 29 and the second source / drain region 30. The memory node-side ohmic contact 31 may simultaneously cover one side of the memory contact node 29 and one side of the second source / drain region 30.

[0111] like Figure 11E As shown, a memory node 32 can be formed that contacts the ohmic contact 31 on the memory node side. To form the memory node 32, a conductive material can be deposited, and an etch-back process can be performed on the conductive material. The memory node 32 may include titanium nitride. The memory node 32 may have a laterally oriented cylindrical shape.

[0112] like Figure 11F As shown, the outer wall of the storage node 32 can be exposed by recessing the intermediate dielectric layers 11 and 15 (see reference numeral 33).

[0113] like Figure 11G As shown, a dielectric layer 34 and a board node 35 can be sequentially formed above the storage node 32.

[0114] Figure 12 This is a cross-sectional view showing a memory cell according to another embodiment of the present invention. Figure 12 The memory cell MC11 can be similar to Figure 8The memory unit MC10.

[0115] Reference Figure 12 The memory cell MC11 may include a bit line BL, a transistor TR, and a capacitor CAP. The transistor TR may include an active layer ACT, a gate dielectric layer GD, and a double word line DWL. The active layer ACT may include a first source / drain region SR, a second source / drain region DR, and a channel CH between the first source / drain region SR and the second source / drain region DR. The capacitor CAP may include a memory node SN, a dielectric layer DE, and a board node PN. The bit line BL may have a cylindrical shape extending in a first direction D1. The active layer ACT may have a strip shape extending in a second direction D2 intersecting the first direction D1. The double word line DWL may have a linear shape extending in a third direction D3 intersecting the first direction D1 and the second direction D2. The double word line DWL may include a first word line WL1 and a second word line WL2. The board node PN of the capacitor CAP may be connected to a board line PL.

[0116] The bit-line side ohmic contact BOC can be formed between the first source / drain region SR and the bit line BL. The bit-line side ohmic contact BOC and the first source / drain region SR can be connected together to the bit line contact node BLC. The bit line contact node BLC can cover the upper surface, lower surface, and one side surface of the first source / drain region SR. The bit line contact node BLC can have a monolithic structure that simultaneously covers the upper surface, lower surface, and one side surface of the first source / drain region SR. The bit-line side ohmic contact BOC can be disposed between the bit line contact node BLC and the bit line BL. The height H1 of the bit-line side ohmic contact BOC can be increased by the bit line contact node BLC. The contact area between the bit line BL and the bit-line side ohmic contact BOC can be increased. The contact area between the bit line BL and the first source / drain region SR can also be increased.

[0117] The bit line contact node (BLC) may include polysilicon, such as polysilicon doped with N-type impurities. The height of the bit line-side ohmic contact (BOC), i.e., the thickness H1 of the bit line-side ohmic contact BOC in the first direction D1, may be greater than the thickness H2 of the active layer ACT in the first direction D1. The bit line-side ohmic contact BOC may have a height that completely covers one side of the bit line contact node (BLC).

[0118] When the silicon of the bit line contact node (BLC) reacts with the metal of the bit line (BL), a bit line-side ohmic contact (BOC) can be formed. The bit line-side ohmic contact (BOC) may include metal silicides.

[0119] A storage node-side ohmic contact SOC can be formed between the second source / drain region (DR) and the storage node (SN). The storage node-side ohmic contact SOC and the second source / drain region (DR) can be jointly connected to a storage contact node (SNC). The storage contact node (SNC) can cover the upper surface, lower surface, and one side of the second source / drain region (DR). The storage contact node (SNC) can have a monolithic structure that simultaneously covers the upper surface, lower surface, and one side of the second source / drain region (DR). The storage node-side ohmic contact SOC can be disposed between the storage contact node (SNC) and the storage node (SN). The height H1 of the storage node-side ohmic contact SOC can be increased by increasing the storage contact node (SNC), thereby increasing the contact area between the storage node (SN) and the storage node-side ohmic contact SOC. The contact area between the storage node (SN) and the second source / drain region (DR) can be increased.

[0120] The storage node-side ohmic contact SOC and the bit line-side ohmic contact BOC can have the same height. The storage contact node SNC can include polysilicon, such as polysilicon doped with N-type impurities. The height of the storage node-side ohmic contact SOC, i.e., its thickness H1 in the first direction D1, can be greater than the thickness H2 of the active layer ACT in the first direction D1. The second source / drain region DR can be doped with N-type impurities diffused from the storage contact node SNC. The storage node-side ohmic contact SOC can have a height that completely covers one side of the storage contact node SNC.

[0121] When silicon in the storage contact node (SNC) reacts with metal, a storage node-side ohmic contact (SOC) can be formed. The storage node-side ohmic contact (SOC) can include metal silicides.

[0122] Reference Figure 12 The bit-line side ohmic contact BOC and the first source / drain region SR do not need to be in direct contact with each other, and the storage node side ohmic contact SOC and the second source / drain region DR do not need to be in direct contact with each other. The bit-line side ohmic contact BOC can directly contact the bit-line contact node BLC. The storage node side ohmic contact SOC can directly contact the storage contact node SNC.

[0123] Figures 13A to 13E This is a diagram illustrating a method for manufacturing a semiconductor memory device according to another embodiment of the present invention. Figures 13A to 13E The method shown can be similar to Figures 10A to 10H Perform as shown.

[0124] First, such as Figures 10A to 10D As shown, a padding layer 20 can be formed that contacts one side of the double letter line 19. The padding layer 20 can be disposed in the groove 17.

[0125] Next, the first end E1 of the first portion P1 of the semiconductor layer 13 can be exposed by etching a portion of the gate dielectric layer 18.

[0126] like Figure 13A As shown, the exposed first end E1 of the semiconductor layer 13 can be recessed by a predetermined thickness in the lateral direction. Therefore, a first end E1' with a reduced lateral length can be formed.

[0127] like Figure 13B As shown, opening 16 can be filled with a conductive layer 21' including impurities. The conductive layer 21' can be polycrystalline silicon containing N-type impurities such as phosphorus.

[0128] Subsequent heat treatment can be performed to allow impurities to diffuse from the conductive layer 21' into the semiconductor layer 13. Therefore, a first source / drain region 22 can be formed at the first end E1' of the semiconductor layer 13.

[0129] like Figure 13C As shown, bit line contact nodes 23' that fill the remaining space of groove 17 can be formed by recessing the conductive layer 21'.

[0130] The groove 17 can be filled with a double word line 19, a pad layer 20, and a bit line contact node 23'. The bit line contact node 23' can have a monolithic structure and can simultaneously cover the vertically flat surface and the horizontally flat surface of the first end E1' of the semiconductor layer 13.

[0131] like Figure 13D As shown, a bit-line side ohmic contact 24' can be formed on the bit-line contact node 23'. The bit-line side ohmic contact 24' may include a metal silicide. For example, the metal silicide can be formed by sequentially depositing a metal layer on the bit-line contact node 23' and annealing the metal layer, and unreacted metal layers can be removed. When the silicon of the bit-line contact node 23' interacts with the metal layer, a metal silicide can be formed.

[0132] like Figure 13E As shown, a bit line BL can be formed that contacts the bit line-side ohmic contact 24'. The bit line BL may include a bit line block 25 and a bit line body 26, and the bit line block 25 may contact the bit line-side ohmic contact 24'. The bit line block 25 may include titanium nitride, and the bit line body 26 may include tungsten.

[0133] In another embodiment of the invention, the bit line-side ohmic contact 24' can be formed simultaneously with the bit line barrier 25. For example, as the bit line barrier 25, a titanium / titanium nitride (Ti / TiN) stack can be deposited and annealed. In this case, titanium can be silicided to form titanium silicide, which can be used as the bit line-side ohmic contact 24', and the titanium nitride can become the bit line barrier 25.

[0134] In one implementation, bit line contact node 23' can be used instead. Figures 1 to 9 Bit line contact node BLC.

[0135] After the bit line BL is formed, it can be like this: Figures 11A to 11G The diagram illustrates the formation of storage contact nodes and capacitors. In another embodiment of the invention, the method for forming storage contact nodes can be similar to that shown below. Figures 13A to 13E The method for forming bit line contact node 23' shown is performed. Therefore, the storage contact node can cover the vertically flat surface and the horizontally flat surface of the second source / drain region 30.

[0136] Figure 14A and Figure 14B This is a cross-sectional view of a memory cell according to another embodiment of the present invention. Figure 14A and Figure 14B In the middle, the part with can be omitted. Figures 1 to 9 Detailed description of the repeating parts.

[0137] Reference Figure 14A and Figure 14B Memory cells MC20 and MC21 may include bit lines BL, transistors TR including double word lines, and capacitors CAP. The double word lines may be formed by a pair of first word lines WL1 and second word lines WL2 with an active layer ACT interposed between them. Each of memory cells MC20 and MC21 may include a bit line contact node BLC, a bit line-side ohmic contact BOC, a memory contact node SNC, and a memory node-side ohmic contact SOC. Figure 14A In the memory cell MC20, both the bit line contact node (BLC) and the storage contact node (SNC) can have a dual structure. Figure 14B In the memory cell MC21, both the bit line contact node (BLC) and the storage contact node (SNC) can have a single-unit structure.

[0138] The first word line WL1 and the second word line WL2 may each include a low work function electrode LWG and a high work function electrode HWG. The low work function electrode LWG and the high work function electrode HWG may be laterally disposed along the second direction D2. The low work function electrode LWG may be adjacent to the second source / drain region DR, while the high work function electrode HWG may be adjacent to the first source / drain region SR. The low work function electrode LWG and the high work function electrode HWG are formed of different work function materials. The high work function electrode HWG has a higher work function than the low work function electrode LWG. The high work function electrode HWG comprises a high work function material. In one embodiment, the high work function electrode HWG may have a work function higher than the mid-gap work function of silicon. The low work function electrode LWG is a material with a work function lower than the mid-gap work function of silicon. In other words, the high work function material may have a work function higher than 4.5 eV, while the low work function material may have a work function lower than 4.5 eV. The low work function electrode LWG may comprise polycrystalline silicon doped with an N-type dopant. The high work function electrode (HWG) may include a metal-based material. The HWG may include tungsten, titanium nitride, or a combination thereof. A barrier may be further formed between the low work function electrode (LWG) and the high work function electrode (HWG).

[0139] The low work function electrode LWG can be adjacent to the capacitor CAP. The low work function electrode LWG can be positioned between the storage contact node SNC and the high work function electrode HWG. The high work function electrode HWG can be adjacent to the bit line BL. The high work function electrode HWG can be positioned between the bit line contact node BLC and the low work function electrode LWG. The high work function electrode HWG and the low work function electrode LWG can be in contact with each other and (when along...) Figure 14A When observing the orientation, they can be positioned at the same level.

[0140] As mentioned above, gate-drain induced leakage (GIDL) can be suppressed by forming a low work function electrode (LWG).

[0141] Figure 15 This is a schematic perspective view of a memory cell according to another embodiment of the present invention.

[0142] Reference Figure 15The memory cell MC31 of the 3D semiconductor memory device may include a bit line BL, a transistor TR, and a capacitor CAP. The transistor TR may include an active layer ACT, a gate dielectric layer GD, and a single-word line SWL. The active layer ACT may include a first source / drain region SR, a second source / drain region DR, and a channel CH between the first source / drain region SR and the second source / drain region DR. The capacitor CAP may include a memory node SN, a dielectric layer DE, and a board node PN. The bit line BL may have a cylindrical shape extending in a first direction D1. The active layer ACT may have a strip shape extending in a second direction D2 intersecting the first direction D1. The single-word line SWL may have a linear shape extending in a third third direction D3 intersecting the first direction D1 and the second direction D2. The board node PN of the capacitor CAP may be connected to the board line PL.

[0143] The bit-line side ohmic contact BOC can be formed between the first source / drain region SR and the bit line BL. The bit-line side ohmic contact BOC and the first source / drain region SR can be jointly connected to the bit line contact node BLC. The bit line contact node BLC can be connected to the upper and lower surfaces of the first source / drain region SR, respectively. The bit line contact node BLC can have a dual structure, such that the bit line contact node BLC is respectively disposed on the upper and lower surfaces of the first source / drain region SR. The bit-line side ohmic contact BOC can be disposed between the bit line contact node BLC and the bit line BL. The height H1 of the bit-line side ohmic contact BOC can be increased by the bit line contact node BLC. The contact area between the bit line BL and the bit-line side ohmic contact BOC can be increased. The contact area between the bit line BL and the first source / drain region SR can also be increased.

[0144] The bit line contact node (BLC) may include polysilicon, such as polysilicon doped with N-type impurities. The height of the bit line-side ohmic contact (BOC), i.e., the thickness H1 of the bit line-side ohmic contact BOC in the first direction D1, may be greater than the thickness H2 of the active layer ACT in the first direction D1. The bit line-side ohmic contact BOC may have a height that completely covers the side surface of the bit line contact node (BLC) and the side surface of the first source / drain region (SR).

[0145] When the silicon of the bit line contact node BLC and the first source / drain region SR reacts with the metal of the bit line BL, a bit line-side ohmic contact BOC can be formed. The bit line-side ohmic contact BOC may include metal silicide.

[0146] A storage node-side ohmic contact SOC can be formed between the second source / drain region DR and the storage node SN. The storage node-side ohmic contact SOC and the second source / drain region DR can be jointly connected to a storage contact node SNC. The storage contact node SNC can be connected to the upper and lower surfaces of the second source / drain region DR, respectively. The storage contact node SNC can have a dual structure, such that it is disposed on both the upper and lower surfaces of the second source / drain region DR. The storage node-side ohmic contact SOC can be disposed between the storage contact node SNC and the storage node SN. The height H1 of the storage node-side ohmic contact SOC can be increased by increasing the storage contact node SNC, thereby increasing the contact area between the storage node SN and the storage node-side ohmic contact SOC. The contact area between the storage node SN and the second source / drain region DR can be increased.

[0147] The memory node-side ohmic contact SOC and the bit line-side ohmic contact BOC can have the same height. The memory contact node SNC can include polysilicon, such as polysilicon doped with N-type impurities. The height of the memory node-side ohmic contact SOC, i.e., the thickness H1 of the memory node-side ohmic contact SOC in the first direction D1, can be greater than the thickness H2 of the active layer ACT. The second source / drain region DR can be doped with N-type impurities diffused from the memory contact node SNC. The memory node-side ohmic contact SOC can have a height that completely covers the side surface of the memory contact node SNC and the side surface of the second source / drain region DR.

[0148] When the silicon of the storage contact node (SNC) and the second source / drain region (DR) reacts with metal, a storage node-side ohmic contact SOC can be formed. The storage node-side ohmic contact SOC may include metal silicides.

[0149] In another embodiment of the present invention, the storage node-side ohmic contact SOC and the storage contact node SNC can be as follows: Figure 1 The image shown is omitted.

[0150] In another embodiment of the invention, each of the bit line contact node (BLC) and the storage contact node (SNC) may have the following characteristics: Figure 12 The shown is a monomer structure.

[0151] In another embodiment of the present invention, the single-word line (SWL) may include, for example: Figure 14A The low work function electrode and the high work function electrode are shown.

[0152] In another embodiment of the present invention, the memory unit MC31 can be configured as follows: Figure 3 The memory cell array shown.

[0153] Figure 16This is a schematic perspective view illustrating a memory cell according to another embodiment of the present invention.

[0154] Reference Figure 16 The memory cell MC32 of the 3D semiconductor memory device may include a bit line BL, a transistor TR, and a capacitor CAP. The transistor TR may include an active layer ACT, a gate dielectric layer GD, and a gate-encircling word line GAA-WL. The active layer ACT may include a first source / drain region SR, a second source / drain region DR, and a channel CH between the first source / drain region SR and the second source / drain region DR. The capacitor CAP may include a memory node SN, a dielectric layer DE, and a plate node PN. The bit line BL may have a cylindrical shape extending in a first direction D1. The active layer ACT may have a strip shape extending in a second direction D2 intersecting the first direction D1. The gate-encircling word line GAA-WL may have a linear shape extending in a third direction D3 intersecting the first direction D1 and the second direction D2. The plate node PN of the capacitor CAP may be connected to a plate line PL. The gate-encircling word line GAA-WL may surround the active layer ACT.

[0155] The bit-line side ohmic contact BOC can be formed between the first source / drain region SR and the bit line BL. The bit-line side ohmic contact BOC and the first source / drain region SR can be jointly connected to the bit line contact node BLC. The bit line contact node BLC can be connected to the upper and lower surfaces of the first source / drain region SR, respectively. The bit line contact node BLC can have a dual structure with the bit line contact node BLC respectively disposed on the upper and lower surfaces of the first source / drain region SR. The bit-line side ohmic contact BOC can be disposed between the bit line contact node BLC and the bit line BL. The height H1 of the bit-line side ohmic contact BOC can be increased by the bit line contact node BLC. The contact area between the bit line BL and the bit-line side ohmic contact BOC can be increased. The contact area between the bit line BL and the first source / drain region SR can also be increased.

[0156] The bit line contact node (BLC) may include polysilicon, such as polysilicon doped with N-type impurities. The height of the bit line-side ohmic contact (BOC), i.e., the thickness H1 of the bit line-side ohmic contact BOC in the first direction D1, may be greater than the thickness H2 of the active layer ACT in the first direction D1. The bit line-side ohmic contact BOC may have a height that completely covers the side surface of the bit line contact node (BLC) and the side surface of the first source / drain region (SR).

[0157] When the silicon of the bit line contact node BLC and the first source / drain region SR reacts with the metal of the bit line BL, a bit line-side ohmic contact BOC can be formed. The bit line-side ohmic contact BOC may include metal silicide.

[0158] A storage node-side ohmic contact SOC can be formed between the second source / drain region DR and the storage node SN. The storage node-side ohmic contact SOC and the second source / drain region DR can be jointly connected to a storage contact node SNC. The storage contact node SNC can be connected to the upper and lower surfaces of the second source / drain region DR, respectively. The storage contact node SNC can have a dual structure with the storage contact node SNC disposed on both the upper and lower surfaces of the second source / drain region DR. The storage node-side ohmic contact SOC can be disposed between the storage contact node SNC and the storage node SN. The height H1 of the storage node-side ohmic contact SOC can be increased by increasing the storage contact node SNC, thereby increasing the contact area between the storage node SN and the storage node-side ohmic contact SOC. The contact area between the storage node SN and the second source / drain region DR can be increased.

[0159] The memory node-side ohmic contact SOC and the bit line-side ohmic contact BOC can have the same height. The memory contact node SNC can include polysilicon, such as polysilicon doped with N-type impurities. The height of the memory node-side ohmic contact SOC, i.e., its thickness H1 in the first direction D1, can be greater than the thickness H2 of the active layer ACT in the first direction D1. The second source / drain region DR can be doped with N-type impurities diffused from the memory contact node SNC. The memory node-side ohmic contact SOC can have a height that completely covers the side surface of the memory contact node SNC and the side surface of the second source / drain region DR.

[0160] When the silicon of the storage contact node (SNC) and the second source / drain region (DR) reacts with metal, a storage node-side ohmic contact SOC can be formed. The storage node-side ohmic contact SOC may include metal silicides.

[0161] In another embodiment of the present invention, the storage node-side ohmic contact SOC and the storage contact node SNC can be as follows: Figure 1 The image shown is omitted.

[0162] In another embodiment of the invention, each of the bit line contact node (BLC) and the storage contact node (SNC) may have the following characteristics: Figure 12 The shown is a monomer structure.

[0163] In another embodiment of the invention, the gate all-around word line GAA-WL may include, for example: Figure 14A The low work function electrode and the high work function electrode are shown.

[0164] In another embodiment of the invention Figure 16 The memory cell MC32 can be configured as follows: Figure 3 The memory cell array shown.

[0165] The present invention described above is not limited to the above embodiments and drawings, and it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A semiconductor memory device, comprising: A transistor extending laterally in a direction parallel to a substrate and including an active layer above the substrate, the active layer having a first end and a second end; Bit line contact nodes are formed on the upper and lower surfaces of the first end of the active layer, respectively; The bit line side ohmic contact extends vertically and is connected to the first end of the active layer and the bit line contact node; Bit lines extend in a direction perpendicular to the substrate and connect to the bit line-side ohmic contacts; A capacitor is connected to the second end of the active layer.

2. The semiconductor memory device according to claim 1, wherein, The active layer includes: Ditch; A first source / drain region is disposed on one side of the channel and connected to the bit line-side ohmic contact and the bit line contact node; and A second source / drain region is located on the other side of the channel and is connected to the capacitor.

3. The semiconductor memory device according to claim 2, wherein, The bit-line side ohmic contact has a height that completely covers the side surface of the bit-line contact node and the side surface of the first source / drain region.

4. The semiconductor memory device according to claim 1, wherein, The bit-line side ohmic contact comprises metal silicide.

5. The semiconductor memory device according to claim 1, wherein, The bit line contact node comprises doped polycrystalline silicon.

6. The semiconductor memory device according to claim 1, wherein, The active layer includes monocrystalline silicon, polycrystalline silicon, germanium, silicon-germanium, or indium gallium zinc oxide (IGZO).

7. The semiconductor memory device according to claim 1, wherein, The bit line contact node covers the upper surface, lower surface, and side surface of the first end of the active layer.

8. The semiconductor memory device of claim 1, further comprising word lines extending above the active layer in a direction intersecting the active layer. in, The active layer includes a thin-body channel that is thinner than the word line.

9. The semiconductor memory device according to claim 8, wherein, The word line includes at least one of a double word line, a single word line, and a gate-wrapped word line.

10. A semiconductor memory device, comprising: A transistor extending laterally in a direction parallel to a substrate and including an active layer above the substrate, the active layer having a first end and a second end; Bit line contact nodes are formed on the upper and lower surfaces of the first end of the active layer, respectively; The bit-line side ohmic contact extends vertically and is connected to the first end of the active layer and the bit-line contact node; Bit lines extend in a direction perpendicular to the substrate and connect to the bit line-side ohmic contacts; Storage contact nodes are formed on the upper and lower surfaces of the second end of the active layer, respectively; An ohmic contact on the storage node side extends vertically and connects to the second end of the active layer and the storage contact node; as well as A capacitor is connected to the ohmic contact on the storage node side.

11. The semiconductor memory device according to claim 10, wherein, The active layer includes: Ditch; A first source / drain region is disposed on one side of the channel and connected to the bit line-side ohmic contact and the bit line contact node; and The second source / drain area is located on the other side of the channel and connected to the storage node-side ohmic contact and the storage contact node.

12. The semiconductor memory device according to claim 11, wherein, The bit-line side ohmic contact has a height that completely covers the side surface of the bit-line contact node and the side surface of the first source / drain region.

13. The semiconductor memory device according to claim 11, wherein, The storage node-side ohmic contact has a height that completely covers the side surface of the storage contact node and the side surface of the second source / drain region.

14. The semiconductor memory device of claim 10, wherein, The bit-line side ohmic contact and the memory node side ohmic contact comprise metal silicide.

15. The semiconductor memory device according to claim 10, wherein, Each of the bit line contact node and the storage contact node comprises doped polysilicon.

16. The semiconductor memory device according to claim 10, wherein, The active layer includes monocrystalline silicon, polycrystalline silicon, germanium, silicon-germanium, or indium gallium zinc oxide (IGZO).

17. The semiconductor memory device according to claim 10, wherein, The capacitor includes a cylindrical storage node connected to an ohmic contact on the storage node side.

18. The semiconductor memory device of claim 10, further comprising word lines extending in a direction intersecting the active layer.

19. The semiconductor memory device according to claim 18, wherein, The word line includes at least one of a double word line, a single word line, and a gate-wrapped word line.

20. The semiconductor memory device of claim 18, wherein, The word lines include: High work function electrode, adjacent to the bit line; and A low work function electrode, which has a lower work function than the high work function electrode, is located adjacent to the capacitor.

21. The semiconductor memory device according to claim 20, in, The high work function electrode comprises a metal-based material, and The low work function electrode comprises polycrystalline silicon doped with N-type impurities.

22. The semiconductor memory device according to claim 10, in, The bit line contact node covers the upper surface, lower surface, and side surface of the first end of the active layer, and The storage contact node covers the upper surface, lower surface, and side surface of the second end of the active layer.

23. A method for manufacturing a semiconductor memory device, the method comprising: A stack is formed, the stack being laterally oriented and including an active layer, the active layer including a first end and a second end; First contact nodes are formed on the upper and lower surfaces of the first end of the active layer, respectively; A first ohmic contact is formed, the first ohmic contact being vertically oriented to cover the first contact node and the first end of the active layer; as well as A first conductive layer is formed, which is connected to the first ohmic contact and is oriented perpendicularly in a direction intersecting the active layer.

24. The method according to claim 23, wherein, The first contact node has a dual structure, such that the first contact node is respectively disposed on the upper surface and the lower surface of the first end of the active layer.

25. The method according to claim 23, wherein, The first contact node covers the upper surface, lower surface and side surface of the first end of the active layer.

26. The method according to claim 23, wherein, The first contact node comprises polycrystalline silicon, and the first ohmic contact comprises metal silicide.

27. The method according to claim 23, wherein, The first conductive layer includes bit lines.

28. The method of claim 23, further comprising, after forming the first conductive layer: Second contact nodes are formed on the upper and lower surfaces of the second end of the active layer, respectively; A second ohmic contact is formed, the second ohmic contact being vertically oriented to cover the second contact node and the second end of the active layer; as well as A second conductive layer is formed to connect to the second ohmic contact.

29. The method according to claim 28, wherein, The second contact node has a dual structure, such that the second contact node is respectively disposed on the upper and lower surfaces of the second end of the active layer.

30. The method according to claim 28, wherein, The second contact node covers the upper surface, lower surface and side surface of the second end of the active layer.

31. The method according to claim 28, wherein, The second contact node comprises polycrystalline silicon, and the second ohmic contact comprises metal silicide.

32. The method according to claim 28, wherein, The second conductive layer includes the storage nodes of the capacitor.

33. The method of claim 32, further comprising, before forming the first contact node: The active layer is inserted between the wires, forming wires that face each other.

34. The method of claim 33, wherein, Each of the wires includes: A high work function electrode is adjacent to the first end of the active layer; and A low work function electrode, which has a lower work function than the high work function electrode and is adjacent to the capacitor.

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