Semiconductor structure, method of fabricating the same, and memory system

Abstract

The embodiments of the present disclosure disclose a semiconductor structure, a manufacturing method thereof and a memory system. The semiconductor structure comprises: a semiconductor layer, the semiconductor layer is provided with a plurality of active pillars extending along a first direction, a gate structure located on one side of the active pillar, a first insulating layer located between two adjacent active pillars, and a first electrode provided at one end of the active pillar along the first direction; the first direction is the thickness direction of the semiconductor layer; a second insulating layer is located on the semiconductor layer; a plurality of connection structures, each of the connection structures is at least partially located in the second insulating layer; the connection structure is connected with the first electrode, and the width of the connection structure in the second direction is greater than the width of the first electrode in the second direction; the second direction is perpendicular to the first direction.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, specifically to a semiconductor structure and its fabrication method, and a memory system. Background Technology

[0002] The memory array architecture of Dynamic Random Access Memory (DRAM) consists of an array of memory cells including transistors and capacitors.

[0003] As the size of dynamic random access memory (DRAM) continues to shrink, so too does the size of transistors. Ensuring a good connection between capacitors and transistors in DRAM has become a pressing issue.

[0004] Public content

[0005] In view of the above, this disclosure provides a semiconductor structure, a method for fabricating the same, and a memory system.

[0006] According to one aspect of this disclosure, a semiconductor structure is provided, comprising:

[0007] A semiconductor layer, wherein a plurality of active pillars extending along a first direction are disposed therein, a gate structure located on one side of the active pillars, a first insulating layer located between two adjacent active pillars, and a first electrode disposed at one end of the active pillars along the first direction; the first direction is the thickness direction of the semiconductor layer;

[0008] A second insulating layer is located on the semiconductor layer;

[0009] A plurality of connection structures, each of which is at least partially located in the second insulating layer; the connection structure is connected to the first electrode, and the width of the connection structure in the second direction is greater than the width of the first electrode in the second direction; the second direction is perpendicular to the first direction.

[0010] In the above scheme, each of the connection structures is located in the second insulating layer and in the first insulating layer.

[0011] In the above scheme, the first insulating layer includes a first sub-insulating layer, a second sub-insulating layer, and a third sub-insulating layer; the plurality of active pillars are arranged in an array along the second direction and the third direction, and two adjacent active pillars along the second direction constitute an active pillar unit; the third direction is perpendicular to the first direction and intersects the second direction;

[0012] The first sub-insulating layer and the second sub-insulating layer are both located between two adjacent active pillar units. The first sub-insulating layer covers the sidewalls of the two adjacent active pillar units, and the second sub-insulating layer covers the sidewalls of the first sub-insulating layer, and a cavity is formed in the second sub-insulating layer. The third sub-insulating layer is located between two active pillars of each active pillar unit. The gate structure is located in the third sub-insulating layer.

[0013] In the above scheme, the material of the connecting structure includes metal compounds.

[0014] In the above scheme, the first insulating layer and the second insulating layer are made of different materials.

[0015] In the above scheme, the material of the first insulating layer includes silicon oxide, and the material of the second insulating layer includes silicon nitride.

[0016] In the above scheme, the width of the first electrode in the second direction is less than the first preset value.

[0017] In the above scheme, the first preset value is 25nm.

[0018] In the above scheme, the semiconductor layer has a first side and a second side opposite to each other along the first direction, and the plurality of active pillars are close to the first side;

[0019] The semiconductor structure also includes:

[0020] A second electrode is located at the other end of the active post along the first direction;

[0021] Multiple bit lines are located on the second side and connected to the second electrode.

[0022] In the above scheme, the semiconductor structure further includes multiple memory structures, which are connected to the connection structure.

[0023] In the above scheme, the semiconductor structure includes a dynamic random access memory, and the storage structure includes a storage capacitor.

[0024] According to another aspect of this disclosure, a memory system is provided, comprising: one or more semiconductor structures as described in any of the above embodiments; and

[0025] A memory controller, which is connected to and controls the semiconductor structure.

[0026] According to another aspect of this disclosure, a method for fabricating a semiconductor structure is provided, the method comprising:

[0027] A semiconductor layer is provided, wherein a plurality of active pillars extending along a first direction, a gate structure located on one side of the active pillars, and a first insulating layer located between two adjacent active pillars are formed in the semiconductor layer; wherein a first doped region is provided at one end of the active pillar along the first direction, and the first direction is the thickness direction of the semiconductor layer;

[0028] Part of the first insulating layer is removed to form multiple first grooves;

[0029] A second insulating layer is formed in the first groove;

[0030] At least a portion of the first doped region and a portion of the second insulating layer are removed to form a plurality of second grooves, and the remaining first doped region forms a first electrode; the width of the second groove in the second direction is greater than the width of the first electrode in the second direction, and the second direction is perpendicular to the first direction;

[0031] A connecting structure is formed in the second groove.

[0032] In the above scheme, the step of removing at least a portion of the first doped region and a portion of the second insulating layer to form a plurality of second grooves includes:

[0033] A portion of the first doped region is removed to form multiple third grooves; the top surface of the first electrode is flush with the top surface of the first insulating layer.

[0034] A portion of the second insulating layer and a portion of the first insulating layer are removed from the sidewall of the third groove to enlarge the third groove and form the second groove.

[0035] In the above scheme, the removal of a portion of the first doped region includes:

[0036] A portion of the first doped region was removed using a dry etching process;

[0037] Removing a portion of the second insulating layer and a portion of the first insulating layer, including:

[0038] A portion of the first insulating layer is removed using a dry etching process, and a portion of the second insulating layer is removed using a wet etching process.

[0039] In the above scheme, the material of the second insulating layer is different from the material of the first insulating layer.

[0040] In the above solution, forming a connecting structure in the second groove includes:

[0041] Semiconductor material pillars are formed in the second groove;

[0042] A metal material layer is formed on the semiconductor material pillar;

[0043] The semiconductor material pillars and the metal material layer are annealed to form a connection structure.

[0044] In the above scheme, forming a semiconductor material pillar in the second groove includes:

[0045] Semiconductor material pillars are formed in the second groove using an epitaxial growth process.

[0046] In the above scheme, the first insulating layer includes a first sub-insulating layer, a second sub-insulating layer, and a third sub-insulating layer; the plurality of active pillars are arranged in an array along the second direction and the third direction, and two adjacent active pillars along the second direction constitute an active pillar unit; the third direction is perpendicular to the first direction and intersects the second direction;

[0047] The first sub-insulating layer and the second sub-insulating layer are both located between two adjacent active pillar units. The first sub-insulating layer covers the sidewalls of the two adjacent active pillar units, and the second sub-insulating layer covers the sidewalls of the first sub-insulating layer, and a cavity is formed in the second sub-insulating layer. The third sub-insulating layer is located between two active pillars of each active pillar unit. The gate structure is located in the third sub-insulating layer.

[0048] In the above scheme, the semiconductor layer has a first side and a second side opposite to each other along the first direction, and the plurality of active pillars are close to the first side;

[0049] The method further includes:

[0050] A second electrode is formed, the second electrode being located at the other end of the active post along the first direction;

[0051] The semiconductor layer is thinned from the second side to expose the second electrode;

[0052] Multiple bit lines are formed; the bit lines are connected to the second electrode.

[0053] The method in the above scheme further includes:

[0054] A storage structure is formed that is connected to the connection structure.

[0055] This disclosure provides a semiconductor structure and its fabrication method, as well as a memory system. The semiconductor structure fabrication method includes: providing a semiconductor layer, wherein a plurality of active pillars extending along a first direction, a gate structure located on one side of the active pillars, and a first insulating layer located between two adjacent active pillars are formed in the semiconductor layer; wherein a first doped region is disposed at one end of the active pillar along the first direction, the first direction being the thickness direction of the semiconductor layer; at least a portion of the first insulating layer is removed to form a plurality of first grooves; a second insulating layer is formed in the first grooves; a portion of the first doped region and a portion of the second insulating layer are removed to form a plurality of second grooves, the remaining first doped region forming a first electrode; the width of the second groove in a second direction is greater than the width of the first electrode in the second direction, the second direction being perpendicular to the first direction; and a connection structure is formed in the second groove. In this embodiment, a portion of the first insulating layer between multiple active pillars is first removed to form multiple first grooves. A second insulating layer is then formed in the first grooves. Next, a portion of the first doped region and a portion of the second insulating layer are removed, and a connection structure is formed in the second groove. Since the width of the second groove in the second direction is greater than the width of the first electrode in the second direction, this improves the problem that when the first doped region is directly used to form the connection structure, the small size effect occurs during the formation of the connection structure due to the small width of the first doped region in the second direction, resulting in poor connection effect of the formed connection structure, large contact resistance between the memory structure and the transistor, and thus reduced performance of the semiconductor structure. Attached Figure Description

[0056] Figure 1 This is a schematic diagram of the structure of a DRAM memory cell provided in an embodiment of the present disclosure;

[0057] Figures 2-7 A cross-sectional schematic diagram of the manufacturing process of a semiconductor structure provided in an embodiment of this disclosure;

[0058] Figure 8a A schematic diagram illustrating the relationship between annealing temperature and crystal phase of a metal compound provided in this embodiment of the disclosure;

[0059] Figure 8b A schematic diagram illustrating the relationship between metal silicide thickness or linewidth and temperature, provided in an embodiment of this disclosure.

[0060] Figure 9a An electron microscope schematic diagram of a semiconductor structure provided in this embodiment of the present disclosure. Figure 1 ;

[0061] Figure 9b An electron microscope schematic diagram of a semiconductor structure provided in this embodiment of the present disclosure. Figure 2 ;

[0062] Figure 10 A schematic flowchart illustrating a method for manufacturing a semiconductor structure according to an embodiment of this disclosure;

[0063] Figures 11-19 A cross-sectional schematic diagram of the manufacturing process of another semiconductor structure provided in this disclosure embodiment;

[0064] Figures 20-27 A cross-sectional schematic diagram of the manufacturing process of another semiconductor structure provided in this disclosure embodiment;

[0065] Figure 28 This is a three-dimensional structural diagram of a semiconductor structure provided in an embodiment of the present disclosure. Detailed Implementation

[0066] To make the technical solutions and advantages of the embodiments of this disclosure clearer, the technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary implementation methods of this disclosure are shown in the accompanying drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the implementation methods set forth herein. Rather, these implementation methods are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art.

[0067] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.

[0068] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.

[0069] Furthermore, for ease of description, spatial relative terms such as “on,” “above,” “above,” “upper,” “above,” “upper,” etc., may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figures. In addition to the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0070] In embodiments of this disclosure, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include various semiconductor materials, such as silicon, silicon germanium, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafer.

[0071] In embodiments of this disclosure, the term "layer" refers to a portion of material including a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers. For example, an interconnect layer may include one or more conductor and contact sublayers (where interconnect lines and / or via contacts are formed), and one or more dielectric sublayers.

[0072] In the embodiments of this disclosure, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0073] The semiconductor structure disclosed herein is at least a portion of the structure that will be used in subsequent processes to form the final device structure. Here, the final device may include a memory, including but not limited to dynamic random access memory (DRAM). The following description uses DRAM as an example only.

[0074] However, it should be noted that the following description of dynamic random access memory is only for illustrating this disclosure and is not intended to limit the scope of this disclosure.

[0075] In some embodiments of this disclosure, the dynamic random access memory is composed of multiple memory cell structures. Each memory cell structure mainly consists of a transistor and a memory cell (storage capacitor) controlled by the transistor. That is, the dynamic random access memory includes an architecture of 1 transistor (T) and 1 capacitor (C) (1T1C). Its main working principle is to use the amount of charge stored in the capacitor to represent whether a binary bit is 1 or 0.

[0076] Figure 1 This is a circuit connection diagram of a 1T1C architecture provided in an embodiment of this disclosure; as shown... Figure 1As shown, the drain of transistor T is electrically connected to the bit line (BL), and the source of transistor T is electrically connected to one of the electrode plates of capacitor C. The other electrode plate of capacitor C can be connected to a reference voltage, which can be ground or other voltages. The gate of transistor T is connected to the word line (WL). The transistor T is turned on or off by applying a voltage through the word line WL. The bit line BL is used to perform read or write operations on transistor T when it is turned on.

[0077] As memory technology advances, the size of dynamic random access memory (DRAM) is constantly shrinking, and the size of transistors is also shrinking. This makes it increasingly difficult to create a connection structure that provides good connectivity between transistors and capacitors.

[0078] This disclosure provides a method for fabricating a semiconductor structure, the method comprising: as follows: Figure 2 As shown, a first doped region 112 is formed at one end of the active pillar 109, and a first insulating layer 108 is formed on both sides of the active pillar 109; next, as Figure 3 As shown, the first doped region 112 is etched back to form the fourth groove 104, and the remaining first doped region forms the first electrode 113 of the transistor; as Figure 4 As shown, a metal material layer 118 is formed on the sidewalls, bottom wall, and first insulating layer of the fourth groove 104; as Figure 5 As shown, a connecting structure 119 composed of a metal compound is formed by two annealing processes, and the remaining metal material layer 118 is removed; as Figure 6 As shown, a conductive material layer 121 is deposited on the connection structure 119 and the first insulating layer 108; as Figure 7 As shown, the planarization process removes the conductive material layer 121 on the first insulating layer 108, and makes the top surface of the conductive material layer 121 flush with the top surface of the first insulating layer 108, and the remaining conductive material layer 121 forms a conductive structure 120.

[0079] In the semiconductor structure fabrication method provided in the above embodiments, two annealing processes are required. Figure 8a This is a schematic diagram illustrating the relationship between annealing temperature and crystal phase of a metal compound provided in embodiments of this disclosure, as shown below. Figure 8a As shown, the first annealing causes the metal material layer 118 to react with a portion of the first doped region 112 to form a high-resistivity metal compound with phase C49. The reaction temperature of the first annealing is lower than T1. The second annealing requires a higher temperature to convert phase C49 into a low-resistivity metal compound with phase C54. The reaction temperature of the second annealing is lower than T2 but higher than T1. When the reaction temperature is higher than T2, agglomeration occurs. Metal compounds, such as metal silicides, have a fatal drawback in their formation. Figure 8bThis is a schematic diagram illustrating the relationship between metal silicide thickness or linewidth and temperature, as provided in the embodiments of this disclosure. Figure 8b As shown, as the thickness or linewidth of the metal silicide decreases, the critical temperature T1 for the transition from the C49 phase to the C54 phase increases, while the critical temperature T2 for the clumping of the C54 phase decreases. This can lead to a critical point where T1 = T2, or even T2 being less than T1. If T2 is less than T1, the metal silicide will directly clumpe after entering the C49 phase, and the C54 phase interval will not exist at all. In other words, the process conditions for reducing the resistivity of the metal silicide cannot be found.

[0080] Research has found that in the semiconductor structure fabrication method provided in the above embodiments, the metal compound is formed directly using the first doped region at one end of the active pillar. Because the active pillar is relatively small, typically a columnar body 20 nm long and 10 nm wide, a small-size effect occurs during metal compound formation. Due to aggregation and continuous silicon consumption, breakage is likely to occur during subsequent heat treatment. This results in poor connection performance of the formed interconnect structure, high contact resistance between the capacitor and transistor, and consequently, reduced semiconductor structure performance. Figure 9a An electron microscope schematic diagram of a semiconductor structure provided in this embodiment of the present disclosure. Figure 1 ; Figure 9b An electron microscope schematic diagram of a semiconductor structure provided in this embodiment of the present disclosure. Figure 2 ;from Figure 9a as well as Figure 9b As shown in the dashed box, some of the connecting structures are broken, resulting in poor connection performance.

[0081] In view of this, in order to solve the above problems, this disclosure provides another method for fabricating a semiconductor structure, which can form a connection structure with low contact resistance between the capacitor and the transistor. Figure 10 This is a schematic flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this disclosure. Figure 10 As shown, the method for fabricating a semiconductor structure provided in this embodiment includes the following steps:

[0082] S100: A semiconductor layer is provided, wherein a plurality of active pillars extending along a first direction, a gate structure located on one side of the active pillars, and a first insulating layer located between two adjacent active pillars are formed in the semiconductor layer; wherein a first doped region is provided at one end of the active pillar along the first direction, and the first direction is the thickness direction of the semiconductor layer;

[0083] S200: Remove part of the first insulating layer to form multiple first grooves;

[0084] S300: A second insulating layer is formed in the first groove;

[0085] S400: At least a portion of the first doped region and a portion of the second insulating layer are removed to form a plurality of second grooves, and the remaining first doped region forms a first electrode; the width of the second groove in the second direction is greater than the width of the first electrode in the second direction, and the second direction is perpendicular to the first direction;

[0086] S500: A connecting structure is formed in the second groove.

[0087] It should be understood that Figure 10 The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown in the method. Figure 10 The steps shown can be adjusted in order according to actual needs. Figures 11 to 19 This is a cross-sectional schematic diagram illustrating the fabrication process of a semiconductor structure according to an embodiment of this disclosure. It should be noted that... Figures 11 to 19 This is a schematic diagram illustrating the complete manufacturing process of a semiconductor structure. Unmarked parts in some of the accompanying drawings can be shared. The following section combines... Figure 10 , Figures 11 to 19 The method for fabricating the semiconductor structure provided in the embodiments of this disclosure will be described in detail.

[0088] In step S100, as Figures 11 to 15 As shown, the main feature is a semiconductor layer 106. The semiconductor layer 106 contains a plurality of active pillars 109 extending along a first direction, a gate structure 107 located on one side of each active pillar 109, and a first insulating layer 108 located between two adjacent active pillars 109. A first doped region 112 is provided at one end of each active pillar 109 along the first direction, which is the thickness direction of the semiconductor layer 106.

[0089] In some embodiments, the method further includes forming a second electrode 111 located at another end of the active post along the first direction.

[0090] In some specific examples, the method of providing the semiconductor layer 106 may specifically include: such as Figure 11 As shown, a semiconductor layer 106 is provided, in which a plurality of semiconductor pillars 110 are formed. A third sub-insulating layer 108-3 is formed between two adjacent semiconductor pillars 110 and on the semiconductor pillars 110. A gate structure 107 is formed on two opposite sidewalls of each semiconductor pillar 110 in a second direction. Figure 12As shown, the semiconductor pillar 110 is etched to form a fifth groove 105. The fifth groove 105 divides one semiconductor pillar 110 into two active pillars 109. The two active pillars 109 between two adjacent fifth grooves 105 constitute an active pillar unit 103. The fifth groove 105 exposes part of the sidewalls of the active pillars 109 and the semiconductor layer between adjacent active pillars 109. Next, as... Figure 13 As shown, the surface of a portion of the sidewall of the exposed active pillar 109 and the semiconductor layer between adjacent active pillars 109 is oxidized to form a first sub-insulating layer 108-1; next, as... Figure 14 As shown, a second electrode 111 and a first doped region 112 are formed at both ends of the active pillar 109 along the first direction. A second sub-insulating material layer 108-22 is filled in the fifth groove 105 and on the third sub-insulating layer 108-3. A cavity is formed in the second sub-insulating material layer 108-22 to isolate adjacent transistors and improve the interference effect between two adjacent transistors. Next, as... Figure 15 As shown, the second sub-insulating material layer 108-22 and the third sub-insulating layer 108-3 are planarized to expose the first doped region 112. After the planarization treatment of the second sub-insulating material layer 108-22, a second sub-insulating layer 108-2 is formed. The top surface of the second sub-insulating layer 108-2 is flush with the top surface of the first doped region 112.

[0091] It should be noted that the second electrode 111 can be formed simultaneously with the first doped region 112, or it can be formed before or after the formation of the first doped region 112.

[0092] In some specific examples, the planarization process includes, but is not limited to, chemical mechanical polishing (CMP) processes.

[0093] In some specific examples, the semiconductor layer 106 may include a substrate, which may include a single-element semiconductor material substrate (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a composite semiconductor material substrate (e.g., a germanium-silicon (SiGe) substrate, etc.), a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc. Preferably, the substrate is a silicon substrate.

[0094] In some specific examples, the gate structure 107 includes a gate and a gate oxide layer.

[0095] In some specific examples, the gate material includes, but is not limited to, polysilicon, conductive metal, or conductive alloy. Conductive metal may include tungsten or copper, etc.

[0096] In some specific examples, the active pillar 109 between the second electrode 111 and the subsequently formed first electrode constitutes the channel region of the transistor, and the gate oxide layer is located between the gate and the channel region to electrically isolate the channel region and the gate and reduce the hot carrier effect of the transistor.

[0097] In some specific examples, the gate oxide layer includes, but is not limited to, silicon oxide. Methods for forming the gate oxide layer include, but are not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), and atomic layer deposition (ALD).

[0098] Here, the second electrode 111 can be the source or drain of the transistor, and the first electrode 113 formed subsequently using a portion of the first doped region 112 can also be the source or drain of the transistor. For example, when the second electrode 111 is the source, the first electrode 113 is the drain; when the second electrode 111 is the drain, the first electrode 113 is the source.

[0099] In some embodiments, the first insulating layer 108 includes a first sub-insulating layer 108-1, a second sub-insulating layer 108-2, and a third sub-insulating layer 108-3; the plurality of active pillars 109 are arranged in an array along a second direction and a third direction, and two adjacent active pillars 109 along the second direction constitute an active pillar unit 103; the third direction is perpendicular to the first direction and intersects the second direction;

[0100] The first sub-insulating layer 108-1 and the second sub-insulating layer 108-2 are both located between two adjacent active pillar units 103. The first sub-insulating layer 108-1 covers the sidewalls of the two adjacent active pillar units 103, and the second sub-insulating layer 108-2 covers the sidewalls of the first sub-insulating layer 108-1, and a cavity is formed in the second sub-insulating layer 108-2. The third sub-insulating layer 108-3 is located between the two active pillars 109 of each active pillar unit 103. The gate structure 107 is located in the third sub-insulating layer 108-3.

[0101] In some specific examples, the first direction can be understood as in Figures 11-19 The Z-axis direction shown is not limited to the Z-axis direction. The second direction can be understood as... Figures 11-19 The X-axis direction shown in the diagram is not limited to the X-axis direction. The third direction can be understood as... Figures 11-19 The Y-axis direction shown in the figure can be understood to mean that the third direction is not limited to the Y-axis direction.

[0102] Here, the intersection of the second direction and the third direction can be understood as the angle between the second direction and the third direction being less than or equal to 90 degrees. In some specific examples, the angle between the second direction and the third direction is equal to 90 degrees.

[0103] In some specific examples, the material of the first insulating layer 108 includes, but is not limited to, silicon oxide.

[0104] In some specific examples, the materials of the first sub-insulating layer 108-1, the second sub-insulating layer 108-2, and the third sub-insulating layer 108-3 can be the same. When the materials of the first sub-insulating layer 108-1 and the second sub-insulating layer 108-2 are the same, there is no clear boundary between them, and the first sub-insulating layer 108-1 and the second sub-insulating layer 108-2 can form a single unit existing between two adjacent active pillar units 103.

[0105] In some specific examples, the methods for forming the second sub-insulating layer 108-2 include, but are not limited to, PVD, CVD, and ALD.

[0106] In some specific examples, the methods for forming the first sub-insulating layer 108-1 include, but are not limited to, oxidation, PVD, CVD, and ALD.

[0107] In some specific examples, the method for forming the fifth groove 105 includes, but is not limited to, dry etching process, specifically dry plasma etching process.

[0108] In some specific examples, the methods for forming the first doped region 112 and the second electrode 111 include, but are not limited to, doping processes and diffusion processes. In some specific examples, the formed semiconductor structure can be an N-type transistor or a P-type transistor.

[0109] In an N-type transistor, both the source and drain are doped with N-type doping; in a P-type transistor, both the source and drain are doped with P-type doping. For example, when the doping type is P-type, the P-type impurity source can be boron (B), aluminum (Al), etc., and is not limited to these; when the doping type is N-type, the N-type impurity source can be phosphorus (P), arsenic (As), etc., and is not limited to these.

[0110] In some specific examples, the width of the first doped region 112 in the second direction is less than a first preset value.

[0111] In some specific examples, the first preset value is 25nm.

[0112] Understandably, as memory size requirements continue to increase, the size of the first doped region 112 of the vertical channel transistor is constantly shrinking. Using the smaller first doped region 112 to form a metal compound interconnect structure for connecting the transistor and the memory structure presents significant manufacturing challenges. The solution proposed in this embodiment reduces manufacturing difficulty and addresses the difficulty of forming a metal compound interconnect structure when the first doped region 112 is small.

[0113] It should be noted that the first preset value given in the above embodiments is only an exemplary demonstration and is not intended to limit the first preset value in this disclosure. In actual applications, the first preset value can be set according to the specific actual process conditions.

[0114] In step S200, as Figure 16 As shown, a portion of the first insulating layer 108 is removed to form a plurality of first grooves 101.

[0115] In some specific examples, the methods for removing the first insulating layer 108 include, but are not limited to, dry etching.

[0116] In some specific examples, such as Figure 16 As shown, the formed first groove 101 exposes part of the sidewalls of two adjacent first doped regions 112. A portion of the sidewalls of the first doped region 112 is also covered by the first insulating layer 108.

[0117] In step S300, as Figure 17 As shown, a second insulating layer 114 is formed in the first groove 101.

[0118] In some embodiments, the material of the second insulating layer 114 is different from the material of the first insulating layer 108.

[0119] In some specific examples, the material of the second insulating layer 114 includes, but is not limited to, silicon nitride.

[0120] It is understandable that the materials of the first insulating layer 108 and the second insulating layer 114 need to be different, so that the impact on the first insulating layer 108 can be reduced when removing part of the second insulating layer 114 in subsequent processes.

[0121] In some specific examples, the methods for forming the second insulating layer 114 include, but are not limited to, PVD, CVD, and ALD.

[0122] In some specific examples, when the second insulating layer 114 is filled in the first groove 101, a portion of the second insulating layer 114 is also filled on the top surface of the first doped region 112. After the second insulating layer 114 is filled, a planarization process is performed on the second insulating layer 114 so that the top surface of the second insulating layer 114 is flush with the top surface of the first doped region 112. In some specific examples, the planarization process includes, but is not limited to, CMP.

[0123] In step S400, as Figure 18 As shown, at least a portion of the first doped region 112 and a portion of the second insulating layer 114 are removed to form a plurality of second grooves 102, and the remaining first doped region 112 forms a first electrode 113; the width of the second groove 102 in the second direction is greater than the width of the first electrode 113 in the second direction, and the second direction is perpendicular to the first direction.

[0124] In some embodiments, the removal of at least a portion of the first doped region 112 and a portion of the second insulating layer 114 to form a plurality of second grooves 102 includes:

[0125] A portion of the first doped region 112 is removed to form a plurality of third grooves; the top surface of the first electrode 113 is flush with the top surface of the first insulating layer 108;

[0126] A portion of the second insulating layer 114 and a portion of the first insulating layer 108 are removed from the sidewall of the third groove to enlarge the third groove and form the second groove 102.

[0127] In some embodiments, removing a portion of the first doped region 112 includes:

[0128] A portion of the first doped region 112 was removed using a dry etching process;

[0129] Removing a portion of the second insulating layer 114 and a portion of the first insulating layer 108 includes:

[0130] A portion of the first insulating layer 108 is removed using a dry etching process, and a portion of the second insulating layer 114 is removed using a wet etching process.

[0131] In some specific examples, a gas etching apparatus can be used to etch the first doped region 112, resulting in better uniformity and more favorable polymer byproducts formed during the etching process.

[0132] In some specific examples, a gas etching apparatus can be used to etch the first insulating layer 108, which can effectively minimize the impact on the active pillar.

[0133] In some specific examples, phosphoric acid with a high selectivity ratio can be used to remove part of the second insulating layer 114, which can minimize the impact on the first insulating layer 108.

[0134] In step S500, a connection structure is formed in the second groove 102.

[0135] In some embodiments, forming a connection structure in the second groove 102 includes:

[0136] like Figure 19 As shown, a semiconductor material pillar 115 is formed in the second groove 102;

[0137] A metal material layer is formed on the semiconductor material pillar 115;

[0138] The semiconductor material pillar 115 and the metal material layer are annealed to form a connection structure.

[0139] In some specific examples, the material of the semiconductor material pillar 115 includes, but is not limited to, polycrystalline silicon.

[0140] In some specific examples, the materials of the metallic material layer include, but are not limited to, Ti, Co, and NiPt.

[0141] In some specific examples, the material of the connection structure includes, but is not limited to, metal compounds, including, but not limited to, titanium silicide, cobalt silicide, and nickel silicide.

[0142] The above embodiments exemplify several metal compounds, but the metal compounds in this disclosure are not limited to these. It is understood that, on the one hand, the metal compound in this disclosure needs to be a conductive material so that the formed connection structure can electrically connect the transistor and the storage capacitor; on the other hand, since the connection structure in this disclosure is obtained by annealing the semiconductor material pillar 115 and the metal material layer, the specific material of the metal compound in this disclosure is related to the material of the semiconductor material pillar 115. For example, when the semiconductor material pillar 115 is polycrystalline silicon, the metal compound can be a metal silicide; when the semiconductor material pillar 115 is germanium, the metal compound can be a metal germanide.

[0143] In some specific examples, after forming the semiconductor material pillar 115, the method further includes removing a portion of the semiconductor material pillar 115 to form a sixth groove; a metal material layer is formed in the sixth groove.

[0144] Understandably, on the one hand, since the width of the second groove 102 in the second direction is greater than the width of the first electrode 113 in the second direction, the width of the formed semiconductor material pillar 115 in the second direction is greater than the width of the first electrode 113 in the second direction. When the semiconductor material pillar 115 and the metal material layer are annealed to form a metal silicide connection structure, the small size effect can be reduced, and a larger metal silicide connection structure can be formed. On the other hand, since the width of the formed connection structure in the second direction is larger, the contact area between the connection structure and the first electrode 113 is larger, thereby reducing the contact resistance between the transistor and the memory structure and improving the performance of the semiconductor structure.

[0145] In some embodiments, forming the semiconductor material pillar 115 in the second groove 102 includes:

[0146] Semiconductor material pillars 115 are formed in the second groove 102 using an epitaxial growth process.

[0147] It is understandable that the semiconductor material pillar 115 formed by epitaxial growth can make better contact with the active pillar 109, thus improving the problem of high resistance due to interface effects.

[0148] In some specific examples, a semiconductor material pillar 115 can be formed in the second groove 102 using a selective epitaxial growth (SEG) process.

[0149] Figures 20-27 This is a cross-sectional schematic diagram illustrating the manufacturing process of another semiconductor structure provided in an embodiment of this disclosure. (See attached diagram.) Figure 20 As shown in Figure 21, after providing the semiconductor layer 106, a portion of the first insulating layer 108 is removed to form the first groove 101. Figure 20 as well as Figure 21 The diagram only shows the formation of semiconductor pillars 110 in the semiconductor layer. In some specific examples, it also includes etching the semiconductor pillars 110 to form active pillars; such as... Figure 22 as well as Figure 23 As shown, the second insulating layer 114 is filled in the first groove 101; as Figure 24 as well as Figure 25 As shown, a portion of the second insulating layer 114 and a portion of the first doped region 112 are removed to form a second groove 102. The remaining first doped region constitutes the first electrode 113 of the transistor. The width of the second groove 102 in the second direction is greater than the width of the first electrode 113 in the second direction. Figure 26 as well as Figure 27As shown, semiconductor material is filled into the second groove 102 to form a semiconductor material pillar 115. The semiconductor material pillar 115 is then used in a subsequent process to form a connection structure.

[0150] In some embodiments, the method further includes:

[0151] A storage structure is formed that is connected to the connection structure.

[0152] In some specific examples, forming a memory structure may include the following steps: forming a memory structure hole on the connection structure; forming a memory structure, such as forming a memory capacitor, in the memory structure hole.

[0153] In some specific examples, the storage capacitor can present various structures. For example, the storage capacitor may include a cup-shaped capacitor (CUP), a cylindrical capacitor (CYL), or a pillar-shaped capacitor (PIL). Each of these capacitors includes a bottom electrode, a top electrode, and a dielectric layer located between the bottom and top electrodes.

[0154] In some specific examples, the bottom electrode is connected to the first electrode 113 in the semiconductor structure, the top electrode of the cup-shaped capacitor CUP is grounded, and the cup-shaped capacitor CUP is used to store the written data.

[0155] It should be noted that, when the bottom electrode areas of the cup-shaped capacitor (CUP), cylindrical capacitor (CYL), and pillar-shaped capacitor (PIL) are equal, the top electrode area of ​​the cylindrical capacitor (CYL) is the largest, followed by the top electrode areas of the cylindrical capacitor (CYL) and pillar-shaped capacitor (PIL). Therefore, in practical applications, the cylindrical capacitor (CYL) can be used as the storage unit of a memory, which is beneficial for improving the integration density of the memory.

[0156] In some embodiments, the semiconductor layer 106 has a first side and a second side disposed opposite to each other along the first direction, and the plurality of active pillars 109 are close to the first side;

[0157] The method further includes:

[0158] The semiconductor layer 106 is thinned from the second side to expose the second electrode 111;

[0159] Multiple bit lines are formed; the bit lines are connected to the second electrode 111.

[0160] Figure 28 A three-dimensional structural schematic diagram of a semiconductor structure is shown, from Figure 28 As can be seen, the semiconductor structure includes bit line 117 and storage capacitor 116. Bit line 117 and storage capacitor 116 are electrically connected to two different electrodes of the transistor, respectively.

[0161] In some specific examples, the process for thinning the semiconductor layer 106 includes, but is not limited to, etching and chemical mechanical polishing processes.

[0162] Understandably, the bit line BL is used for signal transmission when the transistor is turned on.

[0163] In some specific examples, bit lines are formed by forming metal lines at predetermined bit line locations. These metal lines include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon, doped silicon, silicides, or any combination thereof.

[0164] In some specific examples, the semiconductor structure includes dynamic random access memory.

[0165] The embodiments disclosed herein merely exemplify some common memories, and the scope of protection of this disclosure is not limited thereto. Any memory containing the semiconductor structure provided in the embodiments of this disclosure falls within the scope of protection of this invention.

[0166] This disclosure provides a method for fabricating a semiconductor structure, comprising: providing a semiconductor layer 106, wherein a plurality of active pillars 109 extending along a first direction, a gate structure 107 located on one side of the active pillars 109, and a first insulating layer 108 located between two adjacent active pillars 109; wherein a first doped region 112 is provided at one end of the active pillar 109 along the first direction, the first direction being the thickness direction of the semiconductor layer 106; removing a portion of the first insulating layer 108 to form a plurality of first grooves 101; forming a second insulating layer 114 in the first grooves 101; removing at least a portion of the first doped region 112 and a portion of the second insulating layer 114 to form a plurality of second grooves 102, the remaining first doped region 112 forming a first electrode 113; the width of the second groove 102 in a second direction is greater than the width of the first electrode 113 in the second direction, the second direction being perpendicular to the first direction; and forming a connection structure in the second groove 102. In this embodiment, a portion of the first insulating layer 108 between multiple active pillars 109 is first removed to form multiple first grooves 101. A second insulating layer 114 is formed in the first grooves 101. Then, a portion of the first doped region 112 and a portion of the second insulating layer 114 are removed, and a connection structure is formed in the second groove 102. Since the width of the second groove 102 in the second direction is greater than the width of the first electrode 113 in the second direction, it can improve the problem that when the first doped region 112 is directly used to form the connection structure, the small size effect occurs when the first doped region 112 is small in the second direction, resulting in poor connection effect of the formed connection structure, large contact resistance between the storage structure and the transistor, and thus reduced performance of the semiconductor structure.

[0167] According to another aspect of this disclosure, embodiments of this disclosure also provide a semiconductor structure, including:

[0168] A semiconductor layer, wherein a plurality of active pillars extending along a first direction are disposed therein, a gate structure located on one side of the active pillars, a first insulating layer located between two adjacent active pillars, and a first electrode disposed at one end of the active pillars along the first direction; the first direction is the thickness direction of the semiconductor layer;

[0169] A second insulating layer is located on the semiconductor layer;

[0170] A plurality of connection structures, each of which is at least partially located in the second insulating layer; the connection structure is connected to the first electrode, and the width of the connection structure in the second direction is greater than the width of the first electrode in the second direction; the second direction is perpendicular to the first direction.

[0171] In some embodiments, each of the connection structures is located in the second insulating layer and in the first insulating layer.

[0172] In some embodiments, the first insulating layer includes a first sub-insulating layer, a second sub-insulating layer, and a third sub-insulating layer; the plurality of active pillars are arranged in an array along a second direction and a third direction, and two adjacent active pillars along the second direction constitute an active pillar unit; the third direction is perpendicular to the first direction and intersects the second direction;

[0173] The first sub-insulating layer and the second sub-insulating layer are both located between two adjacent active pillar units. The first sub-insulating layer covers the sidewalls of the two adjacent active pillar units, and the second sub-insulating layer covers the sidewalls of the first sub-insulating layer, and a cavity is formed in the second sub-insulating layer. The third sub-insulating layer is located between two active pillars of each active pillar unit. The gate structure is located in the third sub-insulating layer.

[0174] In some embodiments, the material of the connection structure includes a metal compound.

[0175] In some embodiments, the first insulating layer and the second insulating layer are made of different materials.

[0176] In some embodiments, the material of the first insulating layer includes silicon oxide, and the material of the second insulating layer includes silicon nitride.

[0177] In some embodiments, the width of the first electrode in the second direction is less than a first preset value.

[0178] In some embodiments, the first preset value is 25nm.

[0179] In some embodiments, the semiconductor layer has a first side and a second side opposite to each other along the first direction, and the plurality of active pillars are close to the first side;

[0180] The semiconductor structure also includes:

[0181] A second electrode is located at the other end of the active post along the first direction;

[0182] Multiple bit lines are located on the second side and connected to the second electrode.

[0183] In some embodiments, the semiconductor structure further includes a plurality of memory structures connected to the connection structure.

[0184] In some embodiments, the semiconductor structure includes a dynamic random access memory, and the memory structure includes a storage capacitor.

[0185] The semiconductor structure provided in the above embodiments has been described in detail in the method section and will not be repeated here.

[0186] According to another aspect of this disclosure, embodiments of this disclosure also provide a memory system, including:

[0187] One or more semiconductor structures as described in the above embodiments; and

[0188] A memory controller, which is connected to and controls the semiconductor structure.

[0189] The semiconductor structure disclosed herein is at least a portion of the structure that will be used in subsequent processes to form a final device structure. Here, the final device may include a memory.

[0190] In some specific examples, the semiconductor structure can be used as computer memory in a memory system or as a cache in a memory system.

[0191] In some specific examples, the semiconductor structure can be used in solid-state drives (SSDs) to improve read and write speeds. Currently, high-end SSDs often embed DRAM to enhance performance and improve random read / write speeds. For instance, during file writing, especially small file writing, small files are processed by DRAM before being stored in Flash memory, resulting in higher storage efficiency and faster speeds for the SSD.

[0192] In the several embodiments provided in this disclosure, it should be understood that the disclosed devices and methods can be implemented in a non-target manner. The device embodiments described above are merely illustrative; for example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed. Furthermore, the various components shown or discussed may be coupled or directly coupled to each other.

[0193] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0194] This disclosure provides specific embodiments, but its scope of protection is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope of this disclosure should be included within its scope of protection. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: A semiconductor layer, wherein a plurality of active pillars extending along a first direction are disposed therein, a gate structure located on one side of the active pillars, a first insulating layer located between two adjacent active pillars, and a first electrode disposed at one end of the active pillars along the first direction; The first direction is the thickness direction of the semiconductor layer; A second insulating layer is located on the semiconductor layer; The first insulating layer and the second insulating layer are made of different materials; The first insulating layer is in contact with the sidewall of the first electrode; Multiple connection structures, each of which is at least partially located in the second insulating layer; The connection structure is connected to the first electrode, and the width of the connection structure in the second direction is greater than the width of the first electrode in the second direction; The second direction is perpendicular to the first direction.

2. The semiconductor structure according to claim 1, characterized in that, Each of the connection structures is located in the second insulating layer and in the first insulating layer.

3. The semiconductor structure according to claim 1, characterized in that, The first insulating layer includes a first sub-insulating layer, a second sub-insulating layer, and a third sub-insulating layer; the plurality of active pillars are arranged in an array along a second direction and a third direction, and two adjacent active pillars along the second direction constitute an active pillar unit; the third direction is perpendicular to the first direction and intersects the second direction; The first sub-insulating layer and the second sub-insulating layer are both located between two adjacent active pillar units. The first sub-insulating layer covers the sidewalls of the two adjacent active pillar units, and the second sub-insulating layer covers the sidewalls of the first sub-insulating layer, and a cavity is formed in the second sub-insulating layer. The third sub-insulating layer is located between two active pillars of each active pillar unit. The gate structure is located in the third sub-insulating layer.

4. The semiconductor structure according to claim 1, characterized in that, The connecting structure is made of a metallic compound.

5. The semiconductor structure according to claim 1, characterized in that, The first insulating layer is made of silicon oxide, and the second insulating layer is made of silicon nitride.

6. The semiconductor structure according to claim 1, characterized in that, The width of the first electrode in the second direction is less than a first preset value.

7. The semiconductor structure according to claim 6, characterized in that, The first preset value is 25nm.

8. The semiconductor structure according to claim 1, characterized in that, The semiconductor layer has a first side and a second side opposite to each other along the first direction, and the plurality of active pillars are close to the first side; The semiconductor structure also includes: A second electrode is located at the other end of the active post along the first direction; Multiple bit lines are located on the second side and connected to the second electrode.

9. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure also includes multiple memory structures, which are connected to the connection structure.

10. The semiconductor structure according to claim 9, characterized in that, The semiconductor structure includes a dynamic random access memory, and the memory structure includes a storage capacitor.

11. A memory system, characterized in that, include: One or more semiconductor structures as described in any one of claims 1-10; as well as A memory controller, which is connected to and controls the semiconductor structure.

12. A method for fabricating a semiconductor structure, characterized in that, The method includes: A semiconductor layer is provided, wherein a plurality of active pillars extending along a first direction, a gate structure located on one side of the active pillars, and a first insulating layer located between two adjacent active pillars are formed in the semiconductor layer; wherein a first doped region is provided at one end of the active pillar along the first direction, and the first direction is the thickness direction of the semiconductor layer; Part of the first insulating layer is removed to form multiple first grooves; A second insulating layer is formed in the first groove; the material of the second insulating layer is different from the material of the first insulating layer. At least a portion of the first doped region and a portion of the second insulating layer are removed to form a plurality of second grooves, and the remaining first doped region forms a first electrode; the width of the second groove in the second direction is greater than the width of the first electrode in the second direction, and the second direction is perpendicular to the first direction; the remaining first insulating layer contacts the sidewall of the first electrode. A connecting structure is formed in the second groove.

13. The manufacturing method according to claim 12, characterized in that, The removal of at least a portion of the first doped region and a portion of the second insulating layer to form a plurality of second grooves includes: A portion of the first doped region is removed to form multiple third grooves; the top surface of the first electrode is flush with the top surface of the first insulating layer. A portion of the second insulating layer and a portion of the first insulating layer are removed from the sidewall of the third groove to enlarge the third groove and form the second groove.

14. The manufacturing method according to claim 13, characterized in that, The removal of a portion of the first doped region includes: A portion of the first doped region was removed using a dry etching process; Removing a portion of the second insulating layer and a portion of the first insulating layer, including: A portion of the first insulating layer is removed using a dry etching process, and a portion of the second insulating layer is removed using a wet etching process.

15. The manufacturing method according to claim 12, characterized in that, The formation of the connecting structure in the second groove includes: Semiconductor material pillars are formed in the second groove; A metal material layer is formed on the semiconductor material pillar; The semiconductor material pillars and the metal material layer are annealed to form a connection structure.

16. The manufacturing method according to claim 15, characterized in that, The step of forming a semiconductor material pillar in the second groove includes: Semiconductor material pillars are formed in the second groove using an epitaxial growth process.

17. The method for fabricating a semiconductor structure according to claim 12, characterized in that, The first insulating layer includes a first sub-insulating layer, a second sub-insulating layer, and a third sub-insulating layer; the plurality of active pillars are arranged in an array along a second direction and a third direction, and two adjacent active pillars along the second direction constitute an active pillar unit; the third direction is perpendicular to the first direction and intersects the second direction; The first sub-insulating layer and the second sub-insulating layer are both located between two adjacent active pillar units. The first sub-insulating layer covers the sidewalls of the two adjacent active pillar units, and the second sub-insulating layer covers the sidewalls of the first sub-insulating layer, and a cavity is formed in the second sub-insulating layer. The third sub-insulating layer is located between two active pillars of each active pillar unit. The gate structure is located in the third sub-insulating layer.

18. The manufacturing method according to claim 12, characterized in that, The semiconductor layer has a first side and a second side opposite to each other along the first direction, and the plurality of active pillars are close to the first side; The method further includes: A second electrode is formed, the second electrode being located at the other end of the active post along the first direction; The semiconductor layer is thinned from the second side to expose the second electrode; Multiple bit lines are formed; the bit lines are connected to the second electrode.

19. The manufacturing method according to claim 12, characterized in that, The method further includes: A storage structure is formed that is connected to the connection structure.

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