Display panel and method of manufacturing the same

Abstract

The present invention discloses a display panel and a manufacturing method thereof, wherein the display panel comprises a substrate, a first active element, a first capacitor and a first gate insulating layer. The first active element is arranged on the substrate and has a first semiconductor pattern and a first gate. The first capacitor has a first capacitor electrode and a second capacitor electrode. The first semiconductor pattern and the first capacitor electrode are formed on a first semiconductor layer. The first gate and the second capacitor electrode are formed on a first conductive layer. The conductivity of the first capacitor electrode is different from the conductivity of the first semiconductor pattern. The first gate insulating layer is arranged between the first semiconductor layer and the first conductive layer.

Description

Technical Field

[0001] The present invention relates to a display technology, and in particular to a display panel. Background Art

[0002] As display specifications continue to improve, the design of display panel drive circuits has become more complex and faces challenges. For example, the higher the pixel resolution of a display panel, the smaller the pixel size, which compresses the configurable space of circuit components and affects the original operating electrical properties. Therefore, how to configure more circuit components that can operate stably in a limited space is a challenge for high-resolution display panels. Summary of the invention

[0003] The present invention provides a display panel, which has a larger layout space for circuits.

[0004] The invention provides a method for manufacturing a display panel, and the manufacturing process of a capacitor has a high integration degree.

[0005] The display panel of the present invention comprises a substrate, a first active element, a first capacitor and a first gate insulating layer. The first active element is arranged on the substrate and has a first semiconductor pattern and a first gate. The first capacitor has a first capacitor electrode and a second capacitor electrode. The first semiconductor pattern and the first capacitor electrode are formed on the first semiconductor layer. The first gate and the second capacitor electrode are formed on the first conductive layer. The conductivity of the first capacitor electrode is different from the conductivity of the first semiconductor pattern. The first gate insulating layer is arranged between the first semiconductor layer and the first conductive layer.

[0006] The manufacturing method of the display panel of the present invention includes forming a semiconductor layer on a substrate, forming a patterned gate insulating layer using a first mask layer, forming a second mask layer on the semiconductor layer, performing an ion implantation process, so that the second semiconductor pattern not covered by the second mask layer is transformed into a first capacitor electrode and forming a conductive layer. The semiconductor layer includes a first semiconductor pattern and a second semiconductor pattern. The second mask layer covers the first semiconductor pattern. The conductivity of the first semiconductor pattern is different from the conductivity of the first capacitor electrode. The conductive layer includes a first gate electrode and a second capacitor electrode. The gate insulating layer is located between the conductive layer and the semiconductor layer. The first gate electrode and the first semiconductor pattern form an active element. The first capacitor electrode and the second capacitor electrode form a capacitor.

[0007] Based on the above, in the manufacturing method of the display panel of one embodiment of the present invention, the steps of forming the two capacitor electrodes constituting the capacitor can be integrated into the manufacturing process of the active element. When forming the semiconductor pattern of the active element, another semiconductor pattern is simultaneously formed and it is conductively formed to form a capacitor electrode of the capacitor, while the other capacitor electrode is formed simultaneously when the gate of the active element is manufactured. That is, the present invention utilizes the existing material film layer to manufacture the required capacitor, which can not only increase the integration of the manufacturing process, but also increase the layout space of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a schematic cross-sectional view of a display panel according to a first embodiment of the present invention;

[0009] FIG. 2A to FIG. 2E yes Figure 1 A cross-sectional schematic diagram of a manufacturing process of a display panel;

[0010] Figure 3A yes Figure 1 A schematic diagram of a pixel driving circuit of a display panel;

[0011] Figure 3B is a schematic diagram of a pixel driving circuit of a display panel according to another embodiment of the present invention;

[0012] FIG. 4A to FIG. 4E is a cross-sectional schematic diagram of a manufacturing process of a display panel according to a second embodiment of the present invention;

[0013] Figure 5 is a schematic cross-sectional view of a display panel according to a third embodiment of the present invention;

[0014] Figure 6 is a schematic cross-sectional view of a display panel according to a fourth embodiment of the present invention.

[0015] Explanation of symbols

[0016] 10, 10A, 10B, 10C: Display panel

[0017] 100, 100A, 100B, 100C: pixel array substrate

[0018] 101:Substrate

[0019] 110, 120, 140, 140A: gate insulating layer

[0020] 140M: Gate insulation material layer

[0021] 130, 150: interlayer insulation layer

[0022] 160: Flat layer

[0023] 200: Display medium layer

[0024] C, C1, C2, C3, C4, C1-A, C1-B: capacitors

[0025] CE1, CE2, CE3, CE4, CE5, CE2-A, CE2-B: Capacitive electrodes

[0026] CE1a, CE1b: Partial

[0027] CH1, CH2: Channel region

[0028] CL1, CL2, CL3, CL4, CL2-A, CL3-A, CL4-A, CL3-B: Conductive layer

[0029] CP1, CP2, CP3: Conductive pattern

[0030] d1, d2: thickness

[0031] DATA: Data signal source

[0032] DE1, DE2: drain

[0033] DR1, DR2: drain region

[0034] GE1, GE2, GE3: Gate

[0035] LOAD: Load

[0036] MK1, MK2, MK1”, MK2”: mask layer

[0037] SC1, SC2, SC”: semiconductor pattern

[0038] SCAN: Gate signal source

[0039] SCL1, SCL2: Semiconductor layer

[0040] SE1, SE2: source

[0041] SR1, SR2: Source region

[0042] T1, T2: Active components

[0043] TH1a, TH1b, TH2, TH3a, TH3b: Through hole

[0044] TP1, TP2, TP3, TP2": Transfer pattern

[0045] VDD: system high voltage

[0046] VSS: System low voltage DETAILED DESCRIPTION

[0047] In the accompanying drawings, the thickness of layers, films, panels, regions, etc., is exaggerated for clarity. It should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to another element, or an intermediate element may also exist. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intermediate elements. As used herein, "connection" may refer to physical and / or electrical connection. Furthermore, "electrical connection" may be the presence of other elements between two elements.

[0048] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element, as shown in the figures. It should be understood that relative terms are intended to include different orientations of the device in addition to the orientation shown in the figures. For example, if the device in one figure is turned over, the elements described as being on the "lower" side of the other elements will be oriented on the "upper" side of the other elements. Therefore, the exemplary term "lower" can include both "lower" and "upper" orientations, depending on the particular orientation of the figure. Similarly, if the device in one figure is turned over, the elements described as being "below" or "below" other elements will be oriented as being "above" the other elements. Therefore, the exemplary terms "above" or "below" can include both above and below orientations.

[0049] Exemplary embodiments are described herein with reference to cross-sectional views as schematic diagrams of idealized embodiments. Therefore, variations in the shapes of the illustrations as a result of, for example, manufacturing techniques and / or tolerances can be expected. Therefore, the embodiments described herein should not be interpreted as being limited to the specific shapes of the regions as shown herein, but rather include shape deviations, for example, caused by manufacturing. For example, a region shown or described as flat may typically have rough and / or nonlinear features. In addition, the sharp angles shown may be rounded. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of the regions, and are not intended to limit the scope of the claims.

[0050] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0051] Figure 1 is a schematic cross-sectional view of a display panel according to a first embodiment of the present invention. FIG. 2A to FIG. 2E yes Figure 1 A cross-sectional schematic diagram of a manufacturing process of a display panel. Figure 3A yes Figure 1 A simplified diagram of a pixel driving circuit for a display panel. Figure 3Bis a schematic diagram of a pixel driving circuit of a display panel according to another embodiment of the present invention.

[0052] Please refer to Figure 1 , the display panel 10 includes a pixel array substrate 100 and a display medium layer 200. In the present embodiment, the display medium layer 200 is, for example, an organic light emitting diode (OLED) element layer, a micro light emitting diode (micro-LED) element layer, a sub-millimeter light emitting diode (mini-LED) element layer, or other suitable self-luminous element layer, but is not limited thereto. In another embodiment not shown, the display medium layer 200 may also be a liquid crystal layer with dimming characteristics. It should be understood that the electrode design used to drive the display medium layer in the display panel will vary depending on the type of the display medium layer, so the present invention is not limited thereto and the detailed description of this part is omitted. More specifically, the pixel array substrate 100 disclosed in the present invention is applicable to both self-luminous display panels and non-self-luminous display panels. The following will be exemplarily described for the pixel array substrate 100 of the present embodiment.

[0053] The pixel array substrate 100 includes a substrate 101 and an active element T1, an active element T2 and a plurality of capacitors disposed on the substrate 101. The material of the substrate 101 is, for example, an inorganic transparent material (such as glass, quartz, or other suitable materials, or a combination thereof), an organic transparent material (such as polyolefins, polyols, polyesters, rubber, thermoplastic polymers, thermosetting polymers, polyaromatic hydrocarbons, polymethyl methacrylate, plastic, polycarbonate, or other suitable materials, or derivatives thereof, or a combination thereof), or a combination thereof, and other hard or soft light-transmitting materials.

[0054] The active device T1 includes a semiconductor pattern SC1, a gate GE1, a source SE1 and a drain DE1. The active device T2 includes a semiconductor pattern SC2, a gate GE2, a source SE2 and a drain DE2, wherein the semiconductor pattern SC2 can be divided into a channel region CH2 and a source region SR2 and a drain region DR2 connecting opposite sides of the channel region CH2, and the conductivity of the source region SR2 and the drain region DR2 is different from the conductivity of the channel region CH2. In detail, the semiconductor pattern SC2 is disposed on the surface of the substrate 101 and is covered with a gate insulating layer 110. The gate GE2 is disposed on the gate insulating layer 110 and overlaps the channel region CH2 of the semiconductor pattern SC2. A gate insulating layer 120 is disposed between the source SE2 (or the drain DE2) and the gate GE2, wherein the source SE2 and the drain DE2 penetrate the gate insulating layer 120 and the gate insulating layer 110 to electrically connect the source region SR2 and the drain region DR2 of the semiconductor pattern SC2, respectively.

[0055] In this embodiment, an active device T1 is disposed on a side of the active device T2 facing away from the substrate 101. For example, an interlayer insulating layer 130 is further disposed on the active device T2, and a semiconductor pattern SC1 of the active device T1 is disposed on the interlayer insulating layer 130 and covered with a gate insulating layer 140 and an interlayer insulating layer 150. The semiconductor pattern SC1 can be divided into a channel region CH1 and a source region SR1 and a drain region DR1 connecting opposite sides of the channel region CH1, and the conductivity of the source region SR1 and the drain region DR1 is different from the conductivity of the channel region CH1. The gate GE1 of the active device T1 is disposed on the gate insulating layer 140 and covered by the interlayer insulating layer 150. The gate GE1 overlaps the channel region CH1 of the semiconductor pattern SC1. The source SE1 and the drain DE1 of the active device T1 are disposed on the interlayer insulating layer 150 and penetrate the interlayer insulating layer 150 to electrically connect the source region SR1 and the drain region DR1 of the semiconductor pattern SC1, respectively. The source electrode SE1 and the drain electrode DE1 may be further covered with a planarization layer 160 .

[0056] For example, Figure 1 The active device T1 and the active device T2 shown in the figure can be used as each pixel circuit of the display panel 10 (eg Figure 3A ) in the embodiment of the present invention, but is not limited thereto. In other embodiments, the active element T1 and the active element T2 may also be applied to other driving circuits of the display panel, such as a gate driving circuit. It should be noted that, in the present embodiment, the gate of the active element is disposed above the semiconductor pattern to form a top-gate type active element. However, the present invention is not limited thereto. According to other embodiments, the gate of the active element may also be disposed below the semiconductor pattern to form a bottom-gate type active element.

[0057] In this embodiment, the active device T1 may further selectively have another gate GE3 below the semiconductor pattern SC1 to form a dual-gate active device, wherein the gate GE3 and the gate GE2 of the active device T2 may be in the same conductive layer CL1 , but not limited thereto.

[0058] On the other hand, in the aforementioned film layers, the pixel circuit of the pixel array substrate 100 may selectively be provided with four capacitors, such as capacitor C1, capacitor C2, capacitor C3 and capacitor C4, but not limited thereto. In other embodiments, the number of capacitors in the pixel circuit may be adjusted according to actual needs, for example, it may be flexible to choose whether to provide capacitor C3 and capacitor C4. It is particularly noted that in this embodiment, the four capacitors are perpendicular to the substrate 101 (e.g. Figure 1 overlap each other in the vertical direction), maximizing the overall capacitance value and helping to save layout space for these capacitors.

[0059] In the present embodiment, the capacitor C1 is disposed on the interlayer insulating layer 130 and covered by the interlayer insulating layer 150, wherein a gate insulating layer 140 is disposed between the capacitor electrode CE1 and the capacitor electrode CE2 of the capacitor C1. More specifically, the capacitor C1 of the present embodiment is manufactured using the film layer where the active element T1 is located. For example, the capacitor electrode CE1 of the capacitor C1 and the semiconductor pattern SC1 of the active element T1 are formed on the same semiconductor layer SCL1, and the capacitor electrode CE2 of the capacitor C1 and the gate GE1 of the active element T1 are formed on the same conductive layer CL3. That is, the manufacturing process of the capacitor C1 and the active element T1 of the present embodiment has a high degree of integration. Although the capacitor electrode CE1 and the semiconductor pattern SC1 are formed on the same semiconductor layer SCL1, their respective conductivity is different. For example, the conductivity of the capacitor electrode CE1 of the capacitor C1 is higher than the conductivity of the channel region CH1 of the semiconductor pattern SC1 of the active element T1.

[0060] Furthermore, in this embodiment, the capacitor electrode CE1 may have a first portion CE1a overlapping the capacitor electrode CE2 in a direction perpendicular to the substrate 101 and a second portion CE1b not covered by the capacitor electrode CE2, wherein the conductivity of the first portion CE1a is different from the conductivity of the second portion CE1b.

[0061] Similar to the configuration relationship between capacitor C1 and active element T1, capacitor C2 is manufactured using the film layer where active element T2 is located. For example, capacitor electrode CE3 of capacitor C2 and semiconductor pattern SC2 of active element T2 are formed in the same semiconductor layer SCL2, while capacitor electrode CE4 of capacitor C2 and gate GE2 of active element T2 are formed in the same conductive layer CL1. Although capacitor electrode CE3 and semiconductor pattern SC1 are formed in the same semiconductor layer SCL2, their respective conductivity is different. For example, the conductivity of capacitor electrode CE3 of capacitor C2 is higher than the conductivity of channel region CH2 of semiconductor pattern SC2 of active element T2.

[0062] In this embodiment, another capacitor electrode CE5 may be selectively provided between the capacitor C1 and the capacitor C2. The capacitor electrode CE5 overlaps with the capacitor electrode CE4 to form the aforementioned capacitor C3. In addition, the capacitor electrode CE5 also overlaps with the capacitor electrode CE1 to form the aforementioned capacitor C4. For example, the capacitor electrode CE5 and the source SE2 and the drain DE2 of the active device T2 may be formed on the same conductive layer CL2, but is not limited thereto.

[0063] In this embodiment, the pixel array substrate 100 may also include a plurality of transfer patterns TP1 formed in the conductive layer CL2, a plurality of transfer patterns TP2 formed in the conductive layer CL3, and a plurality of conductive patterns CP1 and conductive patterns CP2 formed in the conductive layer CL4, and these transfer patterns and conductive patterns are used to provide electrical connections between active components or capacitors and corresponding leads.

[0064] For example, the capacitor electrode CE1 and the capacitor electrode CE2 of the capacitor C1 can be electrically connected to two corresponding circuit traces via the conductive pattern CP2 and the conductive pattern CP1, respectively. The capacitor electrode CE4 of the capacitor C2 can be electrically connected to the drain DE1 of the active component T1 via the transfer pattern TP1, the transfer pattern TP2 and the transfer pattern TP3, and the capacitor electrode CE3 of the capacitor C2 can be electrically connected to a corresponding circuit trace via the capacitor electrode CE5, the transfer pattern TP2 and the conductive pattern CP1. The source SE2 and the drain DE2 of the active component T2 can each be electrically connected to a corresponding circuit trace with the conductive pattern CP1 via the transfer pattern TP2. However, the present invention is not limited to this. In other embodiments, the electrical connection relationship between the active component or capacitor and the circuit trace can also be implemented by the configuration of different transfer patterns or conductive patterns.

[0065] The following is an exemplary description of the manufacturing process of the display panel 10. Figure 2AFirst, a semiconductor layer SCL2, a gate insulating layer 110, a conductive layer CL1, a gate insulating layer 120, a conductive layer CL2, an interlayer insulating layer 130 and a semiconductor layer SCL1 are sequentially formed on a substrate 101. Based on the consideration of conductivity, the conductive layer CL1 and the conductive layer CL2 are generally made of metal materials (such as molybdenum, aluminum, copper, palladium, or a combination thereof), but not limited thereto. The materials of the gate insulating layer and the interlayer insulating layer are, for example, silicon oxide, silicon nitride, silicon oxynitride, a stack of the above materials or other suitable materials. The material of the semiconductor layer SCL2 includes, for example, polycrystalline silicon.

[0066] The semiconductor layer SCL2 includes a semiconductor pattern SC2 and a capacitor electrode CE3. The conductive layer CL1 includes a gate GE2, a gate GE3 and a capacitor electrode CE4. The conductive layer CL2 includes a source SE2, a drain DE2, a transfer pattern TP1 and a capacitor electrode CE5. The semiconductor layer SCL1 includes a semiconductor pattern SC1 and a semiconductor pattern SC". Among them, the gate GE2, the semiconductor pattern SC2, the source SE2 and the drain DE2 constitute an active element T2, the capacitor electrode CE3 and the capacitor electrode CE4 constitute a capacitor C2, and the capacitor electrode CE4 and the capacitor electrode CE5 constitute a capacitor C3. The source SE2 and the drain DE2 are electrically connected to the semiconductor pattern SC2 via two through holes TH1a of the gate insulating layer 110 and the gate insulating layer 120 respectively. The transfer pattern TP1 is electrically connected to the capacitor electrode CE4 via the through hole TH1b of the gate insulating layer 120. The capacitor electrode CE5 is electrically connected to the capacitor electrode CE3 via the through hole TH1a.

[0067] It is particularly noted that, in order to make the conductivity of the capacitor electrode CE3 and the semiconductor pattern SC2 of the same semiconductor layer SCL2 different, an ion implantation step may be performed before forming the conductive layer CL1 or the gate insulating layer 110 to increase the conductivity of the capacitor electrode CE3. Since the formation of the source region SR2 and the drain region DR2 of the semiconductor pattern SC2 can also be performed by ion implantation, when performing the ion implantation step of the source region SR2 and the drain region DR2, the capacitor electrode CE3 may be ion implanted at the same time, but the present invention is not limited thereto. In other embodiments, the ion implantation step of the semiconductor pattern SC2 may also use the gate GE2 as a mask, and is performed after the ion implantation step of the capacitor electrode CE3 is completed.

[0068] Please refer to Figure 2BThen, a mask layer MK1 covering the semiconductor pattern SC1 is formed on the semiconductor layer SCL1, and another ion implantation process is performed. It is particularly noted that the mask layer MK1 does not cover another semiconductor pattern SC". After the ion implantation process is completed, the semiconductor pattern SC" will be conductive due to ion doping and transformed into a capacitor electrode CE1. The material of the semiconductor layer SCL1 includes, for example, indium gallium zinc oxide (IGZO). Figure 2C As shown, after removing the mask layer MK1, a gate insulating material layer 140M is formed on the semiconductor layer SCL1, and another mask layer MK2 is used to pattern the gate insulating material layer 140M to form a plurality of through holes TH2. These through holes TH2 will expose a portion of the conductive layer CL2, such as the source electrode SE2, the drain electrode DE2, the transfer pattern TP1 and the capacitor electrode CE5. In the present embodiment, the material of the mask layer is, for example, a photoresist material, but is not limited thereto.

[0069] Please refer to Figure 2D After forming a plurality of through holes TH2, a conductive layer CL3 is formed on the gate insulating material layer 140M, wherein the conductive layer CL3 may include a gate electrode GE1, a capacitor electrode CE2 and a plurality of transfer patterns TP2. For example, in this embodiment, the patterning process of the conductive layer CL3 may also selectively include Figure 2C The gate insulating material layer 140M in the semiconductor layer SCL1 is subjected to another patterning step to form a second patterned gate insulating layer 140. It is particularly noted that the second patterning of the gate insulating material layer 140M is performed by, for example, etching with the conductive layer CL3 as a mask layer, or etching with the conductive layer CL3 using the same mask layer. That is, the gate insulating layer 140 located between the semiconductor layer SCL1 and the conductive layer CL3 is formed in a direction perpendicular to the substrate 101 (e.g. Figure 2D In the vertical direction), it substantially completely overlaps with the conductive layer CL3, but is not limited thereto.

[0070] It is particularly noted that the capacitor electrode CE1 and the capacitor electrode CE2 electrically isolated by the gate insulating layer 140 may form a capacitor C1 , and the capacitor electrode CE1 and the capacitor electrode CE5 electrically isolated by the interlayer insulating layer 130 may form another capacitor C4 .

[0071] Next, an interlayer insulating layer 150 and a conductive layer CL4 are sequentially formed on the conductive layer CL3. Figure 2EAs shown. Among them, the conductive layer CL4 includes a source SE1, a drain DE1, a conductive pattern CP1, a conductive pattern CP2, a conductive pattern CP1 and a conductive pattern CP2. The conductive pattern CP1 and the transfer pattern TP3 are electrically connected to the multiple transfer patterns TP2 of the conductive layer CL2 via multiple through holes TH3a of the interlayer insulating layer 150. The source SE1, the drain DE1 and the conductive pattern CP2 are electrically connected to the semiconductor layer SCL1 via multiple through holes TH3b of the interlayer insulating layer 150. Among them, the source SE1, the drain DE1, the gate GE1 and the semiconductor pattern SC1 constitute an active element T1. In this embodiment, the capacitor C1 can transfer the required capacitive charge through the conductive pattern CP1 and the conductive pattern CP2 of the conductive layer CL4 above it, but is not limited to this.

[0072] Furthermore, after forming the conductive layer CL3 and before forming the interlayer insulating layer 150, another ion implantation process can be performed on the semiconductor pattern SC1 and the capacitor electrode CE1 using the conductive layer CL3 as a mask, so that the semiconductor pattern SC1 is divided into a source region SR1, a drain region DR1 and a channel region CH1, and the capacitor electrode CE1 is divided into a first portion CE1a and a second portion CE1b. In other words, the conductivity of the source region SR1 and the drain region DR1 of the semiconductor pattern SC1 is higher than the conductivity of the channel region CH1, and the conductivity of the second portion CE1b of the capacitor electrode CE1 is higher than the conductivity of the first portion CE1a.

[0073] Please also refer to Figure 1 After forming the planar layer 160 and the display medium layer 200 on the conductive layer CL4, the display panel 10 of this embodiment can be manufactured.

[0074] Please refer to Figure 1 and Figure 3A For example, the aforementioned active component T1, active component T2 and multiple capacitors can be used in the pixel driving circuit of the display panel 10, and the capacitor C can be composed of the aforementioned capacitor C1, capacitor C2, capacitor C3 and capacitor C4 connected in series. For example: the gate end of the active component T2 is electrically connected to the drain end of the active component T1 and one end of the capacitor C, and the source end of the active component T2 is electrically connected to a system high voltage VDD and the other end of the capacitor C. The drain end of the active component T2 is electrically connected to one end of the load LOAD. The other end of the load LOAD is electrically connected to a system low voltage VSS. The gate end of the active component T1 can be electrically connected to a gate signal source SCAN, and its source end can be electrically connected to a data signal source DATA. In the present embodiment, this load LOAD is, for example, a light emitting diode, but is not limited to this.

[0075] More specifically, in this embodiment, the active device T2 and the active device T1 can be used as a driving TFT and a switching TFT of the pixel driving circuit, respectively, but the present invention is not limited thereto. In other embodiments, the active device T1 can be used as a driving TFT of the pixel driving circuit, and the active device T2 can be used as a switching TFT of the pixel driving circuit.

[0076] On the other hand, in this embodiment, the capacitor C is connected across the source terminal and the gate terminal of the active element T2 to maintain the stability of the driving current transmitted to the load LOAD, but the present invention is not limited thereto. In another embodiment, the capacitor C may also be connected across the drain terminal and the gate terminal of the active element T2 (e.g. Figure 3B shown).

[0077] Some other embodiments will be listed below to explain the present invention in detail, wherein the same components will be marked with the same symbols, and the description of the same technical content will be omitted. For the omitted parts, please refer to the aforementioned embodiments and will not be repeated below.

[0078] FIG. 4A to FIG. 4E is a cross-sectional schematic diagram of the manufacturing process of the display panel of the second embodiment of the present invention. Figure 4E The pixel array substrate 100A of the display panel 10A of this embodiment is Figure 1 The difference between the pixel array substrate 100 of the display panel 10 is that the formation order of the gate insulating layer 140A of this embodiment is different from that of Figure 1 The gate insulating layer 140 is not subjected to a second patterning process. FIG. 2A to FIG. 2C In the manufacturing process, the gate insulating layer 140A of the present embodiment is formed before the ion implantation manufacturing process of the semiconductor layer SCL1.

[0079] like Figure 4A and Figure 4B As shown, after the semiconductor layer SCL1 is formed, a gate insulating material layer 140M and a mask layer MK1" are formed thereon, and the gate insulating material layer 140M is patterned using the mask layer MK1" to form a gate insulating layer 140A having a plurality of through holes TH2 and an interlayer insulating layer 130. It is particularly noteworthy that the thickness d1 of the mask layer MK1" at the portion overlapping the semiconductor pattern SC1 is greater than the thickness d2 of the mask layer MK1" at another portion overlapping the semiconductor pattern SC". For example, the mask layer MK1" of the present embodiment may be formed by exposing a photoresist material using a halftone photomask, but is not limited thereto.

[0080] After the formation step of the gate insulating layer 140A is completed, the mask layer MK1″ is subjected to an etching process to form a mask layer MK2″ having different mask patterns, such as Figure 4C As shown, the mask layer MK2" covers the semiconductor pattern SC1, but does not cover another semiconductor pattern SC". Next, an ion implantation process is performed to make the semiconductor pattern SC" not covered by the mask layer MK2" conductive and transformed into a capacitor electrode CE1.

[0081] Next, the mask layer MK2'' is removed, and a patterned conductive layer CL3 is formed on the gate insulating layer 140A. Figure 4D It is particularly noted that the gate insulating layer 140A of this embodiment only has a plurality of openings overlapping the plurality of transfer patterns TP2. That is, the gate insulating layer 140A of this embodiment is not Figure 1 The secondary patterning of the gate insulating layer 140 may therefore also exist in the area not covered by the conductive layer CL3.

[0082] Next, an interlayer insulating layer 150, a conductive layer CL4, a planar layer 160 and a display medium layer 200 are sequentially formed on the conductive layer CL3. Figure 4E As shown. Among them, the conductive layer CL4 includes a source SE1, a drain DE1, a conductive pattern CP1, a conductive pattern CP2, a conductive pattern CP1 and a conductive pattern CP2. The conductive pattern CP1 and the transfer pattern TP3 are electrically connected to the multiple transfer patterns TP2 of the conductive layer CL2 via multiple through holes TH3a of the interlayer insulating layer 150. The source SE1, the drain DE1 and the conductive pattern CP2 are electrically connected to the semiconductor layer SCL1 via multiple through holes TH3b of the interlayer insulating layer 150. Among them, the source SE1, the drain DE1, the gate GE1 and the semiconductor pattern SC1 constitute an active element T1. In this embodiment, the capacitor C1 can transfer the required capacitive charge through the conductive pattern CP1 and the conductive pattern CP2 of the conductive layer CL4 above it, but it is not limited to this. This completes the production of the display panel 10A of this embodiment.

[0083] Figure 5 FIG. 2 is a cross-sectional view of a display panel according to a third embodiment of the present invention. Figure 5 The display panel 10B of this embodiment is Figure 1 The main difference between the display panel 10 and the display panel 10B is that the number and structure of the capacitors are different. In this embodiment, the capacitor C1-A of the pixel array substrate 100B of the display panel 10B is formed by the conductive layer CL2-A below (not Figure 1For example, the conductive layer CL2-A may further include a conductive pattern CP3, and the conductive layer CL3-A may further include a transfer pattern TP2". The transfer pattern TP2" and the capacitor electrode CE2-A penetrate the gate insulating layer 140 and the interlayer insulating layer 130 to electrically connect the two conductive patterns CP3 respectively. The transfer pattern TP2" also penetrates the gate insulating layer 140 to electrically connect the capacitor electrode CE1. That is, the present embodiment uses the two conductive patterns CP3 in the conductive layer CL2-A to replace the capacitor electrode CE1. Figure 1 Therefore, the conductive layer CL4-A of this embodiment does not have any conductive pattern CP1 and conductive pattern CP2. Figure 1 The conductive pattern CP1 and the conductive pattern CP2 overlap with the capacitor C1.

[0084] Figure 6 FIG. 4 is a cross-sectional view of a display panel according to a fourth embodiment of the present invention. Figure 6 The display panel 10C of this embodiment is Figure 1 The difference between the display panel 10 and the display panel 10 is that the circuit connection relationship of the capacitor C1 is different. In this embodiment, the capacitor C1-B of the pixel array substrate 100C of the display panel 10C is formed by the conductive layer CL2 below (not Figure 1 Therefore, the conductive layer CL4-A of this embodiment does not have a Figure 1 The conductive pattern CP1 and the conductive pattern CP2 overlap with the capacitor C1. For example, the conductive layer CL3-B may also include a transfer pattern TP2". The transfer pattern TP2" and the capacitor electrode CE2-B penetrate the gate insulating layer 140 and the interlayer insulating layer 130 to electrically connect the two capacitor electrodes CE5 and the transfer pattern TP1 respectively. The transfer pattern TP2" also penetrates the gate insulating layer 140 to electrically connect the capacitor electrode CE1. That is, the capacitor C1-B, the capacitor C2, the capacitor C3 and the capacitor C4 of this embodiment are different from Figure 1 to connect.

[0085] In summary, in the manufacturing method of the display panel of one embodiment of the present invention, the steps of forming the two capacitor electrodes constituting the capacitor can be integrated into the manufacturing process of the active element. When forming the semiconductor pattern of the active element, another semiconductor pattern is simultaneously formed and it is conductively formed to form a capacitor electrode of the capacitor, while the other capacitor electrode is formed simultaneously when the gate of the active element is manufactured. That is, the present invention utilizes the existing material film layer to manufacture the required capacitor, which can not only increase the integration of the manufacturing process, but also increase the layout space of the circuit.

Claims

1. A display panel, comprising: substrate; A first active element is disposed on the substrate and has a first semiconductor pattern and a first gate; A first capacitor having a first capacitor electrode and a second capacitor electrode, wherein the first semiconductor pattern and the first capacitor electrode are formed in a first semiconductor layer, and the first gate electrode and the second capacitor electrode are formed in a first conductive layer, wherein the conductivity of the first capacitor electrode is different from the conductivity of the first semiconductor pattern; A first gate insulating layer is disposed between the first semiconductor layer and the first conductive layer; A second active element is disposed between the first active element and the substrate, and has a second semiconductor pattern and a second gate; as well as The second capacitor is overlapped with the first capacitor and has a third capacitor electrode and a fourth capacitor electrode, wherein the second semiconductor pattern and the third capacitor electrode are formed in the second semiconductor layer, and the fourth capacitor electrode and the second gate are formed in the second conductive layer. 2 . The display panel as claimed in claim 1 , wherein a material of the first semiconductor layer comprises indium gallium zinc oxide, and a material of the second semiconductor layer comprises polysilicon.

3. The display panel according to claim 1, further comprising: A fifth capacitor electrode is disposed between the first capacitor and the second capacitor; A second gate insulating layer is disposed between the second conductive layer and the fifth capacitor electrode; as well as The interlayer insulating layer is disposed between the first semiconductor layer and the fifth capacitor electrode, wherein the fifth capacitor electrode and the fourth capacitor electrode form a third capacitor, and the fifth capacitor electrode and the first capacitor electrode form a fourth capacitor. 4 . The display panel as claimed in claim 1 , wherein the first active element further comprises a third gate, the first semiconductor pattern is located between the first gate and the third gate, and the third gate is formed in the second conductive layer.

5. The display panel as claimed in claim 1, wherein the first semiconductor pattern has a channel region overlapping the first gate and a source region and a drain region respectively connected to opposite sides of the channel region, the first capacitor electrode has a first portion overlapping the second capacitor electrode and a second portion not overlapping the second capacitor electrode, the conductivity of the source region and the drain region is higher than the conductivity of the channel region, and the conductivity of the second portion of the first capacitor electrode is higher than the conductivity of the first portion.

6. A method for manufacturing a display panel as claimed in claim 1, comprising: forming a semiconductor layer on a substrate, the semiconductor layer comprising a first semiconductor pattern and a second semiconductor pattern; forming a patterned gate insulating layer using the first mask layer; forming a second mask layer covering the first semiconductor pattern on the semiconductor layer; Performing an ion implantation process to transform the second semiconductor pattern not covered by the second mask layer into a first capacitor electrode, wherein the conductivity of the first semiconductor pattern is different from the conductivity of the first capacitor electrode; as well as A conductive layer is formed, the conductive layer includes a first gate and a second capacitor electrode, the gate insulation layer is located between the conductive layer and the semiconductor layer, wherein the first gate and the first semiconductor pattern form an active element, and the first capacitor electrode and the second capacitor electrode form a capacitor.

7. The method for manufacturing a display panel according to claim 6, further comprising: After the step of forming the gate insulating layer is completed, an etching process is performed on the first mask layer to form the second mask layer. 8 . The method for manufacturing a display panel as claimed in claim 6 , wherein a thickness of a portion of the first mask layer overlapping the first semiconductor pattern and the first gate is greater than a thickness of another portion of the first mask layer overlapping the second semiconductor pattern. 9 . The method for manufacturing a display panel as claimed in claim 6 , wherein the ion implantation process is performed after the gate insulating layer is formed. 10 . The method for manufacturing a display panel as claimed in claim 6 , wherein the ion implantation process is performed before forming the gate insulating layer.

11. The method for manufacturing a display panel according to claim 6, further comprising: Using the conductive layer as a mask, another ion implantation step is performed on the first semiconductor pattern and the first capacitor electrode, so that the first semiconductor pattern is divided into a source region, a drain region and a channel region, and the first capacitor electrode is divided into a first part and a second part, wherein the conductivity of the source region and the drain region is higher than the conductivity of the channel region, and the conductivity of the second part is higher than the conductivity of the first part.

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