Semiconductor device and method of monitoring temperature of semiconductor device

Abstract

A semiconductor device and a method of monitoring a temperature of a semiconductor device, the semiconductor device including a temperature-independent current generator that generates a reference current that is substantially temperature-independent and a mirror current that is a substantially replica of the reference current, a pulse signal generator that samples the mirror current to generate a pulse signal, and a counter that obtains a number of the pulse signals generated by the pulse signal generator, allows the pulse signal generator to generate the pulse signal when it is determined that the number of the pulse signals thus obtained is less than a predetermined threshold, and inhibits the pulse signal generator from generating the pulse signal when it is determined that the number of the pulse signals thus obtained is equal to the predetermined threshold.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device, and more particularly to a semiconductor device comprising a temperature-independent current generator. Background Technology

[0002] Semiconductor devices such as integrated circuits (ICs) are specified to operate within a specific temperature range. Typically, if a semiconductor device operates at high speed, the resulting heat increases. Summary of the Invention

[0003] One embodiment of this disclosure provides a semiconductor device including a temperature-independent current generator, a first pulse signal generator, and a first counter. The temperature-independent current generator generates a temperature-independent reference current and a mirror current of a replica of the reference current. The first pulse signal generator is coupled to the temperature-independent current generator and samples the mirror current to generate a pulse signal. The first counter is coupled to the first pulse signal generator and acquires a first number of pulse signals generated by the first pulse signal generator. When it is determined that the first number of pulse signals acquired is less than a predetermined threshold, the first pulse signal generator is allowed to generate pulse signals, and when it is determined that the first number of pulse signals acquired is equal to the predetermined threshold, the first pulse signal generator is prohibited from generating pulse signals.

[0004] Another embodiment of this disclosure provides a semiconductor device including a temperature-dependent current generator, a second pulse signal generator, and a second counter. The temperature-dependent current generator generates a temperature-dependent current. The second pulse signal generator is coupled to the temperature-dependent current generator and samples the temperature-dependent current to generate a pulse signal. The second counter is coupled to the second pulse signal generator and acquires the number of pulse signals generated by the second pulse signal generator. When it is determined that the number of pulse signals acquired is less than a predetermined threshold, the second pulse signal generator is allowed to generate pulse signals; when it is determined that the number of pulse signals acquired is equal to the predetermined threshold, the second pulse signal generator is prohibited from generating pulse signals.

[0005] Another embodiment of this disclosure provides a method for monitoring the temperature of a semiconductor device, comprising the steps of: generating a temperature-independent reference current; replicating the reference current to generate a first mirror current, a second mirror current, and a third mirror current; sampling the first mirror current to generate a plurality of first pulse signals; counting a first number of the first pulse signals to generate a first digital code; generating a temperature-dependent current based on the second and third mirror currents; sampling the temperature-dependent current to generate a plurality of second pulse signals; and counting a second number of the second pulse signals to generate a second digital code, thereby using the first digital code and the second digital code to monitor the temperature of the semiconductor device. Attached Figure Description

[0006] The various aspects of this disclosure can be best understood in conjunction with the accompanying drawings and the following detailed description.

[0007] Figure 1 Schematic block diagrams illustrating exemplary semiconductor devices according to various embodiments of this disclosure;

[0008] Figure 2 A schematic circuit diagram illustrating various embodiments of a temperature-independent current generator according to this disclosure;

[0009] Figure 3A A schematic circuit diagram illustrating an exemplary first pulse signal generator according to various embodiments of this disclosure;

[0010] Figure 3B A schematic circuit diagram illustrating various embodiments of the second pulse signal generator according to this disclosure;

[0011] Figure 4 A schematic circuit diagram illustrating an exemplary switch according to various embodiments of this disclosure;

[0012] Figure 5 A schematic circuit diagram illustrating an exemplary temperature-dependent current generator according to various embodiments of this disclosure;

[0013] Figure 6 A schematic circuit diagram illustrating exemplary current mismatch correction circuits / voltage offset correction circuits according to various embodiments of this disclosure;

[0014] Figure 7 A schematic circuit diagram illustrating another exemplary temperature-dependent current generator according to various embodiments of this disclosure;

[0015] Figure 8 A schematic circuit diagram illustrating another exemplary temperature-dependent current generator according to various embodiments of this disclosure;

[0016] Figure 9 A schematic circuit diagram illustrating an exemplary first counter according to various embodiments of the present disclosure;

[0017] Figure 10 A schematic circuit diagram illustrating various embodiments of the second counter according to this disclosure;

[0018] Figure 11 A schematic circuit diagram illustrating another exemplary second counter according to various embodiments of the present disclosure;

[0019] Figure 12 A schematic circuit diagram illustrating an exemplary semiconductor device coupled to an external temperature measuring instrument according to various embodiments of the present disclosure;

[0020] Figure 13 Schematic timing diagrams illustrating exemplary signals associated with semiconductor devices according to various embodiments of this disclosure;

[0021] Figure 14 A flowchart illustrating an exemplary method for monitoring the temperature of a semiconductor device according to various embodiments of this disclosure;

[0022] Figure 15 A schematic block diagram illustrating another exemplary semiconductor device according to various embodiments of the present disclosure;

[0023] Figure 16 A flowchart illustrating another exemplary method for monitoring the temperature of a semiconductor device according to various embodiments of this disclosure.

[0024] [Symbol Explanation]

[0025] 100: Semiconductor devices

[0026] 110: Temperature-independent current generator

[0027] 120: Temperature-dependent current generator

[0028] 130: Reference Voltage Generator

[0029] 140: First Pulse Signal Generator

[0030] 150: Second Pulse Signal Generator

[0031] 160: First Counter

[0032] 170: Second Counter

[0033] 210: Reference Current Generation Circuit

[0034] 220: Current mirror circuit

[0035] 230: Operational Amplifier

[0036] 310, 320: Comparators

[0037] 410: NMOS transistor

[0038] 420: PMOS transistor

[0039] 510: Current Extractor

[0040] 520: Thermal Sensor

[0041] 530: Current Mismatch Correction Circuit

[0042] 540: Voltage offset correction circuit

[0043] 550: Operational Amplifier

[0044] 700, 800: Temperature-dependent current generator

[0045] 910: First Counter Section

[0046] 920: Second Counter Section

[0047] 930: Third Counter Section

[0048] 940: First flip-flop

[0049] 950: Second flip-flop

[0050] 960: Third flip-flop

[0051] 970: Fourth flip-flop

[0052] 1010: Fourth Counter Section

[0053] 1030: Fifth Counter Section

[0054] 1110: Fourth Counter Section

[0055] 1130: Fifth Counter Section

[0056] 1200: External temperature measuring instrument

[0057] 1400: Method

[0058] 1410, 1420, 1430, 1440, 1450, 1460, 1470, 1480, 1490: Operation

[0059] 1500: Semiconductor Devices

[0060] 1600: Method

[0061] 1610, 1620, 1630, 1640, 1650, 1660, 1670, 1680, 1690: Operations

[0062] C1: Capacitor

[0063] C a_0 ~C a_x C a_i C a_i+1 C b_0 ~C b_y Output terminal

[0064] CH0, CH1: Output terminals

[0065] CHOP1, CHOP2: Chopper signals

[0066] DC1, DC2: Digital Code

[0067] ENABLE: signal

[0068] I1, I2: Current

[0069] I CTAT CTAT current

[0070] I MIRROR1 ~I MIRROR3 : Mirror current

[0071] IN: Input node

[0072] I PTAT PTAT current

[0073] I REF Reference current

[0074] M1~M5: Transistors

[0075] Measured_Done:signal

[0076] N: No

[0077] N1~N7: Nodes

[0078] OUT: Output node

[0079] PS1, PS2: Pulse signals

[0080] Q1, Q2: Transistors

[0081] R1~R6: Resistors

[0082] RESET: Reset signal

[0083] S1~S8: Switches

[0084] SWITCH1, SWITCH2: Switch signals

[0085] V1, V2: Voltage

[0086] V CAP1 V CAP2 Capacitor voltage

[0087] V CTAT First input voltage

[0088] V CTAT ':Second input voltage

[0089] V DD First power supply voltage

[0090] V REF Reference voltage

[0091] Vss: Second power supply voltage

[0092] Y: Yes

[0093] I TD Temperature-dependent current Detailed Implementation

[0094] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of elements and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. Furthermore, element symbols and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself define the relationships between the various embodiments and / or configurations discussed.

[0095] Semiconductor devices, such as integrated circuits (ICs), are designed to operate within a specific temperature range. Typically, if a semiconductor device operates at high speeds, the resulting heat increases. If this heat increase exceeds the specified temperature range, the characteristics of the semiconductor device can change in ways that may adversely affect its performance and reliability. Therefore, it may be necessary to monitor the temperature of the semiconductor device. Thermal sensors that detect temperature and generate a temperature-dependent (i.e., temperature-varying) current can be embedded within the semiconductor device. External temperature measuring instruments can then be connected to the semiconductor device to measure its temperature using this temperature-dependent current.

[0096] Thermal sensors can be implemented in semiconductor devices. In one example, the thermal sensor detects the temperature of the semiconductor device and generates a temperature-dependent (i.e., temperature-varying) current. This temperature-dependent current can be either proportional to absolute temperature (PTAT) or complementary to absolute temperature (CTAT). PTAT current has a positive temperature coefficient and is therefore directly proportional to temperature; that is, PTAT current increases with increasing temperature. Conversely, CTAT current has a negative temperature coefficient and is therefore inversely proportional to temperature; that is, CTAT current decreases with increasing temperature. When it is desired to use a temperature-dependent current to monitor the temperature of a semiconductor device, the device can be connected to an external reference clock generator. This makes temperature monitoring of the semiconductor device cumbersome, time-consuming, and inconvenient.

[0097] The systems and methods described herein include semiconductor devices, such as those according to embodiments. Figure 1 The semiconductor device 100 is configured to avoid connection to an external reference clock generator during temperature monitoring. For example, the semiconductor device 100 includes a temperature-dependent current generator (e.g., Figure 5 The device includes a temperature-dependent current generator 120 that generates a temperature-dependent current, such as a PTAT or CTAT current, which is temperature-dependent, i.e., varies with temperature. It also includes current mismatch correction circuitry, such as current mismatch correction circuitry 530, and voltage offset correction circuitry, such as voltage offset correction circuitry 540. Each circuit helps to generate a relatively accurate temperature-dependent current through the temperature-dependent current generator. Instead of an external reference clock generator, a counter, such as counter 160 or counter 170, is included in the semiconductor device to generate a chopping signal. Each of the current mismatch correction circuitry 530 and the voltage offset correction circuitry 540 responds to the chopping signal by periodically reversing its polarity, thereby enabling the temperature-dependent current generator to produce a relatively accurate temperature-dependent current.

[0098] In more detail, Figure 1 A schematic block diagram illustrating an exemplary semiconductor device 100 according to various embodiments of this disclosure is provided. Figure 1 As described, the semiconductor device 100, such as an integrated circuit (IC), includes a temperature-independent current generator 110, a temperature-dependent current generator 120, a reference voltage generator 130, a first pulse signal generator 140, a second pulse signal generator 150, a first counter 160, and a second counter 170, all connected to a circuit for receiving a first power supply voltage (V). DDNode (N1) and used to receive voltages lower than the first power supply voltage (V) DD The second power supply voltage (Vss) (e.g., 0V) is between nodes (N2).

[0099] Temperature-independent current generator 110 is used to generate a reference current, for example. Figure 2 The reference current (I) in REF The temperature-independent current generator 110 is essentially independent of temperature, meaning it does not change with temperature. The temperature-independent current generator 110 is further used to generate one or more mirror currents (I0). MIRROR1 ~I MIRROR3 ), which is essentially the reference current (I REF ) copy.

[0100] Reference voltage generator 130 is used to generate a reference voltage (V) REF In an exemplary embodiment, the reference voltage (V) REF ) is the power supply voltage (V) DD A small portion of the reference voltage generator. In this exemplary embodiment, the reference voltage generator 130 may be in the form of a voltage divider and includes a pair of resistors connected in series between nodes (N1, N2) and a reference voltage (V) located between the resistors. REF The mating surface of the reference voltage generator 130 is used in other embodiments.

[0101] The first pulse signal generator 140 is connected to the temperature-independent current generator 110 and the reference voltage generator 130, and is used to apply the reference voltage (V). REF ) for mirror current (I MIRROR1 Sampling is performed to generate a pulse signal (PS1).

[0102] The first counter 160 is connected to the first pulse signal generator 140 and is used to count / acquire the number of pulse signals (PS1) generated by the first pulse signal generator 140. The first counter 160 is further used to output a digital code (DC1), i.e., a sequence of 1s and 0s, representing the number of pulse signals (PS1) thus acquired. Note that the digital code (DC1) of the first counter 160 and the digital code (DC2) of the second counter 170 can be used by an external temperature measuring instrument coupled to the semiconductor device 100 to measure the temperature of the semiconductor device 100, for example... Figure 12 The external temperature measuring instrument is 1200.

[0103] The first counter 160 is further used to determine whether the number of pulse signals (PS1) obtained therefrom is less than or equal to a predetermined threshold value. When it is determined that the number of pulse signals (PS1) obtained therefrom is less than the predetermined threshold value, the first pulse signal generator 140 is allowed to generate pulse signals, and when it is determined that the number of pulse signals (PS1) obtained therefrom is equal to the predetermined threshold value, the first pulse signal generator 140 is prohibited from generating pulse signals.

[0104] Temperature-dependent current generator 120 is connected to temperature-independent current generator 110 and is used to generate current based on mirror current (Ii). MIRROR2 I MIRROR3 This generates a temperature-dependent (i.e., temperature-varying) temperature-dependent current (I0). TD In this exemplary embodiment, the temperature-dependent current (I) TD The temperature-dependent current (TAT) increases as the temperature of the semiconductor device 100 increases, and is therefore referred to as the PTAT current. In an alternative embodiment, the temperature-dependent current (ITAT) increases as the temperature of the semiconductor device 100 increases, and is therefore referred to as the PTAT current. TD The current decreases as the temperature of the semiconductor device 100 increases, and is therefore referred to as the CTAT current.

[0105] The second pulse signal generator 150 is connected to the temperature-dependent current generator 120 and the reference voltage generator 130, and is used to apply the reference voltage (V). REF ) for temperature-dependent current (I TD The sample is taken to generate a pulse signal (PS2).

[0106] The second counter 170 is connected to the second pulse signal generator 150 and the first counter 160 and is used to count / acquire the number of pulse signals (PS2) generated by the second pulse signal generator 150. The second counter 170 is further used to output a digital code (DC2), i.e., a sequence of 1s and 0s, indicating the number of pulse signals (PS2) thus acquired. As described above, the semiconductor device 100 can be coupled to an external temperature measuring instrument that uses digital codes (DC1, DC2) to measure its temperature, for example... Figure 12 The external temperature measuring instrument is 1200.

[0107] An exemplary support circuit for the temperature-independent current generator 110 is in Figure 2 The circuits are depicted in the diagram. It should be understood that these circuits are provided as examples and not as limitations, and other suitable temperature-independent current generator 110 circuits are within the scope of this disclosure. Figure 2 A schematic circuit diagram illustrating an exemplary temperature-independent current generator 110 according to various embodiments of this disclosure is provided. Figure 2As described, the temperature-independent current generator 110 is in the form of a bandgap circuit and includes a reference current generation circuit 210 and a current mirror circuit 220. The reference current generation circuit 210 is used to generate a reference current (I0). REF The circuit includes an operational amplifier 230, transistors (M1, Q1), and resistors R1 and R2. A current mirror circuit 220 is connected to a reference current generation circuit 210 and is used to generate one or more mirror currents (I0, I0). MIRROR1 ~I MIRROR3 These mirror currents are the reference currents (I). REF A substantial copy (e.g., within 1%, 5%, or 10%), and comprising one or more transistors (M2 to M4).

[0108] During operation, after startup, operational amplifier 230 forces the input voltages at its op-amp inputs to be substantially equal. Therefore, the output of operational amplifier 230 transitions from a high signal level to a low signal level. This activates transistors (M1, Q1). Consequently, the PTAT current (I...) PTAT The current flows through resistor (R1) and transistor (Q1), and the CTAT current flows through resistor (R2). For example... Figure 2 As explained, the CTAT current (I) CTAT Add to PTAT current (I) PTAT Thus, the reference current generating circuit 210 generates a reference current (I). REF Since transistors (M2-M4) are connected in parallel with transistor (M1), the reference current (I) is essentially the current used for reference. REF The mirror current (I) of the replica MIRROR1 ~I MIRROR3 ) flows through transistors (M2~M4).

[0109] The exemplary support circuits for the first pulse signal generator 140 and the second pulse signal generator 150 are respectively in Figure 3A and Figure 3B The circuits are depicted in the diagram. It should be understood that these circuits are provided as examples and not as limitations, and other suitable first pulse signal generator 140 circuits and second pulse signal generator 150 circuits are within the scope of this disclosure. Figure 3A A schematic circuit diagram illustrating an exemplary first pulse signal generator 140 according to various embodiments of the present disclosure. Figure 3B A schematic circuit diagram illustrating various embodiments of the exemplary second pulse signal generator 150 according to this disclosure is provided. Figure 3AAs described, the first pulse signal generator 140 includes a first switch (S1), a second switch (S2), a capacitor (C1), and a comparator 310. The first switch (S1) and the second switch (S2) respond to a switch signal (SWITCH1) from the first counter 160, controlling their switching actions in the manner described below. Although not shown, an inverter is connected between the first counter 160 and the second switch (S2). Similarly, when the switch signal (SWITCH1) at the first switch (S1) is at a high / low signal level, the complement of the switch signal (SWITCH1), i.e., a low / high signal level, is at the second switch (S2), and vice versa.

[0110] The first switch (S1) has a first switch terminal connected to the temperature-independent current generator 110, a second switch terminal connected to node (N3), and a third switch terminal for receiving a switch signal (SWITCH1). The second switch (S2) has a first switch terminal connected to node (N2), a second switch terminal connected to node (N3), and a third switch terminal for receiving a switch signal (SWITCH1).

[0111] The capacitor (C1) is connected in parallel with the second switch (S2). The comparator 310 has a first comparator input connected to node (N3), a second comparator input connected to reference voltage generator 130, and a comparator output connected to first counter 160.

[0112] like Figure 3B As described, the second pulse signal generator 140 includes a first switch (S3), a second switch (S4), a capacitor (C2), and a comparator 320. The first switch (S3) and the second switch (S4) control their switching operation in response to a switch signal (SWITCH2) from the second counter 170 in the manner described below. Although not shown, an inverter is connected between the second counter 170 and the second switch (S4). Similarly, when the switch signal (SWITCH2) at the first switch (S3) is at a high / low signal level, the complement of the switch signal (SWITCH2), i.e., a low / high signal level, is at the second switch (S4), and vice versa.

[0113] The first switch (S3) has a first switch terminal connected to the temperature-dependent current generator 120, a second switch terminal connected to node (N4), and a third switch terminal for receiving a switch signal (SWITCH2). The second switch (S4) has a first switch terminal connected to node (N2), a second switch terminal connected to node (N4), and a third switch terminal for receiving a switch signal (SWITCH2).

[0114] The capacitor (C2) is connected in parallel with the second switch (S4). The comparator 320 has a first comparator input connected to node (N4), a second comparator input connected to the reference voltage generator 130, and a comparator output connected to the second counter 170.

[0115] During operation, pulse signal generators 140 and 150 receive switch signals (SWITCH1, SWITCH2) with high signal levels, thereby enabling the first switch (S1, S3) and substantially simultaneously disabling the second switch (S2, S4). This action charges capacitors (C1, C2). Consequently, a capacitor voltage (V) appears at nodes (N3, N4). CAP1 V CAP2 The capacitor voltage (V) increases. CAP1 V CAP2 Increased to substantially equal to the reference voltage (V) REF When the pulse signals (PS1, PS2) at the comparator outputs of comparators 310 and 320 change from a low signal level to a high signal level, pulse signal generators 140 and 150 receive switch signals (SWITCH1, SWITCH2) with a low signal level, thereby disabling the first switch (S1, S3) and substantially enabling the second switch (S2, S4) simultaneously. This causes capacitors (C1, C2) to discharge. This, in turn, results in a capacitor voltage (V) appearing at nodes (N3, N4). CAP1 V CAP2 The capacitor voltage (V) decreases. CAP1 V CAP2 Reduced to below the reference voltage (V) REF When the pulse signals (PS1, PS2) at the comparator output terminals of comparators 310 and 320 change from a high signal level back to a low signal level, the pulse signal generators 140 and 150 generate pulse signals (PS1, PS2).

[0116] In an exemplary embodiment, at least one of the switches (S1 to S4) has Figure 4 The configuration shown. Other configurations using switches (S1 to S4) in other embodiments. Figure 4 Schematic circuit diagrams illustrating exemplary switches (S1 to S4) according to various embodiments of this disclosure are provided. Figure 4As explained, the switches (S1 to S4) are of the transmission gate type and include an N-type metal-oxide-semiconductor (NMOS) transistor 410, a P-type MOS transistor (PMOS) 420 connected in parallel with the NMOS transistor 410, an input node (IN) connected between the source of the NMOS transistor 410 and the source of the PMOS transistor 420 and serving as the first switching terminal of the switches (S1 to S4), and an output node (OUT) connected between the drain of the NMOS transistor 410 and the drain of the PMOS transistor 420 and serving as the second switching terminal of the switches (S1 to S4). A node (N5), serving as the third switching terminal of the switches (S1 to S4), is connected to the gate of the NMOS transistor 410. An inverter 430 is connected between node (N5) and the gate of the PMOS transistor 420. Therefore, when the switch signal at node (N5) (i.e., the third switch terminal of switches S1 to S4) is at a high signal level, NMOS transistor 410 and PMOS transistor 420 are enabled and a low-resistance path exists between the input node (IN) and the output node (OUT) (i.e., between the first switch terminal and the second switch terminal of switches S1 to S4).

[0117] On the other hand, when the switch signal at node (N5) (i.e., the third switch terminal of switches S1 to S4) is at a low signal level, NMOS transistor 410 and PMOS transistor 420 are disabled, and a high resistance path exists between the input node (IN) and the output node (OUT) (i.e., between the first switch terminal and the second switch terminal of switches S1 to S4).

[0118] An exemplary support circuit for the temperature-dependent current generator 120 is in Figure 5 The circuits are depicted in the diagram. It should be understood that these circuits are provided as examples and not as limitations, and other temperature-dependent current generator 120 circuits are within the scope of this disclosure. Figure 5 A schematic circuit diagram illustrating an exemplary temperature-dependent current generator 120 according to various embodiments of this disclosure is provided. Figure 5 As described, the temperature-dependent current generator 120 includes a current extractor 510 and a thermal sensor 520. The current extractor 510 is used to generate a self-mirror current (Ir). MIRROR3 Extract temperature-dependent current (I) TDThe current, PTAT, is included in the current mismatch correction circuit 530, voltage offset correction circuit 540, operational amplifier 550, transistor (M5), and resistor (R3). The current mismatch correction circuit 530 has positive and negative input terminals connected to the drains of transistors (M3, M4) of the temperature-independent current generator 110, respectively, and positive and negative output terminals connected to nodes (N6, N7), respectively.

[0119] The voltage offset correction circuit 540 has a positive input terminal connected to node (N6) and a negative input terminal connected to node (N8). The voltage offset correction circuit 540 further has a positive output terminal and a negative output terminal connected to the first and second op-amp input terminals of operational amplifier 550, respectively. The op-amp output terminal of operational amplifier 550 is connected to the gate of transistor (M5). The source of transistor (M5) is connected to node (N8). Resistor (R3) has a substantially zero temperature coefficient and is connected between node (N2) and node (N8). In this exemplary embodiment, the thermal sensor 520 includes a transistor (Q2) having a negative temperature coefficient and including a source connected to node (N6) and a gate and drain connected to each other and connected to node (N2).

[0120] During operation, please refer to Figure 5 The thermal sensor 520 detects the temperature of the semiconductor device 100. Simultaneously, the mirror current (I...) MIRROR2 I MIRROR3 The current flows from transistors (M3, M4) to nodes (N6, N7) via the current mismatch correction circuit 530. Because transistor (Q2) has a negative temperature coefficient, meaning the voltage across transistor (Q2) is inversely proportional to temperature, the first input voltage (V) CTAT The first input voltage (V) appears at the first op-amp input terminal of operational amplifier 550. Then, operational amplifier 550 converts the first input voltage (V) into voltage at the first op-amp input terminal. CTAT This is converted into a CTAT current (I) flowing through the resistor (R3) and the transistor (M5). CTAT ), thus the second input voltage (V CTAT The ') appears at the second op-amp input of operational amplifier 550. For example... Figure 5 As explained, the self-image current (I) MIRROR3 Subtract CTAT current (I) CTAT ), thus the current extractor 510 self-mirror current (I MIRROR3 Extract temperature-dependent current (I) TD This refers to the PTAT current.

[0121] Ideally, the mirror current (I) flowing through the transistors (M3, M4) MIRROR2 I MIRROR3The threshold voltages of transistors (M3, M4) may differ from each other due to variations in manufacturing processes, transistor aging, etc. Therefore, even if transistors (M3, M4) have substantially the same dimensions, i.e., substantially equal W / L ratios, the mirror current (IL) will be different. MIRROR2 I MIRROR3 Significant current mismatch may still occur. A current mismatch correction circuit 530 is used to reduce this current mismatch. For example, in an exemplary embodiment, the current mismatch correction circuit 530 has… Figure 6 The configuration shown is illustrated. Other configurations of the current mismatch correction circuit 530 are used in other embodiments. Figure 6 A schematic circuit diagram illustrating an exemplary current mismatch correction circuit 530 according to various embodiments of this disclosure is provided. Figure 6 As explained, the current mismatch correction circuit 530 responds to the chopper signal (CHOP1) that transitions between the high and low signal levels of the first counter 160, reducing the mirror current (I) in a manner described below. MIRROR2 I MIRROR3 The current mismatch occurs between the current input and output of the current mismatch correction circuit 530. For example, when the chopper signal (CHOP1) is at a high signal level, that is, when the switches (S5, S8) are enabled and the switches (S6, S7) are disabled, the positive input of the current mismatch correction circuit 530 is connected to the positive output of the current mismatch correction circuit 530, and the negative input of the current mismatch correction circuit 530 is connected to the negative input of the current mismatch correction circuit 530. Therefore, the current (I1) at the positive output of the current mismatch correction circuit 530 is the mirror current (I1) at the positive input of the current mismatch correction circuit 530. MIRROR2 The value is equal to the value of the negative output current (I2) of the current mismatch correction circuit 530 and the value of the mirror current (I) of the negative input current of the current mismatch correction circuit 530. MIRROR3 )value.

[0122] On the other hand, when the chopper signal (CHOP1) is at a low signal level, that is, when switches (S5, S8) are disabled and switches (S6, S7) are enabled, the positive input terminal of the current mismatch correction circuit 530 is connected to the negative output terminal of the current mismatch correction circuit 530, and the negative input terminal of the current mismatch correction circuit 530 is connected to the positive output terminal of the current mismatch correction circuit 530. Therefore, the current (I1) at the positive output terminal of the current mismatch correction circuit 530 is the mirror current (I1) at the negative input terminal of the current mismatch correction circuit 530. MIRROR3 The value is equal to the value of the negative output current (I2) of the current mismatch correction circuit 530, and the value of the current mirrored at the positive input current (I) of the current mismatch correction circuit 530 is equal to the value of the current mirrored at the positive input current (I). MIRROR2 That is, by periodically reversing the polarity of the current mismatch correction circuit 530, the average value of the current (I1) eventually becomes the mirror current (Imirror current). MIRROR2I MIRROR3 The average value of the current (I2) is the average value of the mirror current (I). Similarly, the average value of the current (I2) eventually becomes the mirror current (I). MIRROR2 I MIRROR3 The average value of ). Therefore, when in the mirror current (I MIRROR2 I MIRROR3 When current mismatch occurs between I1 and I2, the average values ​​of the currents can be made equal to each other. Thus, even if the current mismatch cannot be eliminated, it can be reduced by the current mismatch correction circuit 530.

[0123] Ideally, the input voltage (V) at the op-amp input terminal of operational amplifier 550 CTAT V CTAT The input transistors are essentially the same size, i.e., have substantially the same W / L ratio, but their threshold voltages may differ due to variations in manufacturing processes, transistor aging, etc. Therefore, even if the input transistors have substantially the same dimensions, i.e., substantially the same W / L ratio, the input voltage (V) will be different from each other. CTAT V CTAT The voltage offset between the two voltages can still be quite high. Voltage offset correction circuit 540 is used to reduce this voltage offset. For example, in an exemplary embodiment, voltage offset correction circuit 540 has… Figure 6 The configuration shown is illustrated. Other configurations of the voltage offset correction circuit 540 are used in other embodiments. Figure 6 A schematic circuit diagram illustrating the voltage offset correction circuit 540 according to various embodiments of this disclosure. For example... Figure 6 As explained, the voltage offset correction circuit 540 responds to the chop signal (CHOP2) that switches between the high and low signal levels of the first counter 160, reducing the input voltage (V) in a manner described below. CTAT V CTAT The voltage offset between the current mismatch correction circuit 530 and the current mismatch correction circuit 540. For example, when the chopper signal (CHOP2) is at a high signal level, that is, when the switches (S5, S8) are enabled and the switches (S6, S7) are disabled, the positive input terminal of the voltage offset correction circuit 540 is connected to the positive output terminal of the voltage offset correction circuit 540, and the negative input terminal of the voltage offset correction circuit 540 is connected to the negative output terminal of the voltage offset correction circuit 540. Therefore, the voltage (V1) at the positive output terminal of the current mismatch correction circuit 530 is equal to the input voltage (V1) at the positive input terminal of the voltage offset correction circuit 540. CTAT The voltage (V2) at the negative output terminal of the voltage offset correction circuit 540 is equal to the input voltage (V) at the negative input terminal of the voltage offset correction circuit 540. CTAT ')value.

[0124] On the other hand, when the chopping signal (CHOP2) is at a low signal level, that is, when switches (S5, S8) are disabled and switches (S6, S7) are enabled, the positive input terminal of the voltage offset correction circuit 540 is connected to the negative output terminal of the voltage offset correction circuit 540, and the negative input terminal of the voltage offset correction circuit 540 is connected to the positive output terminal of the voltage offset correction circuit 540. Therefore, the voltage (V1) at the positive output terminal of the voltage offset correction circuit 540 is equal to the input voltage (V1) at the negative input terminal of the voltage offset correction circuit 540. CTAT The voltage (V2) at the negative output terminal of the voltage offset correction circuit 540 is equal to the input voltage (V) at the positive input terminal of the voltage offset correction circuit 540. CTAT The value of ) is obtained by periodically reversing the polarity of the voltage offset correction circuit 530. That is, by periodically reversing the polarity of the voltage offset correction circuit 530, the average value of the voltage (V1) eventually becomes the input voltage (V). CTAT V CTAT The average value of the current (V2) is the average value of the input voltage (V). Similarly, the average value of the current (V2) eventually becomes the average value of the input voltage (V). CTAT V CTAT The average value of '). Therefore, when the input voltage (V CTAT V CTAT When a voltage offset occurs between (V1, V2), the average values ​​of the voltages can be made equal to each other. Thus, even if the voltage offset cannot be eliminated, it can be reduced by the voltage offset correction circuit 540.

[0125] Figure 7 A schematic circuit diagram illustrating another exemplary temperature-dependent current generator 700 according to various embodiments of this disclosure is provided. The temperature-dependent current generator 700 differs from the temperature-dependent current generator 120 in that the thermal sensor 520 of the temperature-dependent current generator 700 includes a resistor (R4) having a negative temperature coefficient connected between nodes (N2, N6). In an alternative embodiment, the thermal sensor 520 of the temperature-dependent current generator 700 includes a diode having a negative temperature coefficient connected between nodes (N2, N6).

[0126] During operation, please refer to Figure 7 The thermal sensor 520 detects the temperature of the semiconductor device 100. Simultaneously, the mirror current (I...) MIRROR2 I MIRROR3 The current flows from transistors (M3, M4) to nodes (N6, N7) via the current mismatch correction circuit 530. Because resistor (R4) has a negative temperature coefficient, meaning the voltage across resistor (R4) is inversely proportional to temperature, the first input voltage (V) CTAT The first input voltage (V) appears at the first op-amp input terminal of operational amplifier 550. Then, operational amplifier 550 converts the first input voltage (V) into voltage at the first op-amp input terminal. CTATThis is converted into a CTAT current (I) flowing through the transistor (M5) and resistor (R3). CTAT ), thus the second input voltage (V CTAT The ') appears at the second op-amp input of operational amplifier 550. For example... Figure 7 As explained, the self-image current (I) MIRROR3 Subtract CTAT current (I) CTAT ), thus the current extractor 510 self-mirror current (I MIRROR3 Extract temperature-dependent current (I) TD This refers to the PTAT current.

[0127] Figure 8 This is a schematic circuit diagram illustrating another exemplary temperature-dependent current generator 800 according to various embodiments of the present disclosure. The temperature-dependent current generator 800 of this embodiment differs from the temperature-dependent current generator 120 in that the current extractor 510 of the temperature-dependent current generator 800 is used for self-mirror current (I0). MIRROR3 Subtract the PTAT current from the self-mirror current (I) MIRROR3 Extract temperature-dependent current (I) TD This refers to the CTAT current. The thermal sensor 520 of the temperature-dependent current generator 800 includes a resistor (R5) that has a positive temperature coefficient and is connected between nodes (N2, N6).

[0128] During operation, please refer to Figure 8 The thermal sensor 520 detects the temperature of the semiconductor device 100. Simultaneously, the mirror current (I...) MIRROR2 I MIRROR3 The current flows from transistors (M3, M4) to nodes (N6, N7) via the current mismatch correction circuit 530. Because resistor (R5) has a positive temperature coefficient, meaning the voltage across resistor (R6) is proportional to temperature, the first input voltage (V) PTAT The first input voltage (V) appears at the first op-amp input terminal of operational amplifier 550. Then, operational amplifier 550 converts the first input voltage (V) into voltage at the first op-amp input terminal. PTAT This is converted into PTAT current (I) flowing through resistor (R5) and transistor (M5). PTAT ), thus the second input voltage (V PTAT The ') appears at the second op-amp input of operational amplifier 550. For example... Figure 8 As explained, the self-image current (I) MIRROR3 Subtract PTAT current (I) PTAT ), thus the current extractor 510 self-mirror current (I MIRROR3 Extract temperature-dependent current (I) TD ), that is, CTAT current.

[0129] An exemplary support circuit for the first counter 160 in Figure 9 The circuits are depicted in the diagram. It should be understood that these circuits are provided as examples and not as limitations, and other first counter 160 circuits are within the scope of this disclosure. Figure 9 A schematic circuit diagram illustrating an exemplary first counter 160 according to various embodiments of this disclosure is provided. Figure 9 As described, the first counter 160 includes a first counter section 910, a second counter section 920, and a third counter section 930. The first counter section 910 includes multiple flip-flops, such as D-type flip-flops, and AND gates. Each flip-flop has an output terminal (C). a_0 ~C a_X Output terminal (C) a_i+1 The AND gate is connected to the reset terminal of the flip-flop. It has a first input terminal connected to the pulse signal generator 140 to receive a pulse signal (PS1) and a second input terminal for receiving an ENABLE signal. The ENABLE signal can be provided by internal or external circuitry of the semiconductor device 100. The output terminal of the AND gate is connected to the clock terminal of the first flip-flop of the first counter section 910 and the switches (S1, S2) of the pulse signal generator 140. This structure of the first counter section 910 allows the first counter 160 to count / acquire the number of pulse signals (PS1) generated by the pulse signal generator 140, output the number of pulse signals (PS1) thus acquired in the form of a series of bits, and generate a switch signal (SWITCH1) and a reset signal (RESET).

[0130] The second counter section 920 includes a first flip-flop 940, a second flip-flop 950, a third flip-flop 960, and a fourth flip-flop 970, such as a d-type flip-flop, an AND gate, and a NAND gate, such as an AND gate and an inverter connected in series. Each of the first flip-flop 940 and the second flip-flop 950 has an output terminal (CH0, CH1). The AND gate has an output terminal (C) connected to the first counter section 910. a_i The first input terminal of the flip-flop 940, the second input terminal for receiving the ENABLE signal, and the output terminal connected to the clock terminal of the first flip-flop 940 are all provided. Each of the third flip-flop 960 and the fourth flip-flop 970 has an input terminal connected to a corresponding output terminal (CH0, CH1). The NAND gate has an output terminal (C...) connected to the first counter section 910. a_i The second counter section 920 has a first input terminal, a second input terminal for receiving the ENABLE signal, and an output terminal connected to the clock terminals of the third flip-flop 960 and the fourth flip-flop 970. This structure of the second counter section 920 allows the first counter 160 to generate chopped signals (CHOP1, CHOP2).

[0131] The third counter section 930 includes multiple flip-flops (e.g., d-type flip-flops) and NAND gates (e.g., a series-connected AND gate and inverter). Each flip-flop has a corresponding output terminal (C) connected to the first counter section 910. a_0 ~C a_X The NAND gate has an input terminal connected to the first counter section 910. a_i The third counter section 930 has a first input terminal, a second input terminal for receiving the ENABLE signal, and an output terminal connected to the clock terminal of the flip-flop. This structure of the third counter section 930 allows the first counter 160 to output a digital code (DC1) to an external temperature measuring instrument, such as... Figure 12 The external temperature measuring instrument is 1200.

[0132] An exemplary support circuit for the second counter 170 is in Figure 10 The circuits are depicted in the diagram. It should be understood that these circuits are provided as examples and not as limitations, and other second counter 170 circuits are within the scope of this disclosure. Figure 10 A schematic circuit diagram illustrating an exemplary second counter 170 according to various embodiments of this disclosure is provided. Figure 10 As described, the second counter 170 includes a fourth counter section 1010 and a fifth counter section 1030. The fourth counter section 1010 includes multiple flip-flops, such as D-type flip-flops and AND gates. Each flip-flop in the fourth counter section 1010 has an output terminal (C). b_0 ~C b_Y The output terminal (C) of the first counter section 910. a_i+1 The AND gate is connected to the reset terminal of the flip-flop of the fourth counter section 1010. The AND gate has a first input terminal connected to the pulse signal generator 150 for receiving the pulse signal (PS2) and an output terminal connected to the first counter section 910 (C). a_i The second input terminal of the AND gate is connected to the clock terminal of the first flip-flop of the fourth counter section 1010 and the switches (S3, S4) of the pulse signal generator 150. This structure of the fourth counter section 1010 allows the second counter 170 to count / acquire the number of pulse signals (PS2) generated by the pulse signal generator 150, and output the number of pulse signals (PS2) obtained therefrom in the form of a series of bits to generate a switch signal (SWITCH2).

[0133] The fifth counter section 1030 includes multiple flip-flops (e.g., d-type flip-flops) and NAND gates (e.g., a series-connected AND gate and inverter). Each flip-flop has a corresponding output terminal (C) connected to the fourth counter section 1010. b_0 ~C b_YThe NAND gate has an input terminal connected to the first counter section 910. a_i The fifth counter section 1030 has a first input terminal, a second input terminal for receiving the ENABLE signal, and an output terminal connected to the clock terminal of the flip-flop. This structure of the fifth counter section 1030 allows the second counter 170 to output a digital code (DC2) to an external temperature measuring instrument, such as... Figure 12 The external temperature measuring instrument is 1200.

[0134] Figure 11 A schematic circuit diagram illustrating another exemplary second counter 170 according to various embodiments of this disclosure is provided. Figure 11 As described, the second counter 170 includes a fourth counter section 1110 and a fifth counter section 1130. The fourth counter section 1110 includes multiple flip-flops, such as D-type flip-flops and AND gates. Each flip-flop in the fourth counter section 1110 has an output terminal (C). b_0 ~C b_Y The clock terminal of the first flip-flop of the fourth counter section 1110 receives a pulse signal (PS2) from the pulse signal generator 150 and is connected to the switches (S3, S4) of the pulse signal generator 150. The output terminal (C) of the first counter section 910... a_i+1 The AND gate is connected to the reset terminal of the flip-flop of the fourth counter section 1110. The AND gate has an output terminal (C) connected to the first counter section 910. a_i The first input terminal of the AND gate and the second input terminal for receiving the ENABLE signal are connected. The output terminal of the AND gate is connected to the enable terminal of the flip-flop of the fourth counter section 1110. This structure of the fourth counter section 1110 allows the second counter 170 to count / obtain the number of pulse signals (PS2) generated by the pulse signal generator 150, so as to output the number of pulse signals (PS2) obtained therefrom in the form of a series of bits, and generate a switch signal (SWITCH2).

[0135] The fifth counter section 1130 includes multiple flip-flops (e.g., d-type flip-flops) and NAND gates (e.g., a series-connected AND gate and inverter). Each flip-flop in the fifth counter section 1130 has a corresponding output terminal (C) connected to the fourth counter section 1110. b_0 ~C b_Y The NAND gate has an input terminal connected to the first counter section 910. a_i The fifth counter section 1130 has a first input terminal, a second input terminal for receiving the ENABLE signal, and an output terminal connected to the clock terminal of the flip-flop. This structure of the fifth counter section 1130 allows the second counter 170 to output a digital code (DC2) to an external temperature measuring instrument, such as... Figure 12 The external temperature measuring instrument is 1200.

[0136] Figure 12 This is a schematic circuit diagram illustrating an exemplary semiconductor device 100 coupled to an external temperature measuring instrument 1200 according to various embodiments of this disclosure. As described above, the external temperature measuring instrument 1200 is used to measure the temperature of the semiconductor device 100. For example, such as Figure 12 As described, the external temperature measuring instrument 1200 is coupled to the first counter 160 and the second counter 170 via, for example, the output pin of the semiconductor device 100, and receives a first digital code (DC1) and a second digital code (DC2). The external temperature measuring instrument 1200 has a pre-established lookup table that stores the ratio of the second digital code (DC2) to the first digital code (DC1) and its corresponding temperature value. The external temperature measuring instrument 1200 receives the first digital code (DC1) and the second digital code (DC2), calculates the ratio of the second digital code (DC2) to the first digital code (DC1), and converts the calculated ratio into a temperature by referring to the pre-established lookup table. After measuring the temperature of the semiconductor device 100, the external temperature measuring instrument 1200 sends a Measured_Done signal to the first counter 160.

[0137] In an alternative embodiment, the first counter 160 does not output a digital code (DC1) to the external temperature measuring instrument 1200. In this alternative embodiment, the external temperature measuring instrument 1200 measures the temperature of the semiconductor device 100 by calculating the ratio of a second digital code (DC2) to a predetermined threshold value, and converts the calculated ratio into temperature with reference to a pre-established lookup table.

[0138] Figure 13 A schematic timing diagram illustrating exemplary signals associated with a semiconductor device 100 according to various embodiments of this disclosure. For example... Figure 13 As explained, the signals associated with the semiconductor device 100 include a RESET signal, a CHOP signal, a DC2 signal, and a Measured_Done signal. The RESET signal is generated by the first counter 160 to reset the digital code (DC1) of the first counter 160 and the digital code (DC2) of the second counter 170 to zero. The CHOP signal is generated by the first counter 160 to reverse the polarity of the current mismatch correction circuit 530 or the voltage offset correction circuit 540. The DC2 signal is the digital code (DC2) provided as the output of the second counter 170 to the external temperature measuring instrument 1200. After the temperature of the semiconductor device 100 is measured by the external temperature measuring instrument 1200, the first counter 160 receives the Measured_Done signal from the external temperature measuring instrument 1200.

[0139] like Figure 13 As explained, the second counter 170 outputs a digital code (DC2) indicated by a series of high and low signal levels of the DC2 signal. A Measured_Done signal with a high signal level is then received by the first counter 160. The first counter 160 then generates a RESET signal that transitions from a low signal level to a high signal level to reset the digital code (DC1) of the first counter 160 and the digital code (DC2) of the second counter 170 to zero. Thereafter, the first counter 160 generates a CHOP signal, such as a chopper signal (CHOP1 or CHOP2), with low / high signal levels having the polarity of the inverted current mismatch correction circuit 530 or the voltage offset correction circuit 540.

[0140] Figure 14 A flowchart illustrating an exemplary method 1400 for monitoring the temperature of a semiconductor device according to various embodiments of this disclosure is provided below. Further reference will now be made. Figure 1 , Figure 2 , Figure 3A , Figure 3B , Figure 5 , Figure 9 and Figure 10 To describe method 1400. It should be understood that method 1400 applies to all methods except... Figure 1 , Figure 2 , Figure 3A , Figure 3B , Figure 5 , Figure 9 and Figure 10 Structures other than the structure described below. Furthermore, it should be understood that additional operations may be provided before, during, and after method 1400, and in alternative embodiments of method 1400, some operations described below may be replaced or eliminated.

[0141] In operation 1410, the temperature-independent current generator 110 generates a mirror current (Ii). MIRROR1 ~I MIRROR3 ), and the reference voltage generator 130 generates a reference voltage (V REF ).

[0142] In operation 1420, the temperature-dependent current generator 120 is based on the mirror current (Ir). MIRROR2 I MIRROR3 ) generates temperature-dependent current (I) TD ).

[0143] In operation 1430, the first pulse signal generator 140 uses a reference voltage (V). REF ) for current (I MIRROR1 The second pulse signal generator 150 samples the signal to generate a pulse signal (PS1), and uses a reference voltage (V) to generate the pulse signal.REF ) for temperature-dependent current (I TD The sample is taken to generate a pulse signal (PS2).

[0144] In operation 1440, the first counter 160 counts / obtains the number of pulse signals (PS1) generated in operation 1430.

[0145] In operation 1450, the second counter 170 counts / obtains the number of pulse signals (PS2) generated in operation 1430.

[0146] In operation 1460, the first counter 160 outputs a digital code (DC1) representing the number of pulse signals (PS1) thus obtained, and the second counter 170 outputs a digital code (DC2) representing the number of pulse signals (PS2) thus obtained.

[0147] In operation 1470, the first counter 160 determines whether the number of pulse signals (PS1) obtained therefrom is equal to a predetermined threshold. If the number of pulse signals (PS1) is not equal to the predetermined threshold, that is, the first counter 160 determines that the number of pulse signals (PS1) obtained therefrom is less than the predetermined threshold, the process returns to operation 1430. Otherwise, that is, the first counter 160 determines that the number of pulse signals (PS1) obtained therefrom is equal to the predetermined threshold, the process proceeds to operation 1480.

[0148] In operation 1480, the first counter 160 generates a reset signal (RESET) to reset the number of pulse signals (PS1) obtained therefrom and the number of pulse signals (PS2) obtained by the second counter 160 to zero.

[0149] In operation 1490, the first counter 160 generates chopping signals (CHOP1, CHOP2) to be received by the current mismatch correction circuit 530 and the voltage offset correction circuit 540, and is used to reverse the polarity of the current mismatch correction circuit 530 and the voltage offset correction circuit 540, respectively. Thereafter, operations 1430 to 1490 are repeated a predetermined number of times.

[0150] Figure 15A schematic block diagram illustrating another exemplary semiconductor device 1500 according to various embodiments of the present disclosure is provided. The semiconductor device 1500 of this embodiment differs from semiconductor device 100 in that a second counter 170, instead of a first counter 160, determines whether the number of pulse signals (PS2) obtained is less than or equal to a predetermined threshold. When the number of pulse signals (PS2) obtained is determined to be less than the predetermined threshold, the second pulse signal generator 150 is allowed to generate pulse signals, and when the number of pulse signals (PS2) obtained is determined to be equal to the predetermined threshold, the second pulse signal generator 150 is prohibited from generating pulse signals.

[0151] The second counter 170 of the semiconductor device 1500 further generates chopping signals (CHOP1, CHOP2) to be received by the current mismatch correction circuit 530 and the voltage offset correction circuit 540, and is used to reverse the polarity of the current mismatch correction circuit 530 and the voltage offset correction circuit 540, respectively. The second counter 170 of the semiconductor device 1500 further generates a reset signal (RESET) to reset the number of pulse signals (PS2) obtained therefrom and the number of pulse signals (PS1) obtained by the first counter 160 to zero.

[0152] Figure 16 A flowchart illustrating an exemplary method 1600 for monitoring the temperature of a semiconductor device according to various embodiments of this disclosure is provided below. Further reference will now be made. Figure 2 , Figure 3A , Figure 3B , Figure 5 and Figure 15 To describe method 1600. It should be understood that method 1600 applies to all methods except... Figure 2 , Figure 3A , Figure 3B , Figure 5 and Figure 15 Structures other than the structure described below. Furthermore, it should be understood that additional operations may be provided before, during, and after method 1600, and in alternative embodiments of method 1600, some operations described below may be replaced or eliminated.

[0153] In operation 1610, the temperature-independent current generator 110 generates a mirror current (Ii). MIRROR1 ~I MIRROR3 ), and the reference voltage generator 130 generates a reference voltage (V REF ).

[0154] In operation 1620, the temperature-dependent current generator 120 is based on the mirror current (Ir). MIRROR2 I MIRROR3 ) generates temperature-dependent current (I) TD ).

[0155] In operation 1630, the first pulse signal generator 140 uses a reference voltage (V). REF ) for current (I MIRROR1 The second pulse signal generator 150 samples the signal to generate a pulse signal (PS1), and uses a reference voltage (V) to generate the pulse signal. REF ) for temperature-dependent current (I TD The sample is taken to generate a pulse signal (PS2).

[0156] In operation 1640, the first counter 160 counts / obtains the number of pulse signals (PS1) generated in operation 1630.

[0157] In operation 1650, the second counter 170 counts / obtains the number of pulse signals (PS2) generated in operation 1630.

[0158] In operation 1660, the first counter 160 outputs a digital code (DC1) indicating the number of pulse signals (PS1) thus obtained, and the second counter 170 outputs a digital code (DC2) indicating the number of pulse signals (PS2) thus obtained.

[0159] In operation 1670, the second counter 170 determines whether the number of pulse signals (PS2) obtained therefrom is equal to a predetermined threshold. If the number of pulse signals (PS2) is not equal to the predetermined threshold, that is, if the second counter 170 determines that the number of pulse signals (PS2) obtained therefrom is less than the predetermined threshold, the process returns to operation 1630. Otherwise, that is, if the second counter 170 determines that the number of pulse signals (PS2) obtained therefrom is equal to the predetermined threshold, the process proceeds to operation 1680.

[0160] In operation 1680, the second counter 170 generates a reset signal (RESET) to reset the number of pulse signals (PS1) obtained by the first counter 160 and the number of pulse signals (PS2) obtained therefrom to zero.

[0161] In operation 1690, the second counter 170 generates chopping signals (CHOP1, CHOP2) to be received by the current mismatch correction circuit 530 and the voltage offset correction circuit 540, and is used to reverse the polarity of the current mismatch correction circuit 530 and the voltage offset correction circuit 540, respectively. Thereafter, operations 1630 to 1690 are repeated a predetermined number of times.

[0162] In one embodiment, a semiconductor device includes a temperature-independent current generator, a pulse signal generator, and a counter. The temperature-independent current generator generates a reference current that is substantially independent of temperature and a mirror current that is a substantially replica of the reference current. The pulse signal generator is coupled to the temperature-independent current generator and samples the mirror current to generate a pulse signal. The counter is coupled to the pulse signal generator and obtains the number of pulse signals generated by the pulse signal generator. When it is determined that the number of pulse signals obtained is less than a predetermined threshold, the pulse signal generator is allowed to generate pulse signals; when it is determined that the number of pulse signals obtained is equal to the predetermined threshold, the pulse signal generator is prohibited from generating pulse signals.

[0163] In some embodiments, the first pulse signal generator includes a first switch, a second switch, a capacitor, and a comparator. The first switch is coupled between a temperature-independent current generator and a node. The second switch is coupled to the node. The capacitor is coupled in parallel to the second switch. The comparator has a first comparator input coupled to the node, a second comparator input for receiving a reference voltage, and a comparator output coupled to a first counter.

[0164] In some embodiments, the temperature-independent current generator is further configured to generate a current proportional to the absolute temperature and a current complementary to the absolute temperature, and to combine the current proportional to the absolute temperature and the current complementary to the absolute temperature to generate a reference current.

[0165] In some embodiments, the temperature-independent current generator is further configured to generate a second mirror current and a third mirror current, which are replicas of the reference current. The semiconductor device further includes a temperature-dependent current generator, a second pulse signal generator, and a second counter. The temperature-dependent current generator is configured to generate a temperature-dependent current based on the first mirror current and the second mirror current. The second pulse signal generator is coupled to the temperature-dependent current generator and is configured to sample the temperature-dependent current to generate a pulse signal. The second counter is coupled to the second pulse signal generator and is configured to count a second number of pulse signals generated by the second pulse signal generator.

[0166] In some embodiments, the second pulse signal generator includes a first switch, a second switch, a capacitor, and a comparator. The first switch is coupled between the temperature-dependent current generator and the node. The second switch is coupled to the node. The capacitor is coupled in parallel to the second switch. The comparator has a first comparator input coupled to the node, a second comparator input for receiving a reference voltage, and a comparator output coupled to a second counter.

[0167] In some embodiments, the temperature-independent current generator is further configured to generate a second mirror current and a third mirror current that are substantially replicas of the reference current, and the temperature-dependent current generator is further configured to: generate one of an absolute temperature proportional voltage and an absolute temperature complementary voltage based on the second mirror current; convert one of the absolute temperature proportional voltage and the absolute temperature complementary voltage into one of an absolute temperature proportional current and an absolute temperature complementary current; and subtract one of the absolute temperature proportional current and the absolute temperature complementary current from the third mirror current to extract the temperature-dependent current.

[0168] In some embodiments, the temperature-dependent current generator further includes a current mismatch correction circuit for reducing current mismatch, and a first counter is further used to generate a chopping signal to be received by the current mismatch correction circuit and to periodically reverse the polarity of the current mismatch correction circuit.

[0169] In some embodiments, the temperature-dependent current generator further includes a voltage offset correction circuit for reducing voltage offset, and a first counter is further used to generate a chopping signal for the voltage offset correction circuit to receive and for periodically reversing the polarity of the voltage offset correction circuit.

[0170] In some embodiments, the temperature-dependent current generator includes an operational amplifier, a first element, and a second element. The operational amplifier is coupled between a first node and a second node. The first element is coupled to the first node. The second element is coupled to the second node. Both the first and second elements have negative temperature coefficients.

[0171] In some embodiments, the temperature-dependent current generator includes an operational amplifier, a first element, and a second element. The operational amplifier is coupled between a first node and a second node. The first element is coupled to the first node. The second element is coupled to the second node. Both the first and second elements have positive temperature coefficients.

[0172] In another embodiment, a semiconductor device includes a temperature-dependent current generator, a pulse signal generator, and a counter. The temperature-dependent current generator generates a temperature-dependent current. The pulse signal generator is coupled to the temperature-dependent current generator and samples the temperature-dependent current to generate a pulse signal. The counter is coupled to the pulse signal generator and obtains the number of pulse signals generated by the pulse signal generator. When it is determined that the number of pulse signals obtained is less than a predetermined threshold, the pulse signal generator is allowed to generate pulse signals; when it is determined that the number of pulse signals obtained is equal to the predetermined threshold, the pulse signal generator is prohibited from generating pulse signals.

[0173] In some embodiments, the second pulse signal generator includes a first switch, a second switch, a capacitor, and a comparator. The first switch is coupled between the temperature-dependent current generator and the node. The second switch is coupled to the node. The capacitor is coupled in parallel to the second switch. The comparator has a first comparator input coupled to the node, a second comparator input for receiving a reference voltage, and a comparator output coupled to a second counter.

[0174] In some embodiments, the temperature-dependent current generator further includes a current mismatch correction circuit. The current mismatch correction circuit is used to reduce current mismatch, and the second counter is further used to generate a chopping signal to be received by the current mismatch correction circuit and to periodically reverse the polarity of the current mismatch correction circuit.

[0175] In some embodiments, the temperature-dependent current generator further includes a voltage offset correction circuit. The voltage offset correction circuit is used to reduce voltage offset, and the second counter is further used to generate a chopping signal for the voltage offset correction circuit to receive and for periodically reversing the polarity of the voltage offset correction circuit.

[0176] In some embodiments, the temperature-dependent current generator includes an operational amplifier, a first element, and a second element. The operational amplifier is coupled between a first node and a second node. The first element is coupled to the first node. The second element is coupled to the second node. Both the first and second elements have negative temperature coefficients.

[0177] In some embodiments, the temperature-dependent current generator includes an operational amplifier, a first element, and a second element. The operational amplifier is coupled between a first node and a second node. The first element is coupled to the first node. The second element is coupled to the second node. Both the first and second elements have positive temperature coefficients.

[0178] In another embodiment, a method for monitoring the temperature of a semiconductor device includes the steps of: generating a reference current that is substantially independent of temperature; replicating the reference current to generate first, second, and third mirror currents; sampling the first mirror current to generate a first pulse signal; counting the number of the first pulse signals to generate a first digital code; generating a temperature-dependent current based on the second and third mirror currents; sampling the temperature-dependent current to generate a second pulse signal; and counting the number of the second pulse signals to generate a second digital code, thereby using the first and second digital codes to monitor the temperature of the semiconductor device.

[0179] In some embodiments, the method further includes the steps of: generating a current proportional to the absolute temperature and a current complementary to the absolute temperature; and combining the current proportional to the absolute temperature and the current complementary to the absolute temperature to generate a reference current.

[0180] In some embodiments, the method further includes the steps of: generating an absolute temperature complementary voltage based on a second mirror current; converting the absolute temperature complementary voltage into an absolute temperature complementary current; and subtracting the absolute temperature complementary current from a third mirror current to extract a temperature-dependent current.

[0181] In some embodiments, the method further includes the steps of: generating an absolute temperature proportional voltage based on a second mirror current; converting the absolute temperature proportional voltage into an absolute temperature proportional current; and subtracting the absolute temperature proportional current from a third mirror current to extract a temperature-dependent current.

[0182] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art should understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to these equivalent constructions without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, Include: A temperature-independent current generator for generating a reference current independent of temperature and a first mirror current, a second mirror current and a third mirror current that are multiple replicas of the reference current; A first pulse signal generator is coupled to the temperature-independent current generator and used to sample the first mirror current to generate a pulse signal; A first counter is coupled to the first pulse signal generator and used to obtain a first number of pulse signals generated by the first pulse signal generator. When it is determined that the first number of pulse signals obtained therefrom is less than a predetermined threshold value, the first pulse signal generator is allowed to generate the pulse signal, and when it is determined that the first number of pulse signals obtained therefrom is equal to the predetermined threshold value, the first pulse signal generator is prohibited from generating the pulse signal. and A temperature-dependent current generator is used to receive the second mirror current and the third mirror current generated by the temperature-independent current generator, and to generate a temperature-dependent current based on the second mirror current and the third mirror current.

2. The semiconductor device as claimed in claim 1, characterized in that, The first pulse signal generator includes: A first switch is coupled between the temperature-independent current generator and a node; A second switch is coupled to this node; A capacitor is connected in parallel to the second switch; and A comparator has a first comparator input coupled to the node, a second comparator input for receiving a reference voltage, and a comparator output coupled to the first counter.

3. The semiconductor device as claimed in claim 1, characterized in that, The temperature-independent current generator is further used for: Generates a current proportional to the absolute temperature and a current complementary to the absolute temperature; and The reference current is generated by combining the current proportional to the absolute temperature and the current complementary to the absolute temperature.

4. The semiconductor device as claimed in claim 1, characterized in that, Further includes: A second pulse signal generator is coupled to the temperature-dependent current generator and used to sample the temperature-dependent current to generate a pulse signal; and A second counter is coupled to the second pulse signal generator and is used to count a second quantity of pulse signals generated by the second pulse signal generator.

5. The semiconductor device as claimed in claim 4, characterized in that, The second pulse signal generator includes: A first switch is coupled between the temperature-dependent current generator and a node; A second switch is coupled to this node; A capacitor is connected in parallel to the second switch; and A comparator has a first comparator input coupled to the node, a second comparator input for receiving a reference voltage, and a comparator output coupled to the second counter.

6. The semiconductor device as claimed in claim 1, characterized in that, The temperature-dependent current generator is further used for: Based on the second mirror current, one of a voltage proportional to the absolute temperature and a voltage complementary to the absolute temperature is generated. Convert one of the absolute temperature proportional voltage and the absolute temperature complementary voltage into one of the absolute temperature proportional current and the absolute temperature complementary current; and The temperature-dependent current is extracted by subtracting one of the current proportional to absolute temperature and the current complementary to absolute temperature from the third mirror current.

7. The semiconductor device as claimed in claim 1, characterized in that, The temperature-dependent current generator further includes a current mismatch correction circuit for reducing a current mismatch, and the first counter is further used to generate a chopping signal for the current mismatch correction circuit to receive and for periodically reversing one polarity of the current mismatch correction circuit.

8. The semiconductor device as claimed in claim 1, characterized in that, The temperature-dependent current generator further includes a voltage offset correction circuit for reducing a voltage offset, and the first counter is further used to generate a chopping signal for the voltage offset correction circuit to receive and for periodically reversing one polarity of the voltage offset correction circuit.

9. The semiconductor device as claimed in claim 1, characterized in that, The temperature-dependent current generator includes: An operational amplifier is coupled between a first node and a second node; A first component, coupled to the first node; and A second component is coupled to the second node, wherein the first component and the second component have a negative temperature coefficient.

10. The semiconductor device as claimed in claim 1, characterized in that, The temperature-dependent current generator includes: An operational amplifier is coupled between a first node and a second node; A first component, coupled to the first node; and A second component is coupled to the second node, wherein the first component and the second component have a positive temperature coefficient.

11. A semiconductor device, characterized in that, Include: A temperature-independent current generator for generating a first current and a second current that are independent of temperature; A temperature-dependent current generator is used to receive the first current and the second current generated by the temperature-independent current generator, and to generate a temperature-dependent current based on the first current and the second current. A second pulse signal generator is coupled to the temperature-dependent current generator and used to sample the temperature-dependent current to generate a pulse signal; and A second counter is coupled to the second pulse signal generator and used to obtain a number of pulse signals generated by the second pulse signal generator. When it is determined that the number of pulse signals obtained is less than a predetermined threshold, the second pulse signal generator is allowed to generate the pulse signal, and when it is determined that the number of pulse signals obtained is equal to the predetermined threshold, the second pulse signal generator is prohibited from generating the pulse signal.

12. The semiconductor device as claimed in claim 11, characterized in that, The second pulse signal generator includes: A first switch is coupled between the temperature-dependent current generator and a node; A second switch is coupled to this node; A capacitor is connected in parallel to the second switch; and A comparator has a first comparator input coupled to the node, a second comparator input for receiving a reference voltage, and a comparator output coupled to the second counter.

13. The semiconductor device as claimed in claim 11, characterized in that, The temperature-dependent current generator further includes a current mismatch correction circuit for reducing a current mismatch, and the second counter is further used to generate a chopping signal for the current mismatch correction circuit to receive and for periodically reversing one polarity of the current mismatch correction circuit.

14. The semiconductor device as claimed in claim 11, characterized in that, The temperature-dependent current generator further includes a voltage offset correction circuit for reducing a voltage offset, and the second counter is further used to generate a chopping signal for the voltage offset correction circuit to receive and for periodically reversing one polarity of the voltage offset correction circuit.

15. The semiconductor device as claimed in claim 11, characterized in that, The temperature-dependent current generator includes: An operational amplifier is coupled between a first node and a second node; A first component, coupled to the first node; and A second component is coupled to the second node, wherein the first component and the second component have a negative temperature coefficient.

16. The semiconductor device as claimed in claim 11, characterized in that, The temperature-dependent current generator includes: An operational amplifier is coupled between a first node and a second node; A first component, coupled to the first node; and A second component is coupled to the second node, wherein the first component and the second component have a positive temperature coefficient.

17. A method for monitoring a temperature of a semiconductor device, characterized in that, Includes the following steps: A temperature-independent reference current is generated by a temperature-independent current generator; The reference current is replicated by a temperature-independent current generator to generate a first mirror current, a second mirror current and a third mirror current. The first mirror current is sampled to generate multiple first pulse signals; Count a first quantity of the plurality of first pulse signals to generate a first digital code; The second and third mirror currents are received by a temperature-dependent current generator. The temperature-dependent current generator generates a temperature-dependent current based on the second mirror current and the third mirror current; The temperature-dependent current is sampled to generate multiple second pulse signals; and A second quantity of the plurality of second pulse signals is counted to generate a second digital code, thereby using the first digital code and the second digital code to monitor a temperature of the semiconductor device.

18. The method as described in claim 17, characterized in that, Further steps include: Generates a current proportional to the absolute temperature and a current complementary to the absolute temperature; and The reference current is generated by combining the current proportional to the absolute temperature and the current complementary to the absolute temperature.

19. The method as described in claim 17, characterized in that, Further steps include: Based on this second mirror current, a voltage complementary to the absolute temperature is generated; Convert the absolute temperature complementary voltage into an absolute temperature complementary current; and The temperature-related current is extracted by subtracting the absolute temperature complementary current from the third mirror current.

20. The method as described in claim 17, characterized in that, Further steps include: Based on this second mirror current, a voltage proportional to the absolute temperature is generated; Convert the absolute temperature proportional voltage into the absolute temperature proportional current; and The temperature-dependent current is extracted by subtracting the current proportional to the absolute temperature from the third mirror current.

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