Clock buffers, clock signal processing methods and electronic devices

Abstract

This invention provides a clock buffer, a clock signal processing method, and an electronic device, relating to the field of electronic device technology. The clock buffer includes a common-mode adjustment module and an amplitude amplification module. The common-mode adjustment module receives the original differential clock signal output from a third-party clock generation circuit, adjusts the original differential clock signal, and outputs an intermediate differential clock signal whose common-mode voltage matches the input common-mode voltage of the amplitude amplification module. The amplitude amplification module receives the intermediate differential clock signal, amplifies it, and outputs a target differential clock signal with an amplitude higher than the original differential clock signal. By adjusting the common-mode voltage of the clock signal to match the input common-mode voltage range of the amplitude amplification module through the common-mode adjustment module, the amplitude amplification module can accurately amplify the clock signal to obtain a target differential clock signal with an accurate duty cycle, thereby solving the duty cycle distortion problem during clock signal amplification.

Description

Technical Field

[0001] This invention relates to the field of electronic technology, and in particular to a clock buffer, a clock signal processing method, and an electronic device. Background Technology

[0002] Clock signals are the foundation of sequential logic in integrated circuits. With increasing data transmission speeds, not only are higher clock speeds required, but also accurate duty cycles. Typically, clock generation circuits generate two clock signals with opposite phases, forming a differential clock signal to provide the clock signal for the integrated circuit.

[0003] In prior art, to improve the driving capability of differential clock signals, a clock buffer is placed at the output of the clock generation circuit. The clock buffer adjusts the amplitude of the differential clock signal output by the clock generation circuit to enhance its driving capability. However, the higher the frequency of the differential clock signal output by the clock generation circuit, the smaller its amplitude. In this case, when a small-amplitude, high-speed signal is converted by the clock buffer, it can cause distortion of the clock signal's duty cycle. Summary of the Invention

[0004] In view of the above problems, embodiments of the present invention are proposed to provide a clock buffer, clock signal processing method and electronic device that overcomes or at least partially solves the above problems, so as to resolve the problem of clock signal duty cycle distortion.

[0005] To address the aforementioned problems, this invention discloses a clock buffer, comprising: a common-mode adjustment module and an amplitude amplification module;

[0006] The common-mode adjustment module is used to receive the original differential clock signal output by the third-party clock generation circuit, and after adjusting the original differential clock signal, output an intermediate differential clock signal; the common-mode voltage of the intermediate differential clock signal is matched with the input common-mode voltage of the amplitude amplification module.

[0007] The amplitude amplification module is connected to the common-mode adjustment module and is used to receive the intermediate differential clock signal, amplify the intermediate differential clock signal, and output the target differential clock signal; the amplitude of the target differential clock signal is higher than the amplitude of the original differential clock signal.

[0008] Optionally, the amplitude amplification module includes two identical amplitude amplification branches and a synchronization unit;

[0009] The amplitude amplification branch includes an amplification switch and an auxiliary switch; the output terminal of the auxiliary switch is connected to the input terminal of the amplification switch.

[0010] The synchronization unit is connected to the amplifying switch and the auxiliary switch respectively; the synchronization unit and the amplifying switch are used to simultaneously receive the intermediate differential clock signal and control the switching states of the amplifying switch and the auxiliary switch in the same amplitude amplification branch to be opposite; the switching state includes a conducting state and an off state.

[0011] Optionally, the synchronization unit includes two identical synchronization branches, and each synchronization branch and one amplitude amplification branch form a voltage amplification circuit;

[0012] The synchronization branch includes a synchronization switch and a feedback switch, and the output terminal and control terminal of the feedback switch are connected to the input terminal of the synchronization switch.

[0013] In one set of voltage amplifier circuits, the control terminal of the auxiliary switch is connected to the control terminal of the feedback switch in another set of voltage amplifier circuits; the control terminals of the amplifying switch and the synchronous switch receive the intermediate differential clock signal to control the amplifying switch in the voltage amplifier circuit and the auxiliary switch in the other set of voltage amplifier circuits to be synchronously turned on or off.

[0014] Optionally, the common-mode adjustment module includes two identical common-mode adjustment branches that are symmetrically arranged.

[0015] The common-mode regulation branch includes a branch switch and a branch load connected in series;

[0016] The branch switching transistors are respectively used to receive the original differential clock signal and control the current waveform in the common-mode regulation branch, so that the circuit waveform is consistent with the base frequency waveform of the received original differential clock signal, so as to output the intermediate differential clock signal in the corresponding common-mode regulation branch.

[0017] Optionally, the common-mode regulation module further includes a current source connected to the common-mode regulation branch to provide the first power supply voltage to the common-mode regulation branch.

[0018] Optionally, the clock buffer further includes a first inverter group and a second inverter group;

[0019] Both the first inverter group and the second inverter group include a target number of corrective inverters connected in series; the target number is not less than 1.

[0020] The input terminal of the first inverter group is connected to the amplitude amplification module, and is used to receive the first terminal clock signal in the target differential clock signal and output the first terminal clock signal after the duty cycle is corrected.

[0021] The input terminal of the second inverter group is connected to the amplitude amplification module to receive the second terminal clock signal in the target differential clock signal and output the second terminal clock signal after correcting the duty cycle.

[0022] Optionally, the target number is 2; the clock buffer further includes a first cross inverter and a second cross inverter for correcting the intersection of the first terminal clock signal after the duty cycle correction and the second terminal clock signal after the duty cycle correction;

[0023] The input terminal of the first cross inverter is connected between two correction inverters in the first inverter group, and the output terminal is connected between two correction inverters in the second inverter group;

[0024] The input of the second cross inverter is connected between two correction inverters in the second inverter group, and the output is connected between two correction inverters in the first inverter group.

[0025] This invention also discloses a clock signal processing method applied to the clock buffer described above, the method comprising:

[0026] It receives the original differential clock signal and outputs an intermediate differential clock signal; the common-mode voltage of the intermediate differential clock signal is matched with the input common-mode voltage of the amplitude amplification module.

[0027] Based on the intermediate differential clock signal, the amplitude amplification module outputs a target differential clock signal; the amplitude of the target differential clock signal is higher than the amplitude of the original differential clock signal.

[0028] Optionally, the method may further include:

[0029] The clock signal at each end of the target differential clock signal is inverted for a target number of times to correct the duty cycle of the target differential clock signal; the target number of times is not less than 1.

[0030] This invention also discloses an electronic device including a clock buffer as described above.

[0031] The embodiments of the present invention have the following advantages:

[0032] In this embodiment of the invention, the clock buffer includes a common-mode adjustment module and an amplitude amplification module. The common-mode adjustment module receives the original differential clock signal output by the clock generation circuit and outputs an intermediate differential clock signal whose common-mode voltage matches the input common-mode voltage of the amplitude amplification module. The amplitude amplification module is connected to the common-mode adjustment module and receives the intermediate differential clock signal, outputting a target differential clock signal with an amplitude higher than the original differential clock signal. When the differential clock signal output by the third-party clock generation circuit has a high rate, resulting in a small amplitude of the original differential clock signal and a waveform approximately sine wave, the common-mode adjustment module adjusts the common-mode voltage of the clock signal to match the input common-mode voltage range of the amplitude amplification module. When the common-mode voltage of the intermediate differential clock signal output by the common-mode adjustment module matches the input common-mode voltage of the amplitude amplification module, the amplitude amplification module can accurately amplify the clock signal to obtain a target clock signal with an accurate duty cycle, thereby solving the duty cycle distortion problem in the clock signal amplification process. Attached Figure Description

[0033] Figure 1 A schematic diagram of the structure of a clock buffer according to an embodiment of the present invention is shown;

[0034] Figure 2a A circuit schematic diagram of a common-mode adjustment module according to an embodiment of the present invention is shown;

[0035] Figure 2b A circuit schematic diagram of a common-mode adjustment module according to an embodiment of the present invention is shown;

[0036] Figure 3 A timing diagram of a clock buffer according to an embodiment of the present invention is shown;

[0037] Figure 4a A circuit diagram of an amplitude amplification module according to an embodiment of the present invention is shown;

[0038] Figure 4b A circuit diagram of an amplitude amplification module according to an embodiment of the present invention is shown;

[0039] Figure 5a A circuit schematic diagram of another common-mode adjustment module in an embodiment of the present invention is shown;

[0040] Figure 5b A circuit schematic diagram of another common-mode adjustment module in an embodiment of the present invention is shown;

[0041] Figure 6 A circuit diagram of an inverter group according to an embodiment of the present invention is shown;

[0042] Figure 7A flowchart illustrating the steps of a clock signal processing method according to an embodiment of the present invention is shown;

[0043] Figure 8 A structural block diagram of an electronic device according to an embodiment of the present invention is shown. Detailed Implementation

[0044] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0045] Reference Figure 1 The diagram shows a schematic of a clock buffer in an embodiment of the present invention. The clock buffer includes a common-mode adjustment module 101 and an amplitude amplification module 102.

[0046] The common-mode adjustment module 101 receives the original differential clock signal output by the third-party clock generation circuit, adjusts the original differential clock signal, and outputs an intermediate differential clock signal. The common-mode voltage of the intermediate differential clock signal is matched with the input common-mode voltage of the amplitude amplification module 102. The amplitude amplification module 102 is connected to the common-mode adjustment module 101, receives the intermediate differential clock signal, amplifies the intermediate differential clock signal, and outputs a target differential clock signal. The amplitude of the target differential clock signal is higher than the amplitude of the original differential clock signal.

[0047] In this embodiment, the differential clock signal includes two clock signals with the same amplitude but opposite phases. The third-party clock generation circuit can be an oscillator and a phase-locked loop (PLL), or other circuit modules used to generate the differential clock signal. The common-mode adjustment module includes a set of differential input terminals and a set of differential output terminals. The first input terminal receives one clock signal from the original differential clock signal, and the second input terminal receives the other clock signal from the original differential clock signal. The common-mode adjustment module adjusts the common-mode voltage of the original differential clock signal to obtain and output an intermediate differential clock signal from the differential output terminal. Similarly, the amplitude amplification module includes a set of differential input terminals and a set of differential output terminals. The first input terminal receives one clock signal from the intermediate differential clock signal, and the second input terminal receives the other clock signal from the intermediate differential clock signal. The amplitude amplification module amplifies the amplitude of the intermediate differential clock signal to obtain and output a target differential clock signal with an amplitude higher than the original differential clock signal from the differential output terminal.

[0048] Optionally, the common-mode regulation module includes two symmetrically arranged and identical common-mode regulation branches. Each common-mode regulation branch includes a branch switch and a branch load connected in series, and the connection point between the branch switch and the branch load constitutes a second output node. One end of each common-mode regulation branch is connected to a first supply voltage, and the other end is grounded. The branch switches in the two common-mode regulation branches are respectively used to receive the clock signal from one end of the original differential clock signal, and respectively control the current waveform in the common-mode regulation branch to be consistent with the fundamental frequency waveform of the received clock signal, so as to output the clock signal from one end of the intermediate differential clock signal at the second output node of the respective common-mode regulation branch.

[0049] For example, such as Figure 2a As shown, Figure 2a The diagram illustrates a common-mode regulation module according to an embodiment of the present invention. The common-mode regulation module includes a first common-mode regulation branch 201 and a second common-mode regulation branch 202. In the first common-mode regulation branch 201, the first branch switch 2011 can be a P-type metal-oxide-semiconductor field-effect transistor (PMOS), and the first branch load 2012 can be an N-type metal-oxide-semiconductor field-effect transistor (NMOS). Similarly, in the second common-mode regulation branch 202, the second branch switch 2021 can be a PMOS transistor, and the second branch load 2022 can be an NMOS transistor. The input terminal of the PMOS transistor is its source, i.e., its current input terminal; the output terminal of the PMOS transistor is its drain, i.e., its current output terminal. The input terminal of an NMOS transistor is its drain, which is also its current input terminal; the output terminal is its source, which is its current output terminal. The control terminal for both PMOS and NMOS transistors is their gate.

[0050] Combination Figure 2a As shown, the source of the first branch switch 2011 and the source of the second branch switch 2021 are both connected to a first supply voltage, which is in the range of... Figure 2a The symbol "VDD" is used to represent this. The drain of the first branch switch 2011 is connected to the drain of the first branch load 2012, and the source of the first branch load 2012 is grounded. Figure 2aThe symbol "VSS" is used to represent this. Similarly, the drain of the second branch switch 2021 is connected to the drain of the second branch load 2022, and the source of the second branch load 2022 is grounded. The gate of the first branch load 2012 is connected to the drain, forming the load of the first common-mode regulation branch 201. Similarly, the gate of the second branch load 2022 is connected to the drain, forming the load of the second common-mode regulation branch 202. The first branch switch 2011 and the second branch switch 2021 are PMOS transistors of the same specification, and the first branch load 2012 and the second branch load 2022 are NMOS transistors of the same specification. The first common-mode regulation branch and the second common-mode regulation branch have the same structure, and the same specification switches are set at corresponding positions, so that the first common-mode regulation branch and the second common-mode regulation branch form two symmetrical and identical branches.

[0051] In some possible implementations, such as Figure 2b As shown, the common-mode regulation module also includes a first common-mode regulation branch 201 and a second common-mode regulation branch 202. The first common-mode regulation branch 201 also includes a first branch switch 2111 and a first branch load 2112 connected in series; the first common-mode regulation branch 202 also includes a first branch switch 2121 and a first branch load 2122 connected in series. The difference is that the first branch switch 2111 is an NMOS transistor and the first branch load 2112 is a PMOS transistor; the second branch switch 2121 is an NMOS transistor and the second branch load 2122 is a PMOS transistor.

[0052] In this circuit, the source of the first branch switch transistor 2111 and the source of the second branch switch transistor 2121 are both grounded. Figure 2a The same symbol "VSS" is used to represent ground; the drain of the first branch switch 2111 is connected to the drain of the first branch load 2112, and the source of the first branch load 2112 is connected to the first supply voltage, and Figure 2a The first supply voltage is represented by the symbol "VDD". The gate of the first branch load 2112 is connected to the drain, forming the load of the first common-mode regulation branch 201. Similarly, the drain of the second branch switch 2121 is connected to the drain of the second branch load 2122, and the source of the second branch load 2122 is connected to the first supply voltage VDD. The gate of the second branch load 2122 is connected to the drain, forming the load of the second common-mode regulation branch 202. The first branch switch 2111 and the second branch switch 2121 are NMOS transistors of the same specification, and the first branch load 2112 and the second branch load 2122 are PMOS transistors of the same specification. Similarly, the first common-mode regulation branch and the second common-mode regulation branch have the same structure, and the same specification switches are set at corresponding positions, so that the first common-mode regulation branch and the second common-mode regulation branch form two symmetrical and identical branches.

[0053] It should be noted that the branch load can also be other types of load, and the branch switch can also be implemented using transistors or other switching transistors. The specific structure of the common-mode regulation branch can be set according to the type of branch load and branch switch, and this embodiment does not impose any restrictions on this.

[0054] For example, such as Figure 3 As shown, Figure 3 A timing diagram of a clock buffer according to an embodiment of the present invention is shown. Figure 3 The horizontal axis represents time, measured in microseconds (μs), and the vertical axis represents voltage, measured in volts (V). The original differential clock signal is a high-frequency, small-amplitude differential clock signal output by the clock generation circuit, including clock signal 301 and clock signal 302. Clock signals 301 and 302 have the same amplitude but opposite phase. Since clock signals 301 and 302 are directly output by a third-party clock generation circuit, their duty cycle is close to or equal to 50%, making the duty cycle relatively accurate. However, due to the high frequency of clock signals 301 and 302, their waveforms are close to sine waves with small amplitudes: a high level of 0.35V, a low level of 0.15V, and a common-mode voltage of 0.25V. It should be noted that clock signals with a clock frequency higher than 1 gigahertz (GHz) can be classified as high-frequency clock signals, or other classification standards can be used to classify clock signals into high-frequency clock signals and low-frequency clock signals. The specific classification standard for clock signals can be set according to requirements, and this embodiment does not impose any restrictions on it.

[0055] In prior art, when the clock signal output by the clock generation circuit has a high frequency, the waveform of the clock signal is close to a sine wave, but the amplitude becomes smaller, making it unable to effectively drive the circuit module connected to the third-party clock generation circuit. In this case, a clock buffer needs to be set at the output of the third-party clock generation circuit to amplify the clock signal and improve its driving capability. However, the clock buffer in the prior art, after amplifying the clock signal, causes distortion in the clock signal's duty cycle, specifically, the duty cycle deviates from 50%.

[0056] In this embodiment, before amplifying the clock signal, the clock buffer can first adjust the common-mode voltage of the differential clock signal through the common-mode adjustment module, so that the common-mode voltage of the differential clock signal matches the input common-mode voltage of the amplitude amplification module. Combined with... Figure 2a , Figure 2b and Figure 3As shown, the control terminals of the first branch switch 2011 or 2111 and the second branch switch 2021 or 2121 form a set of differential input terminals, which can be connected to the differential output terminal of a third-party clock generation circuit to receive the original differential clock signals output by the third-party clock generation circuit, namely clock signal 301 and clock signal 302. The specifications of the first branch switch 2011 or 2111 can be adjusted to match the amplitude of the clock signal 301, so that the first branch switch 2011 or 2111 operates under the control of the clock signal 301, and controls the current waveform in the first common-mode regulation branch 201 to be consistent with the fundamental frequency waveform of the clock signal 301.

[0057] Similarly, by adjusting the specifications of the second branch switch 2021 or 2121 to match the amplitude of the clock signal 302, the second branch switch 2021 or 2121 operates under the control of the clock signal 302, controlling the current waveform in the second common-mode regulation branch 202 to be consistent with the fundamental frequency waveform of the clock signal 302. Simultaneously, the connection point between the first branch switch 2011 and the first branch load 2012 (or the connection point between the first branch switch 2111 and the first branch load 2112) forms a second output node, and the connection point between the second branch switch 2021 and the second branch load 2022 (or the connection point between the second branch switch 2121 and the second branch load 2122) forms another second output node. When the first and second branch switches operate under the control of the original differential clock signal, clock signals 303 and 304, i.e., intermediate differential clock signals, can be output from the two second output nodes respectively. Since the current waveform in the first common-mode regulation branch 201 is consistent with the fundamental frequency waveform of clock signal 301, the waveform of clock signal 303 is consistent with the fundamental frequency waveform of clock signal 301. Similarly, the waveform of clock signal 304 is consistent with the fundamental frequency waveform of clock signal 302. Figure 3 As shown, in the intermediate differential clock signal composed of clock signal 303 and clock signal 304, the high point voltage of clock signal 303 and clock signal 304 is 0.6V, the low point voltage is 0.4V, and the common mode voltage is 0.5V.

[0058] In practical applications, the specifications of the first branch switch 2011 and the second branch switch 2021 (or the first branch switch 2111 and the second branch switch 2121), as well as the specifications of the first branch load 2012 and the second branch load 2022 (or the first branch load 2112 and the second branch load 2122), can be set according to the input common-mode voltage range of the amplitude amplification module, so that the common-mode voltage of the clock signal 303 and the clock signal 304 is within the input common-mode voltage range of the amplitude amplification module, that is, the common-mode voltage of the intermediate differential clock signal is matched with the input common-mode voltage of the amplitude amplification module.

[0059] In this embodiment, the common-mode adjustment module consists of two symmetrically arranged and identical common-mode adjustment branches. Each common-mode adjustment branch includes a branch switch and a branch load connected in series, resulting in a simple circuit structure that simplifies the clock buffer's circuit structure. Simultaneously, the common-mode adjustment branch can control the waveform of the intermediate differential clock signal to match the base frequency waveform of the original differential clock signal. When the original differential clock signal exhibits duty cycle distortion, controlling the waveform of the intermediate differential clock signal to match the base frequency waveform of the original differential clock signal ensures that the duty cycle of the intermediate differential clock signal is consistent with the base frequency duty cycle of the original differential clock signal, thereby adjusting the duty cycle of the intermediate differential clock signal. Furthermore, when the duty cycle of the original differential clock signal is distorted, the base frequency waveform of the original differential clock signal remains unchanged. Therefore, controlling the waveform of the intermediate differential clock signal to match the base frequency waveform of the original differential clock signal avoids duty cycle distortion in the intermediate differential clock signal.

[0060] In one embodiment, the amplitude amplification module includes two identical amplitude amplification branches and a synchronization unit. Each amplitude amplification branch includes an amplifying switch and an auxiliary switch. The input of the auxiliary switch is connected to a second power supply voltage, and its output is connected to the input of the amplifying switch. The output of the amplifying switch is grounded. The connection point between the amplifying switch and the auxiliary switch forms a first output node. The synchronization unit is connected to both the amplifying switch and the auxiliary switch. The synchronization unit and the amplifying switch receive an intermediate differential clock signal and control the amplifying switch in one amplitude amplification branch to be turned on and the amplifying switch in the other amplitude amplification branch to be turned off. It also controls the auxiliary switch in one amplitude amplification branch to be turned on and the auxiliary switch in the other amplitude amplification branch to be turned off, so that a clock signal from one end of the target differential clock signal is output at the first output node in each amplitude amplification branch. The switching states of the amplifying switch and the auxiliary switch in the same amplitude amplification branch are opposite, including an on state and an off state.

[0061] For example, such as Figure 4a As shown, Figure 4a The diagram illustrates a circuit schematic of an amplitude amplification module according to an embodiment of the present invention. In this module, a first amplifying switch 401 and a first auxiliary switch 402 form a first amplitude amplification branch, and a second amplifying switch 403 and a second auxiliary switch 404 form a second amplitude amplification branch. The first amplifying switch 401 and the second amplifying switch 403 are NMOS transistors of the same specification, and the first auxiliary switch 402 and the second auxiliary switch 404 are PMOS transistors of the same specification. The input terminals of the first auxiliary switch 402 and the second auxiliary switch 404, i.e., the sources of the PMOS transistors, are connected to a second power supply voltage, providing power to the first and second amplitude amplification branches. Figure 4aThe symbol "VDD" indicates the second supply voltage. The output terminals of the first amplifying switch 401 and the second amplifying switch 403, i.e., the sources of the NMOS transistors, are grounded. Figure 4a The symbol "VSS" indicates ground. The drain of the first auxiliary switch 402 is connected to the drain of the first amplifying switch 401, and the drain of the second auxiliary switch 404 is connected to the drain of the second amplifying switch 403. The first amplitude amplification branch and the second amplitude amplification branch have the same structure and are equipped with switches of the same specifications at corresponding positions, so that the first amplitude amplification branch and the second amplitude amplification branch form two completely identical branches. Optionally, the synchronization unit includes two identical synchronization branches, each synchronization branch forming a voltage amplification circuit with one amplitude amplification branch; the synchronization branch includes a synchronization switch and a feedback switch, the input terminal of the feedback switch is connected to the second power supply voltage, the output terminal and the control terminal of the feedback switch are connected to the input terminal of the synchronization switch, and the output terminal of the synchronization switch is grounded. In one voltage amplifier circuit, the control terminal of the auxiliary switch is connected to the control terminal of the feedback switch in another voltage amplifier circuit. The control terminals of the amplification switch and the synchronization switch are connected to the clock signal at one end of the intermediate differential clock signal to control the amplification switch in the voltage amplifier circuit and the auxiliary switch in the other voltage amplifier circuit to be synchronously turned on or off.

[0062] For example, such as Figure 4a As shown, the first synchronous switch 405 and the first feedback switch 406 form the first synchronous branch, and the second synchronous switch 407 and the second feedback switch 408 form the second synchronous branch. The first synchronous switch 405 and the second synchronous switch 407 are NMOS transistors of the same specification, and the first feedback switch 406 and the second feedback switch 408 are PMOS transistors of the same specification. In the first synchronous branch, the source of the first feedback switch 406 is connected to the second supply voltage, and its gate is connected to its drain; the drain of the first synchronous switch 405 is connected to the drain of the first feedback switch 406, and its source is grounded. In the second synchronous branch, the source of the second feedback switch 408 is connected to the second supply voltage, and its gate is connected to its drain; the drain of the second synchronous switch 407 is connected to the drain of the second feedback switch 408, and its source is grounded. The first and second synchronous branches have the same structure and use switches of the same specification in the same position, making them two identical branches.

[0063] The first synchronization branch and the first amplitude amplification branch form the first group of voltage amplifier circuits, and the second synchronization branch and the second amplitude amplification branch form the second group of voltage amplifier circuits. In the first group of voltage amplifier circuits, the gates of the first amplification switch 401 and the first synchronization switch 405 are connected to receive the clock signal from one end of the intermediate differential clock signal, such as... Figure 3The clock signal 303 is shown. Under the action of the clock signal 303, the first amplifying switch 401 and the first synchronous switch 405 are synchronously turned on or off. Simultaneously, the gate of the first feedback switch 406 is connected to the gate of the second auxiliary switch 404 in the second voltage amplifier circuit. Since the gate of the first feedback switch 406 is connected to the drain, the gate of the first feedback switch 406 is at a low level when the first synchronous switch 405 is turned on, thus making the state of the first feedback switch 406 consistent with the switching state of the first synchronous switch 405, both being in the on state. Furthermore, since the gates of the first feedback switch 406 and the second auxiliary switch 404 are connected, and their switching states are consistent, the first feedback switch 406 can feed back the switching state of the first amplifying switch 401 to the second auxiliary switch 404, causing the second auxiliary switch 404 to be synchronously turned on or off with the first amplifying switch 401. Similarly, in the second voltage amplifier circuit, the gates of the second amplifying switch 403 and the second synchronous switch 407 are connected to receive the clock signal from the other end of the intermediate differential clock signal, such as... Figure 3 The clock signal 304 shown causes the second synchronous switch 407 and the second amplifying switch 403 to be turned on or off synchronously. The second feedback switch 408 can feed back the switching state of the second amplifying switch 403 to the first auxiliary switch 402 in the first amplifier circuit, so that the first auxiliary switch 402 and the second amplifying switch 403 are turned on or off synchronously.

[0064] Combination Figure 3 As shown, the specifications of the first amplifying switch 401, the second amplifying switch 403, the first auxiliary switch 402, and the second auxiliary switch 404 are matched with the voltages of clock signals 303 and 304. Clock signals 303 and 304 are out of phase. When the first amplifying switch 401 and the second auxiliary switch 404 are turned on, the second amplifying switch 403 and the first auxiliary switch 402 are turned off. At this time, the level of the first output node formed between the first amplifying switch 401 and the first auxiliary switch 402 is pulled low by the turned-on first amplifying switch 401, while the level of the first output node formed between the second amplifying switch 403 and the second auxiliary switch 404 is pulled high by the turned-on second auxiliary switch 404. When clock signals 303 and 304 are continuously input, the two first output nodes output as shown below. Figure 3The clock signals 305 and 306, which are opposite in phase and have square wave waveforms, constitute the target differential clock signal. Furthermore, referring to Figure 2, by controlling the magnitude of the second supply voltage, the high and low levels of clock signals 305 and 306 can be controlled, thereby amplifying the original differential clock signal to obtain a target differential clock signal with an amplitude higher than the original differential clock signal.

[0065] In some other possible implementations, see Figure 4b As shown, the amplitude amplification module also includes a first amplification switch 411 and a first auxiliary switch 412 forming a first amplitude amplification branch, and a second amplification switch 413 and a second auxiliary switch 414 forming a second amplitude amplification branch. The difference lies in that the first amplification switch 411 and the second amplification switch 413 are PMOS transistors of the same specification, while the first auxiliary switch 412 and the second auxiliary switch 414 are NMOS transistors of the same specification; the sources of the first auxiliary switch 412 and the second auxiliary switch 414 are grounded, and... Figure 2a , Figure 2b , Figure 4a Similarly, ground is indicated by "VSS"; the sources of the first amplifying switch 411 and the second amplifying switch 413 are connected to the second supply voltage, and Figure 4a Similarly, the second supply voltage is represented by "VDD". Likewise, the drain of the first auxiliary switch 412 is connected to the drain of the first amplifying switch 411, and the drain of the second auxiliary switch 414 is connected to the drain of the second amplifying switch 413. The first amplitude amplification branch and the second amplitude amplification branch have the same structure, and the same type of switch transistors are placed at corresponding positions, making the first amplitude amplification branch and the second amplitude amplification branch two completely identical branches.

[0066] The synchronization unit also includes a first synchronization branch composed of a first synchronization switch 415 and a first feedback switch 416, and a second synchronization branch composed of a second synchronization switch 417 and a second feedback switch 418. The difference lies in that the first synchronization switch 415 and the second synchronization switch 417 are PMOS transistors of the same specification, while the first feedback switch 416 and the second feedback switch 418 are NMOS transistors of the same specification. In the first synchronization branch, the source of the first feedback switch 416 is connected to ground VSS, and the gate and drain of the first feedback switch 416 are connected; the drain of the first synchronization switch 415 is connected to the drain of the first feedback switch 416, and the source of the first synchronization switch 415 is connected to the second supply voltage VDD. In the second synchronization branch, the source of the second feedback switch 418 is grounded, and the gate and drain of the second feedback switch 418 are connected; the drain of the second synchronization switch 417 is connected to the drain of the second feedback switch 418, and the source of the second synchronization switch 417 is connected to the second supply voltage VDD. Similarly, the first synchronous branch and the second synchronous branch have the same structure and are equipped with the same type of switch tubes at the same positions, so that the first synchronous branch and the second synchronous branch constitute two identical branches.

[0067] Similarly, the first synchronization branch and the first amplitude amplification branch form the first group of voltage amplifier circuits, and the second synchronization branch and the second amplitude amplification branch form the second group of voltage amplifier circuits. In the first group of voltage amplifier circuits, the gates of the first amplification switch 411 and the first synchronization switch 415 are connected to receive the clock signal from one end of the intermediate differential clock signal, such as... Figure 3 The clock signal 303 is shown. Under the action of the clock signal 303, the first amplifying switch 411 and the first synchronous switch 415 are synchronously turned on or off. At the same time, the gate of the first feedback switch 416 is connected to the gate of the second auxiliary switch 414 in the second voltage amplifier circuit. Since the gate of the first feedback switch 416 is connected to the drain, the gate of the first feedback switch 416 (connected to the second power supply voltage VDD) is at a high level when the first synchronous switch 415 is turned on, so that the state of the first feedback switch 416 is consistent with the switching state of the first synchronous switch 415, both being in the on state.

[0068] Furthermore, since the gates of the first feedback switch 416 and the second auxiliary switch 414 are connected, and the switching states of the first feedback switch 416 and the second auxiliary switch 414 are consistent, the first feedback switch 416 can feed back the switching state of the first amplification switch 411 to the second auxiliary switch 414, so that the second auxiliary switch 414 and the first amplification switch 411 are synchronously turned on or off.

[0069] Similarly, in the second voltage amplifier circuit, the gates of the second amplifying switch 413 and the second synchronous switch 417 are connected to receive the clock signal from the other end of the intermediate differential clock signal, such as... Figure 3 The clock signal 304 shown causes the second synchronous switch 417 and the second amplifying switch 413 to be turned on or off synchronously. The second feedback switch 418 can feed back the switching state of the second amplifying switch 413 to the first auxiliary switch 412 in the first amplifier circuit, so that the first auxiliary switch 412 and the second amplifying switch 413 are turned on or off synchronously.

[0070] Combination Figure 3 As shown, the specifications of the first amplifying switch 411, the second amplifying switch 413, the first auxiliary switch 412, and the second auxiliary switch 414 are matched with the voltages of clock signals 303 and 304. Clock signals 303 and 304 are out of phase. When the first amplifying switch 411 and the second auxiliary switch 414 are turned on, the second amplifying switch 413 and the first auxiliary switch 412 are turned off. At this time, the level of the first output node (connected to the second supply voltage VDD) formed by the first amplifying switch 411 and the first auxiliary switch 412 is pulled high to a high level by the turned-on first amplifying switch 411, while the level of the first output node (connected to ground VSS) formed by the second amplifying switch 413 and the second auxiliary switch 414 is pulled low to a low level by the turned-on second auxiliary switch 414. When clock signals 303 and 304 are continuously input, the two first output nodes output as shown in the diagram. Figure 3 The clock signals 305 and 306, which are opposite in phase and have square wave waveforms, form the target differential clock signal.

[0071] Furthermore, referring to Figure 2, by controlling the magnitude of the second power supply voltage, the high and low levels of clock signals 305 and 306 can be controlled, thereby amplifying the original differential clock signal and obtaining a target differential clock signal with an amplitude higher than the original differential clock signal.

[0072] It should be noted that the above are merely illustrative examples, and the amplitude amplification module can also be implemented using other types of amplification circuits. The specific structure of the amplitude amplification module, as well as the specific structure of the synchronization unit within the amplitude amplification module, can be set according to requirements, and this embodiment does not impose any limitations on this.

[0073] In this embodiment, the amplitude amplification module consists of two identical amplitude amplification branches and a synchronization unit. The amplitude amplification branches only include an amplification switch and an auxiliary switch, resulting in a simple structure that simplifies the circuit structure of the clock buffer. Similarly, the synchronization unit includes two identical synchronization branches, further simplifying the circuit structure of the clock buffer.

[0074] Optionally, the common-mode regulation module may also include a current source connected to the common-mode regulation branch to provide a first supply voltage to the common-mode regulation branch.

[0075] For example, such as Figure 5a As shown, Figure 5a The circuit diagram of another common-mode regulation module in an embodiment of the present invention is shown. The current source 203 can be composed of a first power switch 2031 and a second power switch 2032, both of which can be PMOS transistors. The source of the first power switch 2031 is connected to the power supply voltage. Figure 5a The symbol "VDD" represents the power supply voltage. The drain of the first power switch 2031 is connected to the source of the second power switch 2032. The first power switch 2031 and the second power switch 2032 form a common-source, common-gate current mirror structure. The drain of the second power switch 2032 is connected to the source of the first branch switch 2011 and the source of the second branch switch 2021. When the gates of the first power switch 2031 and the second power switch 2032 are connected to a bias voltage, a first supply voltage can be output at the drain of the second power switch 2032 to provide a first supply voltage for the first common-mode regulation branch and the second common-mode regulation branch.

[0076] In some other possible implementations, see Figure 5b As shown, similarly, the current source 203 can also be composed of a first power switch 2131 and a second power switch 2132, both of which can be PMOS transistors. The source of the first power switch 2131 is connected to the power supply voltage. Figure 5b The symbol "VDD" represents the power supply voltage. The drain of the first power switch 2131 is connected to the source of the second power switch 2132. The first power switch 2131 and the second power switch 2132 form a common-source, common-gate current mirror structure.

[0077] The drain of the second power switch 2132 is connected to the source of the first branch load 2112 and the second branch load 2122, respectively. When the gates of the first power switch 2131 and the second power switch 2132 are connected to a bias voltage, a first supply voltage can be output at the drain of the second power switch 2132 to provide a first supply voltage for the first common-mode regulation branch and the second common-mode regulation branch.

[0078] The above are merely illustrative examples. The specific structure and type of the current source can be configured according to the common-mode regulation branch structure. This embodiment does not impose any restrictions on this.

[0079] In this embodiment, a current source is provided at one end of the common-mode regulation branch to provide a first supply voltage to the common-mode regulation branch, which can control the power consumption of the common-mode regulation branch and thus reduce the power consumption of the entire clock buffer.

[0080] Optionally, the clock buffer may also include a first inverter group and a second inverter group;

[0081] Both the first inverter group and the second inverter group include a target number of correction inverters connected in series; the target number is not less than 1; the input terminal of the first inverter group is connected to the amplitude amplification module to receive the first terminal clock signal in the target differential clock signal and output the first terminal clock signal after correcting the duty cycle.

[0082] The input of the second inverter group is connected to the amplitude amplification module to receive the second-end clock signal in the target differential clock signal and output the second-end clock signal after the duty cycle is corrected.

[0083] For example, such as Figure 6 As shown, Figure 6 The diagram illustrates a circuit schematic of an inverter group according to an embodiment of the present invention. The clock buffer may further include a first inverter group 601 and a second inverter group 602, with a target quantity of 2. That is, the first inverter group 601 and the second inverter group 602 are each composed of two correction inverters connected in series. The two inverters in the first inverter group 601 are correction inverters, and the two inverters in the second inverter group 602 are correction inverters. It should be noted that each inverter group may include one, two, or three correction inverters, and the number of correction inverters in each inverter group can be specifically set according to requirements. This embodiment does not impose any limitations on this.

[0084] Because the amplifying and auxiliary switching transistors cannot be fully turned on or off, the target differential clock signal output by the amplitude amplification branch may not reach its full swing. For example... Figure 3As shown, if the high level is 1V and the low level is 0V at full swing, then the high level of clock signal 305 and clock signal 306 is 0.9V and the low level is 0.1V, which is close to full swing.

[0085] In this embodiment, the input terminal of the first inverter group 601 is connected to the first output node in the first amplitude amplification branch, used to receive the first terminal clock signal in the target differential clock signal, i.e., clock signal 305, and output the first terminal clock signal after correcting the duty cycle, i.e. Figure 3 The clock signal 307 is used in the circuit. Similarly, the input of the second inverter group 602 is connected to the first output node in the second amplitude amplification branch to receive the second clock signal of the target differential clock signal, i.e., clock signal 306, and output the second clock signal after correcting the duty cycle. Figure 3 The clock signal 308 in the system. For example... Figure 3 As shown, after two phase inversion corrections, the high level of the first-end clock signal and the low level of the second-end clock signal are 1V and 0V, respectively, achieving full swing.

[0086] In this embodiment of the application, an inverter group is provided in the clock buffer. By correcting the amplitude of the target differential clock signal output by the amplitude amplification module through the inverter group, a full-swing target clock signal can be obtained, thereby providing the driving capability of the target clock signal.

[0087] Optionally, the target number is 2; the clock buffer also includes a first cross inverter and a second cross inverter for correcting the crossover point of the first terminal clock signal after the duty cycle correction and the second terminal clock signal after the duty cycle correction;

[0088] The input of the first cross inverter is connected between two correction inverters in the first inverter group, and the output is connected between two correction inverters in the second inverter group.

[0089] The input of the second cross inverter is connected between the two correction inverters in the second inverter group, and the output is connected between the two correction inverters in the first inverter group.

[0090] For example, such as Figure 6As shown, the first inverter group 601 and the second inverter group 602 each include two correction inverters connected in series. The input of the first cross inverter 604 is connected between the two correction inverters in the first inverter group 601, and the output is connected between the two correction inverters in the second inverter group 602. Similarly, the input of the second cross inverter 603 is connected between the two correction inverters in the second inverter group 602, and the output is connected between the two correction inverters in the first inverter group 601. The first and second cross inverters are used to correct the crossover point of clock signals 307 and 308, preventing distortion of clock signals 307 and 308.

[0091] In this embodiment of the application, a cross inverter is set between the first inverter group and the second inverter group to correct the crossover point of the clock signal, which can avoid the problem of distortion of the target differential clock signal.

[0092] In summary, in this embodiment, the clock buffer includes a common-mode adjustment module and an amplitude amplification module. The common-mode adjustment module receives the original differential clock signal output by the clock generation circuit and outputs an intermediate differential clock signal whose common-mode voltage matches the input common-mode voltage of the amplitude amplification module. The amplitude amplification module is connected to the common-mode adjustment module and receives the intermediate differential clock signal, outputting a target differential clock signal with an amplitude higher than the original differential clock signal. When the differential clock signal output by the third-party clock generation circuit has a high rate, resulting in a small amplitude of the original differential clock signal and a waveform approximately sine wave, the common-mode adjustment module adjusts the common-mode voltage of the clock signal to match the input common-mode voltage range of the amplitude amplification module. When the common-mode voltage of the intermediate differential clock signal output by the common-mode adjustment module matches the input common-mode voltage of the amplitude amplification module, the amplitude amplification module can accurately amplify the clock signal to obtain a target clock signal with an accurate duty cycle, thereby solving the duty cycle distortion problem during clock signal amplification.

[0093] Reference Figure 7 The diagram illustrates a flowchart of a clock signal processing method according to an embodiment of the present invention. This method can be applied to the aforementioned clock buffer and may include:

[0094] Step 701: Receive the original differential clock signal, adjust the original differential clock signal, and output the intermediate differential clock signal.

[0095] The common-mode voltage of the intermediate differential clock signal is matched with the input common-mode voltage of the amplitude amplification module.

[0096] In this embodiment, step 701 can be executed by the common mode adjustment module shown in Figure 2 or Figure 5. The specific execution process of step 701 can be referred to the above examples, and will not be elaborated in this embodiment.

[0097] Step 702: After amplifying the intermediate differential clock signal, the amplitude amplification module outputs the target differential clock signal.

[0098] The amplitude of the target differential clock signal is higher than that of the original differential clock signal.

[0099] In this embodiment, step 702 can be executed by the amplitude amplification module shown in Figure 4. The specific execution process of step 702 can be referred to the above example, and will not be elaborated in this embodiment.

[0100] In some possible implementations, after amplifying the intermediate differential clock signal, the amplitude amplification module outputs the target differential clock signal, including:

[0101] It receives the intermediate differential clock signal and controls the switching states of the amplification switch and the auxiliary switch in the same amplitude amplification branch to be reversed, so that the amplitude amplification module outputs the target differential clock signal.

[0102] The switch state includes the on state and the off state.

[0103] In some possible implementations, receiving the original differential clock signal, adjusting the original differential clock signal, and outputting an intermediate differential clock signal includes:

[0104] The method receives the original differential clock signal and controls the current waveform in the common-mode regulation branch to make the circuit waveform consistent with the fundamental frequency waveform of the received original differential clock signal, so as to output an intermediate differential clock signal in the common-mode regulation branch. In some possible implementations, the method may further include:

[0105] The clock signal at each end of the target differential clock signal is inverted according to the target number of times to correct the duty cycle of the target differential clock signal; the target number of times is not less than 1.

[0106] In this embodiment, the step of inverting the clock signal at each end of the target differential clock signal by the target number of times can be performed by... Figure 6The first and second inverter groups shown are executed, with the number of corrected inverters in each inverter group equal to the target number of times. In summary, in this embodiment, the original differential clock signal is received, and an intermediate differential clock signal with a common-mode voltage matching the input common-mode voltage of the amplitude amplification module is output. Based on the intermediate differential clock signal, the amplitude amplification module outputs a target differential clock signal with an amplitude higher than the original differential clock signal. When the differential clock signal output by the third-party clock generation circuit has a high rate, resulting in a small amplitude and an approximately sinusoidal waveform for the original differential clock signal, by adjusting the common-mode voltage of the clock signal to match the input common-mode voltage range of the amplitude amplification module, when the common-mode voltage of the intermediate differential clock signal output by the common-mode adjustment module matches the input common-mode voltage of the amplitude amplification module, the amplitude amplification module can accurately amplify the clock signal to obtain a target clock signal with an accurate duty cycle, thereby solving the duty cycle distortion problem during clock signal amplification.

[0107] Figure 8 A structural block diagram of an electronic device according to an embodiment of the present invention is shown. For example, the electronic device 800 may be a mobile phone, computer, digital broadcasting terminal, messaging device, game console, tablet device, medical device, fitness equipment, personal digital assistant, etc.

[0108] Reference Figure 8 The electronic device 800 may include one or more of the following components: a processing component 802, a memory 804, a power supply component 806, a multimedia component 808, an audio component 810, an input / output (I / O) interface 812, a sensor component 814, and a communication component 816.

[0109] Processing component 802 typically controls the overall operation of electronic device 800, such as operations associated with display, telephone calls, data communication, camera operation, and recording operations. Processing component 802 may include one or more processors 920 to execute instructions to complete all or part of the steps of the methods described above. Furthermore, processing component 802 may include one or more units to facilitate interaction between processing component 802 and other components. For example, processing component 802 may include a multimedia unit to facilitate interaction between multimedia component 808 and processing component 802.

[0110] Memory 804 is configured to store various types of data to support the operation of electronic device 800. Examples of this data include instructions for any application or method operating on electronic device 800, contact data, phonebook data, messages, pictures, videos, etc. Memory 804 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0111] Power supply component 806 provides power to various components of electronic device 800. Power supply component 806 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to electronic device 800.

[0112] Multimedia component 808 includes a screen that provides an output interface between the electronic device 800 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touchscreen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors may sense not only the boundaries of the touch or swipe action but also the duration and pressure associated with the touch or swipe operation. In some embodiments, multimedia component 808 includes a front-facing camera and / or a rear-facing camera. When the electronic device 800 is in an operating mode, such as a shooting mode or a video mode, the front-facing camera and / or the rear-facing camera may receive external multimedia data. Each front-facing camera and rear-facing camera may be a fixed optical lens system or have focal length and optical zoom capabilities.

[0113] Audio component 810 is configured to output and / or input audio signals. For example, audio component 810 includes a microphone (MIC) configured to receive external audio signals when electronic device 800 is in an operating mode, such as call mode, recording mode, and voice recognition mode. The received audio signals may be further stored in memory 804 or transmitted via communication component 816. In some embodiments, audio component 810 also includes a speaker for outputting audio signals.

[0114] I / O interface 812 provides an interface between processing component 802 and peripheral interface units, such as keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to, home buttons, volume buttons, power buttons, and lock buttons.

[0115] Sensor assembly 814 includes one or more sensors for providing state assessments of various aspects of electronic device 800. For example, sensor assembly 814 can detect the on / off state of electronic device 800, the relative positioning of components such as the display and keypad of electronic device 800, changes in position of electronic device 800 or a component of electronic device 800, the presence or absence of user contact with electronic device 800, orientation or acceleration / deceleration of electronic device 800, and temperature changes of electronic device 800. Sensor assembly 814 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. Sensor assembly 814 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, sensor assembly 814 may also include an accelerometer, gyroscope, magnetometer, pressure sensor, or temperature sensor.

[0116] Communication component 816 is configured to facilitate wired or wireless communication between electronic device 800 and other devices. Electronic device 800 can access wireless networks based on communication standards, such as WiFi, 2G, or 3G, or combinations thereof. In one exemplary embodiment, communication component 816 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, communication component 816 also includes a near-field communication (NFC) unit to facilitate short-range communication. For example, the NFC unit may be implemented based on radio frequency identification (RFID) technology, Infrared Data Association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0117] In an exemplary embodiment, the electronic device 800 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processing circuits (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components.

[0118] In this embodiment, the electronic device also includes a clock buffer as described above.

[0119] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0120] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, apparatus, or computer program products. Therefore, embodiments of the present invention can take the form of entirely hardware embodiments, entirely software embodiments, or embodiments combining software and hardware aspects. Furthermore, embodiments of the present invention can take the form of computer program products implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0121] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0122] These computer program instructions may also be stored in a computer-readable storage medium capable of directing a computer or other programmable data processing terminal device to operate in a predictive manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0123] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal equipment, causing a series of operational steps to be performed on the computer or other programmable terminal equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable terminal equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0124] Although preferred embodiments of the present invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present invention.

[0125] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0126] The present invention has provided a detailed description of a clock buffer and device, an electronic device, and a storage medium. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A clock buffer, characterized in that, include: Common-mode adjustment module and amplitude amplification module; The common-mode adjustment module is used to receive the original differential clock signal output by the third-party clock generation circuit, and after adjusting the original differential clock signal, output an intermediate differential clock signal; the common-mode voltage of the intermediate differential clock signal is matched with the input common-mode voltage of the amplitude amplification module. The common-mode regulation module includes two symmetrically arranged and identical common-mode regulation branches; each common-mode regulation branch includes a branch switch and a branch load connected in series; the branch switches are respectively used to receive the original differential clock signal and control the current waveform in the common-mode regulation branch respectively; when the duty cycle of the original differential clock signal is distorted, the waveform of the intermediate differential clock signal is controlled to be consistent with the fundamental frequency waveform of the original differential clock signal, and the intermediate differential clock signal is output in the corresponding common-mode regulation branch. Wherein, the input common-mode voltage matching means that the common-mode voltage of the intermediate differential clock signal is within the input common-mode voltage range of the amplitude amplification module; The amplitude amplification module is connected to the common-mode adjustment module and is used to receive the intermediate differential clock signal, amplify the intermediate differential clock signal, and output the target differential clock signal; the amplitude of the target differential clock signal is higher than the amplitude of the original differential clock signal. The amplitude amplification module includes two identical amplitude amplification branches and a synchronization unit; The amplitude amplification branch includes an amplifying switch and an auxiliary switch; the output terminal of the auxiliary switch is connected to the input terminal of the amplifying switch; the output terminal of the amplifying switch is grounded; the connection point between the amplifying switch and the auxiliary switch constitutes a first output node; and a clock signal of one end of the target differential clock signal is output at the first output node in each of the amplitude amplification branches. The synchronization unit is connected to the amplifying switch and the auxiliary switch respectively; the synchronization unit and the amplifying switch are used to simultaneously receive the intermediate differential clock signal and control the switching states of the amplifying switch and the auxiliary switch in the same amplitude amplification branch to be opposite; the switching state includes a conducting state and an off state.

2. The clock buffer according to claim 1, characterized in that, The synchronization unit includes two identical synchronization branches, and each synchronization branch and one amplitude amplification branch form a voltage amplification circuit. The synchronization branch includes a synchronization switch and a feedback switch, and the output terminal and control terminal of the feedback switch are connected to the input terminal of the synchronization switch. In one set of voltage amplifier circuits, the control terminal of the auxiliary switch is connected to the control terminal of the feedback switch in another set of voltage amplifier circuits; the control terminals of the amplifying switch and the synchronous switch receive the intermediate differential clock signal to control the amplifying switch in the voltage amplifier circuit and the auxiliary switch in the other set of voltage amplifier circuits to be synchronously turned on or off.

3. The clock buffer according to claim 1, characterized in that, The common-mode regulation module further includes a current source connected to the common-mode regulation branch to provide a first power supply voltage to the common-mode regulation branch.

4. The clock buffer according to any one of claims 1-3, characterized in that, The clock buffer also includes a first inverter group and a second inverter group; Both the first inverter group and the second inverter group include a target number of corrective inverters connected in series; the target number is not less than 1. The input terminal of the first inverter group is connected to the amplitude amplification module, and is used to receive the first terminal clock signal in the target differential clock signal and output the first terminal clock signal after the duty cycle is corrected. The input terminal of the second inverter group is connected to the amplitude amplification module to receive the second terminal clock signal in the target differential clock signal and output the second terminal clock signal after correcting the duty cycle.

5. The clock buffer according to claim 4, characterized in that, The target number is 2; the clock buffer also includes a first cross inverter and a second cross inverter for correcting the intersection of the first-end clock signal after the duty cycle correction and the second-end clock signal after the duty cycle correction; The input terminal of the first cross inverter is connected between two correction inverters in the first inverter group, and the output terminal is connected between two correction inverters in the second inverter group; The input of the second cross inverter is connected between two correction inverters in the second inverter group, and the output is connected between two correction inverters in the first inverter group.

6. A clock signal processing method, characterized in that, Applied to the clock buffer as described in any one of claims 1-5, the method comprises: The system receives the original differential clock signal, adjusts it, and outputs an intermediate differential clock signal; the common-mode voltage of the intermediate differential clock signal is matched with the input common-mode voltage of the amplitude amplification module. After amplifying the intermediate differential clock signal, the amplitude amplification module outputs a target differential clock signal; the amplitude of the target differential clock signal is higher than the amplitude of the original differential clock signal.

7. The method according to claim 6, characterized in that, Also includes: The clock signal at each end of the target differential clock signal is inverted for the target number of times to correct the duty cycle of the target differential clock signal. The target number is not less than 1.

8. An electronic device, characterized in that, Includes the clock buffer as described in any one of claims 1-5.

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