A highest potential selection circuit for a bidirectional level conversion chip

Abstract

The application discloses a highest potential selection circuit for a bidirectional level conversion chip, and has the characteristics that the circuit comprises a logic unit, a selection unit and a voltage stabilizing unit; the logic unit is connected with the selection unit and the voltage stabilizing unit respectively, and is used for performing logic judgment on an input voltage based on a highest potential voltage Vmax and generating an output voltage Vout; the selection unit is used for selecting the highest potential voltage Vmax based on comparison between the output voltage Vout of the logic unit and a chip power supply voltage Vcc; and the voltage stabilizing unit is used for performing delay voltage stabilizing operation on the highest potential voltage Vmax generated by the selection unit, so as to feed back the stabilized highest potential voltage Vmax to the selection unit. The circuit in the application can ensure the stability of the highest potential, prevent the power tube from being burned out due to overcurrent, and ensure that the output delay of the bidirectional level conversion circuit is small.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and more specifically, to a highest potential selection circuit for a bidirectional level conversion chip. Background Technology

[0002] In existing technologies, bidirectional level shifting circuits are typically used in conjunction with a highest potential selection circuit. This is to prevent some bidirectional level shifting circuits with reverse current protection from generating an output voltage higher than the chip's power supply voltage, which could cause the output power transistor to remain on for an extended period and burn out. The highest potential selection circuit compares the chip's power supply voltage with the output voltage of the bidirectional level shifting circuit, selecting the higher voltage as the gate voltage of the power transistor, thereby preventing the output transistor from turning on and generating a large current that could burn out the power transistor.

[0003] Currently, the commonly used highest potential selection circuit consists of two diodes. The anodes of the two diodes are connected to the output voltage terminal of the bidirectional level conversion circuit and the chip power supply voltage terminal, respectively, while the cathodes of both serve as the output terminals of the highest potential selection circuit, used to output the highest potential. This circuit connection method results in the highest potential always being lower than the chip power supply voltage or the output voltage of the bidirectional level conversion circuit; specifically, it must be lower than the forward voltage of the diodes used in the circuit. However, to ensure that the power transistor is not burned out, the diodes need to be completely turned off under the corresponding logic, meaning the output highest potential should be as close as possible to the larger of the chip voltage or the output voltage. Therefore, in this type of highest potential selection circuit, the diodes used must have sufficiently low forward voltages and sufficiently large diode sizes. This leads to a significant increase in chip area and a substantial reduction in the usable area of ​​the chip.

[0004] On the other hand, during the selection process of the highest potential selection circuit and the output voltage of the bidirectional level conversion circuit, the highest potential output by the circuit will fluctuate to some extent with changes in the output voltage level. This fluctuation will significantly affect the output performance of the bidirectional level conversion circuit, for example, by causing a delay in the output voltage. To prevent fluctuations in the highest potential, a capacitor can be added to the highest potential selection circuit to overcome some of the fluctuations caused by level switching. However, the capacitor that provides anti-jitter effect not only further increases the chip area, but its anti-jitter effect is also very limited.

[0005] Therefore, there is an urgent need for a new highest potential selection circuit for bidirectional level conversion chips. Summary of the Invention

[0006] To address the shortcomings of existing technologies, the present invention aims to provide a highest potential selection circuit for a bidirectional level conversion chip. The selection unit ensures that the highest voltage in the circuit is always selected, and the voltage regulation unit is used to achieve a stable output of the highest voltage based on a time delay method.

[0007] The present invention adopts the following technical solution. A highest potential selection circuit for a bidirectional level conversion chip, the circuit includes a logic unit, a selection unit, and a voltage regulator unit; wherein, the logic unit is connected to the selection unit and the voltage regulator unit respectively, and is used to perform logical judgment on the input voltage based on the highest potential voltage Vmax and generate an output voltage Vout; the selection unit is used to select and generate the highest potential voltage Vmax based on the comparison between the output voltage Vout of the logic unit and the chip power supply voltage Vcc; the voltage regulator unit is used to perform a delayed voltage regulation operation on the highest potential voltage Vmax generated by the selection unit, thereby feeding back the stabilized highest potential voltage Vmax to the selection unit.

[0008] Preferably, the logic unit is part of a bidirectional level conversion chip, including a first buffer, a second buffer, a first switch, and a second switch; wherein, the input terminals of the first buffer and the second buffer respectively receive input voltages from the chip; the device voltage terminal of the first buffer is the highest potential voltage Vmax, and the device voltage terminal of the second buffer is the chip power supply voltage Vcc; the output terminals of the first buffer and the second buffer are respectively connected to the gates of the first switch and the second switch, and the source and drain terminals of the first switch and the second switch are connected in series between the chip power supply voltage and the low potential; the connection point between the first switch and the second switch is the output terminal of the logic unit.

[0009] Preferably, both the first and second buffers are inverting buffers; the first switch is a PMOS transistor and the second switch is an NMOS transistor, wherein the source of the first switch is connected to the chip power supply voltage, the body is connected to the highest potential voltage Vmax, the drain is connected to the drain of the second switch as the output terminal of the logic unit, and the source of the second switch is grounded.

[0010] Preferably, the selection unit includes a first selection diode, a second selection diode, and a selection capacitor Cap; wherein, the positive terminal of the first selection diode is connected to the chip power supply voltage Vcc, and the negative terminal is connected to one end of the second selection diode and the selection capacitor respectively, and serves as the output of the selection unit to generate the highest potential voltage Vmax; the positive terminal of the second selection diode is connected to the output voltage Vout of the logic unit; and the other end of the selection capacitor is grounded.

[0011] Preferably, when the output voltage Vout of the logic unit is greater than the chip power supply voltage Vcc, the selection unit selects the output voltage Vout as the reference voltage for the highest potential voltage Vmax, and the generated highest potential voltage Vmax = Vout - Vdio; when the output voltage Vout of the logic unit is less than the chip power supply voltage Vcc, the selection unit selects the output voltage Vcc as the reference voltage for the highest potential voltage Vmax, and the generated highest potential voltage Vmax = Vcc - Vdio; where Vdio is the forward voltage of the first selection diode and the second selection diode.

[0012] Preferably, the voltage regulator unit is used to perform a delay operation on the voltage signal at the output of the first buffer, and clamp the highest potential voltage Vmax when the input voltage is level-switched based on the delay.

[0013] Preferably, the voltage regulator unit includes a first inverter, a second inverter, and a Zener PMOS transistor; wherein the first inverter and the second inverter are cascaded, the input terminal of the first inverter is connected to the output terminal of the first buffer in the logic unit, and the output terminal of the second inverter is connected to the gate of the Zener PMOS transistor; the device voltage terminals of the first inverter and the second inverter are connected to the highest potential voltage Vmax; the source and body terminals of the Zener PMOS transistor are respectively connected to the highest potential voltage Vmax, and the drain is connected to the chip power supply voltage Vcc.

[0014] Preferably, the logic circuit is the internal circuit of the bidirectional level conversion chip.

[0015] Preferably, the bidirectional level conversion chip is a 74AVC8T245 chip.

[0016] Preferably, the logic unit generates an output voltage Vout based on the highest potential voltage Vmax after stabilization generated by the voltage regulator unit; the output voltage Vout remains synchronized with the chip power supply voltage under the action of the highest potential voltage Vmax after stabilization.

[0017] The beneficial effects of this invention are that, compared with the prior art, the highest potential selection circuit for a bidirectional level conversion chip in this invention, by adding a voltage regulation unit, ensures that the highest potential is sufficiently stable, which not only prevents the power transistor from burning out due to overcurrent, but also ensures that the output delay of the bidirectional level conversion circuit is small. The circuit structure of this invention is simple and occupies a small layout area.

[0018] The beneficial effects of the present invention also include:

[0019] 1. The voltage regulator unit used in this invention has a simple structure and requires few components. It only needs one delay circuit and one switching transistor to achieve a stable output of the highest voltage. This invention optimizes the existing technology that requires large diodes and large capacitors to form an effective highest voltage selection circuit, reduces the selection criteria for components in the highest voltage selection circuit, and reduces the overall layout area of ​​the chip at minimal cost.

[0020] 2. The voltage regulation unit in this invention employs an input delay approach to avoid jitter caused by changes in the highest potential due to variations in the output and power supply voltages. This minimizes jitter resulting from level changes, thereby preventing output delays in the bidirectional level conversion circuit caused by jitter in the highest potential. Therefore, this invention further achieves accurate output from the bidirectional level conversion chip, prevents chip output delays, improves chip performance, prevents logic judgment errors caused by delays, enhances chip performance, and reduces the bit error rate in the system.

[0021] 3. The voltage regulation unit in this invention, on the one hand, cancels the Vout level switching at the rising edge of the signal at point B through a Zener PMOS transistor; on the other hand, it maintains the excellent falling edge characteristic of the original technical solution by keeping the Zener PMOS transistor in the off state at the falling edge of the signal at point B. Through the Zener PMOS transistor, overall control of Vmax is achieved, thereby preventing Vout delay.

[0022] 4. In this invention, the addition of a Zener PMOS transistor stabilizes the maximum potential voltage Vmax, thereby expanding the selection range for components such as capacitor Cap and diode in the selection unit. For example, a smaller capacitor Cap and a smaller diode can still achieve an effective maximum potential voltage Vmax. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the circuit structure of the logic unit in the bidirectional level conversion circuit of the prior art and the highest potential selection circuit for the bidirectional level conversion chip of the present invention.

[0024] Figure 2 The diagram shows the circuit structure of the selection unit in the highest potential selection circuit of the present invention for a bidirectional level conversion chip, which is a high potential selection circuit in the prior art.

[0025] Figure 3 This is a schematic diagram of the voltage state at various locations in a bidirectional level conversion circuit in the prior art.

[0026] Figure 4This is a schematic diagram of the circuit structure of the voltage regulator unit in the highest potential selection circuit of a bidirectional level conversion chip according to the present invention.

[0027] Figure 5 This is a schematic diagram of the voltage state at various locations in the highest potential selection circuit of a bidirectional level conversion chip according to the present invention. Detailed Implementation

[0028] The present application will be further described below with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solutions of the present invention, and should not be construed as limiting the scope of protection of the present application.

[0029] Figure 1 This is a schematic diagram of the circuit structure of the logic unit in the bidirectional level conversion circuit of the prior art and the highest potential selection circuit for the bidirectional level conversion chip of the present invention. Figure 2 This is a schematic diagram of the circuit structure of the selection unit in the highest potential selection circuit of the present invention, which is used in a bidirectional level conversion chip. (See diagram below.) Figure 1 , Figure 2 As shown, a prior art highest potential selection circuit for a bidirectional level conversion chip includes a bidirectional level conversion circuit and a highest potential selection circuit.

[0030] In the bidirectional level conversion circuit, a buffer can make a logical judgment based on the highest potential output by the highest potential selection circuit and generate an output voltage based on the highest potential.

[0031] Specifically, to prevent the power transistor from burning out, the device voltage of the register corresponding to the PMOS transistor in the existing bidirectional level shifting circuit can be set to the highest potential Vmax. This highest potential Vmax is generated by a highest potential selection circuit, which compares the chip power supply voltage Vcc with the output voltage Vout of the bidirectional level shifting circuit, selecting the larger value as an approximate output of Vmax.

[0032] Ideally, Vmax should be equal to the larger of Vcc or Vout. However, since the highest potential selection circuit needs to be implemented using two diodes, the actual value of Vmax is either Vcc - Vdio or Vout - Vdio. Here, Vdio refers to the forward voltage of the two diodes in the circuit. Generally speaking, the smaller the forward voltage drop across the diodes, i.e., Vdio, the better the effect of the highest potential selection circuit. The generated Vmax is used as a reference voltage by the register; that is, when the register's logic output is high, its output level should be equal to Vmax. This ensures that the gate voltage of the PMOS transistor connected to the register output is greater than its source voltage Vcc for a period of time. Therefore, the PMOS transistor will not be continuously turned on, and there will be no continuous large current inside, thus preventing burnout.

[0033] Furthermore, because the circuit uses a highest potential selection circuit, its highest output potential is affected by Vout and Vcc. For example, when the voltage at point A switches from a high potential to a low potential, or from a low potential to a high potential, the output voltage Vout will also switch accordingly. Since the highest potential Vmax is generated based on Vout, when Vout switches, Vmax will be affected and generate impulse pulses towards higher or lower potentials, i.e., jitter. Although a selection capacitor Cap can be set in the highest potential selection circuit to restore the highest potential Vmax to its original state, the effect of the capacitor is usually insufficient to reduce the jitter that occurs rapidly within a short period of time.

[0034] The jitter in the highest potential Vmax alters the performance of the first buffer that generates the output based on Vmax, affecting the output voltage at point B. Typically, this jitter causes a voltage fluctuation of approximately several hundred millivolts, slowing down the rising edge of the output signal at point B. On the other hand, due to the larger size of the power transistor connected to point B, the parasitic capacitance on its gate also causes a delay in the input voltage at point B. Specifically, the power transistor's turn-on and turn-off performance is slower relative to the input at point B, causing a short-term tilt in the rising and falling edges of the output voltage Vout, rather than a transient change. Both of these factors contribute to a delay in the output signal Vout relative to the output signal at point A.

[0035] It should be noted that, due to the parasitic capacitance, the drop at point B is slowed down during the falling edge. However, at the same time, point B is also affected by the upward jitter of Vmax. This effect can offset the slowed drop speed of the level at point B caused by the parasitic capacitance, so that point B still has good switching performance on the falling edge.

[0036] The aforementioned reasons create a vicious cycle, easily leading to output errors in bidirectional level conversion circuits. This problem can cause very serious issues when using bidirectional level conversion chips to perform data transmission or control functions, and therefore must be avoided.

[0037] Figure 3 This is a schematic diagram showing the voltage states at various points in a bidirectional level conversion circuit in the prior art. For example... Figure 3 As shown, in the existing circuit, the voltage at point A serves as the input voltage for the bidirectional level shifting circuit, determining the subsequent logic of the register and the switching transistor. As mentioned above, because Vmax is affected by the output voltage Vout, which has the same logic direction as the input voltage at point A, it fluctuates, thus slowing down the rise time response of the voltage at point B, causing a delay. This delay at point B, along with the parasitic capacitance of the PMOS transistor, further delays the output voltage Vout, resulting in a cyclical shift of the output voltage across one or more time periods.

[0038] This invention discloses a highest potential selection circuit that adds a voltage regulator unit to the existing circuit design, thereby preventing output voltage delay and ensuring the accuracy of the circuit output. A highest potential selection circuit for a bidirectional level conversion chip is characterized by comprising a logic unit, a selection unit, and a voltage regulator unit; wherein the logic unit, connected to the selection unit and the voltage regulator unit respectively, is used to perform logical judgment on the input voltage based on the highest potential voltage Vmax and generate an output voltage Vout; the selection unit is used to select and generate the highest potential voltage Vmax based on a comparison between the output voltage Vout of the logic unit and the chip power supply voltage Vcc; the voltage regulator unit is used to perform a delayed voltage regulation operation on the highest potential voltage Vmax generated by the selection unit, thereby feeding back the stabilized highest potential voltage Vmax to the selection unit.

[0039] Specifically, the logic unit corresponds to the bidirectional level conversion circuit in the prior art, and the selection unit corresponds to the highest potential selection circuit in the prior art. In this invention, a voltage regulator unit is added to the logic unit and the selection unit. This voltage regulator unit can be connected to both the logic unit and the selection unit, respectively, to control the stable output of the highest potential voltage Vmax, and to feed this output back to the buffer of the logic unit.

[0040] Preferably, the logic unit is part of a bidirectional level conversion chip, including a first buffer, a second buffer, a first switch, and a second switch; wherein, the input terminals of the first buffer and the second buffer respectively receive input voltages from the chip; the device voltage terminal of the first buffer is the highest potential voltage Vmax, and the device voltage terminal of the second buffer is the chip power supply voltage Vcc; the output terminals of the first buffer and the second buffer are respectively connected to the gates of the first switch and the second switch, and the source and drain terminals of the first switch and the second switch are connected in series between the chip power supply voltage and the low potential; the connection point between the first switch and the second switch is the output terminal of the logic unit.

[0041] Understandably, the input at point A flows into two branches. The first branch includes a first buffer and a PMOS transistor connected in series. After being buffered by the first buffer, the gate of the PMOS transistor identifies whether the signal at point A can turn on the PMOS transistor, thus outputting a logic signal to the output terminal accordingly. Similarly, the second branch includes a second buffer and an NMOS transistor, which also helps to form an output voltage at the output terminal.

[0042] Preferably, both the first and second buffers are inverting buffers; the first switch is a PMOS transistor and the second switch is an NMOS transistor, wherein the source of the first switch is connected to the chip power supply voltage, the body is connected to the highest potential voltage Vmax, the drain is connected to the drain of the second switch as the output terminal of the logic unit, and the source of the second switch is grounded.

[0043] Specifically, to implement the bidirectional level shifting logic in the invention, both the first and second buffers can be configured as positive-phase buffers or both as negative-phase buffers. This configuration ensures that both the first and second buffers output signals opposite to point A. After the signals from the first and second buffers are input to the gates of the PMOS and NMOS transistors respectively, when the signal input is high, the PMOS transistor conducts at a low level, thereby pulling up the output voltage Vout; conversely, when the signal input is low, the NMOS transistor conducts at a high level, thereby pulling down the output voltage Vout.

[0044] In addition, since the body terminal of the first PMOS transistor is connected to the highest potential voltage Vmax, reverse current to the first PMOS transistor is prevented when the output voltage Vout is higher than the source voltage Vcc of the transistor.

[0045] Preferably, the selection unit includes a first selection diode, a second selection diode, and a selection capacitor Cap; wherein, the positive terminal of the first selection diode is connected to the chip power supply voltage Vcc, and the negative terminal is connected to one end of the second selection diode and the selection capacitor respectively, and serves as the output of the selection unit to generate the highest potential voltage Vmax; the positive terminal of the second selection diode is connected to the output voltage Vout of the logic unit; and the other end of the selection capacitor is grounded.

[0046] Understandably, when the selection unit uses two diodes connected to Vcc and Vout respectively, the highest potential Vmax at the negative terminal of the diode will be generated based on the larger voltage. To ensure the relative stability of the highest potential Vmax and prevent it from being affected by the voltage signals that frequently switch potentials in the logic unit, a selection capacitor Cap with a large capacitance value is also connected at the Vmax terminal. This capacitor can discharge when the potential of Vout switches from high to low and charge when the potential of Vout switches from low to high, thereby keeping the potential of Vmax within a fixed range.

[0047] Preferably, when the output voltage Vout of the logic unit is greater than the chip power supply voltage Vcc, the selection unit selects the output voltage Vout as the reference voltage for the highest potential voltage Vmax, and the generated highest potential voltage Vmax = Vout - Vdio; when the output voltage Vout of the logic unit is less than the chip power supply voltage Vcc, the selection unit selects the output voltage Vcc as the reference voltage for the highest potential voltage Vmax, and the generated highest potential voltage Vmax = Vcc - Vdio; where Vdio is the forward voltage of the first selection diode and the second selection diode.

[0048] As can be understood, the above describes the logic for the highest output voltage Vmax of the logic power supply. Its output performance is affected by the forward voltage Vdio of the first and second selection diodes. Under normal chip operation, Vmax should be maintained between Vcc and Vdio.

[0049] Preferably, the voltage regulator unit is used to perform a delay operation on the voltage signal at the output of the first buffer, and clamp the highest potential voltage Vmax when the input voltage is switched based on the delay.

[0050] Specifically, the input terminal of the voltage regulator unit is connected to the output terminal of the first buffer, i.e., point B in the circuit. Through this connection, the voltage signal at point B is input to the voltage regulator unit to perform a time-delay operation, and after the delay, a voltage signal at point C is generated, controlling the turn-on or turn-off of the Zener PMOS transistor. When the voltage at point C is high, the Zener PMOS transistor will be turned off to prevent the voltage regulator unit from affecting Vmax. On the other hand, when the voltage at point C is low, the Zener PMOS transistor will be turned on, clamping the source voltage, i.e., the highest potential voltage Vmax, of the PMOS transistor at a position higher than the drain voltage, Vcc, of the PMOS transistor.

[0051] Figure 4 This is a schematic diagram of the voltage regulator unit in the highest potential selection circuit of a bidirectional level conversion chip according to the present invention. The specific connection method of the circuit in the voltage regulator unit is as follows: Figure 4 As shown.

[0052] Preferably, the voltage regulator unit includes a first inverter, a second inverter, and a Zener PMOS transistor; wherein the first inverter and the second inverter are cascaded, the input terminal of the first inverter is connected to the output terminal of the first buffer in the logic unit, and the output terminal of the second inverter is connected to the gate of the Zener PMOS transistor; the device voltage terminals of the first inverter and the second inverter are connected to the highest potential voltage Vmax; the source and body terminals of the Zener PMOS transistor are respectively connected to the highest potential voltage Vmax, and the drain is connected to the chip power supply voltage Vcc.

[0053] Specifically, the first and second inverters implement a time delay for the voltage at point B, which is the voltage signal with the reverse logic from point A. During this time delay, when the voltage regulator unit is not connected, the highest potential voltage Vmax will jitter. In this invention, during this time delay, the voltage signal at point C will not switch from high to low or from low to high; that is, the gate voltage of the Zener PMOS transistor will not change, and the conduction or cutoff state of the Zener PMOS transistor will also remain unchanged. Specifically, when the input voltage, i.e., the voltage signal at point A, changes from high to low, the voltage signal at point B will change in the opposite direction. The voltage signal at point C will not immediately change from low to high, but will rise from low to high after a short time delay. Under the influence of the low level on the gate of the Zener PMOS transistor, although the level switch has been performed at point A, the PMOS transistor remains on, making Vmax equal to Vcc. This ensures that when the level switch is performed at point A, Vmax is stabilized by the voltage regulator unit in a state without jitter. Although Vmax will fluctuate with level switching, the signal delay stabilizes it. At this point, the fluctuation of Vmax is controlled within a very small range; both the duration and amplitude of the fluctuation are reduced, or even eliminated. Therefore, the fluctuation of Vmax will not cause a delay in the output voltage Vout.

[0054] In addition, since the body and source terminals of the Zener PMOS transistor are simultaneously connected to the highest level voltage Vmax, reverse flow is prevented when the drain voltage Vcc of the transistor is greater than the source voltage Vmax, thus maintaining the normal logic of the circuit.

[0055] Preferably, the logic circuit is the internal circuit of the bidirectional level conversion chip. Preferably, the bidirectional level conversion chip is a 74AVC8T245 chip.

[0056] Specifically, the 74AVC8T245 chip is an 8-bit, bidirectional, power-operated transceiver chip with configurable voltage conversion and a tri-state output dual-supply bus. It features two data input / output pins, An and Bn, a direction control input pin, DIR, an output potential input pin, OE, and dual power supply pins VCCa and VCCb. The dual power supply pins VCCa and VCCb can be powered at any voltage between 0.8V and 3.6V, making the device suitable for any low-voltage node, such as 0.8V, 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V. This chip has been widely used in various partially powered circuits to provide an off-current Ioff, which shuts down the circuit's output, preventing damage to the chip from harmful backflow during power outages. The chip's latch-up performance and ESD protection are superior to similar chips. The maximum data transfer rate can reach 320Mbps.

[0057] Preferably, the logic unit generates an output voltage Vout based on the highest potential voltage Vmax after stabilization generated by the voltage regulator unit; the output voltage Vout remains synchronized with the chip power supply voltage under the action of the highest potential voltage Vmax after stabilization.

[0058] Specifically Figure 5 This is a schematic diagram showing the voltage state at various locations in the highest potential selection circuit of a bidirectional level conversion chip according to the present invention. The voltage conditions at various locations in the circuit of the present invention are as follows: Figure 5 As shown.

[0059] When the potential at point A is still periodically switching between high and low levels, after passing through the inverter between points A and B and the cascaded inverter between points B and C, the potential output at point C is not only an inversion of the potential at point A, but also includes the delay time of the three inverters. Therefore, as Figure 5 As shown, the output signal at point C lags slightly behind the output signal at point A.

[0060] Because the output at point C lags, point C maintains its original potential while point A switches levels. In other words, when the power transistor changes state from off to on, causing a change in Vout, the on / off state of the Zener PMOS transistor remains completely unchanged. When Vout changes from high to low and the signal at point B changes from low to high, the gate of the Zener PMOS transistor remains low, allowing it to continue conducting and maintaining the stability of Vmax. At this point, the jitter caused by the selection and logic units on Vmax is largely overcome by the voltage regulator, thus stabilizing Vmax at its original state.

[0061] On the other hand, when Vout transitions from low to high, the gate of the Zener PMOS transistor remains high, which keeps the Zener PMOS transistor off, thus ensuring that Vmax is not affected by the voltage regulator circuit. Since the falling edge signal at point B already guarantees the same excellent performance (i.e., no delay), the voltage regulator circuit of this invention prevents the Zener PMOS from affecting other parts of the circuit when the signal at point B is at its falling edge, ensuring the excellent performance of the original circuit.

[0062] The beneficial effects of this invention are that, compared with the prior art, the highest potential selection circuit for a bidirectional level conversion chip in this invention, by adding a voltage regulation unit, ensures that the highest potential is sufficiently stable, which not only prevents the power transistor from burning out due to overcurrent, but also ensures that the output delay of the bidirectional level conversion circuit is small. The circuit structure of this invention is simple and occupies a small layout area.

[0063] The applicant of this invention has provided a detailed description of the embodiments of the invention in conjunction with the accompanying drawings. However, those skilled in the art should understand that the above embodiments are merely preferred embodiments of the invention. The detailed description is only intended to help readers better understand the spirit of the invention and is not intended to limit the scope of protection of the invention. On the contrary, any improvements or modifications made based on the inventive spirit of the invention should fall within the scope of protection of the invention.

Claims

1. A highest potential selection circuit for a bidirectional level conversion chip, characterized in that: The circuit includes a logic unit, a selection unit, and a voltage regulation unit; wherein... The logic unit is connected to the selection unit and the voltage regulation unit respectively, and is used to perform logical judgment on the input voltage based on the highest potential voltage Vmax and generate the output voltage Vout. The logic unit is part of the bidirectional level conversion chip, including a first buffer, a second buffer, a first switch, and a second switch; The selection unit is used to select the highest potential voltage Vmax based on a comparison between the output voltage Vout of the logic unit and the chip power supply voltage Vcc. The voltage regulation unit is used to perform a delayed voltage regulation operation on the highest potential voltage Vmax generated by the selection unit, thereby feeding back the stabilized highest potential voltage Vmax to the selection unit. The voltage regulator unit includes a first inverter, a second inverter, and a Zener PMOS transistor; wherein... The first inverter and the second inverter are cascaded. The input terminal of the first inverter is connected to the output terminal of the first buffer in the logic unit, and the output terminal of the second inverter is connected to the gate of the Zener PMOS transistor. The device voltage terminals of the first inverter and the second inverter are connected to the highest potential voltage Vmax; The source and body of the Zener PMOS transistor are connected to the highest potential voltage Vmax, and the drain is connected to the chip power supply voltage Vcc.

2. The highest potential selection circuit for a bidirectional level conversion chip according to claim 1, characterized in that: The input terminals of the first and second buffers respectively receive the input voltage from the chip; The device voltage terminal voltage of the first buffer is the highest potential voltage Vmax, and the device voltage terminal voltage of the second buffer is the chip power supply voltage Vcc; The output terminals of the first and second buffers are respectively connected to the gates of the first and second switching transistors, and the source and drain terminals of the first and second switching transistors are connected in series between the chip power supply voltage and the low potential. The connection point between the first and second switching transistors is the output terminal of the logic unit.

3. The highest potential selection circuit for a bidirectional level conversion chip according to claim 2, characterized in that: Both the first and second caches are inverting caches; The first switch is a PMOS transistor and the second switch is an NMOS transistor. The source of the first switch is connected to the chip power supply voltage, the body is connected to the highest potential voltage Vmax, and the drain is connected to the drain of the second switch as the output terminal of the logic unit. The source of the second switch is grounded.

4. The highest potential selection circuit for a bidirectional level conversion chip according to claim 3, characterized in that: The selection unit includes a first selection diode, a second selection diode, and a selection capacitor Cap; wherein... The positive terminal of the first selection diode is connected to the chip power supply voltage Vcc, and the negative terminal is connected to one end of the second selection diode and the selection capacitor, respectively, and serves as the output of the selection unit to generate the highest potential voltage Vmax. The positive terminal of the second selection diode is connected to the output voltage Vout of the logic unit; The other end of the selected capacitor is grounded.

5. The highest potential selection circuit for a bidirectional level conversion chip according to claim 4, characterized in that: When the output voltage Vout of the logic unit is greater than the chip power supply voltage Vcc, the selection unit selects the output voltage Vout as the reference voltage for the highest potential voltage Vmax. At this time, the generated highest potential voltage Vmax = Vout - Vdio. When the output voltage Vout of the logic unit is less than the chip power supply voltage Vcc, the selection unit selects the output voltage Vcc as the reference voltage for the highest potential voltage Vmax. At this time, the generated highest potential voltage Vmax = Vcc - Vdio. Wherein, Vdio is the forward voltage of the first selection diode and the second selection diode.

6. The highest potential selection circuit for a bidirectional level conversion chip according to claim 5, characterized in that: The voltage regulation unit is used to perform a delay operation on the voltage signal at the output of the first buffer, and clamp the highest potential voltage Vmax when the input voltage is switched based on the delay.

7. The highest potential selection circuit for a bidirectional level conversion chip according to claim 6, characterized in that: The logic unit is the internal circuit of the bidirectional level conversion chip.

8. The highest potential selection circuit for a bidirectional level conversion chip according to claim 6, characterized in that: The bidirectional level conversion chip is a 74AVC8T245 chip.

9. The highest potential selection circuit for a bidirectional level conversion chip according to claim 8, characterized in that: The logic unit generates the output voltage Vout based on the highest stable potential voltage Vmax generated by the voltage regulator unit. The output voltage Vout is synchronized with the chip power supply voltage under the action of the highest potential voltage Vmax after stabilization.

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