A phase-locked loop and a control method of a phase-locked loop

Abstract

This invention discloses a phase-locked loop (PLL) and its control method, comprising: a digital PLL configured to receive an input clock and a feedback clock, and output a control word; a latch control circuit configured to receive the control word output by the digital PLL, latch the received control word and output the received control word when a lock signal is valid, and output the latched control word when the lock signal is invalid; a first analog PLL configured to receive a reference clock and the control word output by the latch control circuit, and output a first clock after locking; a second analog PLL configured to receive a reference clock and the control word output by the digital PLL, and output a second clock after locking; and a first selector configured to receive the first clock and the second clock, output the first clock as a feedback clock when the lock signal is valid, and output the second clock as a feedback clock when the lock signal is invalid, thereby ensuring the overall stability and uninterrupted operation of the PLL.

Description

Technical Field

[0001] This invention relates to, but is not limited to, the field of communications, and particularly to a phase-locked loop and a control method for the phase-locked loop. Background Technology

[0002] Clock and reset are essential components of a hardware system. Clock is typically provided by a crystal oscillator or a phase-locked loop (PLL). A PLL can be a standalone chip on a hardware board or a submodule embedded within a chip.

[0003] A phase-locked loop (PLL) is a feedback circuit. Its function is to synchronize the phase of the circuit's clock with an external clock. During operation, when the frequency of the output signal equals the frequency of the input signal, the output voltage maintains a fixed phase difference with the input voltage; in other words, the phases of the output and input voltages are locked.

[0004] Generally, a phase-locked loop (PLL) needs to enter a hold state when the input clock changes, such as when the clock signal is lost or switched. At this time, the feedback loop is disconnected. Once the input clock recovers or the switching ends and the loop stabilizes again, it exits the hold state, the feedback loop restarts, and the PLL re-enters a stable loop state. Throughout the entire process of the PLL entering the hold state from a stable loop state and then exiting the hold state to re-entering the stable loop state, the continuity and stability of the PLL's output clock are the key indicators for evaluating the PLL's performance.

[0005] Currently, the common method for a phase-locked loop (PLL) to exit the hold state is as follows: after the input clock stabilizes again, the output clock from the hold state is re-divided to generate a new feedback clock. The new feedback clock and the new input clock form a new local feedback loop, allowing the new feedback clock to gradually stabilize within the local feedback loop. Once stable, the PLL exits the hold state. This method can reduce clock interruptions and instability during switching to some extent, but it is not suitable for digital PLLs that control analog PLLs via control words, which have complex structures. Summary of the Invention

[0006] This application provides a phase-locked loop, including:

[0007] A digital phase-locked loop is configured to receive an input clock and a feedback clock, and output a control word.

[0008] The latching control circuit is configured to receive the control word output by the digital phase-locked loop, latch the received control word and output the received control word when the latching signal is valid, and output the latched control word when the latching signal is valid.

[0009] The first analog phase-locked loop is configured to receive a reference clock and the control word output by the latch control circuit, and output a first clock after locking, which is the output of the entire phase-locked loop.

[0010] The second analog phase-locked loop is configured to receive the reference clock and the control word output by the digital phase-locked loop, and output the locked second clock.

[0011] A first selector is configured to receive a first clock and a second clock, output the first clock as the feedback clock when the lock signal is valid, and output the second clock as the feedback clock when the lock signal is invalid.

[0012] This application also provides a control method for a phase-locked loop, applicable to any of the phase-locked loops described in the embodiments, the control method comprising:

[0013] When the phase-locked loop is in normal working condition, the input clock and / or the state inside the phase-locked loop are detected to obtain a first detection result;

[0014] When the first detection result is an abnormal state, the locking signal is set to invalid, and the phase-locked loop enters a holding state; in the holding state, the control word received by the first analog phase-locked loop is the control word of the latch, and the feedback clock received by the digital phase-locked loop is the second clock.

[0015] The phase-locked loop and its control method provided in at least one embodiment of this application have the following advantages compared with the prior art:

[0016] When the phase-locked loop (PLL) is in the hold state, the digital PLL and the second analog PLL form a feedback loop, which can simulate the feedback loop established between the digital PLL and the first analog PLL under normal conditions without affecting the overall output of the PLL. This can solve the problem of the unstable state of the PLL before the feedback loop re-stabilizes when the complex PLL exits the hold state, making the overall PLL stable and uninterrupted.

[0017] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the solutions described in the description and the accompanying drawings. Attached Figure Description

[0018] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0019] Figure 1This is a schematic diagram of a typical phase-locked loop (PLL).

[0020] Figure 2 A schematic diagram of a complex phase-locked loop (PLL) where a digital PLL controls an analog PLL via a control word;

[0021] Figure 3 This is a schematic diagram of the phase-locked loop provided in an example embodiment of the present invention;

[0022] Figure 4 This is a flowchart of a phase-locked loop control method provided in an example embodiment of the present invention;

[0023] Figure 5 A flowchart of a phase-locked loop control method provided in another exemplary embodiment of the present invention. Detailed Implementation

[0024] This application describes several embodiments, but these descriptions are exemplary and not restrictive, and it will be apparent to those skilled in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with, or may replace, any feature or element of any other embodiment.

[0025] This application includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in this application may also be combined with any conventional features or elements to form a unique inventive scheme as defined by the claims. Any feature or element of any embodiment may also be combined with features or elements from other inventive schemes to form another unique inventive scheme as defined by the claims. Therefore, it should be understood that any feature shown and / or discussed in this application may be implemented individually or in any suitable combination. Therefore, the embodiments are not limited except by the limitations imposed by the appended claims and their equivalents. Furthermore, various modifications and changes may be made within the scope of the appended claims.

[0026] Furthermore, in describing representative embodiments, the specification may have presented methods and / or processes as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that it does not depend on such a specific order. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Moreover, the claims concerning the method and / or process should not be limited to the steps performed in the written order, and those skilled in the art will readily understand that these orders can be varied and still remain within the spirit and scope of the embodiments of this application.

[0027] Figure 1 This is a schematic diagram of a typical phase-locked loop, such as... Figure 1 As shown, the input clock is first divided, and then frequency and phase are detected by the feedback after frequency division; the frequency and phase detection results are then filtered to obtain a stable signal to control the voltage-controlled oscillator to generate a high-frequency clock; the high-frequency clock is output after frequency division, and the frequency division result is also sent to the frequency and phase detector as feedback.

[0028] Given an input clock, a phase-locked loop (PLL) will process it to produce an output clock. The output clock can be a multiple or division of the input clock, and it can be an integer multiple or division, or a multiple or division with a fractional part, depending on the parameters and input / output specifications of the different PLLs. Generally, the input clock, output clock, and voltage-controlled oscillator (VCO) all have range requirements. For example, the input clock range is typically required to be between 10MHz and 500MHz, the output clock range between 6.25MHz and 800MHz, and the VCO range between 1000MHz and 10000MHz.

[0029] The range requirement limits the application of the phase-locked loop (PLL), for example, an application with an input of 8kHz and an output of 155.52MHz. Figure 1 This is not achievable with a typical phase-locked loop (PLL) structure. However, in engineering applications, to avoid power consumption or accuracy loss during transmission, the input clock frequency is often relatively low. To make PLLs suitable for a wider range of applications, a digital PLL is usually used to process the input clock. This digital PLL also contains frequency and phase detectors and filters, but the digital voltage-controlled oscillator (VCO) is removed. The output of the filter in the digital PLL is a control word, which is used to control the analog PLL.

[0030] Figure 2 This is a schematic diagram of a complex phase-locked loop (PLL) where a digital PLL controls an analog PLL via control words, as shown below. Figure 2 As shown, the digital phase-locked loop processes the input clock, outputs a control word, and sends the control word to the analog phase-locked loop. The structure of the analog phase-locked loop and... Figure 1In essence, a digital phase-locked loop (PLL) is a common PLL with a standard output control word. Here, the state of the second frequency divider within the analog PLL is determined by the control word output from the digital PLL. The product of the analog PLL's reference clock frequency and the control word equals the output frequency of the analog PLL's voltage-controlled oscillator (VCO). Together, the analog and digital PLLs form a larger loop: the clock signal locked by the analog PLL is fed back to the digital PLL, which then generates a control word based on the input clock to control the analog PLL's output. The control word serves both as the frequency division control from the digital PLL's VCO output to the frequency and phase detector and as the multiplication factor for the analog PLL's reference clock.

[0031] A digital phase-locked loop (PLL) controls the input clock of a complex analog PLL via a control word. In this case, the analog PLL's reference clock is a fixed base clock. The input clock to the digital PLL, however, can vary depending on the application. Complex PLLs can accept a wider range of input frequencies than simple analog PLLs.

[0032] Generally, a phase-locked loop (PLL) needs to enter a hold state when the input clock changes, such as when the clock signal is lost or switched. At this time, the feedback loop is disconnected. Once the input clock recovers or the switching ends and the loop stabilizes again, it exits the hold state, the feedback loop restarts, and the PLL re-enters a stable loop state. Throughout the entire process of the PLL entering the hold state from a stable loop state and then exiting the hold state to re-entering the stable loop state, the continuity and stability of the PLL's output clock are the key indicators for evaluating the PLL's performance.

[0033] Currently, a good method for exiting the hold state of a conventional phase-locked loop (PLL) is as follows: after the input clock stabilizes again, the output clock from the hold state is re-divided to generate a new feedback clock. This new feedback clock and the new input clock form a new local feedback loop, allowing the new feedback clock to gradually stabilize within this loop before exiting the PLL hold state. This method can reduce clock interruptions and instability during switching to some extent. However, this method is not suitable for complex structures where digital PLLs control analog PLLs via control words. PLLs where digital PLLs control analog PLLs via control words are called complex PLLs. That is, when exiting the hold state in a complex PLL, the entire PLL will experience a period of instability before the feedback loop stabilizes again.

[0034] Figure 3 This is a schematic diagram of the phase-locked loop provided in an example embodiment of the present invention, as shown below. Figure 3 As shown, a phase-locked loop may include: a digital phase-locked loop, a latching control circuit, a first analog phase-locked loop, a second analog phase-locked loop, and a first selector.

[0035] This invention provides a phase-locked loop (PLL) suitable for complex structures where a digital PLL controls an analog PLL via a control word. By setting a second analog PLL, when the entire PLL is in a hold state, the digital PLL and the second analog PLL form a feedback loop (e.g., ...). Figure 3 The second feedback loop in the PLL can be reinitialized and reset without affecting the overall output of the PLL. This method can solve the unstable state of the PLL before the first feedback loop stabilizes when the complex PLL exits the holding state, thus making the PLL stable and uninterrupted.

[0036] The phase-locked loop provided in this embodiment of the invention is applicable to complex structures such as analog phase-locked loops controlled by digital phase-locked loops through control words. It can receive a wide range of frequency points and low frequency points, and has a wider range of applications.

[0037] like Figure 3 As shown, the first feedback loop is a closed loop of digital phase-locked loop → first analog phase-locked loop → digital phase-locked loop, and the second feedback loop is a closed loop of digital phase-locked loop → second analog phase-locked loop → digital phase-locked loop.

[0038] A digital phase-locked loop is configured to receive an input clock and a feedback clock, and output a control word.

[0039] The digital phase-locked loop can be a general phase-locked loop in this field, such as... Figure 1 The diagram shows a typical phase-locked loop (PLL). Under normal conditions, the input clock signal passes through the digital PLL and outputs a control word sequence.

[0040] When the input clock changes, such as clock loss, clock fragmentation, frequency deviation exceeding the range, or external clock switching, the entire phase-locked loop is triggered to enter the hold state.

[0041] The latch control circuit is configured to receive the control word output by the digital phase-locked loop, latch the received control word and output the received control word when the latch signal is valid, and output the latched control word when the latch signal is invalid.

[0042] Under normal conditions, the latch control circuit periodically samples the control words of the latched digital phase-locked loop (PLL). Multiple samples of the control words form a sequence, which is then stored locally. Once the PLL is fully locked, the latch control circuit latches a sequence of control words. This latched control word is used when the PLL enters the hold state.

[0043] The first analog phase-locked loop is configured to receive a reference clock and a control word output from the latch control circuit, and output the first clock after locking. The first clock is the output of the entire phase-locked loop.

[0044] The first analog phase-locked loop (PLL) controls its internal voltage-controlled oscillator (VCO) to generate a high-frequency clock based on the control word and reference clock. This high-frequency clock is then divided to obtain the locked clock, which is fed back to the digital PLL. Therefore, under normal operating conditions, the first feedback loop is established between the digital PLL and the analog PLL. The reference clock can be a stable local crystal oscillator.

[0045] The first analog phase-locked loop can be a general phase-locked loop in this field, such as... Figure 1 The diagram shows a typical phase-locked loop (PLL). The first analog PLL can be referred to as the master analog PLL.

[0046] The second analog phase-locked loop is configured to receive a reference clock and a control word output from the digital phase-locked loop, and output a locked second clock.

[0047] The second feedback loop, composed of a second analog phase-locked loop and a second digital phase-locked loop, completely simulates the first feedback loop. This solves the problem that existing technologies can only generate a feedback clock through division, relying on the output of the analog phase-locked loop and the reference clock input, thus failing to fully simulate the first feedback loop. Furthermore, it addresses the limitation that existing technologies can only achieve frequency division, not frequency multiplication, while the second feedback loop, composed of the second analog phase-locked loop and the second digital phase-locked loop, can respond to any input clock, thus having a wider range of applications.

[0048] The second analog phase-locked loop can be a general phase-locked loop in this field, such as... Figure 1 The diagram shows a typical phase-locked loop (PLL). The second analog PLL can be referred to as the auxiliary analog PLL. The first and second analog PLLs share the same reference clock; that is, both analog PLLs use the same reference clock.

[0049] The first selector is configured to receive a first clock and a second clock, output the first clock as a feedback clock when the lock signal is valid, and output the second clock as a feedback clock when the lock signal is invalid.

[0050] The selector can be used to select either the first clock output from the first analog phase-locked loop as the feedback clock, or the second clock output from the second analog phase-locked loop as the feedback clock.

[0051] Under normal conditions, the input clock outputs a control word sequence through the digital phase-locked loop (PDL), which then feeds the control word sequence to the first analog phase-locked loop (PLL). The first analog PLL, based on the control word and the reference clock, controls its internal voltage-controlled oscillator (VCO) to generate a high-frequency clock. This high-frequency clock is then divided to obtain the locked clock, which is then fed back to the DLL via a first selector, forming the first feedback loop. Therefore, under normal operating conditions, the first feedback loop is established between the DLL and the first analog PLL.

[0052] Under normal conditions, the latch control circuit periodically samples the control word of the latched digital phase-locked loop. The multiple samples of the control word form a control word sequence, which the latch control circuit stores locally.

[0053] When the input clock changes, such as clock loss, clock fragmentation, frequency deviation exceeding the range, or external clock switching, the entire phase-locked loop is triggered to enter the hold state.

[0054] When in a holding state, the latch control circuit receives an invalid latch signal and selects the locally latched control word sequence as input to the first analog phase-locked loop. In this way, the control word sequence received by the first analog phase-locked loop is continuous and stable, and the latched clock output by the first analog phase-locked loop is also continuous and stable.

[0055] After the phase-locked loop (PLL) is in a hold state, the first selector selects the output of the second analog PLL and sends it to the digital PLL as feedback input. At this point, a second feedback loop is formed between the digital PLL and the second analog PLL. This loop responds to changes in the input clock, and once the input clock stabilizes, the second feedback loop subsequently stabilizes. During this process, either the digital PLL or the second analog PLL can be reset and its parameters reconfigured as needed to obtain any desired results or to verify specific parameters and ideas. After the reset or configuration is complete, the second feedback loop will gradually stabilize, and the control word sequence output by the digital PLL will also stabilize.

[0056] Once the feedback loop in the hold state stabilizes, the entire PLL system can exit the hold state at any time as needed. When exiting the hold state, the latch control circuit selects the control word sequence directly output by the digital PLL from the latched control word sequence, and the first selector synchronously switches to the output of the first analog PLL as the feedback input of the digital PLL. Since the outputs of the first and second analog PLLs have the same frequency and phase, the first feedback loop immediately enters loop closure, thus achieving continuous and stable overall clock output for the PLL.

[0057] The phase-locked loop provided in this embodiment of the invention, when the entire phase-locked loop is in the hold state, the digital phase-locked loop and the second analog phase-locked loop form a feedback loop, which can simulate the feedback loop established between the digital phase-locked loop and the first analog phase-locked loop under normal conditions, without affecting the overall output of the phase-locked loop. It can solve the problem of the unstable state of the entire phase-locked loop before the feedback loop re-stabilizes when the complex phase-locked loop exits the hold state, so that the entire phase-locked loop is stable and uninterrupted.

[0058] In one exemplary embodiment of the present invention, the latch control circuit may include:

[0059] The latch is configured to receive, sample, and latch the control word output by the digital phase-locked loop when the latch signal is valid, and to stop sampling and latching the control word output by the digital phase-locked loop when the latch signal is invalid.

[0060] The second selector is configured to receive the control word output by the digital phase-locked loop and the control word of the latch, output the received control word when the latch signal is invalid, and output the latch control word when the latch signal is valid.

[0061] like Figure 3 As shown, the latch control circuit may include a latch and a second selector. After the phase-locked loop is fully locked, the latch will latch a sequence of control words. The latched control words are used when the phase-locked loop enters the holding state.

[0062] Under normal conditions, the latch periodically samples the control word of the latched digital phase-locked loop. The multiple samples of the control word form a control word sequence, which the latch stores locally.

[0063] When maintaining the state, the second selector selects the control word sequence that the latch has locked locally and sends it to the first analog phase-locked loop as input. In this way, the control word sequence received by the first analog phase-locked loop is continuous and stable, and the locked clock output by the first analog phase-locked loop is also continuous, stable and uninterrupted.

[0064] In one example, the second selector opens first, followed by the first selector. The locking indication output by the digital phase-locked loop can be sent to both the first and second selectors simultaneously, and there is a delay when the locking indication output by the digital phase-locked loop is sent to the first selector. The specific duration of the delay can be configured by software, and this embodiment does not limit it.

[0065] In an exemplary embodiment of the present invention, when the input reference clock and control word are the same, the first clock and the second clock output by the second analog phase-locked loop and the first analog phase-locked loop have the same frequency and the phase difference is within a preset difference range.

[0066] The first and second analog phase-locked loops have the same structure and parameters. The output frequencies of the first and second analog phase-locked loops are the same, and their output phases are basically the same.

[0067] Once the feedback loop in the hold state stabilizes, the entire PLL system can exit the hold state at any time as needed. When exiting the hold state, the second selector selects the control word sequence directly output by the digital PLL from the latched control word sequence, while the first selector synchronously switches to the output of the first analog PLL. Since the outputs of the first and second analog PLLs have the same frequency and phase, the first feedback loop established between the digital PLL and the first analog PLL immediately enters loop closure, thus achieving continuous and stable overall clock output for the PLL.

[0068] In one exemplary embodiment of the present invention, the phase-locked loop may further include a detection circuit;

[0069] The detection circuit is configured to detect the state of the input clock and / or the internal state of the phase-locked loop and output a lock signal; wherein, when the detection result is an abnormal state, an invalid lock signal is output, and when the detection result is a normal state, an valid lock signal is output.

[0070] The detection circuit periodically checks the input clock and internal states. In case of an anomaly, it indicates an abnormality through a latch signal. Enabling the latch signal initiates normal operation. Disabling the latch signal deactivates the latch, initiating a hold state and invalidating the latch signal output to the latch, thus selecting the latched control word sequence. Upon entering the hold state, the feedback loop between the digital phase-locked loop (PLL) and the first analog PLL is broken until exiting the hold state. After exiting the hold state, the feedback loop between the digital PLL and the first analog PLL is re-established.

[0071] The main states inside a digital phase-locked loop can include at least one of the following: frequency locking and phase locking. A configurable delay and lockout indication output enable are provided. That is, after both frequency locking and phase locking conditions are met, a final lockout signal (or lockout indication) is output after a certain delay, provided the lockout indication output is enabled.

[0072] In one example, the detection circuit detects the internal state of the phase-locked loop and outputs a locking signal. When both frequency locking and phase locking are satisfied, the detection result is a normal state, and a valid locking signal is output; when at least one of frequency locking and phase locking is not satisfied, the detection result is an abnormal state, and an invalid locking signal is output. The specific determination of frequency locking and phase locking can adopt existing determination schemes, which are not limited or elaborated here in this embodiment.

[0073] In one example, the detection circuit detects the input clock and outputs a lock signal. When the input clock changes, such as when the clock signal is lost or switched, the detection result is an abnormal state, and an invalid lock signal is output; when the input clock is stable or normal, the detection result is a normal state, and a valid lock signal is output.

[0074] In one example embodiment of the present invention, the detection circuit can be integrated into the digital phase-locked loop. In this case, the latch's locking signal is the locking signal of the digital phase-locked loop.

[0075] After the phase-locked loop (PLL) is fully locked, the latch stores a sequence of control words. These latched control words are used when the PLL enters the hold state. The detection circuit in the digital PLL periodically checks the input clock and internal states. If an anomaly occurs, it indicates an error on the lock signal output by the digital PLL, either by enabling the lock signal or disabling it, thus controlling the PLL to enter the hold state and selecting the latched control word sequence. Upon entering the hold state, the feedback loop between the digital PLL and the first analog PLL is broken until the hold state is exited. After exiting the hold state, the feedback loop between the digital PLL and the first analog PLL is re-established.

[0076] In an alternative embodiment, the detection circuit can be integrated into other circuits such as a second analog phase-locked loop, or it can be set up separately.

[0077] In one example embodiment of the present invention, both the first selector and the second selector are two-to-one selectors.

[0078] In this embodiment, the first selector can be a two-to-one selector, so as to output a first clock as a feedback clock when the lock signal is valid, and output a second clock as a feedback clock when the lock signal is invalid.

[0079] In this embodiment, the second selector can be a two-to-one selector to output the received control word when the lock signal is valid and output the latched control word when the lock signal is invalid.

[0080] Figure 4 This is a flowchart illustrating a phase-locked loop (PLL) control method according to an example embodiment of the present invention. The PLL control method can be applied to any PLL shown in the embodiment. Figure 4 As shown, the control method for a phase-locked loop may include:

[0081] S401: When the phase-locked loop is in normal working condition, the input clock and / or the state inside the phase-locked loop are detected to obtain the first detection result.

[0082] The detection circuit periodically detects the input clock and various internal states. When the input clock changes, such as clock loss, clock splitting, frequency deviation exceeding the range, or external clock switching, the first detection result is determined to be an abnormal state, triggering the entire phase-locked loop to enter the holding state.

[0083] S402: When the first detection result is an abnormal state, the lock signal is set to invalid and the phase-locked loop enters the hold state; in the hold state, the control word received by the first analog phase-locked loop is the latched control word, and the feedback clock received by the digital phase-locked loop is the second clock.

[0084] The detection circuit periodically checks the input clock and various internal states. When an abnormality occurs, it will indicate this through a lock signal, invalidating the lock signal and thus controlling the system to enter a hold state.

[0085] When in a holding state, the latch control circuit receives an invalid latch signal and selects the locally latched control word sequence as input to the first analog phase-locked loop. In this way, the control word sequence received by the first analog phase-locked loop is continuous and stable, and the latched clock output by the first analog phase-locked loop is also continuous and stable.

[0086] After the phase-locked loop (PLL) is in a hold state, the first selector selects the output of the second analog PLL and sends it to the digital PLL as feedback input. At this point, a second feedback loop is formed between the digital PLL and the second analog PLL. This loop responds to changes in the input clock, and once the input clock stabilizes, the second feedback loop subsequently stabilizes. During this process, either the digital PLL or the second analog PLL can be reset and its parameters reconfigured as needed to obtain any desired results or to verify specific parameters and ideas. After the reset or configuration is complete, the second feedback loop will gradually stabilize, and the control word sequence output by the digital PLL will also stabilize.

[0087] The phase-locked loop (PLL) control method provided in this invention provides a feedback loop formed by the digital PLL and the second analog PLL when the PLL is in a holding state. This can simulate the feedback loop established between the digital PLL and the first analog PLL under normal conditions without affecting the overall output of the PLL. This method can solve the unstable state of the PLL before the feedback loop re-stabilizes when the complex PLL exits the holding state, thus ensuring the overall stability of the PLL without interruption.

[0088] In an example embodiment of the present invention, when the phase-locked loop is in a holding state, the input clock and / or the state inside the phase-locked loop are detected to obtain a second detection result;

[0089] When the second detection result is normal, the locking signal is set to valid, causing the phase-locked loop to exit the holding state and enter the normal working state. In the normal working state, the control word received by the first analog phase-locked loop is the control word output by the digital phase-locked loop, and the feedback clock received by the digital phase-locked loop is the first clock.

[0090] Once the feedback loop in the hold state stabilizes, the entire PLL system can exit the hold state at any time as needed. When exiting the hold state, the latch control circuit selects the control word sequence directly output by the digital PLL from the latched control word sequence, and the first selector synchronously switches to the output of the first analog PLL as the feedback input of the digital PLL. Since the outputs of the first and second analog PLLs have the same frequency and phase, the first feedback loop immediately enters loop closure, thus achieving continuous and stable overall clock output for the PLL.

[0091] If the first test result indicates that the status is normal, the lock signal is kept valid, allowing the phase-locked loop to continue operating normally.

[0092] Under normal conditions, the input clock outputs a control word sequence through the digital phase-locked loop (PDL), which then feeds the control word sequence to the first analog phase-locked loop (PLL). The first analog PLL, based on the control word and the reference clock, controls its internal voltage-controlled oscillator (VCO) to generate a high-frequency clock. This high-frequency clock is then divided to obtain the locked clock, which is then fed back to the DLL via a first selector, forming the first feedback loop. Therefore, under normal operating conditions, the first feedback loop is established between the DLL and the first analog PLL.

[0093] Under normal conditions, the latch control circuit periodically samples the control word of the latched digital phase-locked loop. The multiple samples of the control word form a control word sequence, which the latch control circuit stores locally.

[0094] In one exemplary embodiment of the present invention, it may further include:

[0095] When the second detection result indicates an abnormal state, the lockout signal is invalidated, allowing the phase-locked loop to remain in the hold state.

[0096] After the phase-locked loop (PLL) is in a hold state, the first selector selects the output of the second analog PLL and sends it to the digital PLL as feedback input. At this point, a second feedback loop is formed between the digital PLL and the second analog PLL. This loop responds to changes in the input clock, and once the input clock stabilizes, the second feedback loop subsequently stabilizes. During this process, either the digital PLL or the second analog PLL can be reset and its parameters reconfigured as needed to obtain any desired results or to verify specific parameters and ideas. After the reset or configuration is complete, the second feedback loop will gradually stabilize, and the control word sequence output by the digital PLL will also stabilize.

[0097] In an exemplary embodiment of the present invention, when the phase-locked loop is in a holding state, detecting the input clock and / or the state inside the phase-locked loop to obtain a second detection result may include:

[0098] When the phase-locked loop is in hold state, it detects whether the state of the input clock is normal, and whether the feedback loop composed of the second analog phase-locked loop, the first selector and the digital phase-locked loop has entered a stable state.

[0099] When the input clock is in a normal state and the feedback loop has entered a stable state, the second detection result is determined to be in a normal state.

[0100] If the input clock is in an abnormal state and the feedback loop has not entered a stable state, the second detection result is determined to be an abnormal state.

[0101] After the entire phase-locked loop (PLL) is in the hold state, the first selector selects the output of the second analog PLL and sends it to the digital PLL as feedback input. At this time, a second feedback loop is formed between the digital PLL and the second analog PLL. This loop responds to changes in the input clock. After the input clock stabilizes, the feedback loop also stabilizes. When the input clock is normal and the feedback loop reaches a stable state, the second detection result is determined to be normal, and the hold state can be exited. When the input clock is abnormal and the feedback loop has not reached a stable state, the second detection result is determined to be abnormal, and the hold state continues.

[0102] The stable state mainly refers to the stability of the feedback loop. After the input clock stabilizes again or becomes normal, the feedback loop subsequently stabilizes.

[0103] To determine whether a phase-locked loop (PLL) is exiting the holding state, it first needs to check if the PLL frequency and phase locking conditions are met. Additionally, the PLL lockout indicator switch must be on. Once the PLL frequency and phase locking conditions are met and the PLL lockout indicator switch is on, the PLL can exit the holding state via the PLL lockout indicator. If the PLL lockout indicator is configured with a delay, the PLL will exit the holding state once the delay condition is met.

[0104] Figure 5 A flowchart of a phase-locked loop control method provided in another exemplary embodiment of the present invention is shown below. Figure 5 As shown, the control method for a phase-locked loop may include:

[0105] S501: Detect the status of the phase-locked loop (PLL). If the PLL is in normal working condition, execute S502; if the PLL is in an abnormal state, execute S506.

[0106] S502: Detects the state of the input clock and / or the internal state of the phase-locked loop to obtain the first detection result.

[0107] When the phase-locked loop is in normal working condition, the input clock and / or the state inside the phase-locked loop are detected to obtain the first detection result.

[0108] S503: Determine whether the first detection result is abnormal; if yes, execute S504; otherwise, execute S505.

[0109] S504: Invalidate the lock signal, the phase-locked loop enters the holding state, and execute S501.

[0110] When the first detection result is an abnormal state, the locking signal is set to invalid, and the phase-locked loop enters the holding state. In the holding state, the control word received by the first analog phase-locked loop is the latched control word, and the feedback clock received by the digital phase-locked loop is the second clock.

[0111] S505: Maintain the lockout signal as valid to keep the phase-locked loop in normal working condition, and execute S501.

[0112] If the first test result indicates that the status is normal, the lock signal is kept valid, allowing the phase-locked loop to continue operating normally.

[0113] S506: Detect the state of the input clock and / or the internal state of the phase-locked loop to obtain a second detection result.

[0114] When the phase-locked loop is in hold state, the input clock and / or the state inside the phase-locked loop are detected to obtain a second detection result.

[0115] S507: Determine whether the second detection result is normal; if yes, proceed to S508; otherwise, proceed to S509.

[0116] S508: Set the lock signal to active, causing the phase-locked loop to exit the holding state and enter the normal working state. Execute S501.

[0117] When the second detection result is normal, the locking signal is set to valid, causing the phase-locked loop to exit the holding state and enter the normal working state. In the normal working state, the control word received by the first analog phase-locked loop is the control word output by the digital phase-locked loop, and the feedback clock received by the digital phase-locked loop is the first clock.

[0118] S509: The lock signal is kept invalid, so that the phase-locked loop continues to be in the hold state, and S501 is executed.

[0119] When the second detection result indicates an abnormal state, the lockout signal is invalidated, allowing the phase-locked loop to remain in the hold state.

[0120] It will be understood by those skilled in the art that all or some of the steps, systems, or apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

Claims

1. A phase-locked loop, characterized by include: A digital phase-locked loop is configured to receive an input clock and a feedback clock, and output a control word. The latching control circuit is configured to receive the control word output by the digital phase-locked loop, latch the received control word and output the received control word when the latching signal is valid, and output the latched control word when the latching signal is invalid. The first analog phase-locked loop is configured to receive a reference clock and the control word output by the latch control circuit, and output a first clock after locking, which is the output of the entire phase-locked loop. The second analog phase-locked loop is configured to receive the reference clock and the control word output by the digital phase-locked loop, and output the locked second clock. A first selector is configured to receive a first clock and a second clock, output the first clock as the feedback clock when the lock signal is valid, and output the second clock as the feedback clock when the lock signal is invalid. Wherein, when the input reference clock and control word are the same, the first clock and the second clock output by the second analog phase-locked loop and the first analog phase-locked loop have the same frequency and the phase difference is within a preset difference range. The latch control circuit includes: The latch is configured to receive and sample the control word output by the digital phase-locked loop when the lock signal is valid, and to stop sampling and latching the control word output by the digital phase-locked loop when the lock signal is invalid. The second selector is configured to receive the control word output by the digital phase-locked loop and the control word of the latch, output the received control word when the latching signal is valid, and output the latching control word when the latching signal is invalid.

2. The phase-locked loop as described in claim 1, characterized in that: The phase-locked loop also includes a detection circuit; The detection circuit is configured to detect the state of the input clock and / or the internal state of the phase-locked loop, and output the locking signal; wherein, when the detection result is an abnormal state, an invalid locking signal is output, and when the detection result is a normal state, a valid locking signal is output.

3. The phase-locked loop as described in claim 2, characterized in that: The detection circuit is integrated into the digital phase-locked loop.

4. The phase-locked loop as described in claim 1, characterized in that the first selector and the second selector are both two-to-one selectors.

5. A control method of a phase-locked loop, applied to the phase-locked loop according to any one of claims 1 to 4, characterized in that, The control method includes: When the phase-locked loop is in normal working condition, the input clock and / or the state inside the phase-locked loop are detected to obtain a first detection result; When the first detection result is an abnormal state, the locking signal is set to invalid, and the phase-locked loop enters a holding state; in the holding state, the control word received by the first analog phase-locked loop is the control word of the latch, and the feedback clock received by the digital phase-locked loop is the second clock; When the phase-locked loop is in a holding state, the input clock and / or the state inside the phase-locked loop are detected to obtain a second detection result; When the second detection result is normal, the locking signal is set to valid, causing the phase-locked loop to exit the holding state and enter the normal working state; in the normal working state, the control word received by the first analog phase-locked loop is the control word output by the digital phase-locked loop, and the feedback clock received by the digital phase-locked loop is the first clock.

6. The control method according to claim 5, characterized by, Also includes: When the first detection result indicates that the state is normal, the locking signal is kept valid, so that the phase-locked loop continues to be in normal working state. When the second detection result indicates an abnormal state, the locking signal is kept invalid, so that the phase-locked loop continues to be in a hold state.

7. The control method as described in claim 5, characterized in that, When the phase-locked loop is in a hold state, the process of detecting the input clock and / or the state inside the phase-locked loop to obtain a second detection result includes: When the phase-locked loop is in the hold state, it is detected whether the state of the input clock is normal, and whether the feedback loop composed of the second analog phase-locked loop, the first selector and the digital phase-locked loop has entered a stable state; When the input clock is in a normal state and the feedback loop enters a stable state, the second detection result is determined to be in a normal state. When the state of the input clock is abnormal and the feedback loop has not entered a stable state, the second detection result is determined to be abnormal.

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