Tier-based media management operations in a memory device

Abstract

Systems and methods are disclosed that include a processing device operatively coupled to a memory device. The processing device performs operations including receiving a memory access command specifying a logical address; determining a physical address associated with the logical address; determining a portion of the memory device referenced by the physical address; determining a durability factor associated with the portion; and causing a media management metric associated with a management unit of the memory device to be increased by a value derived from the durability factor, where the management unit is referenced by the physical address.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to memory subsystems, and more specifically, to improving memory performance using deck-based media management operations in a memory device. Background Technology

[0002] A memory subsystem may include one or more memory devices for storing data. Memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize a memory subsystem to store data at memory devices and retrieve data from memory devices. Summary of the Invention Attached Figure Description

[0003] This disclosure will be more fully understood in light of the detailed description provided below and the accompanying drawings of various embodiments thereof.

[0004] Figure 1 This describes an example computing system including a memory subsystem according to some embodiments of the present disclosure.

[0005] Figure 2 This is a flowchart of an example method for performing media management operations according to some embodiments of the present disclosure.

[0006] Figure 3 An instance layer maintained by a memory device is illustrated schematically according to some embodiments of the present disclosure.

[0007] Figure 4 The instance metadata maintained by the memory subsystem controller is illustrated schematically according to some embodiments of the present disclosure.

[0008] Figure 5 This is a block diagram of an example computer system in which embodiments of the present disclosure can be operated. Detailed Implementation

[0009] This disclosure pertains to performing layer-based media management operations in a memory device. The memory subsystem may be a storage device, a memory module, or a combination of a storage device and a memory module. The following description, in conjunction with… Figure 1 Describe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem that includes one or more components, such as a memory device for storing data. The host system can provide data to be stored in the memory subsystem and can request to retrieve data from the memory subsystem.

[0010] The memory subsystem may contain high-density non-volatile memory devices, where data retention is required when no power is supplied to the memory devices. An example of a non-volatile memory device is a NAND flash memory device. The following section combines... Figure 1 Other examples of non-volatile memory devices are described. A non-volatile memory device is a package of one or more dies. Each die may contain two or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane contains a collection of physical blocks. In some embodiments, each block may contain multiple sub-blocks. Each plane carries a matrix of memory cells formed on a silicon wafer and connected by conductors called word lines and bit lines, such that word lines connect multiple memory cells forming rows of the memory cell matrix, while bit lines connect multiple memory cells forming columns of the memory cell matrix.

[0011] Depending on the cell type, each memory cell can store one or more bits of binary information and has various logical states associated with the number of bits being stored. Logical states can be represented by binary values ​​(e.g., "0" and "1" or combinations thereof). A set of memory cells called a memory page can be programmed in a single operation, for example, by selecting consecutive bit lines together.

[0012] Individual segments, data units, or blocks of a memory device can only be written to, read from, and / or erased a limited number of times before physical wear and tear causes the memory device to fail. To counteract this limited endurance of memory devices, techniques for managing wear and tear on memory devices have been developed. One technique for managing endurance is media management, such as wear leveling. Wear leveling operations attempt to distribute data operations (e.g., read, write, and erase operations) evenly across the memory device, and thus evenly distribute the corresponding physical wear and tear. A memory device can be divided into multiple management units (MUs), such as pages or blocks of the memory device, each of which experiences physical wear and tear. A MU can be a group of pages spanning a die and / or channel. A MU can represent an individual segment of the memory device that can be written to or erased in a single operation. Write counts (e.g., the number of write operations performed on a MU to write data to a MU during its lifetime), read counts (e.g., the number of read operations performed on a MU to read data from a MU during its lifetime), or erase counts (e.g., the number of erase operations performed on a MU to erase data from a MU during its lifetime) can be strong indicators of wear and tear on a MU of a memory device. Therefore, some wear leveling techniques use a sorting process to identify MUs with high read or write counts and MUs with low read or write counts. Data from MUs with high read or write counts can be exchanged with data from MUs with low read or write counts in an attempt to distribute wear evenly across the MUs of the memory device.

[0013] For example, some memory devices, such as three-dimensional (3D) intersection devices, may comprise multiple sections. For instance, a layer or layer can be defined as an array of two-dimensional (2D) memory cells electronically addressable via vertical access lines. Multiple layers can be stacked within the memory device (e.g., vertically stacked). Each layer may have its own distinct durability level. As discussed above, durability can reflect the expected number of times a layer can be written to, read from, and / or erased before physical wear causes it to fail. For example, in a two-level memory device, one layer may fail after approximately eight million program / erase cycles (PECs), while another layer may fail after approximately four million PECs. If one layer in a multi-level memory device fails, the entire memory device may fail.

[0014] Therefore, wear leveling operations may underutilize layers with relatively high durability while overutilizing layers with relatively low durability. This could reduce the lifespan of the memory device because layers with relatively low durability can trigger the failure of the entire memory device.

[0015] This disclosure addresses the above and other deficiencies by implementing layer-based media management operations in the memory device. In some embodiments, the memory subsystem controller may implement media management metrics for each MU at each layer of the memory device. Media management metrics can be calculated using any combination of MU write counts, MU read counts, MU erase counts, layer durability factors, read factors, etc. MU write counts may reflect the number of write operations performed on the MU during its lifetime. MU read counts may reflect the amount of read operations performed on the MU during its lifetime. MU erase counts may reflect the amount of erase operations performed on the MU during its lifetime. The read factor may be a weighted value used to normalize (e.g., adjust counts measured on different scales to a common scale) the write count or read count. The layer durability factor may reflect the planned durability of the layer. The memory subsystem controller may use a memory management scheme in which a higher layer durability factor reduces the frequency at which the media management metric increases in response to each memory access command, or reduces the value by which the media management metric increases in response to each memory access command. Layer durability values ​​can be predetermined values ​​that reflect statistical data and analytical results related to the manufacturing process of a memory device, the performance of other memory devices manufactured under similar conditions, or any other measure related to the manufacturing, inspection, testing, or performance of a memory device.

[0016] In some embodiments, the memory subsystem controller may determine whether a media management metric used for the MU meets a threshold criterion. For example, the memory subsystem controller may determine whether the value of the media management metric exceeds a predetermined threshold. The predetermined threshold may be set during the manufacturing and / or calibration of the memory subsystem. In response to a media management metric exceeding the predetermined threshold, the memory subsystem controller may perform a media management operation to relocate data stored at the MU to a different MU.

[0017] The advantages of this disclosure include, but are not limited to, improved and longer lifespan of the memory device. For example, layer-based media management metrics can distribute data operations across multiple layers based on the expected durability of each layer. This allows the memory subsystem to extend the lifespan of the memory device by preventing a single layer from reaching its failure point before other layers on the memory device are nearing the end of their lifespan. Therefore, embodiments of this disclosure improve the performance and durability of the memory device by balancing the physical wear and tear of layers based on their durability.

[0018] Figure 1 This description describes an example computing system 100 including a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of the like.

[0019] The memory subsystem 110 may be a storage device, a memory module, or a combination of both. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small form factor DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0020] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), Internet of Things (IoT) enabled device, embedded computer (e.g., computer contained in a vehicle, industrial equipment or networked commercially available device), or such computing device that includes memory and processing power.

[0021] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1 This describes an example of a host system 120 coupled to a memory subsystem 110. As used herein, “coupled to…” or “coupled with…” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intervening component), whether wired or wireless, including connections such as electrical, optical, and magnetic connections.

[0022] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120 uses, for example, memory subsystem 110 to write data to and read data from memory subsystem 110.

[0023] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Dual Data Rate (DDR) memory bus, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM sockets supporting Dual Data Rate (DDR)), etc. The physical host interface can be used to transmit data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a physical host interface (e.g., a PCIe bus), host system 120 can further utilize an NVM High Speed ​​(NVMe) interface to access memory components (e.g., memory device 130). The physical host interface provides an interface for transmitting control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1 The memory subsystem 110 is described as an example. Generally, the host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0024] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0025] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND flash memory and in-place write memory, such as three-dimensional cross-point ("3D cross-point") memory devices, which are cross-point arrays of non-volatile memory cells. The cross-point array of non-volatile memory can be combined with a stackable cross-grid data access array to perform bit storage based on changes in volume resistance. Furthermore, compared to many flash-based memories, cross-point non-volatile memory can perform in-place write operations, where non-volatile memory cells can be programmed without pre-erasing them. NAND flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0026] Each of the memory devices 130 may contain one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells (e.g., multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC)) may store multiple bits per cell. In some embodiments, each memory device 130 may contain one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, PLC, or any combination thereof. In some embodiments, a particular memory device may contain an SLC portion, an MLC portion, a TLC portion, a QLC portion, or a PLC portion of memory cells. The memory cells of the memory device 130 may be grouped into pages, which may refer to logical units of the memory device used to store data. For some types of memory (e.g., NAND), pages may be grouped to form blocks. Some types of memory (e.g., 3D cross-connect) may group pages across the die and channels to form management units (MUs). A MU is an instance of a data unit. A Super Management Unit (SMU) is another instance of a data unit and can contain a group of multiple MUs (e.g., 1000 MUs, 2000 MUs, etc.).

[0027] The memory device 130 may include one or more layers. A layer may be defined as an array of memory cells having conductive access lines. Multiple layers may be stacked within the memory device 130. Each layer may have its own different durability level (e.g., an indication of approximately how many times the layer can be written to, read from, and / or erased before physical wear causes the layer to fail).

[0028] While non-volatile memory components, such as 3D cross-point non-volatile memory cell arrays and NAND flash memories (e.g., 2D NAND, 3D NAND), are described, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0029] The memory subsystem controller 115 (or simply controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, or erasing data at the memory device 130, and other such operations. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system with dedicated (i.e., hard-decoded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0030] The memory subsystem controller 115 may be a processing device that includes one or more processors (e.g., processor 117) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logical flows, and routines that control the operation of the memory subsystem 110, including handling communication between the memory subsystem 110 and the host system 120.

[0031] In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes an embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110 (including handling communication between the memory subsystem 110 and the host system 120).

[0032] In some embodiments, local memory 119 may include memory registers storing memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although in Figure 1 The instance memory subsystem 110 has been described as including a memory subsystem controller 115, but in another embodiment of this disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but instead may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0033] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can translate these commands or operations into instructions or appropriate commands to enable the desired access to the memory device 130. The memory subsystem controller 115 may be responsible for other operations, such as media management operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, caching operations, and address translation between logical addresses (e.g., logical block addresses (LBAs), namespaces) and physical addresses (e.g., physical MU addresses, physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may additionally include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into instructions for accessing the memory device 130, and translate responses associated with the memory device 130 into information for the host system 120.

[0034] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and an address circuitry (e.g., row decoder and column decoder) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0035] In some embodiments, memory device 130 includes a local media controller 135, which operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory system controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory subsystem 110 is a managed memory device that includes a raw memory device 130 having on-die control logic (e.g., local controller 132) and a controller (e.g., memory subsystem controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0036] The memory subsystem 110 includes a media management component 113 that can be used to perform media management operations based on layer durability metrics for each layer of the memory device 130. In some embodiments, the memory subsystem controller 115 includes at least a portion of the media management component 113. In some embodiments, the media management component 113 is part of the host system 110, an application, or an operating system. In other embodiments, the local media controller 135 includes at least a portion of the media management component 113 and is configured to perform the functionality described herein.

[0037] Media management component 113 can perform wear leveling based on media management metrics. Media management metrics can reflect the wear level experienced by a MU or SMU and can be used to determine whether data should be moved from one MU (or SMU) to another. For example, media management component 113 can maintain a media management metric for each MU of the memory device. For example, media management component 113 can maintain a data structure (e.g., a metadata table) consisting of multiple records, where each record associates a MU (via a MU identifier) ​​with a corresponding media management metric value. Figure 4 An example of a metadata table is shown below.

[0038] Media management component 113 can then determine whether the media management metric used for the MU meets a threshold criterion. For example, media management component 113 can determine whether the value of the media management metric exceeds a predetermined threshold. The predetermined threshold can be set during the manufacturing and / or calibration of memory subsystem 110. In response to a media management metric exceeding the predetermined threshold, media management component 113 can perform a media management operation to relocate the data stored at the MU to a different MU.

[0039] In some embodiments, media management operations include copying data from the MU to an available physical location on the memory device 130 via media management component 113. This available physical location may be selected as, for example, the physical location with the lowest write count, the least recently accessed physical location, etc. A list of available physical locations may be maintained in a free pool stored in local memory 119. After copying the data, media management component 113 immediately records a mapping of the logical address associated with the data from the MU to an available physical address in a lookup table. In one embodiment, the lookup table is maintained in local memory 119 of the memory subsystem controller 115. Therefore, when the memory subsystem controller 115 applies a logical address to the lookup table, the corresponding physical address is output. In other embodiments, the mapping may be maintained in another type of data structure (e.g., an array, a linked list, etc.).

[0040] In some embodiments, media management metrics may be based on media management metric schemes, such as layer-dependent write schemes, layer-dependent write and read schemes, or any other scheme based on write operations, read operations, and / or erase operations. In some embodiments, a layer-dependent write-only scheme may be expressed as the ratio of MU write count to a layer durability factor (e.g., [MU write count] / [layer durability factor]). In some embodiments, a layer-dependent write and read scheme may be expressed as the MU read count divided by the sum between the read factor and the MU write count, wherein the sum is divided by the layer durability factor (e.g., ([MU write count] + ([MU read count] / [read factor])) / [layer durability factor]). In other embodiments, a layer-dependent write and read scheme may be expressed as the ratio of MU write count to a layer durability write factor plus the ratio of MU read count to a layer durability read factor (e.g., ([MU write count] / [layer durability write factor]) + ([MU read count] / [layer durability read factor])).

[0041] The MU write count reflects the number of write operations performed on the MU during its lifetime. For example, the media management component 113 can track the write operations performed on each MU. For each write operation performed on a MU, the media management component 113 can increment the MU write counter by 1.

[0042] The MU read count reflects the amount of read operations performed on the MU during its lifetime. For example, the media management component 113 can track the read operations performed on each MU. For each read operation performed on a MU, the media management component 113 can increment the MU read counter by 1.

[0043] The physical loss on the MU caused by a read operation may be less than the physical loss caused by a write operation. To combine the read and write counts of the MU, the read or write counts of the MU can be normalized (e.g., adjusted to a common scale) by weighting the write or read counts. In some embodiments, the read factor may reflect the weight of a read operation relative to a write operation. The weight of a read operation relative to a write operation may be determined and set during the manufacture of the memory subsystem 110 or during the programming and / or calibration of the memory subsystem 110. Thus, the read factor enables the media management component 113 to adjust the magnitude of the effect of each read operation on the media management metric. For example, a read factor of 64 means that 64 read operations are weighted the same as a single write operation. In some embodiments, the read factor may be 16, 32, 64, 128, 256, or any other value. In some embodiments, the read factor may be set to a different value for each layer. The read factor for each layer may be determined and set during the manufacture of the memory subsystem 110 or during the programming and / or calibration of the memory subsystem 110. The read factor reflects the ratio of the overhead caused by a specific number of read commands to the overhead caused by a specific number of write commands.

[0044] A layer durability factor reflects the planned durability of a layer. In an exemplary instance, one of four values ​​(1, 2, 4, and 8) may be assigned to each layer of memory device 130. Each of the four values ​​may be associated with a layer durability metric, where value 1 indicates a baseline durability level, value 2 indicates a durability level stronger than that indicated by value 1, value 4 indicates a durability level stronger than that indicated by value 2, and value 8 indicates a durability level stronger than that indicated by value 4. Layer durability values ​​may be determined and set during the manufacture of memory subsystem 110 or during the programming and / or calibration of memory subsystem 110. Layer durability values ​​may reflect statistical data and analytical results related to the manufacturing process, the performance of other memory subsystems manufactured under similar conditions, the historical error rate of the relevant memory subsystem, or any other metric or parameter related to the manufacture, inspection, testing, or performance of memory subsystem 110.

[0045] In some embodiments, the media management scheme may use different layer durability factors for different types of memory access commands. For example, the media management metric scheme may use one value for write commands (e.g., layer durability write factor), another value for read commands (layer durability read factor), and yet another value for erase commands (layer durability erase factor).

[0046] As an illustrative example, using a layer-dependent write-only scheme and employing MUs, for each MU, the media management component 113 may increment the MU write operation counter by one for each write operation performed on the MU. The media management metric for the MU may be equal to the MU write operation counter divided by the layer durability factor. The wear leveling component 113 may compare the media management metric with a predetermined threshold. This comparison may be performed periodically by the wear leveling component 113, after each write operation, etc. In response to the media management metric exceeding the predetermined threshold, the media management component 113 may perform a media management operation to relocate the data stored at the MU to a different MU.

[0047] As an illustrative example, using a layer-dependent write and write scheme, for each MU, the media management component 113 may increment the MU write operation counter by one for each write operation performed on the MU, and increment the read operation counter by one divided by the read factor for each read operation performed on the MU. The media management metric for the MU may be equal to the sum of the MU write operation counter and the MU read operation counter divided by the layer durability factor. The wear leveling component 113 may compare the media management metric with a predetermined threshold. In response to the media management metric exceeding the predetermined threshold, the media management component 113 may perform a media management operation to relocate the data stored at the MU to a different MU.

[0048] In some embodiments, for each received write command, the media management component 113 may determine the layer durability factor of the layer referenced by the physical address of the write command. In response to a layer durability factor of one, the media management component 113 may increment the media management metric by one. In response to a layer durability factor greater than one (value m), the media management component 113 may generate a random number within a specified range (e.g., between 0 or 1 and N). In response to the random number failing to exceed the ratio of N to m (e.g., N / m), the media management metric is incremented by one. The table may contain multiple records, such that each record indicates a specified range for each layer durability factor. The specified range may be determined and set during the manufacture of the memory subsystem 110 or during the programming and / or calibration of the memory subsystem 110. The specified range may be used to normalize (e.g., adjust to a common scale) the incremental increase of the media management metric by a weighted write count that varies with the layer durability factor. For example, a layer durability factor 2 may indicate that the layer can withstand twice the PEC compared to a layer with a layer durability factor 1. Within the specified range of 1-N, N can be set to the value 4. Therefore, in response to the random number generator generating a value of 1 or 2, the media management component 113 will increase the media management metric by a value of 1 (1 and 2 do not exceed the N / m value 2). In response to the random number generator generating a value of 3 or 4, the media management component 113 will not increase the media management metric (3 and 4 exceed the N / m value 2).

[0049] In some embodiments, for each received read command, the media management component 113 may determine the layer durability factor of the layer referenced by the physical address translated from the logical address of the read command. In response to the product of the layer durability factor and the read factor being 1, the media management component 113 may increment the media management metric by 1. In response to the product of the layer durability factor and the read factor being greater than one (value m), for each read command on the layer, the media management component 113 may generate a random number within a specified range (e.g., between 0 or 1 and N). In response to the random number failing to exceed N / m, the media management metric is incremented by one.

[0050] In some embodiments, media management metrics may be determined based on write operations, read operations, erase operations, layer durability factors, read factors, or any combination thereof. In schemes utilizing erase operations, an erase counter may reflect the number of erase operations performed on the MU during its lifetime (erased data of the MU). An erase factor may reflect the weight of erase operations relative to write and / or read operations.

[0051] Figure 2 This is a flowchart illustrating an example method 200 of a process performed for media management operations according to some embodiments of the present disclosure. Method 200 may be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 200 is performed by… Figure 1 The wear leveling component 113 performs the operation. Although shown in a specific order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in each embodiment. Other process flows are also possible.

[0052] At operation 210, the processing logic can receive memory access commands for a specified logical address. For example, the processing logic can receive write commands, read commands, erase commands, etc.

[0053] At operation 220, the processing logic may determine the physical address associated with the logical address. In some embodiments, the physical address may reside in the address space of the layer.

[0054] At operation 230, the processing logic can determine the portion of the memory device referenced by a physical address. For example, the processing logic can use a table to determine which part (e.g., layer) of the memory device contains the address space.

[0055] At operation 240, the processing logic may determine the durability factor associated with the portion. For example, the processing logic may use a data structure (e.g., a metadata table) to look up the durability factor at the layer.

[0056] At operation 250, the processing logic may increase a media management metric associated with a management unit of the memory device by a value derived from a durability factor. The management unit may be referenced by a physical address. In some embodiments, the processing logic may use a media management scheme to determine whether to increase the media management metric, by how much, or any combination thereof. For example, the processing logic may generate a value that varies with the durability factor and, in response to the value satisfying a threshold criterion, increase the media management metric associated with the physical address. The value may be generated by generating a random number within a specified range and determining whether the random number exceeds a function of the random number and the durability factor.

[0057] In some embodiments, in response to determining that a media management metric meets a criterion, a media management operation is performed with respect to data located in an address space associated with a physical address. For example, the media management operation may include processing logic writing data stored in the address space associated with the physical address to a new address space at a different physical address. The different physical address may be selected as, for example, a physical address with the lowest write count, a least recently accessed physical address, etc. The processing logic may then map the logical address to the different physical address.

[0058] Figure 3 The following schematically illustrates instance layers maintained by memory device 300 according to some embodiments of the present disclosure. Memory device 300 may be similar to memory 130 and / or memory device 140. MU is an instance of a data unit. For example, MU may be a page (e.g., the smallest data unit that can be written to or read from a crosspoint array) of a non-volatile memory or block (e.g., the smallest erasable data unit in a flash-based memory) of flash memory. Super Management Unit (SMU) is another instance of a data unit and may contain a set of multiple management units (e.g., 1000 MUs, 2000 MUs, etc.).

[0059] Memory device 300 includes layers 310 and 320. Each layer 310, 320 may include multiple SMUs. As shown, layer 310 includes SMUs 315A to 315N, and layer 320 includes SMUs 325A to 325N. Each SMU may contain a fixed number of MUs. Media management component 113 may maintain media management metrics for each SMU of memory device 300. In response to performing a memory access operation on an SMU, media management component 113 may use one or more media management schemes of this disclosure to increase the media management metrics for the SMU.

[0060] Figure 4 The following schematically illustrates instance metadata maintained by a memory subsystem controller according to some embodiments of the present disclosure. In some embodiments, media management component 113 may maintain metadata table 400. In some embodiments, metadata table 400 may be stored in the memory of the memory subsystem (e.g., at memory devices 130, 140, local memory 119, etc.) and may be referenced by media management component 113 to determine media management metrics for a particular MU or SMU. Figure 4 As illustrated in the example, metadata table 400 maintains entries for each SMU in layers 310 and 320 related to media management metrics. Each SMU may contain an identifier. Media management component 113 may use one or more media management schemes of this disclosure to add media management metrics for the SMUs.

[0061] Figure 5 An example machine illustrating computer system 500 is described, capable of executing a set of instructions within said computer system 500 for causing said machine to perform any or more methods discussed herein. In some embodiments, computer system 500 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110) or can be used to perform controller operations (e.g., execute the operating system to perform operations corresponding to...). Figure 1 (Operation of media management component 113). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, operating at the capacity of a server or client machine in a client-server network environment.

[0062] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network appliance, server, network router, switch, or bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions specifying actions to be taken by the machine. Furthermore, although a single machine is described, the term "machine" should also be understood to include any set of machines that individually or collectively execute one or more sets of instructions to perform any one or more of the methods discussed herein.

[0063] The example computer system 500 includes a processing device 502, a main memory 504 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 506 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 518, which communicate with each other via a bus 530. The processing device 502 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, etc. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets, or a combination of instruction sets. The processing device 502 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. The processing device 502 is configured to execute instructions 526 to perform the operations and steps discussed herein. The computer system 500 may additionally include a network interface device 508 for communication on the network 520.

[0064] Data storage system 518 may include machine-readable storage medium 524 (also referred to as computer-readable medium) on which one or more instruction sets 526 or software embodying any or more of the methods or functions described herein are stored. Instructions 526 may also reside wholly or at least partially in main memory 504 and / or processing device 502 during execution by computer system 500, the main memory 504 and processing device 502 also constituting machine-readable storage medium. Machine-readable storage medium 524, data storage system 518 and / or main memory 504 may correspond to... Figure 1 The memory subsystem 110.

[0065] In one embodiment, instruction 526 includes instructions for implementing the corresponding Figure 1The media management component 113 provides functional instructions. Although the machine-readable storage medium 524 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any one or more of the methods disclosed herein. The term "machine-readable storage medium" should therefore be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0066] Some parts of the previously described algorithms and symbolic representations of operations on data bits within computer memory have been presented. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. In this document, and generally in general, an algorithm is conceived as a self-consistent sequence of operations that produce a desired result. An operation is an operation that requires physical manipulation of a physical quantity. Typically (but not always), these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has been shown that it is sometimes convenient to refer to these signals as bits, values, elements, symbols, characters, items, numbers, etc., primarily for common use.

[0067] However, it should be remembered that all these and similar terms will be associated with appropriate physical quantities and are merely convenient notations for application to those quantities. This disclosure can refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities in the registers and memories of a computer system into other data similarly represented as physical quantities in the computer system's memory or registers or other such information storage systems.

[0068] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for the desired purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such computer programs may be stored in computer-readable storage media, such as, but not limited to, any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards, or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0069] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may prove convenient to construct more specialized devices to perform the methods described herein. The structures of various such systems will be presented as illustrated in the description below. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that the teachings of this disclosure as described herein can be implemented using various programming languages.

[0070] This disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon for programming a computer system (or other electronic device) to perform processes according to this disclosure. Machine-readable media includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. For example, machine-readable (e.g., computer-readable) media includes machine-readable (e.g., computer-readable) storage media such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory devices, etc.

[0071] In the foregoing description, embodiments of this disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to this disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than restrictive sense.

Claims

1. A system comprising: Memory devices; and A processing device operatively coupled to the memory device to perform operations including the following: Receive memory access commands for a specified logical address; Determine the physical address associated with the logical address; Determine the portion of the memory device referenced by the physical address; Determine the durability factor associated with the aforementioned portion; and Increase the media management metric associated with the management unit of the memory device by a value derived from the durability factor, wherein a higher durability factor results in a smaller increase in the value of the media management metric, and wherein the management unit is referenced by the physical address; and In response to determining that the value of the media management metric satisfies a criterion, a media management operation is performed with respect to the location of the memory device, wherein the location is identified by the physical address.

2. The system of claim 1, wherein the media management operation includes writing data stored in an address space associated with the physical address to a new address space of a different physical address.

3. The system of claim 2, wherein the processing device further performs operations including the following: Map the logical address to the different physical addresses.

4. The system of claim 2, wherein the different physical addresses are associated with a management unit including the lowest write count.

5. The system of claim 1, wherein the processing device further performs operations including the following: Receive read command; and Based on the value generated using the durability factor and the read factor associated with the weight of read operations relative to write operations, a media management metric associated with the physical address is increased.

6. The system of claim 1, wherein the processing device further performs operations including the following: Receive erase command; and Based on the value generated using the durability factor and the erase factor associated with the weight of an erase operation relative to at least one of a write or read operation, a media management metric associated with the physical address is increased.

7. A method comprising: The processor receives a memory access command for a specified logical address. Determine the physical address associated with the logical address; Determine the portion of the memory device referenced by the physical address; Determine the durability factor associated with the aforementioned portion; This produces a value that varies with the durability factor, and In response to the value satisfying a threshold criterion, the media management metric associated with the management unit of the memory device is increased, wherein a higher durability factor results in a smaller increase in the value of the media management metric, and wherein the management unit is referenced by the physical address; and In response to determining that the value of the media management metric satisfies a criterion, a media management operation is performed with respect to the location of the memory device, wherein the location is identified by the physical address.

8. The method of claim 7, wherein generating the value that varies with the durability factor comprises: Generate random numbers within a specified range; and Determine whether the random number exceeds another function of the random number and the durability factor.

9. The method of claim 7, wherein the media management operation includes writing data stored in an address space associated with the physical address to a new address space of a different physical address.

10. The method of claim 9, wherein the different physical address is associated with a management unit including the lowest write count.

11. The method of claim 7, further comprising: Receive read command; A new value is generated that varies with the durability factor and a read factor is associated with the weight of the read operation relative to the write operation; and In response to the new value satisfying the threshold criterion, the media management metric associated with the physical address is increased.

12. The method of claim 7, further comprising: Receive erase command; A new value is generated that varies with the durability factor and an erase factor is associated with the weight of the erase operation relative to at least one of the write or read operations; and In response to the new value satisfying the threshold criterion, the media management metric associated with the physical address is increased.

13. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing means operatively coupled to a memory device, perform operations including: Receive memory access commands for a specified logical address; Determine the physical address associated with the logical address; Determine the portion of the memory device referenced by the physical address; Determine the durability factor associated with the aforementioned portion; and Increase the media management metric associated with the management unit of the memory device by a value derived from the durability factor, wherein a higher durability factor results in a smaller increase in the value of the media management metric, and wherein the management unit is referenced by the physical address; and In response to determining that the value of the media management metric satisfies a criterion, a media management operation is performed with respect to the location of the memory device, wherein the location is identified by the physical address.

14. The non-transitory computer-readable storage medium of claim 13, wherein the media management operation includes writing data stored in an address space associated with the physical address to a new address space of a different physical address.

15. The non-transitory computer-readable storage medium of claim 14, wherein the distinct physical address is associated with a management unit including a minimum write count.

16. The non-transitory computer-readable storage medium of claim 13, wherein the processing means further performs operations including: Receive read command; and Based on the value generated using the durability factor and the read factor associated with the weight of read operations relative to write operations, a media management metric associated with the physical address is increased.

17. The non-transitory computer-readable storage medium of claim 13, wherein the processing means further performs operations including: Receive erase command; and Based on the value generated using the durability factor and the erase factor associated with the weight of an erase operation relative to at least one of a write or read operation, a media management metric associated with the physical address is increased.

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