Setting switching for single-level cells

Abstract

This disclosure relates to set switching for single level cell (SLC). A memory system can receive an access command from a host. The access command can correspond to an SLC block or a multi-level cell block. If the access command corresponds to an SLC block, the memory system can modify the access command to include one or more bits indicating a set for performing the access operation corresponding to the access command. The set can define one or more operating parameters for performing the access operation. The memory system can use a bit to indicate the set for indicating a page address of a multi-level cell block. The memory system can issue the access command to a memory device, which can perform the access operation using the set indicated in the one or more bits included by the memory system.

Description

[0001] Cross-references

[0002] This patent application claims priority to U.S. Patent Application No. 17 / 736,902, filed May 4, 2022, entitled “Setting Switching for Single-Level Cells,” and U.S. Provisional Patent Application No. 63 / 211,341, filed June 16, 2021, entitled “Setting Switching for Single-Level Cells,” each of which is assigned to the assignee and each of which is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field relates to setting switching for single-level units. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices such as computers, user devices, cameras, and digital displays. Information is stored by programming memory cells within the memory device to various states. For example, a binary memory cell can be programmed to one of two supported states, typically corresponding to logic 1 or logic 0. In some instances, a single memory cell can support more than two possible states, either of which can be stored by the memory cell. To access the information stored by the memory device, a component can read or sense the state of one or more memory cells within the memory device. To store information, a component can write or program one or more memory cells within the memory device to corresponding states.

[0005] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), 3D crosspoint memory, NOR (Non-OR), and NAND (NAND) memory devices. Memory devices can be volatile or non-volatile. Volatile memory cells (e.g., DRAM cells) may lose their programmed state over time unless periodically refreshed by an external power supply. Non-volatile memory cells (e.g., NAND memory cells) can maintain their programmed state for a long period of time even without an external power supply. Summary of the Invention

[0006] Describe an apparatus. The apparatus may include a memory device and a controller, the controller being coupled to the memory device and configured to cause the apparatus to: receive an access command for the memory device from a host system; determine whether the access command corresponds to a single-level cell of the memory device; modify the access command, at least in part based on the determination that the access command corresponds to the single-level cell, to include one or more bits indicating settings for accessing one or more memory cells of the single-level cell block; and, based on the modification, issue the access command to the memory device including the one or more bits indicating the settings for the single-level cell block.

[0007] Describe an apparatus. The apparatus may include a memory array and a controller, the controller being coupled to the memory array and configured to cause the apparatus to: receive an access command from a memory system; determine whether the access command corresponds to a single-level cell of the memory array; and, based on the determination that the access command corresponds to the single-level cell, perform an access operation corresponding to the access command using settings for the single-level cell block indicated by one or more bits of the access command.

[0008] A non-transitory computer-readable medium storing code is described. The non-transitory computer-readable medium storing code may include instructions that, when executed by a processor of an electronic device, cause the electronic device to: receive an access command for a memory device from a host system; determine whether the access command corresponds to a single-level cell of the memory device; modify the access command to include one or more bits indicating settings for accessing one or more memory cells in a block of single-level cells based on the determination that the access command corresponds to the single-level cell; and, based on the modification, issue the access command to the memory device including the one or more bits indicating the settings for the single-level cell block.

[0009] A non-transitory computer-readable medium storing code is described. The non-transitory computer-readable medium storing code may include instructions that, when executed by a processor of an electronic device, cause the electronic device to: receive an access command from a memory system; determine whether the access command corresponds to a single-level cell of the memory device; and, based on the determination that the access command corresponds to the single-level cell, perform an access operation corresponding to the access command using settings for the single-level cell block indicated by one or more bits of the access command.

[0010] Describe a method. The method may include: receiving an access command for a memory device from a host system; determining whether the access command corresponds to a single-level cell of the memory device; modifying the access command to include one or more bits indicating settings for accessing one or more memory cells of a single-level cell block based on the determination that the access command corresponds to the single-level cell; and issuing the access command to the memory device based on the modification, including the one or more bits indicating the settings for the single-level cell block. Attached Figure Description

[0011] Figure 1 and 2 This document describes an instance of a system that supports setting switching for Single Level Cells (SLCs) based on the examples disclosed herein.

[0012] Figure 3 and 4 This document describes an instance of a process flow that supports setting switching for SLC, based on the examples disclosed herein.

[0013] Figure 5 This describes an example of a set of memory cells that supports setting switching for SLC, based on the examples disclosed herein.

[0014] Figure 6 A block diagram illustrating a memory system that supports setting switching for SLC, based on the examples disclosed herein.

[0015] Figure 7 A block diagram illustrating a memory device that supports setting switching for SLC, based on the examples disclosed herein.

[0016] Figure 8 and 9 The flowchart illustrates one or more methods for switching settings for SLC, based on the examples disclosed herein. Detailed Implementation

[0017] In some memory systems, a set of multiple settings (e.g., tuning parameters) can be used to perform access operations (e.g., read, write, or erase operations) on memory cell blocks. For example, a memory system may use a first setting (e.g., a set of tuning parameters) to perform relatively fast (i.e., compared to other settings) access commands. In some cases, multiple memory cell blocks in a specific partition of a memory array may use the same settings. Some memory systems may determine the settings of memory cell blocks using block address ranges or based on the partition of the memory cell block. However, in some cases, a memory cell block from a first partition (e.g., a first range of the block) may replace a defective memory cell block from a second range or partition, where the first and second ranges may be configured for different settings. In such cases, using a block address range scheme to determine the settings of a memory cell block may result in the use of settings (e.g., tuning parameters) different from those previously used to write to the memory cell block. In some instances, such deviations in the settings used for access operations may potentially lead to access operation failures, increased system latency, or both.

[0018] To mitigate the issue of performing access operations on memory blocks with settings that do not match previous settings, memory systems can support dynamically indicating settings in access commands. By specifying which settings to use in the access command, the memory system can configure the memory device to use the same settings as the previous access operation, preventing unexpected voltage threshold distributions or failed read operations. In some cases, the memory system can use one or more bits of the access command to indicate the settings used for the access command. For example, some memory blocks (e.g., single-level cell (SLC) blocks) may use relatively fewer address bits compared to other memory blocks, such as multi-level cell (MLC) blocks, three-level cell (TLC) blocks, and four-level cell (QLC) blocks. The memory system can use one or more bits of the access command corresponding to the SLC block to indicate the settings used to perform the access command on the SLC block. Therefore, a memory device receiving an access command can read from or write to an SLC block using the same settings by selecting the settings indicated by the access command (rather than determining the settings from the block address, which may be misaligned due to block replacement operations). Using the same settings to read from and write to memory cell blocks can improve system performance by increasing system reliability, reducing system latency, and reducing power consumption associated with executing additional access commands (e.g., in response to failed access commands).

[0019] First refer to Figure 1 and 2 Features of this disclosure are described in the context of systems and apparatus. References Figures 3 to 5 The features of this disclosure are described in the context of process flow and memory units. References Figures 6 to 9 These and other features of this disclosure are further illustrated and described in the context of device diagrams and flowcharts relating to setting switching for SLC.

[0020] Figure 1 This document describes an example of a system 100 that supports setting switching for SLC, based on the examples disclosed herein. System 100 includes a host system 105 coupled to a memory system 110.

[0021] The memory system 110 may be or include any device or set of devices, wherein the device or set of devices includes at least one memory array. For example, the memory system 110 may be or include a universal flash memory (UFS) device, an embedded multimedia controller (eMMC) device, a flash device, a universal serial bus (USB) flash device, a secure digital card (SD card), a solid-state drive (SSD), a hard disk drive (HDD), a dual in-line memory module (DIMM), a small form factor DIMM (SO-DIMM), or a non-volatile DIMM (NVDIMM), and other possibilities.

[0022] System 100 may be contained in a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transportation), device with Internet of Things (IoT) capabilities, embedded computer (e.g., embedded computer contained in a vehicle, industrial equipment or networked commercial device), or any other computing device containing memory and processing devices.

[0023] System 100 may include a host system 105, which may be coupled to a memory system 110. In some instances, this coupling may include an interface to a host system controller 106, which may be an instance of a controller or control component configured to cause the host system 105 to perform various operations according to the examples described herein. The host system 105 may include one or more devices, and in some cases, may include a processor chipset and a software stack executed by the processor chipset. For example, the host system 105 may include an application configured to communicate with the memory system 110 or devices therein. The processor chipset may include one or more cores, one or more caches (e.g., memory native to the host system 105 or included in the host system), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a Peripheral Component Interconnect High Speed ​​(PCIe) controller, a Serial Advanced Technology Attachment (SATA) controller). The host system 105 may use the memory system 110 to, for example, write data to and read data from the memory system 110. Although in Figure 1 The diagram shows a memory system 110, but the host system 105 can be coupled to any number of memory systems 110.

[0024] Host system 105 may be coupled to memory system 110 via at least one physical host interface. In some cases, host system 105 and memory system 110 may be configured to communicate via the physical host interface using associated protocols (e.g., to exchange or otherwise transmit control, address, data, and other signals between memory system 110 and host system 105). Examples of physical host interfaces may include, but are not limited to, SATA interfaces, UFS interfaces, eMMC interfaces, PCIe interfaces, USB interfaces, Fibre Channel interfaces, Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Dual Data Rate (DDR) interfaces, DIMM interfaces (e.g., DDR-enabled DIMM sockets), Open NAND Flash Interface (ONFI), and Low Power Dual Data Rate (LPDDR) interfaces. In some instances, one or more such interfaces may be included in or otherwise supported between host system controller 106 of host system 105 and memory system controller 115 of memory system 110. In some instances, host system 105 may be coupled to memory system 110 via a corresponding physical host interface for each memory device 130 included in memory system 110, or via a corresponding physical host interface for each type of memory device 130 included in memory system 110 (e.g., host system controller 106 may be coupled to memory system controller 115).

[0025] Memory system 110 may include memory system controller 115 and one or more memory devices 130. Memory device 130 may include one or more memory arrays of any type of memory cells (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). Although in Figure 1 The example shows two memory devices 130-a and 130-b, but the memory system 110 may contain any number of memory devices 130. Furthermore, if the memory system 110 contains more than one memory device 130, the different memory devices 130 within the memory system 110 may contain the same or different types of memory cells.

[0026] The memory system controller 115 may be coupled to and communicate with the host system 105 (e.g., via a physical host interface) and may be an example of a controller or control component configured to cause the memory system 110 to perform various operations according to the examples described herein. The memory system controller 115 may also be coupled to and communicate with the memory device 130 to perform operations generally referred to as access operations at the memory device 130, such as reading data, writing data, erasing data, or refreshing data, and other such operations. In some cases, the memory system controller 115 may receive commands from the host system 105 and communicate with one or more memory devices 130 to execute such commands (e.g., at a memory array within one or more memory devices 130). For example, the memory system controller 115 may receive commands or operations from the host system 105 and may translate these commands or operations into instructions or appropriate commands to implement the desired access to the memory device 130. In some cases, the memory system controller 115 may exchange data with the host system 105 and with one or more memory devices 130 (e.g., in response to or otherwise associated with a command from the host system 105). For example, the memory system controller 115 may translate responses associated with the memory device 130 (e.g., data packets or other signals) into corresponding signals for the host system 105.

[0027] The memory system controller 115 may be configured for other operations associated with the memory device 130. For example, the memory system controller 115 may perform or manage operations such as wear leveling, unused cell collection, error control operations such as error detection or error correction, encryption, caching, media management, background refresh, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 130.

[0028] The memory system controller 115 may include hardware, such as one or more integrated circuits or discrete components, buffer memories, or combinations thereof. The hardware may include circuitry with dedicated (e.g., hard-decoded) logic to perform the operations attributed herein to the memory system controller 115. The memory system controller 115 may be or include a microcontroller, a dedicated logic circuitry system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry.

[0029] The memory system controller 115 may also include local memory 120. In some cases, local memory 120 may include read-only memory (ROM) or other memory that can store operational code (e.g., executable instructions) that can be executed by the memory system controller 115 to perform the functions attributed to the memory system controller 115 herein. In some cases, local memory 120 may additionally or alternatively include static random access memory (SRAM) or other memory that can be used by the memory system controller 115 for, for example, internal storage or computation related to the functions attributed to the memory system controller 115 herein. Additionally or alternatively, local memory 120 may act as a cache for the memory system controller 115. For example, if data is read from or written to memory device 130, data may be stored in local memory 120 and may be available in local memory 120 for subsequent retrieval or manipulation (e.g., updating) by the host system 105 according to a caching strategy (e.g., with reduced latency relative to memory device 130).

[0030] although Figure 1 The memory system 110 described herein has been illustrated as including a memory system controller 115, but in some cases, the memory system 110 may not include a memory system controller 115. For example, the memory system 110 may additionally or alternatively rely on an external controller (e.g., implemented by the host system 105) or one or more local controllers 135 within the memory device 130 to perform the functions attributed herein to the memory system controller 115. Generally, one or more functions attributed herein to the memory system controller 115 may, in some cases, be performed by the host system 105, the local controller 135, or any combination thereof. In some cases, the memory device 130, at least partially managed by the memory system controller 115, may be referred to as a managed memory device. An example of a managed memory device is a managed NAND (MNAND) device.

[0031] Memory device 130 may include one or more arrays of non-volatile memory cells. For example, memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase-change memory (PCM), auto-select memory, other chalcogenide-based memories, ferroelectric random access memory (RAM) (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), electrically erasable programmable ROM (EEPROM), or any combination thereof. Alternatively or additionally, memory device 130 may include one or more arrays of volatile memory cells. For example, memory device 130 may include RAM memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0032] In some instances, memory device 130 may (e.g., on the same die or within the same package) include a local controller 135, which can perform operations on one or more memory cells of the respective memory device 130. The local controller 135 may operate in conjunction with memory system controller 115, or may perform one or more functions attributed herein to memory system controller 115. For example, such as Figure 1 As described, memory device 130-a may include local controller 135-a, and memory device 130-b may include local controller 135-b.

[0033] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include a memory die 160. For example, in some cases, memory device 130 may be a package containing one or more dies 160. In some instances, die 160 may be a piece of electronic-grade semiconductor diced from a wafer (e.g., a silicon die diced from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a corresponding set of blocks 170, wherein each block 170 may include a corresponding set of pages 175, and each page 175 may include a set of memory cells.

[0034] In some cases, the NAND memory device 130 may include memory cells configured to each store one bit of information, which may be referred to as SLC. Alternatively, the NAND memory device 130 may include memory cells configured to each store multiple bits of information, which may generally be referred to as multilevel cells or, more specifically, as MLC when configured to each store two bits of information, TLC when configured to each store three bits of information, QLC when configured to each store four bits of information, or more generally as multilevel memory cells. Multilevel memory cells can provide greater storage density than SLC memory cells, but in some cases, may involve narrower read or write tolerances or greater complexity to support the circuitry.

[0035] In some cases, plane 165 may refer to a group of blocks 170, and in some cases, parallel operations may occur within different planes 165. For example, parallel operations may be performed on memory cells within different blocks 170, as long as the different blocks 170 are located in different planes 165. In some cases, individual blocks 170 may be referred to as physical blocks, and virtual blocks 180 may refer to a group of blocks 170 within which parallel operations may occur. For example, parallel operations may be performed on blocks 170-a, 170-b, 170-c, and 170-d within planes 165-a, 165-b, 165-c, and 165-d, respectively, and blocks 170-a, 170-b, 170-c, and 170-d may be collectively referred to as virtual blocks 180. In some cases, a virtual block may contain blocks 170 from different memory devices 130 (e.g., blocks in one or more planes including memory devices 130-a and 130-b). In some cases, blocks 170 within a virtual block may have the same block address within their respective planes 165 (e.g., block 170-a may be “block 0” of plane 165-a, block 170-b may be “block 0” of plane 165-b, and so on). In some cases, performing parallel operations in different planes 165 may be subject to one or more limitations, such as performing parallel operations on memory cells within different pages 175 that have the same page address within their respective planes 165 (e.g., involving command decoding, page address decoding circuitry, or other circuitry shared across planes 165).

[0036] In some cases, block 170 may contain memory cells organized into rows (page 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 may share a common word line (e.g., coupled thereto), and memory cells in the same string may share a common digital line (which may alternatively be called a bit line) (e.g., coupled thereto).

[0037] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first-level granularity (e.g., at the page level), but may be erased at a second-level granularity (e.g., at the block level). That is, page 175 may be the smallest unit of memory (e.g., a group of memory cells) that can be independently programmed or read (e.g., programmed or read in parallel as part of a single programming or reading operation), and block 170 may be the smallest unit of memory (e.g., a group of memory cells) that can be independently erased (e.g., erased in parallel as part of a single erase operation). Furthermore, in some cases, NAND memory cells may be erased before they can be rewritten with new data. Therefore, for example, in some cases, used page 175 may not be updated until the entire block 170 containing page 175 has been erased.

[0038] In some cases, to update some data within block 170 while preserving other data within block 170, memory device 130 may copy the data to be preserved to a new block 170 and write the updated data to one or more remaining pages of the new block 170. Memory device 130 (e.g., local controller 135) or memory system controller 115 may mark or otherwise designate data held in the old block 170 as invalid or obsolete, and may update the logical-to-physical (L2P) mapping table so that the logical address (e.g., LBA) of the data is associated with the new valid block 170 rather than the old invalid block 170. In some cases, such copying and remapping may be performed instead of erasing and rewriting the entire old block 170, for example, due to latency or wear and tear considerations. In some cases, one or more copies of the L2P mapping table may be stored within memory cells of memory device 130 (e.g., within one or more blocks 170 or plane 165) for use by local controller 135 or memory system controller 115 (e.g., for reference and updating).

[0039] In some cases, the memory system controller 115 or the local controller 135 may perform operations on the memory device 130 (e.g., as part of one or more media management algorithms), such as wear leveling, background refresh, useless cell collection, cleanup, block scanning, health monitoring, or other operations, or any combination thereof. For example, within the memory device 130, block 170 may have some pages 175 containing valid data and some pages 175 containing invalid data. To avoid waiting for all pages 175 in block 170 to have invalid data before erasing and reusing block 170, an algorithm called "useless cell collection" may be invoked to allow block 170 to be erased and freed up for subsequent write operations. Waste cell collection can refer to a set of media management operations that include, for example, selecting block 170 containing valid and invalid data, selecting page 175 within the block containing valid data, copying the valid data from the selected page 175 to a new location (e.g., a free page 175 in another block 170), marking the data in the previously selected page 175 as invalid, and erasing the selected block 170. Therefore, the number of erased blocks 170 can be increased, making more blocks 170 available for storing subsequent data (e.g., data subsequently received from host system 105).

[0040] System 100 may include any number of non-transitory computer-readable media that support setting switching for SLC. For example, host system 105, memory system controller 115, or memory device 130 may include or otherwise have access to one or more non-transitory computer-readable media that store instructions (e.g., firmware) to perform the functions belonging to host system 105, memory system controller 115, or memory device 130 herein. For example, such instructions, if executed by host system 105 (e.g., by host system controller 106), memory system controller 115, or memory device 130 (e.g., by local controller 135), may cause host system 105, memory system controller 115, or memory device 130 to perform one or more associated functions as described herein.

[0041] In some cases, memory system 110 may utilize memory system controller 115 to provide a managed memory system, which may include, for example, one or more memory arrays and associated circuitry combined with a local (e.g., on-die or in-package) controller (e.g., local controller 135). An example of a managed memory system is an MNAND system.

[0042] In some memory devices 130, memory cell blocks 170 configured to store one bit of data per memory cell (i.e., SLC block) can be configured to use one of a plurality of settings to store data. In some cases, the settings may be referred to as trims, SLC trims, trim settings, or configurations, and other instances thereof. Each setting may include indications of one or more operating parameters for performing access operations when the setting is used. For example, a setting may define a voltage distribution of voltage levels for the SLC block. That is, a setting may indicate voltage levels corresponding to logic states of the SLC block, such as voltage levels corresponding to logic "0", voltage levels corresponding to logic "1", voltage level differences between two logic states, or combinations thereof.

[0043] In some cases, the set of settings may include dynamic settings (e.g., dynamic SLC or dynamic tuning) configured relative to other settings for fast write performance. For example, dynamic settings may be used for SLC blocks in a portion of the write burst mode defined for memory system 110.

[0044] The settings may also include static settings (e.g., static SLC or static tuning) for high durability configurations relative to other dynamic settings. For example, if a relatively high number of access commands are executed on block 170 (e.g., above a threshold number), block 170 of the memory cell can use static settings to execute access commands such that the memory cells of block 170 can meet the lifetime threshold of memory device 130 (e.g., a terabyte write (TBW) threshold).

[0045] In some cases, the settings may also include high-durability settings relative to static and dynamic settings for high-durability configurations (e.g., high-durability SLC or high-durability tuning). For example, a block 170 of memory cells executing access commands using high-durability settings can execute a relatively high number of access commands over the lifetime of the memory cells (i.e., a higher number of access commands than a block of memory cells using dynamic or static settings). However, static and dynamic settings can support relatively higher data accuracy reliability than high-durability settings.

[0046] Additionally, the setup may include a generation state-aware (PSA) setting (e.g., PSA SLC or PSA trim) configured for writing data prior to the infrared (IR) reflow process. For example, the memory device may undergo one or more manufacturing processes, such as soldering to a memory system or printed circuit board (PCB), after data is programmed into the memory device's cells. In some cases, the manufacturing process may subject the memory cells to relatively harsh conditions, such as high temperatures (e.g., above a temperature threshold), compared to other uses. Such conditions can potentially adversely affect the integrity of the data programmed into the memory cells prior to the manufacturing process. The memory cell block 170 storing data written using the PSA setting may have relatively high reliability compared to other setups. That is, data written using the PSA setting can be configured to maintain accuracy after one or more manufacturing processes (e.g., IR reflow).

[0047] In some cases, memory system 110 may be configured with a set of contiguous memory cell blocks 170 in which one of the settings is to be used. For example, memory system 110 may use start and stop addresses to indicate a range of block addresses for applying a particular setting. In some cases, the block address range may be configured, for example, via firmware during a pre-boot sequence.

[0048] In some other systems, a memory device may execute access commands based on settings indicated by a block address range. That is, the memory device can use the address contained in the access command to determine the block address range and, consequently, which setting to use to execute the access command. Using block address ranges to indicate settings may not allow overlap between address ranges. That is, each physical address may correspond to a single setting. However, in some cases, multi-plane operations (e.g., access operations accessing multiple memory cell blocks in a single plane) may access two or more blocks, each corresponding to a different block address range and therefore a different setting. In such cases, the multi-plane operation can use one of the settings (e.g., the setting corresponding to the lowest access plane) to access each of the memory cell blocks indicated in the multi-plane operation. That is, some memory cell blocks can be accessed using settings different from those indicated by the block address range. Accessing memory cell blocks using different settings can increase the probability of errors, reduce execution speed, increase power consumption, or any combination thereof.

[0049] Alternatively, in some other systems, the memory system may use a single configured Media-Local-Bus Interface (MLBi) to trigger configuration switching. For example, whenever a memory device needs to switch configurations for access operations, the memory system may issue a dedicated MLBi command to switch to the new configuration. However, systems using dedicated MLBi commands may not support certain operations, such as cache programming and cache read operations. For example, firmware at the memory system may mix cache programming and cache read operations across different partitions to improve performance. To support dedicated MLBi commands, the memory system may stop issuing commands to the memory device if a switch between partitions is attributable to random reads of the read table, redundant arrays of independent NAND (RAIN) parity programming operations, table updates, host commands indicating different partitions, or any combination of these or other operations. The memory system may stop issuing commands to issue dedicated MLBi commands to perform configuration switching, thereby significantly degrading the performance of the memory system (e.g., below a performance threshold).

[0050] In contrast, memory system 110 may include indications of settings in the access command, allowing memory device 130 to determine which settings to use based on the access command rather than a block address range or a separate dedicated MLBi command. Therefore, regardless of the physical block address and access type (e.g., single-plane 165 vs. multi-plane 165), memory device 130 can use the information provided in the access command itself to access the indicated block 170 using appropriate settings (e.g., SLC fine-tuning).

[0051] Figure 2 This document describes an instance of system 200 that supports setting switching for SLC, based on the examples disclosed herein. System 200 may be used as a reference. Figure 1 Examples of the described system 100 or its aspects thereof. System 200 may include a memory system 210 configured to store data received from host system 205 and to send data to host system 205 upon request by host system 205 using access commands (e.g., read commands or write commands). System 200 may be implemented as referenced. Figure 1 The various aspects of the system 100 described. For example, memory system 210 and host system 205 may be instances of memory system 110 and host system 105, respectively.

[0052] As described herein, memory system 210 may include memory device 240 for storing, for example, data transferred between memory system 210 and host system 205 in response to receiving an access command from host system 205. Memory device 240 may include, as referenced... Figure 1The memory device 240 may include one or more memory devices as described. For example, memory device 240 may include NAND memory, PCM, self-select memory, 3D cross-point, other chalcogenide-based memory, FERAM, MRAM, NOR (e.g., NOR flash) memory, STT-MRAM, CBRAM, RRAM, or OxRAM.

[0053] Memory system 210 may include a memory controller 230 for controlling the transfer of data directly to and from memory device 240, for example, for storing data, retrieving data, and determining memory locations where data is to be stored and retrieved. The memory controller 230 may communicate with memory device 240 directly or via a bus (not shown) using protocols specific to each type of memory device 240. In some cases, a single memory controller 230 may be used to control multiple memory devices 240 of the same or different types. In some cases, memory system 210 may include multiple memory controllers 230, for example, different memory controllers 230 for each type of memory device 240. In some cases, the memory controller 230 may implement a reference... Figure 1 The local controller 135 is described in various aspects.

[0054] The memory system 210 may additionally include an interface 220 for communicating with the host system 205, and a buffer 225 for temporarily storing data being transferred between the host system 205 and the memory device 240. The interface 220, buffer 225, and memory controller 230 can be used to transfer data between the host system 205 and the memory device 240 (e.g., as shown by data path 250), and can be collectively referred to as the data path components.

[0055] Using buffer 225 to temporarily store data during transmission allows data to be buffered while commands are being processed, thereby reducing latency between commands and allowing for arbitrary data sizes associated with commands. This also allows for handling command bursts, and once the burst stops, the buffered data can be stored or transmitted (or both). Buffer 225 may contain relatively fast memory (e.g., some type of volatile memory such as SRAM or DRAM) or hardware accelerators or both to allow for fast storage and retrieval of data in and out of buffer 225. Buffer 225 may include data path switching components for bidirectional data transfer between buffer 225 and other components.

[0056] Temporary storage of data within buffer 225 refers to the storage of data in buffer 225 during the execution of an access command. That is, after the access command is completed, the associated data may no longer be maintained in buffer 225 (e.g., it may be overwritten by data from an additional access command). Additionally, buffer 225 can be a non-cached buffer. That is, host system 205 may not read data directly from buffer 225. For example, a read command can be added to a queue without performing an operation to match the address with an address already existing in buffer 225 (e.g., no cached address matching or lookup operation).

[0057] The memory system 210 may additionally include a memory system controller 215 for executing commands received from the host system 205 and controlling data path components when moving data. The memory system controller 215 may be as described in reference... Figure 1 An example of the described memory system controller 115. A bus 235 can be used for communication between system components.

[0058] In some cases, one or more queues (e.g., command queue 260, buffer queue 265, and storage queue 270) may be used to control the processing of access commands and the movement of corresponding data. This can be advantageous, for example, if the memory system 210 processes more than one access command from the host system 205 in parallel. As examples of possible implementations, command queue 260, buffer queue 265, and storage queue 270 are depicted at interface 220, memory system controller 215, and storage controller 230, respectively. However, queues (if used) may be located anywhere within the memory system 210.

[0059] Data transferred between host system 205 and memory device 240 may take a different path within memory system 210 than non-data information (e.g., commands, status information). For example, system components in memory system 210 may communicate with each other using bus 235, while data may use data path 250 via data path components instead of bus 235. Memory system controller 215 may control how and whether data is transferred between host system 205 and memory device 240 by communicating with data path components via bus 235 (e.g., using a protocol specific to memory system 210).

[0060] If host system 205 transmits an access command to memory system 210, the command can be received by interface 220, for example, according to a protocol (e.g., UFS protocol or eMMC protocol). Therefore, interface 220 can be considered as the front end of memory system 210. Upon receiving each access command, interface 220 can transmit the command to memory system controller 215, for example, via bus 235. In some cases, each command can be added to command queue 260 via interface 220 to transmit the command to memory system controller 215.

[0061] The memory system controller 215 can determine that an access command has been received based on (e.g., in response to) communication from interface 220. In some cases, the memory system controller 215 can determine that the command has been received by retrieving the access command from command queue 260. The command can be removed from command queue 260 after it has been retrieved by the memory system controller 215, for example. In some cases, the memory system controller 215 can cause interface 220 to remove the command from command queue 260, for example, via bus 235.

[0062] Once it is determined that an access command has been received, the memory system controller 215 can execute the access command. For a read command, this may mean obtaining data from the memory device 240 and transferring data to the host system 205. For a write command, this may mean receiving data from the host system 205 and moving data to the memory device 240.

[0063] In either case, the memory system controller 215 may use the buffer 225, particularly for temporary storage of data received from or sent to the host system 205. The buffer 225 can be considered as an intermediate part of the memory system 210. In some cases, buffer address management (e.g., pointers to address locations within the buffer 225) may be performed by hardware (e.g., dedicated circuitry) in the interface 220, the buffer 225, or the memory controller 230.

[0064] In order to process a write command received from host system 205, memory system controller 215 may first determine whether buffer 225 has sufficient available space to store the data associated with the command. For example, memory system controller 215 may determine the amount of space available in buffer 225 to store the data associated with the write command, for example via firmware (e.g., controller firmware).

[0065] In some cases, buffer queue 265 can be used to control a stream of commands associated with data stored in buffer 225, the stream of commands including write commands. Buffer queue 265 may contain access commands associated with data currently stored in buffer 225. In some cases, commands in command queue 260 can be moved to buffer queue 265 via memory system controller 215 and can remain in buffer queue 265 while the associated data is stored in buffer 225. In some cases, each command in buffer queue 265 may be associated with an address at buffer 225. That is, a pointer indicating where the data associated with each command is stored in buffer 225 can be maintained. Using buffer queue 265, multiple access commands can be received sequentially from host system 205 and at least a portion of the access commands can be processed in parallel.

[0066] If buffer 225 has sufficient space to store the write data, memory system controller 215 may cause interface 220 to transmit an availability indication (e.g., a "ready to transfer" indication) to host system 205, for example, according to a protocol (e.g., UFS protocol or eMMC protocol). When interface 220 subsequently receives data associated with the write command from host system 205, interface 220 may use data path 250 to transfer the data to buffer 225 for temporary storage. In some cases, interface 220 may obtain the location within buffer 225 for storing data from buffer 225 or buffer queue 265. Interface 220 may indicate to memory system controller 215, for example, via bus 235 whether data transfer to buffer 225 has been completed.

[0067] Once the written data has been stored in buffer 225 via interface 220, the data can be transferred from buffer 225 and stored in memory device 240. This can be accomplished using memory controller 230. For example, memory system controller 215 can cause memory controller 230 to retrieve data from buffer 225 using data path 250 and transfer the data to memory device 240. Memory controller 230 can be considered as the back-end of memory system 210. Memory controller 230 can, for example, indicate to memory system controller 215 via bus 235 that the data transfer to memory device 240 has been completed.

[0068] In some cases, storage queue 270 can be used to assist in the transfer of write data. For example, memory system controller 215 can (e.g., via bus 235) push write commands from buffer queue 265 to storage queue 270 for processing. Storage queue 270 may contain entries for each access command. In some instances, storage queue 270 may additionally include: a buffer pointer (e.g., an address) indicating where in buffer 225 the data associated with the command is stored; and a storage pointer (e.g., an address) indicating the location in memory device 240 associated with the data. In some cases, storage controller 230 can obtain the location within buffer 225 from which data is to be obtained, either from buffer 225, buffer queue 265, or storage queue 270. Storage controller 230 can manage the locations within memory device 240 used to store data (e.g., performing wear leveling, waste cell collection, etc.). Entries can be added to storage queue 270, for example, via memory system controller 215. After the data transfer is complete, the entry can be removed from the storage queue 270, for example, by the storage controller 230 or the memory system controller 215.

[0069] In order to process a read command received from host system 205, memory system controller 215 may first determine whether buffer 225 has sufficient available space to store the data associated with the command. For example, memory system controller 215 may determine the amount of space available in buffer 225 to store the data associated with the read command, for example via firmware (e.g., controller firmware).

[0070] In some cases, buffer queue 265 can be used to supplement buffer storage of data associated with a read command in a manner similar to that discussed above with respect to write commands. For example, if buffer 225 has sufficient space to store the read data, memory system controller 215 can cause memory controller 230 to retrieve the data associated with the read command from memory device 240 and store the data in buffer 225 for temporary storage using data path 250. Memory controller 230 can indicate to memory system controller 215, for example, via bus 235, whether the data transfer to buffer 225 has been completed.

[0071] In some cases, the storage queue 270 can be used to assist in the transfer of read data. For example, the memory system controller 215 can push a read command to the storage queue 270 for processing. In some cases, the storage controller 230 can obtain the location within the memory device 240 from the buffer 225 or the storage queue 270 for retrieving data. In some cases, the storage controller 230 can obtain the location within the buffer 225 for storing data from the buffer queue 265. In some cases, the storage controller 230 can obtain the location within the buffer 225 for storing data from the storage queue 270. In some cases, the memory system controller 215 can move commands processed by the storage queue 270 back to the command queue 260.

[0072] Once data has been stored in buffer 225 by storage controller 230, it can be transferred out of buffer 225 and sent to host system 205. For example, storage system controller 215 can enable interface 220 to retrieve data from buffer 225 using data path 250 and transfer the data to host system 205, for example, according to a protocol (e.g., UFS protocol or eMMC protocol). For example, interface 220 can process commands from command queue 260 and can indicate to storage system controller 215, for example, via bus 235, that the data transfer to host system 205 is complete.

[0073] The memory system controller 215 can execute received commands in a sequence (e.g., according to the first-in-first-out order of the command queue 260). For each command, the memory system controller 215 can cause the data corresponding to the command to move in and out of buffer 225, as discussed above. While the data is moved into and stored in buffer 225, the command can remain in buffer queue 265. If processing of the command has been completed (e.g., if the data corresponding to the access command has been transferred out of buffer 225), the command can be removed from buffer queue 265, for example, via the memory system controller 215. If a command is removed from buffer queue 265, the address where the data previously associated with the command was stored can be used to store the data associated with the new command.

[0074] The memory system controller 215 may be additionally configured for operations associated with the memory device 240. For example, the memory system controller 215 may perform or manage operations such as wear leveling, unused cell collection, error control operations such as error detection or error correction, encryption, caching, media management, background refresh, health monitoring, and address translation between logical addresses (e.g., LBAs) associated with commands from the host system 205 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 240. That is, the host system 205 may issue commands indicating one or more LBAs, and the memory system controller 215 may identify one or more physical block addresses indicated by the LBAs. In some cases, one or more consecutive LBAs may correspond to non-consecutive physical block addresses. In some cases, the memory controller 230 may be configured to perform one or more of the above operations in conjunction with or in place of the memory system controller 215. In some cases, the memory system controller 215 may perform the functions of the memory controller 230, and the memory controller 230 may be omitted.

[0075] In some cases, host system 205 may transmit access command 275 (e.g., read command, write command, or erase command) to memory system 210. Memory system 210 may modify and issue access command 275 to memory device 240 in response to receiving access command 275. Access command 275 received by memory system 210 may contain an indication of a memory cell address within memory device 240. The indication may include column address, row address, page address, bank address, or any combination thereof.

[0076] The memory system 210 may modify the access command 275 received from the host system 205 using, for example, a flash translation layer (FTL) included in the memory system controller 215. The FTL may modify the access command 275 in response to determining whether the memory cell indicated in the access command 275 is an SLC block or a multi-level cell block (e.g., an MLC block, a TLC block, a QLC block, or another memory cell block configured to store more than one bit of data).

[0077] In some cases, in response to determining that one or more memory cells indicated by access command 275 are part of one or more SLC blocks, the FTL may modify access command 275 to include indications for settings of the memory cell block (e.g., one of a group of multiple configured settings, as referenced). Figure 1(As described). In some cases, the FTL may contain a mapping between partitions and settings for virtual block addresses. That is, each virtual block address for a memory cell block may be associated with a partition and corresponding setting of the memory device, regardless of the physical address of the memory cell block. The FTL may modify access command 275 to include an indication of the settings (e.g., SLC setting 280) to be used in an access operation for the memory cell block indicated by access command 275. Memory system 210 may issue the modified access command 275 containing the indication of SLC setting 280 to memory device 240, such that memory device 240 may perform the access operation indicated by access command 275 using the indicated SLC setting 280.

[0078] For example, an access command 275 (i.e., a multi-level cell access command) for a multi-level cell block (e.g., an MLC block, TLC block, or QLC block) may contain an address using more bits than the address corresponding to an access command 275 for an SLC block (i.e., an SLC access command). However, in some cases, the number of bits allocated to indicate the address in the access command may be the same size for both the SLC access command and the multi-level cell access command. Therefore, there may be one or more bits included in the access command that can be used for address indication in the multi-level cell access command and for different purposes in the SLC access command. In some cases, the memory system 210 may reuse such bits to indicate SLC setting 280 in the SLC access command.

[0079] Access commands 275 can be issued from memory system 210 to memory device 240 in multiple cycles using a bus with a certain number of data pins (e.g., an 8-pin bus). Each cycle may contain a certain number of bits equal to the number of data pins, where each bit may correspond to a bit field containing n indices, such as a column address (CA) bit field, a page address (PA) bit field, a bank address (BA) bit field, a logical cell address (LA) bit field, a plane setting (PS) bit field, or any combination thereof. Each bit may be ordered within its corresponding bit field according to index n (e.g., bit CA7 may be the 7th bit in the CA bit field). Table 1 shows examples of addresses indicated using an 8-pin bus in multiple cycles:

[0080] First CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0 second Low CA14 CA13 CA12 CA11 CA10 CA9 CA8 third PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 fourth BA15 BA14 PS13 PS12 PA11 PA10 PA9 PA8 fifth BA23 BA22 BA21 BA20 BA19 BA18 BA17 BA16 sixth Low Low Low Low Low LA2 LA1 LA0

[0081] Table 1: Instance Address Bit Usage

[0082] If access command 275 is an SLC access command, then there may be (e.g., according to the address cycle described in Table 1) reserved bits not used in the address cycle for indicating addresses in the multilevel cell access command. For example, the bits indicated as PA bits PA11 and PA10 in Table 1 can be used to indicate bits 10 and 11 in the PA bit field for a multilevel cell access command, but can be used to indicate settings (e.g., SLC setting 280) in an SLC access command. Such bits can be reused because the number of possible page addresses supported for an SLC access command can be indicated using ten bits, compared to the twelve bits used for multilevel cell access commands. If access command 275 received from host system 205 indicates SLC, then PA11 and PA10 bits can be set to default values ​​(e.g., 00) in access command 275. The memory system controller 215 (e.g., FTL) can modify one or more bits of the access command 275 (e.g., two bits corresponding to PA11 and PA10) to include an indication of a setting (e.g., SLC setting 280) as part of the access command 275. For example, the memory system controller 215 can indicate from a set of settings (see reference...) Figure 1 The settings (description) are shown in Table 2:

[0083] 0 0 Static settings 0 1 Dynamic settings 1 0 High durability settings 1 1 PSA settings

[0084] Table 2: Instance Setting Encoding Table

[0085] Therefore, memory system 210 can modify access command 275 to indicate, for example, that a static setting will be used to perform the access operation indicated by access command 275 by setting both PA11 and PA10 bits to 0. Alternatively, other mappings can be used to map any number of bits of access command 275 to any set of SLC settings 280, compared to the example mappings shown in Table 2.

[0086] The format used for access command 275 may be configured at memory system 210, memory device 240, or both. Access command 275 may include one or more bits indicating the action to be performed (e.g., read operation, write operation, erase operation). Access command 275 may also include one or more bits indicating the address of a memory cell or block of memory cells that can be accessed in response to the access command (e.g., as described herein with reference to Table 1). For example, access command 275 may include one or more bits indicating CA, BA, PA, LA, or any combination of these or other address information. In some cases, access command 275 may include one or more bits indicating a setting (e.g., one of the set of SLC settings 280) (e.g., one or more bits corresponding to bit indices of one or more of the address bits). For example, depending on whether the access command 275 is an SLC access command or a multilevel cell access command, the access command 275 may contain one or more bits that can be interpreted by the memory device 240 in different ways (e.g., as an instruction to SLC set 280 or a portion of an address).

[0087] Figure 3 This document describes an example of a process flow 300 supporting SLC setting switching, based on the examples disclosed herein. Process flow 300 can be executed by a memory system, which may be a reference... Figure 1 and 2 An example of a memory system is described. The memory system can communicate with a host system and a memory device, which may be used as a reference. Figure 1 and 2 Examples of the corresponding apparatus described. In some cases, the operations of process flow 300 may be performed in a different order than that shown. Alternatively or additionally, specific operations may be excluded from process flow 300, other operations may be added to process flow 300, or both.

[0088] At position 305, a prefix command can be received. For example, the memory system can receive a prefix command from the host system. In some cases, the prefix command can indicate SLC mode. That is, the prefix command can indicate whether a subsequent access command (e.g., the next received access command) corresponds to an SLC block.

[0089] At 310, access commands can be received. For example, the memory system can receive access commands from the host system. The access command can be an example of a read command, write command, or erase command and may contain an indication of a memory cell block. For example, an access command sent from the host system may contain the virtual address of the memory cell block to which the corresponding access operation is to be performed. The access command may contain one or more bits indicating CA, one or more bits indicating PA, one or more bits indicating PS, one or more bits indicating BA, one or more bits indicating LA, or any combination thereof.

[0090] At 315, it can be determined whether the access command corresponds to an SLC block. For example, the memory system can determine whether the memory cell block indicated in the access command (e.g., in the virtual address of the access command) is an SLC block or a multilevel cell block, such as an MLC block, TLC block, or QLC block. In some cases, the determination can be performed using a prefix command received at 305. For example, the prefix command can indicate whether the access command corresponds to an SLC block.

[0091] If the access command is determined to correspond to an SLC block at 315, a partition can be selected at 320. Using FTL, the memory system can select a partition of a set of cells of the SLC block using usage data from the host system, such as partitions selected during the pre-boot sequence. For example, usage data from the host system may indicate whether the memory system will perform an access operation in a partition that supports relatively low latency operation, relatively high reliability operation, relatively high durability, or a combination thereof. In some cases, the memory system can use the selected partition to determine the settings for the SLC block. For example, the memory system can be configured such that it can determine the corresponding partition to which the virtual block belongs and the corresponding settings available for said virtual block (e.g., based on the corresponding partition).

[0092] The settings may define one or more operational parameters for an access operation corresponding to an access command. For example, the one or more operational parameters may include a voltage applied during the access operation, the duration of the applied voltage during the access operation, a reference voltage for the access operation, a programming verification command for the access operation, or any combination thereof, and other examples. The settings may correspond to a reference... Figure 1 One of a set of settings described. For example, the settings may correspond to dynamic SLC, static SLC, high-durability SLC, or PSA SLC.

[0093] At position 325, an indication can be inserted into the access command. For example, the memory system can modify the access command to include one or more bits indicating the settings for accessing one or more memory cells of the SLC block. In some cases, the access command can be modified by encoding the settings by setting unused bits in the address corresponding to the access command, as described, for example, with reference to Table 2. For example, the memory system can mask the PA11 and PA10 address bits with the encoded bits corresponding to the settings, based on an indication from the memory system controller (e.g., FTL). The modified bits can indicate which of a configured set of settings will be used to access the memory cells of the SLC block.

[0094] At 330, an access command may be issued. For example, the memory system may issue an access command to the memory device, which is received from the host system at 310 and modified, for example, by the memory system controller at 325 to include an indication of the settings. The issued access command may include one or more bits indicating settings for the SLC block. The memory device may use the settings indicated by the one or more bits to perform the access operation associated with the access command. Thus, the memory device may use appropriate settings (e.g., the same settings previously used, such that memory cells of the SLC block are correctly programmed or read according to previous access operations) to access the SLC block.

[0095] In some cases, an access command may not correspond to an SLC block. In such cases (e.g., if it is determined at 315 that the access command does not correspond to an SLC block), the address can be identified at 335. For example, the memory system can use a set of bits in the access command to determine the address. This set of bits may include one or more bits indicating address information in the multilevel cell access command, the one or more bits corresponding to one or more bit indices that are the same as the bits indicating settings in the SLC access command. The one or more bits may indicate at least a portion of the page address for the multilevel cell block (e.g., MLC block, TLC block, QLC block, etc.). That is, the memory system can determine that the access command corresponds to a multilevel cell block, and the address indicated in the access command includes additional bits that might not exist if the access command corresponds to an SLC block (e.g., reference...). Figure 2 Describes and dynamically reuses page address bits PA11 and PA10 set in SLC access commands.

[0096] At position 340, access commands can be issued. For example, the memory system can issue access commands corresponding to multi-level cell blocks to the memory device.

[0097] Various aspects of process flow 300 may be implemented by a controller and other components. Alternatively, aspects of process flow 300 may be implemented as instructions stored in memory (e.g., firmware stored in memory coupled to a memory system). For example, if the instructions are executed by a controller (e.g., memory system controller 115 or memory system controller 215), the controller may perform the operation of process flow 300.

[0098] Figure 4 This document describes an example of a process flow 400 supporting setting switching for SLC, based on the examples disclosed herein. Process flow 400 can be executed by a memory device, which may be a reference... Figure 1 and 2 Examples of described memory devices. The memory device can communicate with a memory system, which may be a reference... Figures 1 to 3 An example of a memory system is described. In some cases, the operations of process flow 400 may be performed in a different order than that shown. Alternatively, specific operations may be excluded from process flow 400, other operations may be added to process flow 400, or both.

[0099] At position 405, access commands can be received. For example, a memory device can receive access commands from a memory system. In some cases, the access command can be a reference. Figure 3 The access commands described herein. That is, access commands can be read commands, write commands, or erase commands, and can correspond to access operations targeting SLC blocks or multi-level cell blocks (MLC blocks, TLC blocks, QLC blocks). Access commands may contain one or more bits indicating CA, one or more bits indicating PA, one or more bits indicating PS, one or more bits indicating BA, one or more bits indicating LA, or any combination thereof.

[0100] At 410, it can be determined whether the access command received at 405 corresponds to an SLC block. For example, the memory device can determine whether the access command received from the memory system corresponds to an SLC block or a multilevel cell block. In some instances, the memory device can use the address indicated by the access command to determine the type of block accessed by the access command. In some other instances, the memory device can receive a prefix command indicating whether the access command corresponds to an SLC block. And in some other instances, the access command may include an indicator indicating whether the access command corresponds to an SLC block or a multilevel cell block.

[0101] If the access command corresponds to an SLC block, a setting can be identified at 415. For example, the memory device can use one or more bits contained in the access command to identify a setting (e.g., see reference...). Figure 1(One of a set of configured settings described). In some cases, the settings can be encoded by one or more bits, where each state of the one or more bits corresponds to a specific setting, for example, as shown in Table 2. In some instances, the one or more bits may correspond to one or more bit indices for the access command. The one or more bit indices may indicate the settings for accessing an SLC block when the access command corresponds to an SLC, or indicate at least a portion of a PA when the access command corresponds to a multi-level unit.

[0102] At 420, the settings identified at 415 can be used to perform access operations corresponding to access commands. For example, a memory device can use the settings identified at 415 for accessing an SLC block to perform an access operation (e.g., perform a read, write, or erase operation). For example, the settings may correspond to dynamic SLC, static SLC, high-endurance SLC, or PSA SLC. The settings may include one or more operating parameters for performing the access operation. In some cases, the one or more operating parameters include a voltage applied during the access operation, the duration of the voltage applied during the access operation, a reference voltage for the access operation, a programming verification command for the access operation, or any combination thereof, and other examples. The memory device can use one or more operating parameters of the indicated settings to perform access operations on one or more memory cells of the indicated SLC block.

[0103] In some cases, an access command can be an instance of a read command. In such cases, performing an access operation may involve using the settings of the SLC block to determine the state of the SLC block and, in response to the access command, posting an indication of the SLC block's state to the memory system. In other cases, an access command can be an instance of a write command or an erase command. In such cases, performing an access operation may involve applying a voltage to the SLC block using the settings of the SLC block to change the logic state indicated by the memory cells of the SLC block (e.g., changing it to "1" or "0").

[0104] In some cases, an access command may not correspond to an SLC block. In such cases (e.g., if it is determined at 410 that the access command corresponds to a multi-level cell block), the address can be identified at 425. For example, the memory device may determine that the access command corresponds to a multi-level cell block, and therefore include one or more additional bits in the access command indicating at least a portion of the page address (e.g., referring to...). Figure 2 The page address bits PA11 and PA10 are described. The memory device may use one or more bits corresponding to one or more bit indices indicating settings in an SLC access command to determine the address of a multilevel cell access command.

[0105] At 430, an access command can be executed. For example, the memory device can execute an access command (e.g., perform a read, write, or erase operation) on one or more multi-level memory cells indicated by an address (containing the one or more bits) included in the access command.

[0106] Various aspects of process flow 400 may be implemented by a controller and other components. Alternatively, aspects of process flow 400 may be implemented as instructions stored in memory (e.g., firmware stored in memory coupled to a memory device). For example, if the instructions are executed by a controller (e.g., local controller 135), the controller may perform the operation of process flow 400.

[0107] Figure 5 This document describes an example of a set of memory cells 500 supporting setting switching for SLC, based on the examples disclosed herein. The set of memory cells 500 may include: a first partition 505, where a first setting is used for access operations on blocks (e.g., first setting block 510); and a second partition 515, where a second setting is used for access operations on blocks (e.g., second setting block 520). Rows in the first partition 505 and the second partition 515 may correspond to block addresses or block identifiers (IDs), while columns in the first partition 505 and the second partition 515 may correspond to plane addresses or plane IDs. That is, memory cell blocks within the same row may share a block address but may reside in separate planes of the memory device. For example, the first setting may be a static setting, while the second setting may be a dynamic setting. That is, the first setting block 510 may be a memory block programmed using static settings, and the second setting block 520 may be a memory block programmed using dynamic settings (e.g., see reference 510). Figure 1 (Described static and dynamic settings). In some instances, a memory device including the set of memory cells 500 may support a system plus an EM1 partition using a first setting (e.g., static SLC tuning), a normal partition using a second setting (e.g., dynamic SLC tuning), an EM2 partition using a third setting (e.g., high-durability SLC tuning), or a combination thereof.

[0108] In some cases, one or more blocks of the first partition 505, the second partition 515, or both may be instances of bad block 525. That is, the data stored in bad block 525 may be corrupted, or bad block 525 may be corrupted and may no longer be reliable. In such cases, the memory device may transfer the data stored in bad block 525 to replacement block 530. The memory device may use the same settings that were used to initially write data to bad block 525 to write data to replacement block 530. For example, the physical address of the written data may be changed, but the virtual or logical address may not be changed, because replacement block 530 can be treated as the replaced bad block 525. In some cases, bad block 525 may be replaced by replacement block 530 in the same plane as bad block 525 (e.g., corresponding to the same column of the set of memory cells 500).

[0109] In some instances, the memory system can perform multi-plane operations. That is, the memory system can perform access operations (e.g., read, write, or erase operations) on blocks that span different planes (e.g., access operations on blocks corresponding to the same block ID that span multiple planes).

[0110] In some cases, a memory system may use a block address range scheme to determine the settings for multi-plane operations. The block address range scheme determines the settings using the physical address of the block, and the same settings may be used across multiple planes of the multi-plane operation (e.g., each plane). However, if a bad block (e.g., bad block 525-a in the first plane and second partition 515) has been replaced by a replacement block 530 (e.g., 535-a replaced by replacement block 530-a in the first plane and first partition 505), the settings for each block included in the multi-plane operation may not correspond to the same settings. In such cases, the memory system may use, for example, the settings corresponding to one of the blocks in the multi-plane operation for each block of the multi-plane operation. Therefore, the block address scheme allows access operations (e.g., read, write, or erase operations) to be performed on memory cell blocks using settings different from those used for previously written to memory cell blocks. For example, if a block addressing scheme is used, even if the block is physically located in the first partition 505, data initially written to the faulty block 525-a can be moved to the replacement block 530-a, and the data in the replacement block 530-a can be written using the second setting. If the memory device performs a multi-plane access operation on row 540, the memory device can identify the replacement block 530-a and determine to use the first setting because the replacement block 530-a is located in the first partition 505. Therefore, the multi-plane access operation can use the first setting to access the second setting block 520-a. However, if the memory device performs a single-plane access operation on the second setting block 520-a, the memory device can determine to use the second setting because the second setting block 520-a is located in the second partition 515. Therefore, such a scheme may result in the use of mismatched settings for the block. In some cases, mismatched settings may cause the memory device to read the block using a voltage threshold different from the voltage used for writing, or to improperly adjust the voltage used for write or erase operations, resulting in an unexpected voltage distribution.

[0111] However, in contrast, the memory system can instead specify the settings for the access operation in the access command, allowing the memory device to avoid using mismatched settings for access operations. For example, see reference... Figures 1 to 4As described, the memory system can modify SLC access commands to indicate settings for performing access operations. Therefore, the memory system can indicate the same settings (e.g., a second setting) for a multi-plane access operation at row 540, a single-plane access operation for a second-setting block 520-a, and a single-plane access operation for replacing block 530-a, such that the memory device accesses the block using the same operating parameters corresponding to the indicated settings. Using one or more bits to indicate settings in the access command allows for reading from and writing to memory cell blocks using the same settings, which improves performance by reducing the likelihood of read errors, increasing read speed in the event of a failed access command, and reducing power consumption associated with performing additional operations. Alternatively, the memory device can support increased flexibility in replacing bad block 525, as bad block 525 can be replaced from any pool (e.g., partition) of fresh blocks (e.g., blocks that can be used to replace block 530), regardless of the pool in which bad block 525 is located.

[0112] Figure 6 A block diagram 600 illustrates a memory system 620 supporting setting switching for SLC, based on an example disclosed herein. The memory system 620 may be a reference... Figures 1 to 5 Examples of various aspects of the described memory system. Memory system 620 or its various components may be examples of constructs for executing various aspects of setting switching during the operation of SLC using access commands as described herein. For example, memory system 620 may include command manager 625, address manager 630, partition manager 635, setting manager 640, or any combination thereof. Each of these components may communicate with each other directly or indirectly (e.g., via one or more buses).

[0113] Command manager 625 may be configured or otherwise supported to support means for receiving access commands for a memory device from a host system. Address manager 630 may be configured or otherwise supported to support means for determining whether an access command corresponds to an SLC of the memory device. In some instances, address manager 630 may be configured or otherwise supported to modify an access command to include one or more bits indicating settings for accessing one or more memory cells of the SLC block, at least in part based on (e.g., in response to) determining that the access command corresponds to an SLC. In some instances, command manager 625 may be configured or otherwise supported to issue an access command containing one or more bits indicating settings for the SLC block to the memory device, at least in part based on said modification (e.g., using an access command generated by said modification).

[0114] In some instances, the address manager 630 may be configured or otherwise supported for determining, at least in part, based on (e.g., in response to) whether an access command corresponds to an SLC, whether the one or more bits are a setting indicating access to an SLC block or an element indicating at least a portion of a page address.

[0115] In some instances, the one or more bits correspond to one or more bit indices for the access command. In some instances, the one or more bit indices are configured to indicate settings for accessing an SLC block when the access command corresponds to an SLC, or to indicate at least a portion of the page address when the access command corresponds to a multi-level unit.

[0116] In some instances, the command manager 625 may be configured or otherwise supported to support means for receiving additional access commands for a memory device from a host system. In some instances, the address manager 630 may be configured or otherwise supported to support means for determining whether an additional access command corresponds to an additional SLC of the memory device. In some instances, the address manager 630 may be configured or otherwise supported to support means for determining, at least in part, based on (e.g., in response to) determining that the additional access command fails to correspond to an additional SLC, that the additional access command contains one or more additional bits corresponding to one or more bit indices that are the same as the one or more bits, the additional one or more bits indicating at least a portion of the page address of a multi-level cell block.

[0117] In some instances, partition manager 635 may be configured or otherwise supported to include means for selecting partitions of a plurality of SLCs at least in part based on (e.g., using) usage data of the host system. In some instances, settings manager 640 may be configured or otherwise supported to include means for determining settings for an SLC block at least in part based on the selected partition (e.g., indicated by the selected partition), wherein access commands are modified to include one or more bits indicating settings for the SLC block that are further at least in part based on the determination of said settings (e.g., executed according to the determination of said settings).

[0118] In some instances, the command manager 625 may be configured or otherwise supported to receive a prefix command indicating an SLC mode from the host system prior to receiving the access command, wherein determining that the access command corresponds to an SLC is at least in part based on the prefix command indicating the SLC mode (e.g., determined using the prefix command).

[0119] In some instances, the settings for accessing SLC blocks are limited to one or more operation parameters for the access operation corresponding to the access command.

[0120] In some instances, the one or more operating parameters include a voltage applied during the access operation, the duration of the voltage applied during the access operation, a reference voltage for the access operation, a programming verification command for the access operation, or any combination thereof.

[0121] In some instances, the settings for SLC blocks include dynamic SLC, static SLC, high-durability SLC, or PSA SLC.

[0122] In some instances, the access command may also include a first one or more bits indicating CA, a second one or more bits indicating PA, a third one or more bits indicating PS, a fourth one or more bits indicating BA, a fifth one or more bits indicating LA, or any combination thereof.

[0123] In some instances, access commands include read commands, write commands, or erase commands.

[0124] Figure 7 A block diagram 700 illustrates a memory device 720 supporting setting switching for SLC according to an example disclosed herein. The memory device 720 may be as described in the reference... Figures 1 to 5 Examples of various aspects of the described memory device. Memory device 720 or its various components may be examples of components used to execute various aspects of setting switching for SLC operation using access commands as described herein. For example, memory device 720 may include command manager 725, address manager 730, operation manager 735, read manager 740, write manager 745, or any combination thereof. Each of these components may communicate with each other directly or indirectly (e.g., via one or more buses).

[0125] Command manager 725 may be configured or otherwise supported to support means for receiving access commands from the memory system. Address manager 730 may be configured or otherwise supported to support means for determining whether an access command corresponds to an SLC of the memory device. In some instances, command manager 725 may be configured or otherwise supported to support means for performing an access operation corresponding to an access command, at least in part based on (e.g., in response to) determining that the access command corresponds to an SLC, using settings for the SLC block indicated by one or more bits of the access command.

[0126] In some instances, the address manager 730 may be configured or otherwise supported for determining, at least in part, based on (e.g., in response to) whether an access command corresponds to an SLC, whether one or more bits of the access command indicate a setting for an SLC block or at least a component indicating a PA.

[0127] In some instances, the one or more bits correspond to one or more bit indices for the access command. In some instances, the one or more bit indices are configured to indicate settings for an SLC block when the access command corresponds to an SLC, or to indicate at least a portion of the PA when the access command corresponds to a multi-level unit.

[0128] In some instances, command manager 725 may be configured or otherwise supported to support means for receiving additional access commands from the memory system. In some instances, address manager 730 may be configured or otherwise supported to support means for determining whether an additional access command corresponds to an additional SLC of the memory device. In some instances, command manager 725 may be configured or otherwise supported to support means for performing an additional access operation corresponding to a PA indicated by one or more additional bits of the additional access command, at least in part based on (e.g., in response to) determining that the additional access command does not correspond to an additional SLC, wherein the one or more additional bits correspond to one or more bit indices that are the same as the one or more bits.

[0129] In some instances, to support the execution of access operations, the operation manager 735 may be configured or otherwise support components for using one or more operation parameters defined by the settings of the SLC block for the access operations.

[0130] In some instances, the one or more operating parameters include a voltage applied during the access operation, the duration of the voltage applied during the access operation, a reference voltage for the access operation, a programming verification command for the access operation, or any combination thereof.

[0131] In some instances, an access command may be an instance of a read command. In some instances, to support the execution of access operations, the read manager 740 may be configured or otherwise supported to support components for determining the state of an SLC block at least in part based on (e.g., using) settings for the SLC block. In some instances, to support the execution of access operations, the read manager 740 may be configured or otherwise supported to support components for issuing indications of the state of the SLC block to the memory system in response to access commands.

[0132] In some instances, the access command may be an instance of a write command or an erase command. In some instances, to support the execution of access operations, the write manager 745 may be configured or otherwise supported for applying voltage to the SLC block at least in part based on (e.g., using) set and access commands for the SLC block.

[0133] In some instances, the settings for SLC blocks include dynamic SLC, static SLC, high-durability SLC, or PSA SLC.

[0134] In some instances, the access command may also include a first one or more bits indicating CA, a second one or more bits indicating PA, a third one or more bits indicating PS, a fourth one or more bits indicating BA, a fifth one or more bits indicating LA, or any combination thereof.

[0135] Figure 8 The flowchart illustrates a method 800 for supporting setting switching for SLC, based on the examples disclosed herein. The operation of method 800 can be implemented by the memory system or its components described herein. For example, the operation of method 800 can be implemented by reference to... Figures 1 to 6 The described memory system performs the function. In some instances, the memory system may execute a set of instructions to control the functional elements of the device to perform the described function. Alternatively, the memory system may use dedicated hardware to perform aspects of the described function.

[0136] At 805, the method may include receiving an access command for a memory device from a host system. Operation of 805 may be performed according to the examples disclosed herein. In some instances, aspects of the operation of 805 may be referenced. Figure 6 The command manager 625 described is executed.

[0137] At 810, the method may include determining whether an access command corresponds to an SLC of a memory device. The operation of 810 can be performed according to the examples disclosed herein. In some instances, aspects of the operation of 810 may be referenced... Figure 6 The address manager 630 described is executed.

[0138] At 815, the method may include modifying the access command, at least in part, based on (e.g., in response to) determining that the access command corresponds to an SLC, to include one or more bits indicating settings for accessing one or more memory cells of the SLC block. Operation of 815 may be performed according to the examples disclosed herein. In some instances, aspects of the operation of 815 may be referenced from... Figure 6 The address manager 630 described is executed.

[0139] At 820, the method may include issuing an access command to the memory device, at least in part, based on the modification (e.g., using an access command generated by the modification), containing one or more bits indicating settings for the SLC block. Operation of 820 may be performed according to the examples disclosed herein. In some instances, aspects of the operation of 820 may be referenced from... Figure 6 The command manager 625 described is executed.

[0140] Aspects of method 800 may be implemented by a controller and other components. Alternatively, aspects of method 800 may be implemented as instructions stored in memory (e.g., firmware stored in memory coupled to a memory system). For example, the instructions, when executed by a controller (e.g., memory system controller 115 or memory system controller 215), may cause the controller to perform the operation of method 800.

[0141] In some instances, the device described herein may perform one or more methods, such as method 800. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: receiving an access command for a memory device from a host system; determining whether the access command corresponds to a Single Memory Block (SLC) of the memory device; modifying the access command, at least in part based on (e.g., in response to) determining that the access command corresponds to an SLC, to include one or more bits indicating settings for accessing one or more memory cells of the SLC block; and issuing an access command to the memory device, at least in part based on the modification (e.g., using an access command generated by the modification), including the one or more bits indicating settings for the SLC block.

[0142] Method 800 and some examples of the devices described herein may further include operations, features, circuit systems, logic, components, or instructions for determining, at least in part, whether the one or more bits indicate a setting for accessing an SLC block or at least a portion of a PA, based on (e.g., in response to) determining whether the access command corresponds to an SLC.

[0143] In some instances of method 800 and the device described herein, the one or more bits correspond to one or more bit indices for an access command, and the one or more bit indices may be configured to indicate settings for accessing an SLC block when the access command corresponds to an SLC, or to indicate at least a portion of a PA when the access command corresponds to a multi-level unit.

[0144] Method 800 and some examples of the devices described herein may further include operations, features, circuitry, logic, components, or instructions for: receiving an additional access command for a memory device from a host system; determining whether the additional access command corresponds to an additional SLC of the memory device; and determining, at least in part, based on (e.g., in response to) determining that the additional access command fails to correspond to an additional SLC, that the additional access command contains one or more additional bits corresponding to one or more bit indices that are the same as the one or more bits, the additional one or more bits indicating at least a portion of the PA of a multi-level cell block.

[0145] Method 800 and some examples of the apparatus described herein may further include operations, features, circuitry, logic, components, or instructions for: selecting partitions of a plurality of SLCs at least in part based on (e.g., using) usage data of a host system; and determining settings for an SLC block at least in part based on (e.g., according to) the selected partitions, wherein modifying an access command to include one or more bits indicating settings for the SLC block may further be at least in part based on (e.g., in response to) determining said settings.

[0146] Method 800 and some instances of the device described herein may further include operations, features, circuitry, logic, components, or instructions for receiving a prefix command indicating an SLC mode from a host system and prior to receiving an access command, wherein determining that the access command corresponds to an SLC may be based at least in part on (e.g., in response to) the prefix command indicating the SLC mode.

[0147] In method 800 and some instances of the device described herein, the settings for accessing the SLC block are limited to one or more operation parameters for the access operation corresponding to the access command.

[0148] In some instances of method 800 and the device described herein, the one or more operating parameters include a voltage applied during the access operation, the duration of the voltage applied during the access operation, a reference voltage for the access operation, a programming verification command for the access operation, or any combination thereof.

[0149] In some instances of method 800 and the devices described herein, the settings for the SLC block include dynamic SLC, static SLC, high-durability SLC, or PSA SLC.

[0150] In some instances of method 800 and the devices described herein, the access command further includes a first one or more bits indicating CA, a second one or more bits indicating PA, a third one or more bits indicating PS, a fourth one or more bits indicating BA, a fifth one or more bits indicating LA, or any combination thereof.

[0151] In method 800 and some instances of the device described herein, the access command includes a read command, a write command, or an erase command.

[0152] Figure 9 The flowchart illustrates a method 900 for supporting setting switching for SLC, based on the examples disclosed herein. Operation of method 900 can be implemented by the memory device or its components described herein. For example, it can be implemented by reference... Figures 1 to 5The memory device described in section 7 performs the operation of method 900. In some instances, the memory device may execute a set of instructions to control the functional elements of the device to perform the described functions. Alternatively, the memory device may use dedicated hardware to perform aspects of the described functions.

[0153] At 905, the method may include receiving an access command from a memory system. The operation of 905 can be performed according to the examples disclosed herein. In some instances, aspects of the operation of 905 may be derived from references... Figure 7 The command manager 725 described is executed.

[0154] At 910, the method may include determining whether an access command corresponds to an SLC of a memory device. The operation of 910 can be performed according to the examples disclosed herein. In some instances, aspects of the operation of 910 may be referenced... Figure 7 The address manager 730 described is executed.

[0155] At 915, the method may include performing an access operation corresponding to an access command based at least in part on (e.g., in response to) determining that the access command corresponds to an SLC, using settings for the SLC block indicated by one or more bits of the access command. The operation at 915 may be performed according to the examples disclosed herein. In some instances, aspects of the operation at 915 may be referenced from... Figure 7 The command manager 725 described is executed.

[0156] Aspects of method 900 may be implemented by a controller and other components. Alternatively, aspects of method 900 may be implemented as instructions stored in memory (e.g., firmware stored in memory coupled to a memory device). For example, if the instructions are executed by a controller (e.g., local controller 135), the controller may perform the operation of method 900.

[0157] In some instances, the device described herein may perform one or more methods, such as method 900. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: receiving an access command for a memory device from a host system; determining whether the access command corresponds to a SLC of the memory device; and performing an access operation corresponding to the access command, at least in part based on (e.g., in response to) determining that the access command corresponds to an SLC, using settings for the SLC block indicated by one or more bits of the access command.

[0158] Method 900 and some examples of the devices described herein may further include operations, features, circuitry, logic, components, or instructions for determining, at least in part, whether one or more bits of the access command indicate a setting for an SLC block or at least a portion of a PA, based on (e.g., in response to) determining whether the access command corresponds to an SLC.

[0159] In some instances of method 900 and the device described herein, the one or more bits correspond to one or more bit indices for an access command, and the one or more bit indices may be configured to indicate settings for an SLC block when the access command corresponds to an SLC, or to indicate at least a portion of a PA when the access command corresponds to a multi-level unit.

[0160] Method 900 and some examples of the devices described herein may further include operations, features, circuitry, logic, components, or instructions for: receiving an additional access command from a memory system; determining whether the additional access command corresponds to an additional SLC of the memory device; and performing an additional access operation corresponding to a PA indicated by one or more additional bits of the additional access command, at least in part based on (e.g., in response to) determining that the additional access command fails to correspond to an additional SLC, wherein the one or more additional bits correspond to one or more bit indices that are the same as the one or more bits.

[0161] In some instances of method 900 and the devices described herein, performing an access operation may include operations, features, circuitry, logic, components, or instructions to use one or more operating parameters defined by settings for the SLC block for the access operation.

[0162] In some instances of method 900 and the device described herein, the one or more operating parameters include a voltage applied during the access operation, the duration of the voltage applied during the access operation, a reference voltage for the access operation, a programming verification command for the access operation, or any combination thereof.

[0163] In some instances of method 900 and the device described herein, the access command may be an instance of a read command, and performing the access operation may include operations, features, circuitry, logic, components, or instructions for determining the state of the SLC block at least in part based on (e.g., using) settings for the SLC block and for issuing an indication of the state of the SLC block to the memory system in response to the access command.

[0164] In some instances of method 900 and the device described herein, the access command may be an instance of a write command or an erase command, and performing the access operation may include operations, features, circuitry, logic, components, or instructions for applying voltage to the SLC block at least in part based on (e.g., using) set and access commands for the SLC block.

[0165] In some instances of method 900 and the devices described herein, the settings for the SLC block include dynamic SLC, static SLC, high-durability SLC, or PSA SLC.

[0166] In some instances of method 900 and the devices described herein, the access command further includes a first one or more bits indicating CA, a second one or more bits indicating PA, a third one or more bits indicating PS, a fourth one or more bits indicating BA, a fifth one or more bits indicating LA, or any combination thereof.

[0167] It should be noted that the methods described above describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, portions of two or more methods described may be combined.

[0168] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, the signal may represent a bus of signals, which may have various bit widths.

[0169] The terms “electronic connectivity,” “conductive contact,” “connection,” and “coupling” can refer to a relationship between components that enables the flow of signals between them. Components are considered to be electronically connected (or electrically contacting, connected, or coupled) to each other if any conductive path exists between them that enables the flow of signals between them at any given time. At any given time, the conductive path between components that are electronically connected (or electrically contacting, connected, or coupled) can be an open or closed circuit based on (e.g., using) the operation of a device containing the connected components. The conductive path between connected components can be a direct conductive path between components, or it can be an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some instances, one or more intermediate components, such as switches or transistors, may be used to interrupt the signal flow between connected components for a period of time.

[0170] The term "coupling" refers to the condition that moves from an open-circuit relationship between components to a closed-circuit relationship. In an open-circuit relationship, signals cannot currently be transmitted between components via a conductive path, while in a closed-circuit relationship, signals can be transmitted between components via a conductive path. If a component, such as a controller, couples other components together, that component initiates a change to allow signals to flow between the other components via conductive paths that were previously not permitted.

[0171] The term "isolation" refers to a relationship between components in which signals cannot currently flow between them. If an open circuit exists between components, the components are separated from each other. For example, components separated by a switch positioned between two components are isolated from each other when the switch is open. If a controller isolates two components, the controller implements a change to prevent signals from flowing between the components using previously permitted conductive paths.

[0172] The terms “if,” “when,” “based on,” or “at least partially based on” are used interchangeably. In some instances, the terms “if,” “when,” “based on,” or “at least partially based on” are used to describe a connection between conditional actions, conditional processes, or parts of a process.

[0173] The term "in response to" can refer to a condition or action that occurs at least partially (if not completely) as a result of a preceding condition or action. For example, a first condition or action may be performed, and a second condition or action may occur at least partially as a result of a preceding condition or action (whether directly after the first condition or action or after one or more other intermediate conditions or actions following the first condition or action).

[0174] Additionally, the terms "directly in response to" or "directly in response to" can refer to a condition or action that occurs as a direct result of a previous condition or action. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of a previous condition or action, regardless of whether other conditions or actions occur. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of a previous condition or action, such that no other intermediate conditions or actions occur between the earlier condition or action and the second condition or action, or a limited number of one or more intermediate steps or actions occur between the earlier condition or action and the second condition or action. Unless otherwise specified, any condition or action described herein as being performed "based on," "at least in part based on," or "in response to" some other step, action, event, or condition may additionally or alternatively (e.g., in alternative instances) be performed "directly in response to" or "directly in response to" such other conditions or actions.

[0175] The devices, including memory arrays, discussed herein can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, and gallium nitride. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemicals including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0176] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include a three-terminal device comprising a source, drain, and gate. Each terminal may be connected to other electronic components via a conductive material, such as a metal. The source and drain may be conductive and may include heavily doped semiconductor regions, such as degenerate semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., the majority carriers are electrons), the FET may be called an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), the FET may be called a p-type FET. The channel may be capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, makes the channel conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "on" or "activated." If a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "off" or "deactivated."

[0177] The descriptions herein, illustrated with reference to the accompanying drawings, depict exemplary configurations and do not represent all implementable or claim-scoped instances. The term "exemplary" as used herein means "serving as an example, illustration, or diagram" and is not necessarily "preferred" or "superior to other instances." The detailed description includes specific details that provide an understanding of the described techniques. However, embodiments may be practiced without these specific details. In some cases, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0178] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by a hyphen following the reference numeral and a second numeral for differentiation among similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components that have the same first reference numeral but are independent of the second reference numeral.

[0179] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored as one or more instructions or code on or transmitted over a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described above can be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functions can also be physically located in various locations, including distributed implementations such that portions of the functions are implemented in different physical locations.

[0180] For example, the various illustrative blocks and components described herein may be implemented or performed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller, or state machine. The processor may be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0181] As used herein, the "or" used in the claims (e.g., the list of items preceding, for example, "at least one of" or "one or more of") indicates an inclusive list, such that a list of at least one of, for example, A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Additionally, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should be understood in the same manner as the phrase "at least partially based on".

[0182] Computer-readable media includes both non-transitory computer storage media and communication media, wherein the communication media includes any media that facilitates the transfer of a computer program from one place to another. Non-transitory storage media can be any available media accessible by a general-purpose or special-purpose computer. By way of example, and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code components in the form of instructions or data structures and is accessible by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Additionally, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or technologies such as infrared, radio, and microwave are included in the definition of media. As used herein, disks and optical discs include CDs, laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of these are also included within the scope of computer-readable media.

[0183] The description herein is provided to enable those skilled in the art to make or use this disclosure. Various modifications to this disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but should be given the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus comprising: Memory devices; as well as A controller, coupled to the memory device and configured to cause the device to perform the following operations: Receive access commands for the memory device from the host system; Determine whether the access command corresponds to a single-level cell of the memory device; The access command is modified, at least in part, to include one or more bits indicating settings for accessing one or more memory cells in the single-level cell block, based on the determination that the access command corresponds to the single-level cell; and Based at least in part on the modification, an access command is issued to the memory device including one or more bits indicating the settings for the single-level cell block.

2. The device of claim 1, wherein the controller is further configured to cause the device to perform the following operations: At least in part, based on determining whether the access command corresponds to the single-level cell, it is determined whether the one or more bits indicate the setting for accessing the single-level cell block or at least a portion of the page address.

3. The device according to claim 2, wherein: The one or more bits correspond to one or more bit indices used for the access command; and The one or more bit indexes are configured to indicate the settings for accessing the single-level cell block when the access command corresponds to the single-level cell, or to indicate at least the portion of the page address when the access command corresponds to a multi-level cell.

4. The device of claim 1, wherein the controller is further configured to cause the device to perform the following operations: Receive additional access commands for the memory device from the host system; Determine whether the additional access command corresponds to an additional single-level cell of the memory device; and The additional access command is determined, at least in part, to include one or more additional bits corresponding to one or more bit indices that are the same as the one or more bits, based on the determination that the additional access command fails to correspond to the additional single-level cell, and the additional one or more bits indicating at least a portion of the page address of the multi-level cell block.

5. The device of claim 1, wherein the controller is further configured to cause the device to perform the following operations: Partitions of multiple single-level units are selected, at least in part, based on the usage data of the host system; and The settings for the single-level cell block are determined at least in part based on the selected partition, wherein modifying the access command to include one or more bits indicating the settings for the single-level cell block is also at least in part based on determining the settings.

6. The device of claim 1, wherein the controller is further configured to cause the device to perform the following operations: The host system receives a prefix command indicating a single-level cell pattern before receiving the access command, wherein the access command is determined to correspond to the single-level cell at least in part based on the single-level cell pattern indicated by the prefix command.

7. The device of claim 1, wherein the settings for accessing the single-level unit block define one or more operation parameters for the access operation corresponding to the access command.

8. The device of claim 7, wherein the one or more operating parameters include a voltage applied during the access operation, the duration for which the voltage is applied during the access operation, a reference voltage for the access operation, a programming verification command for the access operation, or any combination thereof.

9. The device of claim 1, wherein the arrangement for the single-level unit block includes a dynamic single-level unit, a static single-level unit, a high-durability single-level unit, or a state-aware single-level unit.

10. The device of claim 1, wherein the access command further includes a first or more bits indicating a column address, a second or more bits indicating a page address, a third or more bits indicating a plane configuration, a fourth or more bits indicating a block address, a fifth or more bits indicating a logic unit address, or any combination thereof.

11. The device of claim 1, wherein the access command includes a read command, a write command, or an erase command.

12. An apparatus comprising: Memory array; as well as A controller, coupled to the memory array and configured to enable the device to perform the following operations: Receive access commands from the memory system; Determine whether the access command corresponds to a single-level cell of the memory array; as well as At least in part, based on the determination that the access command corresponds to the single-level cell, the access operation corresponding to the access command is performed using the settings for the single-level cell block indicated by one or more bits of the access command.

13. The device of claim 12, wherein the controller is further configured to cause the device to perform the following operations: At least in part, based on determining whether the access command corresponds to the single-level cell, it is determined whether one or more bits of the access command indicate the setting for the single-level cell block or at least a portion of the page address.

14. The device according to claim 13, wherein: The one or more bits correspond to one or more bit indices used for the access command; and The one or more bit indexes are configured to indicate the settings for the single-level cell block when the access command corresponds to the single-level cell, or to indicate at least the portion of the page address when the access command corresponds to a multi-level cell.

15. The device of claim 12, wherein the controller is further configured to cause the device to perform the following operations: Receive additional access commands from the memory system; Determine whether the additional access command corresponds to an additional single-level cell of the memory array; and At least in part, based on the determination that the additional access command fails to correspond to the additional single-level unit, an additional access operation corresponding to the additional access command is performed for the page address indicated by one or more additional bits of the additional access command, wherein the one or more additional bits correspond to one or more bit indices that are the same as the one or more bits.

16. The device of claim 12, wherein the controller configured to cause the device to perform the access operation is configured to cause the device to perform the following operations: For the access operation, one or more operation parameters defined by the settings for the single-level cell block are used.

17. The device of claim 16, wherein the one or more operating parameters include a voltage applied during the access operation, a duration for which the voltage is applied during the access operation, a reference voltage for the access operation, a programming verification command for the access operation, or any combination thereof.

18. The device of claim 12, wherein the access command includes a read command, and the controller configured to cause the device to perform the access operation is configured to cause the device to perform the following operations: The state of the single-level cell block is determined at least in part based on the settings for the single-level cell block; and The system issues an indication of the state of the single-level cell block in response to the access command.

19. The device of claim 12, wherein the access command includes a write command or an erase command, and the controller configured to cause the device to perform the access operation is configured to cause the device to perform the following operations: The voltage is applied to the single-level cell block at least in part based on the settings and access commands for the single-level cell block.

20. The device of claim 12, wherein the arrangement for the single-level unit block includes a dynamic single-level unit, a static single-level unit, a high-durability single-level unit, or a state-aware single-level unit.

21. The device of claim 12, wherein the access command further includes a first or more bits indicating a column address, a second or more bits indicating a page address, a third or more bits indicating a plane configuration, a fourth or more bits indicating a block address, a fifth or more bits indicating a logic unit address, or any combination thereof.

22. A non-transitory computer-readable medium storing code comprising instructions that, when executed by a processor of an electronic device, cause the electronic device to perform the following operations: Receive access commands for the memory device from the host system; Determine whether the access command corresponds to a single-level cell of the memory device; The access command is modified, at least in part, to include one or more bits indicating settings for accessing one or more memory cells in the single-level cell block, based on the determination that the access command corresponds to the single-level cell; and Based at least in part on the modification, an access command is issued to the memory device including one or more bits indicating the settings for the single-level cell block.

23. The non-transitory computer-readable medium of claim 22, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to perform the following operations: At least in part, based on determining whether the access command corresponds to the single-level cell, it is determined whether the one or more bits indicate the setting for accessing the single-level cell block or at least a portion of the page address.

24. The non-transitory computer-readable medium according to claim 23, wherein: The one or more bits correspond to one or more bit indices used for the access command; and The one or more bit indexes are configured to indicate the settings for accessing the single-level cell block when the access command corresponds to the single-level cell, or to indicate at least the portion of the page address when the access command corresponds to a multi-level cell.

25. The non-transitory computer-readable medium of claim 22, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to perform the following operations: Receive additional access commands for the memory device from the host system; Determine whether the additional access command corresponds to an additional single-level cell of the memory device; as well as The additional access command is determined, at least in part, to include one or more additional bits corresponding to one or more bit indices that are the same as the one or more bits, based on the determination that the additional access command fails to correspond to the additional single-level cell, and the additional one or more bits indicating at least a portion of the page address of the multi-level cell block.

26. The non-transitory computer-readable medium of claim 22, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to perform the following operations: Partitions of multiple single-level units are selected, at least in part, based on the usage data of the host system; and The settings for the single-level cell block are determined at least in part based on the selected partition, wherein modifying the access command to include one or more bits indicating the settings for the single-level cell block is also at least in part based on determining the settings.

27. The non-transitory computer-readable medium of claim 22, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to perform the following operations: The host system receives a prefix command indicating a single-level cell pattern before receiving the access command, wherein the access command is determined to correspond to the single-level cell at least in part based on the single-level cell pattern indicated by the prefix command.

28. The non-transitory computer-readable medium of claim 22, wherein the settings for accessing the single-level cell block define one or more operation parameters for an access operation corresponding to the access command.

29. The non-transitory computer-readable medium of claim 28, wherein the one or more operating parameters include a voltage applied during the access operation, the duration for which the voltage is applied during the access operation, a reference voltage for the access operation, a programming verification command for the access operation, or any combination thereof.

30. The non-transitory computer-readable medium of claim 22, wherein the arrangement for the single-level unit block includes a dynamic single-level unit, a static single-level unit, a high-durability single-level unit, or a state-aware single-level unit.

31. A non-transitory computer-readable medium storing code comprising instructions that, when executed by a processor of an electronic device, cause the electronic device to perform the following operations: Receive access commands from the memory system; Determine whether the access command corresponds to a single-level cell of the memory device; and At least in part, based on the determination that the access command corresponds to the single-level cell, the access operation corresponding to the access command is performed using the settings for the single-level cell block indicated by one or more bits of the access command.

32. The non-transitory computer-readable medium of claim 31, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to perform the following operations: At least in part, based on determining whether the access command corresponds to the single-level cell, it is determined whether one or more bits of the access command indicate the setting for the single-level cell block or at least a portion of the page address.

33. The non-transitory computer-readable medium according to claim 32, wherein: The one or more bits correspond to one or more bit indices used for the access command; and The one or more bit indexes are configured to indicate the settings for the single-level cell block when the access command corresponds to the single-level cell, or to indicate at least the portion of the page address when the access command corresponds to a multi-level cell.

34. The non-transitory computer-readable medium of claim 31, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to perform the following operations: Receive additional access commands from the memory system; Determine whether the additional access command corresponds to an additional single-level cell of the memory device; and At least in part, based on the determination that the additional access command fails to correspond to the additional single-level unit, an additional access operation corresponding to the additional access command is performed for the page address indicated by one or more additional bits of the additional access command, wherein the one or more additional bits correspond to one or more bit indices that are the same as the one or more bits.

35. A method executed by a memory system, comprising: Receive access commands for the memory device from the host system; Determine whether the access command corresponds to a single-level cell of the memory device; The access command is modified, at least in part, to include one or more bits indicating settings for accessing one or more memory cells in the single-level cell block, based on the determination that the access command corresponds to the single-level cell; and Based at least in part on the modification, an access command is issued to the memory device including one or more bits indicating the settings for the single-level cell block.

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