Chip, chip testing method, and computer readable storage medium

Abstract

The present disclosure relates to a chip, a test method of the chip and a computer readable storage medium. It relates to the field of chip design. The chip comprises a plurality of interrupt interfaces, an interrupt test device and an internal bus, the interrupt test device is coupled with the plurality of interrupt interfaces through the internal bus, and the interrupt test device comprises: a selection module configured to select at least one target mode to be executed from a plurality of preset modes upon receiving a trigger signal, and select at least one target interrupt interface to be tested from the plurality of interrupt interfaces according to the target mode; an excitation module configured to send a test excitation to each target interrupt interface so as to start an interrupt service program corresponding to each target interrupt interface; and a test module configured to receive a result value returned by each interrupt service program, and output an interrupt test result of the target interrupt interface corresponding to the interrupt service program according to the result value.

Description

Technical Field

[0001] This disclosure relates to the field of chip design technology, and more specifically, to a chip, a chip testing method, and a computer-readable storage medium. Background Technology

[0002] An error in the interrupt on the Micro Control Unit (MCU) can cause abnormal behavior during MCU operation. To prevent this, it is necessary to test the interrupts on the MCU.

[0003] Currently, for MCU users, in order to obtain test results for interrupts on the MCU, it is necessary to design a corresponding interrupt test program for the MCU, so as to test whether there are any abnormalities in the interrupts on the MCU.

[0004] In practice, due to the need to ensure the accuracy of timing control and to consider various response mechanisms when MCU interrupts occur, the development process of the above test program is complex, inefficient, and costly. Furthermore, even if the test program corresponding to the MCU can be successfully obtained, the verification of interrupts on the MCU based on the test program can only be carried out in a separate test environment. It cannot be brought into the actual operating environment of the MCU, and it cannot verify the abnormal behavior that may occur in the actual operating environment, which has significant limitations. Summary of the Invention

[0005] One object of this disclosure is to provide a new technical solution for a chip.

[0006] According to a first aspect of this disclosure, a chip is provided. The chip includes multiple interrupt interfaces, an interrupt testing device, and an internal bus. The interrupt testing device is coupled to the multiple interrupt interfaces via the internal bus. The interrupt testing device includes: a selection module, configured to select at least one target mode to be executed from multiple preset modes upon receiving a trigger signal, and select at least one target interrupt interface to be tested from the multiple interrupt interfaces according to the target mode; a stimulus module, configured to send a test stimulus to each target interrupt interface to start the interrupt service routine corresponding to each target interrupt interface; and a test module, configured to receive the result value returned by each interrupt service routine and output the interrupt test result of the target interrupt interface corresponding to the interrupt service routine based on the result value.

[0007] Optionally, the multiple preset modes include a first mode, and the selection module is specifically used to: when the target mode is the first mode, select the target interrupt interface to be tested from multiple interrupt interfaces in sequence according to the first mode.

[0008] Optionally, the multiple preset modes include a second mode. The selection module is specifically used to: when the target mode is the second mode, determine at least one first interrupt interface from multiple interrupt interfaces according to the second mode, and sequentially select the target interrupt interface to be tested from the at least one first interrupt interface; the test module is further used to: obtain the number of tests for the target interrupt interface from the selection module before receiving the result value returned by each interrupt service routine; after outputting the interrupt test result of the target interrupt interface corresponding to the interrupt service routine according to the result value, obtain the number of consecutive starts of the interrupt service routine corresponding to the target interrupt interface; and, if the number of consecutive starts is less than the number of tests, jump to the stimulus module so that the stimulus module sends a test stimulus to the target interrupt interface again to start the interrupt service routine corresponding to the target interrupt interface.

[0009] Optionally, the multiple preset modes include a third mode. The selection module is specifically used for: when the target mode is the third mode, determining at least one set of interrupt interface groups based on the third mode among multiple interrupt interfaces, each interrupt interface group including multiple second interrupt interfaces, and each second interrupt interface having a different priority; and sequentially selecting the target interrupt interface group to be tested from the at least one set of interrupt interface groups, taking each second interrupt interface in the target interrupt interface group as the target interrupt interface, thus obtaining multiple target interrupt interfaces. The testing module is specifically used for: receiving the result values ​​returned by multiple target interrupt service routines corresponding to the multiple target interrupt interfaces; sorting the multiple target interrupt interfaces according to the time of the return result values ​​of the multiple target interrupt service routines in chronological order to obtain a first order; and sorting the multiple target interrupt interfaces according to the order of priority from high to low to obtain a second order, and determining the interrupt test result based on the first order and the second order.

[0010] Optionally, the chip further includes: a first timing module, configured to start timing in response to a first timing trigger event; and to generate a first test stimulus trigger signal if the timing duration exceeds a preset first timing duration; wherein the first timing trigger event is that the selection module selects at least one target interrupt interface to be tested from multiple interrupt interfaces according to a target mode; the stimulus module is specifically configured to, in response to the first test stimulus trigger signal, send a test stimulus to each target interrupt interface so as to start the interrupt service routine corresponding to each target interrupt interface.

[0011] Optionally, the chip further includes: a second timing module, configured to start timing in response to a second timing trigger event; wherein the second timing trigger event is that the selection module selects each second interrupt interface in the target interrupt interface group as a target interrupt interface, resulting in multiple target interrupt interfaces; and, when the timing duration reaches the second timing duration corresponding to the target interrupt interface under test, generating a second test stimulus trigger signal corresponding to the target interrupt interface under test; wherein the target interrupt interface under test is any one of the multiple target interrupt interfaces; the stimulus module is specifically configured to, in response to the second test stimulus trigger signal corresponding to the target interrupt interface under test, send a test stimulus to the target interrupt interface under test, so as to start the interrupt service routine corresponding to the target interrupt interface under test.

[0012] According to a second aspect of this disclosure, a chip testing method is also provided. The chip includes multiple interrupt interfaces, an interrupt testing device, and an internal bus. The interrupt testing device is coupled to the multiple interrupt interfaces via the internal bus. The method includes: upon receiving a trigger signal, selecting at least one target mode to be executed from multiple preset modes; selecting at least one target interrupt interface to be tested from the multiple interrupt interfaces according to the target mode; sending a test stimulus to each target interrupt interface to start the interrupt service routine corresponding to each target interrupt interface; receiving the result value returned by each interrupt service routine; and outputting the interrupt test result of the target interrupt interface corresponding to the interrupt service routine based on the result value.

[0013] Optionally, the multiple preset modes include a first mode, and selecting at least one target interrupt interface to be tested from multiple interrupt interfaces according to the target mode includes: when the target mode is the first mode, sequentially selecting the target interrupt interface to be tested from multiple interrupt interfaces according to the first mode.

[0014] Optionally, the multiple preset modes include a second mode. Selecting at least one target interrupt interface to be tested from multiple interrupt interfaces according to the target mode includes: when the target mode is the second mode, determining at least one first interrupt interface from the multiple interrupt interfaces according to the second mode, and sequentially selecting the target interrupt interface to be tested from the at least one first interrupt interface; before receiving the result value returned by each interrupt service routine, the method further includes: obtaining the number of tests for the target interrupt interface from the selection module; after outputting the interrupt test result of the target interrupt interface corresponding to the interrupt service routine based on the result value, the method further includes: obtaining the number of consecutive starts of the interrupt service routine corresponding to the consecutively started target interrupt interface; and, if the number of consecutive starts is less than the number of tests, jumping to the stimulus module so that the stimulus module sends a test stimulus to the target interrupt interface again to start the interrupt service routine corresponding to the target interrupt interface.

[0015] Optionally, the multiple preset modes include a third mode. Selecting at least one target interrupt interface to be tested from multiple interrupt interfaces according to the target mode includes: when the target mode is the third mode, determining at least one group of interrupt interfaces from the multiple interrupt interfaces according to the third mode, each interrupt interface group including multiple second interrupt interfaces, and each second interrupt interface having a different priority; and sequentially selecting the target interrupt interface group to be tested from the at least one group of interrupt interfaces, taking each second interrupt interface in the target interrupt interface group as the target interrupt interface, thus obtaining multiple target interrupt interfaces; receiving the result value returned by each interrupt service routine, and outputting the interrupt test result of the target interrupt interface corresponding to the interrupt service routine based on the result value, including: receiving the result values ​​returned by multiple target interrupt service routines corresponding to the multiple target interrupt interfaces; sorting the multiple target interrupt interfaces according to the time of the return result values ​​of the multiple target interrupt service routines in the order of the time from first to last, thus obtaining a first order; and sorting the multiple target interrupt interfaces according to the order of priority from high to low, thus obtaining a second order, and determining the interrupt test result based on the first order and the second order.

[0016] Optionally, the method further includes: responding to a first timing trigger event to start timing; and generating a first test stimulus trigger signal if the timing duration exceeds a preset first timing duration; wherein the first timing trigger event is that the selection module selects at least one target interrupt interface to be tested from multiple interrupt interfaces according to the target mode; sending a test stimulus to each target interrupt interface to start the interrupt service routine corresponding to each target interrupt interface, including: responding to the first test stimulus trigger signal to send a test stimulus to each target interrupt interface to start the interrupt service routine corresponding to each target interrupt interface.

[0017] Optionally, the method further includes: responding to a second timing trigger event to start timing; wherein the second timing trigger event is that the selection module selects each second interrupt interface in the target interrupt interface group as a target interrupt interface, resulting in multiple target interrupt interfaces; and generating a second test stimulus trigger signal corresponding to the target interrupt interface under test when the timing duration reaches the second timing duration corresponding to the target interrupt interface under test; wherein the target interrupt interface under test is any interrupt interface among the multiple target interrupt interfaces; sending a test stimulus to each target interrupt interface to start the interrupt service routine corresponding to each target interrupt interface, including: responding to the second test stimulus trigger signal corresponding to the target interrupt interface under test, sending a test stimulus to the target interrupt interface under test to start the interrupt service routine corresponding to the target interrupt interface under test.

[0018] According to a third aspect of this disclosure, a computer-readable storage medium is also provided, on which a computer program is stored, which, when executed by a processor, implements the method according to a second aspect of this disclosure.

[0019] One beneficial effect of this disclosure is that it provides a chip that carries its own interrupt testing function. In this case, chip users no longer need to design corresponding interrupt test programs for the chip in order to obtain test results for interrupts on the chip. This not only avoids the problems of complex operation, low efficiency and high cost in the development process of test programs, but also enables the testing of interrupts on the chip in the actual operating environment, bringing many conveniences to the use of the chip.

[0020] Other features and advantages of the embodiments of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0021] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments of the present disclosure and, together with their description, serve to explain the principles of the embodiments of the present disclosure.

[0022] Figure 1 A schematic diagram of a chip structure is provided for a disclosed embodiment;

[0023] Figure 2 A schematic diagram of another chip structure provided for a disclosed embodiment;

[0024] Figure 3 A schematic diagram of another chip structure provided for a disclosed embodiment;

[0025] Figure 4 A flowchart of a chip testing method provided for a disclosed embodiment;

[0026] Figure 5 This is a schematic diagram of the hardware structure of an interrupt testing device provided in a public embodiment. Detailed Implementation

[0027] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the invention.

[0028] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the invention or its application or use.

[0029] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0030] In all the examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.

[0031] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0032] <Equipment Example>

[0033] Figure 1 This is a schematic diagram of a chip structure provided in an embodiment of this disclosure. Figure 1 As shown, chip 10 includes multiple interrupt interfaces 11, an interrupt test device 12, and an internal bus 13. The interrupt test device 12 is coupled to the multiple interrupt interfaces 11 via the internal bus 13.

[0034] In some examples, such as Figure 1 As shown, the plurality of interrupt interfaces 11 may include at least one internal interrupt interface and at least one external interrupt interface. At least one internal interrupt interface is, for example... Figure 1 Interrupt interfaces I1 to Im, at least one external interrupt interface, for example Figure 1 Interrupt interfaces I(m+1)~In are defined in the code; where n>m>0, and n and m are natural numbers.

[0035] Interrupt interface 11 is a hardware interface, such as a pin set on chip 10.

[0036] like Figure 1 As shown, the interruption test device 12 includes: a selection module 121, an excitation module 122, and a test module 123.

[0037] Selection module 121 is used to select at least one or more target modes to be executed from multiple preset modes when a trigger signal is received, and to select at least one target interrupt interface to be tested from multiple interrupt interfaces according to the target mode.

[0038] The stimulus module 122 is used to send test stimuli to each target interrupt interface so as to start the interrupt service routine corresponding to each target interrupt interface.

[0039] Test module 123 is used to receive the result value returned by each interrupt service routine and output the interrupt test result of the target interrupt interface corresponding to the interrupt service routine based on the result value.

[0040] In some examples, such as Figure 1 As shown, a timer 14 can be set to send the aforementioned trigger signal to the selection module 121. The period for the timer to send the trigger signal can be set by those skilled in the art according to actual conditions, and this embodiment does not limit this.

[0041] In other examples, the trigger signal can be the chip's startup signal.

[0042] In some embodiments, the multiple preset modes in the selection module 121 include a first mode. In this case, the selection module 121 is specifically used to: when the target mode is the first mode, sequentially select the target interrupt interface to be tested from multiple interrupt interfaces according to the first mode.

[0043] For example, such as Figure 1 As shown, the multiple interrupt interfaces 11 include interrupt interfaces I1 to In. In the first mode, one of the interrupt interfaces I1 to In can be selected as the target interrupt interface in a first preset order. The first preset order can be set by those skilled in the art according to actual conditions, and this embodiment does not limit it.

[0044] After that, the test stimulus is sent to the target interrupt interface selected in the selection module 121 through the stimulus module 122 so as to start the interrupt service routine corresponding to the target interrupt interface.

[0045] The test module 123 receives the result value returned by each interrupt service routine and outputs the interrupt test result of the target interrupt interface corresponding to the interrupt service routine based on the result value.

[0046] For example, the result value returned by the interrupt service routine includes 1 and 0. If the result value returned by the interrupt service routine is 1, it means that the interrupt service routine is running normally, and a signal indicating that the interrupt test result is normal is output; if the result value returned by the interrupt service routine is 0, it means that the interrupt service routine is running abnormally, and a signal indicating that the interrupt test result is abnormal is output.

[0047] For example, see Figure 1As shown, in the first mode, the selection module 121 sequentially selects interrupt interface I1, interrupt interface I2...interrupt interface In from multiple interrupt interfaces as the target interrupt interface. In this case, the excitation module 122 sequentially sends test excitations to interrupt interface I1, interrupt interface I2...interrupt interface In in order to start the interrupt service routine corresponding to the target interrupt interface. Finally, the test module 123 sequentially receives the result values ​​returned by the interrupt service routines corresponding to interrupt interface I1, interrupt interface I2...interrupt interface In, and sequentially outputs the interrupt test results of interrupt interface I1, interrupt interface I2...interrupt interface In according to the result values ​​of interrupt interface I1, interrupt interface I2...interrupt interface In.

[0048] In some embodiments, the plurality of preset modes include a second mode. In this case, the selection module 121 is specifically used to: determine at least one first interrupt interface among the plurality of interrupt interfaces according to the second mode when the target mode is the second mode, and sequentially select the target interrupt interface to be tested from the at least one first interrupt interface.

[0049] The first interrupt interface is, for example, the interface that requires continuous interrupt testing. In practice, the specific first interrupt interface (or which of the multiple interrupt interfaces) can be configured by those skilled in the art based on the actual situation.

[0050] For example, multiple first interrupt interfaces include, as Figure 1 In the first mode, the interrupt interfaces I1 to Im shown can be selected as target interrupt interfaces in a second preset order. The second preset order can be set by those skilled in the art according to actual circumstances, and this embodiment does not limit this setting.

[0051] After this, the excitation module 122 sends a test excitation to the target interrupt interface selected in the selection module 121 so as to start the interrupt service routine corresponding to the target interrupt interface.

[0052] In the second mode, the test module 123 first obtains the test count of the target interrupt interface from the selection module 121, then receives the result value returned by the interrupt service routine corresponding to the target interrupt interface, and outputs the interrupt test result of the target interrupt interface corresponding to the interrupt service routine based on the result value. For example, the result value returned by the interrupt service routine includes 1 and 0. If the result value returned by the interrupt service routine is 1, it indicates that the interrupt service routine is running normally, and a signal indicating that the interrupt test result is normal is output; if the result value returned by the interrupt service routine is 0, it indicates that the interrupt service routine is running abnormally, and a signal indicating that the interrupt test result is abnormal is output. After this, the continuous start count of the interrupt service routine corresponding to the target interrupt interface is obtained, and it is determined whether the continuous start count is less than the test count; if the determination result is yes, that is, the continuous start count is less than the test count, then the process jumps to the excitation module 122, so that the excitation module 122 sends a test excitation to the target interrupt interface selected in the selection module 121 again to start the interrupt service routine corresponding to the target interrupt interface; if the determination result is no, that is, the continuous start count is greater than or equal to the test count, then the current process ends.

[0053] For example, see Figure 1 As shown, in the second mode, the selection module 121 sequentially selects interrupt interface I1, interrupt interface I2... interrupt interface Im from multiple interrupt interfaces as the target interrupt interface. In this case, the excitation module 122 sequentially sends test excitations to interrupt interface I1, interrupt interface I2... interrupt interface Im in order to start the interrupt service routine corresponding to the target interrupt interface. For each target interrupt interface selected by the selection module 121, the test module 123 obtains the test count for that target interrupt interface from the selection module 121. For example, if the target interrupt interface selected by the selection module 121 is interrupt interface I1, the test module 123 obtains the test count for interrupt interface I1 from the selection module 121, then receives the result value returned by the interrupt service routine corresponding to interrupt interface I1, and subsequently obtains the consecutive start count of the interrupt service routine corresponding to interrupt interface I1, and determines whether the consecutive start count is less than the test count. If the determination result is yes, that is, the consecutive start count is less than the test count, then it jumps to the stimulus module 122 so that the stimulus module 122 sends a test stimulus to interrupt interface I1 again and starts the interrupt service routine corresponding to interrupt interface I1. If the determination result is no, that is, the consecutive start count is greater than or equal to the test count, then the test process for interrupt interface I1 ends. It can be understood that for interrupt interfaces I2 to interrupt interface Im, the method by which the test module 123 obtains the interrupt test result is the same as the method by which it obtains the interrupt test result for interrupt interface I1, and will not be repeated here.

[0054] In some embodiments, the multiple preset modes include a third mode. In this case, the selection module 121 is specifically configured to: when the target mode is the third mode, determine at least one set of interrupt interface groups based on the third mode among the multiple interrupt interfaces, each interrupt interface group including multiple second interrupt interfaces, and each second interrupt interface having a different priority; and sequentially select a target interrupt interface group to be tested from the at least one set of interrupt interface groups, taking each second interrupt interface in the target interrupt interface group as a target interrupt interface, thereby obtaining multiple target interrupt interfaces. After this, the stimulus module 122 sends test stimuli to the multiple target interrupt interfaces selected by the selection module 121 to initiate the interrupt service routines corresponding to the multiple target interrupt interfaces.

[0055] In the third mode, the test module 123 receives the result values ​​returned by the multiple target interrupt service routines corresponding to the multiple target interrupt interfaces. Then, based on the time of the return result values ​​of the multiple target interrupt service routines, the multiple target interrupt interfaces are sorted in chronological order to obtain a first order. After that, the multiple target interrupt interfaces are sorted in descending order of priority to obtain a second order. The interrupt test result is determined based on the first order and the second order. If the first order and the second order are consistent, a signal indicating that the interrupt test result is normal is output; if the first order and the second order are inconsistent, a signal indicating that the interrupt test result is abnormal is output.

[0056] Specifically, the third mode can be used to test whether the priority execution of multiple interrupt interfaces is correct.

[0057] For example, please refer to Figure 1As shown, at least one interrupt interface group includes a first interrupt interface group M1, which includes interrupt interface I1 and interrupt interface I2, with interrupt interface I1 having a higher priority than interrupt interface I2. In this case, in the third mode, selection module 121 selects interrupt interface I1 and interrupt interface I2 as target interrupt interfaces. Afterward, activation module 122 sends test stimuli to interrupt interface I1 and interrupt interface I2 to activate the interrupt service routine corresponding to each target interrupt interface. Test module 123 receives the first result value returned by the target interrupt service routine corresponding to interrupt interface I1 and the second result value returned by the target interrupt service routine corresponding to interrupt interface I2. Specifically, if the test module 123 first receives the first result value returned by the target interrupt service routine corresponding to interrupt interface I1, and then receives the second result value returned by the target interrupt service routine corresponding to interrupt interface I2, and sorts interrupt interface I1 and interrupt interface I2 in chronological order according to the time of receiving the first and second result values, it obtains the first order I1-I2. Then, it sorts interrupt interface I1 and interrupt interface I2 in chronological order according to priority, obtaining the second order I1-I2. If the first order I1-I2 is consistent with the second order I1-I2, then a signal indicating that the interrupt test result is normal is output. If test module 123 first receives the second result value returned by the target interrupt service routine corresponding to interrupt interface I2, and then receives the first result value returned by the target interrupt service routine corresponding to interrupt interface I1, and sorts interrupt interface I1 and interrupt interface I2 in chronological order according to the time of receiving the first and second result values, it obtains the first order I2-I1. Then, it sorts interrupt interface I1 and interrupt interface I2 in descending order of priority, obtaining the second order I1-I2. If the first order I2-I1 is consistent with the second order I1-I2, then an interrupt test result abnormal signal is output.

[0058] It is understood that the above description of at least one set of interrupt interface groups in the third mode, and each interrupt interface group including multiple second interrupt interfaces, is merely exemplary. In specific implementations, the number of at least one set of interrupt interface groups and which of the multiple interrupt interfaces each interrupt interface group includes can be set by those skilled in the art according to the actual situation.

[0059] It should be noted that the multiple preset modes listed above are merely exemplary. In specific implementations, the multiple preset modes include, but are not limited to, the first mode, the second mode, and the third mode described above. The execution order of the multiple preset modes can be set by those skilled in the art according to the actual situation, and this disclosure does not limit this.

[0060] It is understood that, upon receiving a trigger signal, the selection module 121 can sequentially select one target mode to be executed from multiple preset modes, or it can simultaneously select multiple target modes to be executed from multiple preset modes, thereby enabling the simultaneous execution of tests on multiple target modes. In specific implementations, the method of selecting at least one target mode to be executed from multiple preset modes can be set by those skilled in the art according to actual circumstances, and this disclosure does not limit this.

[0061] In some embodiments, in order for the stimulus module 122 to synchronously send multiple test stimuli, such as... Figure 2 As shown, the chip 10 may further include: a first timing module 15, used to start timing in response to a first timing trigger event; and to generate a first test stimulus trigger signal when the timing duration exceeds a preset first timing duration; wherein, the first timing trigger event is selected by the selection module 121 from multiple interrupt interfaces according to the target mode; the stimulus module 122 is specifically used to send a test stimulus to each target interrupt interface in response to the first test stimulus trigger signal, so as to start the interrupt service routine corresponding to each target interrupt interface.

[0062] The duration of the first timing can be set by those skilled in the art according to the actual situation, and this disclosure does not limit it.

[0063] In some embodiments, to improve the accuracy of test results regarding the correctness of priority execution for multiple interrupt interfaces, the excitation module 122 can be controlled in the third mode to asynchronously send test stimuli corresponding to multiple target interrupt interfaces. To achieve the above objective, as... Figure 3 As shown, chip 10 may further include: a second timing module 16, used to start timing in response to a second timing trigger event; wherein the second timing trigger event is that the selection module selects each second interrupt interface in the target interrupt interface group as a target interrupt interface, resulting in multiple target interrupt interfaces; and, when the timing duration reaches the second timing duration corresponding to the target interrupt interface under test, generating a second test stimulus trigger signal corresponding to the target interrupt interface under test; wherein the target interrupt interface under test is any interrupt interface among the multiple target interrupt interfaces; the stimulus module 122 is specifically used to send a test stimulus to the target interrupt interface under test in response to the second test stimulus trigger signal corresponding to the target interrupt interface under test, so as to start the interrupt service routine corresponding to the target interrupt interface under test.

[0064] The second timing duration can be set by those skilled in the art according to the actual situation, and this disclosure does not limit it.

[0065] One beneficial effect of this disclosure is that it provides a chip that carries its own interrupt testing function. In this case, chip users no longer need to design corresponding interrupt test programs for the chip in order to obtain test results for interrupts on the chip. This not only avoids the problems of complex operation, low efficiency and high cost in the development process of test programs, but also enables the testing of interrupts on the chip in the actual operating environment, bringing many conveniences to the use of the chip.

[0066] <Method Implementation>

[0067] Figure 4 This is a flowchart illustrating a chip testing method provided in an embodiment of the present disclosure. The chip includes multiple interrupt interfaces, an interrupt testing device, and an internal bus. The interrupt testing device is coupled to the multiple interrupt interfaces via the internal bus, as shown below. Figure 4 As shown, the method includes the following steps S410 to S430:

[0068] Step S410: Upon receiving a trigger signal, select at least one target mode to be executed from multiple preset modes, and select at least one target interrupt interface to be tested from multiple interrupt interfaces according to the target mode.

[0069] Step S420: Send a test stimulus to each target interrupt interface to start the interrupt service routine corresponding to each target interrupt interface.

[0070] Step S430: Receive the result value returned by each interrupt service routine, and output the interrupt test result of the target interrupt interface corresponding to the interrupt service routine based on the result value.

[0071] Multiple preset modes include a first mode, which selects at least one target interrupt interface to be tested from multiple interrupt interfaces based on the target mode, including:

[0072] When the target mode is the first mode, the target interrupt interface to be tested is selected sequentially from multiple interrupt interfaces according to the first mode.

[0073] Optionally, the multiple preset modes include a second mode. Selecting at least one target interrupt interface to be tested from multiple interrupt interfaces according to the target mode includes: when the target mode is the second mode, determining at least one first interrupt interface from the multiple interrupt interfaces according to the second mode, and sequentially selecting the target interrupt interface to be tested from the at least one first interrupt interface; before receiving the result value returned by each interrupt service routine, the method further includes: obtaining the number of tests for the target interrupt interface from the selection module; after outputting the interrupt test result of the target interrupt interface corresponding to the interrupt service routine based on the result value, the method further includes: obtaining the number of consecutive starts of the interrupt service routine corresponding to the consecutively started target interrupt interface; and, if the number of consecutive starts is less than the number of tests, jumping to the stimulus module so that the stimulus module sends a test stimulus to the target interrupt interface again to start the interrupt service routine corresponding to the target interrupt interface.

[0074] Optionally, the multiple preset modes include a third mode. Selecting at least one target interrupt interface to be tested from multiple interrupt interfaces according to the target mode includes: when the target mode is the third mode, determining at least one group of interrupt interfaces from the multiple interrupt interfaces according to the third mode, each interrupt interface group including multiple second interrupt interfaces, and each second interrupt interface having a different priority; and sequentially selecting the target interrupt interface group to be tested from the at least one group of interrupt interfaces, taking each second interrupt interface in the target interrupt interface group as the target interrupt interface, thus obtaining multiple target interrupt interfaces; receiving the result value returned by each interrupt service routine, and outputting the interrupt test result of the target interrupt interface corresponding to the interrupt service routine based on the result value, including: receiving the result values ​​returned by multiple target interrupt service routines corresponding to the multiple target interrupt interfaces; sorting the multiple target interrupt interfaces according to the time of the return result values ​​of the multiple target interrupt service routines in chronological order to obtain a first order; and sorting the multiple target interrupt interfaces according to the priority from high to low to obtain a second order, and determining the interrupt test result based on the first order and the second order.

[0075] Optionally, the method further includes: responding to a first timing trigger event to start timing; and generating a first test stimulus trigger signal if the timing duration exceeds a preset first timing duration; wherein the first timing trigger event is that the selection module selects at least one target interrupt interface to be tested from multiple interrupt interfaces according to the target mode; sending a test stimulus to each target interrupt interface to start the interrupt service routine corresponding to each target interrupt interface, including: responding to the first test stimulus trigger signal to send a test stimulus to each target interrupt interface to start the interrupt service routine corresponding to each target interrupt interface.

[0076] Optionally, the method further includes: responding to a second timing trigger event to start timing; wherein the second timing trigger event is that the selection module selects each second interrupt interface in the target interrupt interface group as a target interrupt interface, resulting in multiple target interrupt interfaces; and generating a second test stimulus trigger signal corresponding to the target interrupt interface under test when the timing duration reaches the second timing duration corresponding to the target interrupt interface under test; wherein the target interrupt interface under test is any interrupt interface among the multiple target interrupt interfaces; sending a test stimulus to each target interrupt interface to start the interrupt service routine corresponding to each target interrupt interface, including: responding to the second test stimulus trigger signal corresponding to the target interrupt interface under test, sending a test stimulus to the target interrupt interface under test to start the interrupt service routine corresponding to the target interrupt interface under test.

[0077] The specific implementation of the above method steps can be found in the corresponding description in the embodiment of chip 10 described above, and will not be repeated here.

[0078] One beneficial effect of this disclosure is that it provides a chip that carries its own interrupt testing function. In this case, chip users no longer need to design corresponding interrupt test programs for the chip in order to obtain test results for interrupts on the chip. This not only avoids the problems of complex operation, low efficiency and high cost in the development process of test programs, but also enables the testing of interrupts on the chip in the actual operating environment, bringing many conveniences to the use of the chip.

[0079] Figure 5 This is a schematic diagram of the hardware structure of an interrupt testing device according to an embodiment of the present disclosure.

[0080] like Figure 5 As shown, the interrupt testing device 500 includes a processor 510 and a memory 520. The memory 520 is used to store an executable computer program, and the processor 510 is used to execute the method as described in any of the above method embodiments under the control of the computer program.

[0081] Each module of the interrupt test device 12 described above can be implemented by the processor 510 in this embodiment executing the computer program stored in the memory 520, or it can be implemented by other circuit structures, which are not limited here.

[0082] This invention can be a system, method, and / or computer program product. A computer program product may include a computer-readable storage medium having computer-readable program instructions loaded thereon for causing a processor to implement various aspects of the invention.

[0083] Computer-readable storage media can be tangible devices capable of holding and storing instructions for use by an instruction execution device. Computer-readable storage media can be, for example—but not limited to—electrical storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination thereof. More specific examples (a non-exhaustive list) of computer-readable storage media include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices, such as punch cards or recessed protrusions storing instructions thereon, and any suitable combination thereof. The computer-readable storage media used herein are not to be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires.

[0084] The computer-readable program instructions described herein can be downloaded from computer-readable storage media to various computing / processing devices, or downloaded via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external computer or external storage device. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to the computer-readable storage media in the respective computing / processing device.

[0085] The computer program instructions used to perform the operations of this invention may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry, such as programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), is personalized by utilizing state information from the computer-readable program instructions. This electronic circuitry can execute the computer-readable program instructions to implement various aspects of the invention.

[0086] Various aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0087] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processor of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner; thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0088] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0089] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions. It will be known to those skilled in the art that implementation in hardware, implementation in software, and implementation using a combination of software and hardware are equivalent.

[0090] The various embodiments of the present invention have been described above. These descriptions are exemplary and not exhaustive, and are not limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein. The scope of the invention is defined by the appended claims.

Claims

1. A chip, characterized in that, The chip includes multiple interrupt interfaces, an interrupt testing device, and an internal bus. The interrupt testing device is coupled to the multiple interrupt interfaces via the internal bus. The interrupt testing device includes: The selection module is used to select at least one target mode to be executed from multiple preset modes when a trigger signal is received, and to select at least one target interrupt interface to be tested from the multiple interrupt interfaces according to the target mode. The incentive module is used to send test incentives to each target interrupt interface in order to start the interrupt service routine corresponding to each target interrupt interface; The testing module is used to receive the result value returned by each interrupt service routine and output the interrupt test result of the target interrupt interface corresponding to the interrupt service routine based on the result value.

2. The chip according to claim 1, characterized in that, The plurality of preset modes includes a first mode, and the selection module is specifically used for: When the target mode is the first mode, the target interrupt interface to be tested is selected sequentially from the plurality of interrupt interfaces according to the first mode.

3. The chip according to claim 1, characterized in that, The plurality of preset modes includes a second mode, and the selection module is specifically used for: When the target mode is the second mode, at least one first interrupt interface is determined from the plurality of interrupt interfaces according to the second mode, and the target interrupt interface to be tested is selected sequentially from the at least one first interrupt interface. The testing module is further configured to: obtain the number of tests for the target interrupt interface from the selection module before receiving the result value returned by each interrupt service routine; and after outputting the interrupt test result of the target interrupt interface corresponding to the interrupt service routine based on the result value, obtain the number of consecutive starts of the interrupt service routine corresponding to the target interrupt interface. In addition, if the number of consecutive starts is less than the number of tests, the system jumps to the stimulus module so that the stimulus sends a test stimulus to the target interrupt interface again and starts the interrupt service routine corresponding to the target interrupt interface.

4. The chip according to claim 1, characterized in that, The plurality of preset modes includes a third mode, and the selection module is specifically used for: When the target mode is the third mode, at least one set of interrupt interface groups is determined according to the third mode among the multiple interrupt interfaces, each interrupt interface group includes multiple second interrupt interfaces, and each second interrupt interface has a different priority; and, a target interrupt interface group to be tested is sequentially selected from the at least one set of interrupt interface groups, and each second interrupt interface in the target interrupt interface group is taken as a target interrupt interface to obtain multiple target interrupt interfaces. The testing module is specifically used to: receive the result values ​​returned by the multiple target interrupt service routines corresponding to the multiple target interrupt interfaces; and sort the multiple target interrupt interfaces according to the time of the return of the result values ​​by the multiple target interrupt service routines, in order of the time from first to last, to obtain a first order; Furthermore, the plurality of target interrupt interfaces are sorted in descending order of priority to obtain a second order, and the interrupt test result is determined based on the first order and the second order.

5. The chip according to any one of claims 1-4, characterized in that, The chip also includes: The first timing module is used to respond to a first timing trigger event and start timing; and to generate a first test stimulus trigger signal when the timing duration exceeds a preset first timing duration; wherein, the first timing trigger event is that the selection module selects at least one target interrupt interface to be tested from the plurality of interrupt interfaces according to the target mode; The incentive module is specifically used to respond to the first test incentive trigger signal and send a test incentive to each target interrupt interface so as to start the interrupt service routine corresponding to each target interrupt interface.

6. The chip according to claim 4, characterized in that, The chip also includes: The second timing module is used to respond to a second timing trigger event and start timing; wherein, the second timing trigger event is that the selection module selects each second interrupt interface in the target interrupt interface group as a target interrupt interface, resulting in multiple target interrupt interfaces; and, when the timing duration reaches the second timing duration corresponding to the target interrupt interface under test, generates a second test stimulus trigger signal corresponding to the target interrupt interface under test; wherein, the target interrupt interface under test is any interrupt interface among the multiple target interrupt interfaces; The incentive module is specifically used to respond to the second test incentive trigger signal corresponding to the interrupt interface of the target under test, and send a test incentive to the interrupt interface of the target under test so as to start the interrupt service routine corresponding to the interrupt interface of the target under test.

7. A method for testing a chip, characterized in that, The chip includes multiple interrupt interfaces, an interrupt testing device, and an internal bus. The interrupt testing device is coupled to the multiple interrupt interfaces via the internal bus. The method is executed by the interrupt testing device and includes: Upon receiving a trigger signal, at least one target mode to be executed is selected from multiple preset modes, and at least one target interrupt interface to be tested is selected from the multiple interrupt interfaces according to the target mode; Send a test stimulus to each target interrupt interface in order to start the interrupt service routine corresponding to each target interrupt interface; Receive the result value returned by each interrupt service routine, and output the interrupt test result of the target interrupt interface corresponding to the interrupt service routine based on the result value.

8. The method according to claim 7, characterized in that, The plurality of preset modes include a first mode, and the step of selecting at least one target interrupt interface to be tested from the plurality of interrupt interfaces according to the target mode includes: When the target mode is the first mode, the target interrupt interface to be tested is selected sequentially from the plurality of interrupt interfaces according to the first mode.

9. The method according to claim 7, characterized in that, The plurality of preset modes includes a second mode, and the step of selecting at least one target interrupt interface to be tested from the plurality of interrupt interfaces according to the target mode includes: When the target mode is the second mode, at least one first interrupt interface is determined from the plurality of interrupt interfaces according to the second mode, and the target interrupt interface to be tested is selected sequentially from the at least one first interrupt interface. Before receiving the result value returned by each interrupt service routine, the method further includes: obtaining the number of tests for the target interrupt interface from the selection module; After outputting the interrupt test result of the target interrupt interface corresponding to the interrupt service routine based on the result value, the method further includes: obtaining the number of consecutive starts of the interrupt service routine corresponding to the target interrupt interface; and, if the number of consecutive starts is less than the number of tests, jumping to the stimulus module so that the stimulus module sends a test stimulus to the target interrupt interface again to start the interrupt service routine corresponding to the target interrupt interface.

10. The method according to claim 7, characterized in that, The plurality of preset modes includes a third mode, and the step of selecting at least one target interrupt interface to be tested from the plurality of interrupt interfaces according to the target mode includes: When the target mode is the third mode, at least one set of interrupt interface groups is determined according to the third mode among the multiple interrupt interfaces, each interrupt interface group includes multiple second interrupt interfaces, and each second interrupt interface has a different priority; and, a target interrupt interface group to be tested is sequentially selected from the at least one set of interrupt interface groups, and each second interrupt interface in the target interrupt interface group is taken as a target interrupt interface to obtain multiple target interrupt interfaces. The process of receiving the result value returned by each interrupt service routine and outputting the interrupt test result of the target interrupt interface corresponding to that interrupt service routine based on the result value includes: The system receives result values ​​returned by multiple target interrupt service routines corresponding to the multiple target interrupt interfaces; sorts the multiple target interrupt interfaces according to the time of the return result values ​​of the multiple target interrupt service routines in order of the time from first to last to obtain a first order; and sorts the multiple target interrupt interfaces according to the priority from high to low to obtain a second order, and determines the interrupt test result based on the first order and the second order.

11. The method according to any one of claims 7-10, characterized in that, The method further includes: In response to the first timing trigger event, timing begins; and if the timing duration exceeds a preset first timing duration, a first test stimulus trigger signal is generated; wherein, the first timing trigger event is the selection module selecting at least one target interrupt interface to be tested from the plurality of interrupt interfaces according to the target mode; Sending a test stimulus to each target interrupt interface to start the interrupt service routine corresponding to each target interrupt interface includes: responding to the first test stimulus trigger signal and sending a test stimulus to each target interrupt interface to start the interrupt service routine corresponding to each target interrupt interface.

12. The method according to claim 10, characterized in that, The method further includes: In response to the second timing trigger event, timing begins; wherein, the second timing trigger event is that the selection module selects each second interrupt interface in the target interrupt interface group as the target interrupt interface, resulting in multiple target interrupt interfaces; and, When the timing duration reaches the second timing duration corresponding to the target interrupt interface under test, a second test stimulus trigger signal corresponding to the target interrupt interface under test is generated; wherein, the target interrupt interface under test is any interrupt interface among the plurality of target interrupt interfaces; Sending a test stimulus to each target interrupt interface to start the interrupt service routine corresponding to each target interrupt interface includes: responding to the second test stimulus trigger signal corresponding to the target interrupt interface under test, sending a test stimulus to the target interrupt interface under test to start the interrupt service routine corresponding to the target interrupt interface under test.

13. A computer-readable storage medium, characterized in that, A computer program is stored on the computer-readable storage medium, which, when executed by a processor, implements the method according to any one of claims 7-12.

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