Chip, chip test monitoring method and computer readable storage medium

Abstract

The present disclosure relates to a chip, a test monitoring method of the chip and a computer readable storage medium. The chip comprises a memory, an internal bus and an interrupt processing monitoring device, the memory is coupled with the interrupt processing monitoring device through the internal bus, the memory stores a plurality of interrupt entry addresses corresponding to a plurality of interrupt service programs, and the interrupt processing monitoring device comprises: a monitoring processing module, configured to start timing in response to a first event that an interrupt entry address of a target interrupt service program is called; wherein the target interrupt service program is any one of the plurality of interrupt service programs; a signal output module, configured to output an error indication signal corresponding to the target interrupt service program in a case that a timing result of the timing is greater than a preset execution time threshold of the target interrupt service program; and a result processing module, configured to perform a stop operation corresponding to the error indication signal on the target interrupt service program, so as to stop execution of the target interrupt service program.

Description

Technical Field

[0001] This disclosure relates to the field of chip design technology, and more specifically, to a chip, a chip testing and monitoring method, and a computer-readable storage medium. Background Technology

[0002] During the execution of the main program, when a Microcontroller Unit (MCU) receives an interrupt signal, it responds to the interrupt signal, jumps to the corresponding interrupt service routine (SSR), and executes the SSR. If an abnormality occurs during the execution of the SSR, such as a malfunction or failure to meet the MCU's interrupt handling timeout, it will cause the corresponding MCU function to malfunction. Currently, to restore the MCU's functionality, a watchdog timer is set and the main program is fed back to reset the MCU.

[0003] In reality, watchdogs have a long feeding cycle and cannot respond promptly to exceptions that occur during the interruption of service procedures, resulting in a long processing time for such exceptions. Summary of the Invention

[0004] One object of this disclosure is to provide a new technical solution for a chip.

[0005] According to a first aspect of this disclosure, a chip is provided, comprising a memory, an internal bus, and an interrupt handling monitoring device. The memory is coupled to the interrupt handling monitoring device via the internal bus. The memory stores multiple interrupt entry addresses corresponding one-to-one with multiple interrupt service routines. The interrupt handling monitoring device includes: a monitoring processing module, configured to start timing in response to a first event in which the interrupt entry address of a target interrupt service routine is invoked; wherein the target interrupt service routine is any one of the multiple interrupt service routines; a signal output module, configured to output an error indication signal corresponding to the target interrupt service routine if the timing result is greater than a preset execution duration threshold of the target interrupt service routine; and a result processing module, configured to perform a stop operation corresponding to the error indication signal on the target interrupt service routine to stop the execution of the target interrupt service routine.

[0006] Optionally, the error indication signal includes a first error indication signal, and the result processing module is specifically used to: stop the target interrupt service routine according to the first error indication signal, and return to the interrupt point to continue executing the main program.

[0007] Optionally, the chip also includes a watchdog timer and a reset terminal coupled to the watchdog timer. The interrupt handling monitoring device is coupled to the watchdog timer through an internal bus. The error indication signal includes a second error indication signal. The result processing module is specifically used to: set the watchdog timer to an overflow state according to the second error indication signal, so that the watchdog timer sends a reset signal to the reset terminal.

[0008] Optionally, the interrupt handling monitoring device further includes: a data recording module, used to record the running data of the target interrupt service routine after the timing starts; and to record the timing result in response to a second event in which the timing result is greater than a preset execution duration threshold of the target interrupt service routine.

[0009] Optionally, the runtime data includes: the interrupt entry address, the interrupt exit address, and the number of interrupt execution instructions of the target interrupt service routine.

[0010] Optionally, the interrupt handling monitoring device further includes: a sending module, used to send the error indication signal to the main program before jumping to the target interrupt service routine after the result processing module performs the stop operation corresponding to the error indication signal on the target interrupt service routine to stop the execution of the target interrupt service routine, so that the main program can obtain the recording result of the data recording module according to the error indication signal, and output the error analysis result after performing error analysis on the running process of the target interrupt service routine according to the recording result.

[0011] According to a second aspect of this disclosure, a test monitoring method for a chip is also provided. The chip includes a memory, an internal bus, and an interrupt handling monitoring device. The memory is coupled to the interrupt handling monitoring device via the internal bus. The memory stores multiple interrupt entry addresses corresponding one-to-one with multiple interrupt service routines. The method is applied to the interrupt handling monitoring device. The method includes: responding to a first event in which the interrupt entry address of a target interrupt service routine is called, starting a timer; wherein the target interrupt service routine is any one of the multiple interrupt service routines; if the timer result is greater than a preset execution duration threshold of the target interrupt service routine, outputting an error indication signal corresponding to the target interrupt service routine; and performing a stop operation corresponding to the error indication signal on the target interrupt service routine to stop the execution of the target interrupt service routine.

[0012] Optionally, the error indication signal includes a first error indication signal. Executing a stop operation corresponding to the error indication signal on the target interrupt service routine to stop the execution of the target interrupt service routine includes: stopping the target interrupt service routine according to the first error indication signal and returning to the interrupt point to continue executing the main program.

[0013] Optionally, the chip also includes a watchdog timer and a reset terminal coupled to the watchdog timer. The interrupt handling monitoring device is coupled to the watchdog timer via an internal bus. The error indication signal includes a second error indication signal. The target interrupt service routine is executed with a stop operation corresponding to the error indication signal to stop the execution of the target interrupt service routine. This includes: setting the watchdog timer to an overflow state according to the second error indication signal, and causing the watchdog timer to send a reset signal to the reset terminal.

[0014] Optionally, the method further includes: recording the execution data of the target interrupt service routine after the timing starts; and recording the timing result in response to a second event in which the timing result is greater than a preset execution duration threshold of the target interrupt service routine.

[0015] Optionally, the above-mentioned runtime data includes: the interrupt entry address, the interrupt exit address, and the number of interrupt execution instructions of the target interrupt service routine.

[0016] Optionally, after performing the stop operation corresponding to the error indication signal on the target interrupt service routine to stop the execution of the target interrupt service routine, the method further includes: sending the error indication signal to the main program before jumping to the target interrupt service routine, so that the main program can obtain the recording result of the data recording module according to the error indication signal, and output the error analysis result after performing error analysis on the running process of the target interrupt service routine according to the recording result.

[0017] According to a third aspect of this disclosure, a computer-readable storage medium is also provided, on which a computer program is stored, which, when executed by a processor, implements the method according to a second aspect of this disclosure.

[0018] One beneficial effect of this disclosure is that it can start timing in response to the first event of the interrupt entry address of the target interrupt service routine being called; and when the timing result is greater than the preset execution duration threshold of the target interrupt service routine, it outputs an error indication signal corresponding to the target interrupt service routine, and then performs a stop operation corresponding to the error indication signal on the target interrupt service routine to stop its execution. This disclosure allows for setting different error indication signals for different interrupt service routines, so that the handling of abnormalities during the execution of the interrupt service routine is no longer limited to resetting the MCU by setting a watchdog timer and feeding the watchdog timer to the main program. This effectively avoids the problem that in some cases, due to the long watchdog timer feeding cycle, it is impossible to respond to abnormalities occurring during the execution of the interrupt service routine in a timely manner, thus resulting in a long processing time for such abnormalities. This achieves the goal of timely response to abnormalities during the execution of the interrupt service routine.

[0019] Other features and advantages of the embodiments of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0020] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments of the present disclosure and, together with their description, serve to explain the principles of the embodiments of the present disclosure.

[0021] Figure 1 This is a schematic diagram of the structure of a chip provided in an embodiment of the present disclosure;

[0022] Figure 2 This is a schematic diagram of another chip structure provided in an embodiment of the present disclosure;

[0023] Figure 3 This is a schematic diagram of another chip structure provided in an embodiment of the present disclosure;

[0024] Figure 4 This is a schematic diagram of the structure of another chip provided in an embodiment of the present disclosure;

[0025] Figure 5 A flowchart illustrating a chip testing and monitoring method provided in this embodiment of the disclosure;

[0026] Figure 6 This is a schematic diagram of the hardware structure of a chip provided for a public embodiment. Detailed Implementation

[0027] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the present disclosure.

[0028] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit this disclosure or its application or use.

[0029] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0030] In all the examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.

[0031] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0032] Hereinafter, various embodiments and examples according to the present disclosure will be described with reference to the accompanying drawings.

[0033] <Equipment Example>

[0034] Figure 1 This is a schematic diagram of a chip structure provided in an embodiment of the present disclosure. The chip 10 may include: a memory 12, an internal bus 14, and an interrupt handling monitoring device 15, which is coupled to the memory 12 through the internal bus 14.

[0035] Figure 2 This is a schematic diagram of a chip structure provided in an embodiment of this disclosure. Figure 2 As shown, chip 10 may further include a watchdog timer 11 and a reset terminal 13 coupled to the watchdog timer 11. Interrupt handling monitoring device 15 can be coupled to watchdog timer 11 via internal bus 14.

[0036] Chip 10 can have multiple interrupt interfaces ( Figure 1 (Not shown in the image). The memory 12 stores multiple interrupt entry addresses that correspond one-to-one with multiple interrupt service routines, and the multiple interrupt entry addresses also correspond one-to-one with multiple interrupt interfaces.

[0037] For example, such as Figure 2 As shown, chip 10 has multiple interrupt interfaces 16, such as Figure 2 Interrupt interfaces I1~In are provided. Multiple interrupt interfaces 16 can be hardware interfaces, for example, pins on chip 10.

[0038] The multiple interrupt interfaces 16 may include at least one internal interrupt interface and at least one external interrupt interface. At least one internal interrupt interface is, for example... Figure 2 Interrupt interfaces I1~Im, at least one external interrupt interface, for example Figure 2 Interrupt interface I(m+1)~In; where n>m>0, and n and m are natural numbers.

[0039] When one of the multiple interrupt interfaces receives an interrupt signal, the interrupt entry address of the target interrupt service routine corresponding to that interrupt interface is invoked, and the target interrupt service routine begins execution. In this case, the interrupt handling monitoring device 15 starts operating.

[0040] like Figure 1 As shown, the interrupt handling monitoring device 15 includes: a monitoring and processing module 151, a signal output module 152, and a result processing module 153.

[0041] The monitoring and processing module 151 is used to start timing in response to the first event in which the interrupt entry address of the target interrupt service routine is called; wherein, the target interrupt service routine is any one of multiple interrupt service routines.

[0042] The signal output module 152 is used to output an error indication signal corresponding to the target interrupt service routine when the timing result is greater than the preset execution duration threshold of the target interrupt service routine.

[0043] The result processing module 153 is used to perform a stop operation corresponding to the error indication signal on the target interrupt service routine, so as to stop the execution of the target interrupt service routine.

[0044] In this embodiment of the disclosure, a preset execution time threshold can be set for each interrupt service routine. The preset execution time threshold for each interrupt service routine is the maximum time required for the interrupt service routine to operate normally.

[0045] In some embodiments, the preset execution duration threshold corresponding to the interrupt service routine is less than or equal to 1ms.

[0046] In some embodiments, an error indication signal corresponding to each interrupt service routine is pre-set. For example, based on whether chip 10 needs to be initialized when an exception occurs in the interrupt service routine, multiple interrupt service routines are divided into at least one first target interrupt service routine and at least one second target interrupt service routine. When an exception occurs in the first target interrupt service routine, chip 10 does not need to be initialized, while when an exception occurs in the second target interrupt service routine, chip 10 needs to be initialized. In this case, the error indication signal of the first target interrupt service routine is set as the first error indication signal, and the error indication signal of the second target interrupt service routine is set as the second error indication signal.

[0047] When the target interrupt service routine is the first target interrupt service routine, the error indication signal output by the signal output module 152 is the first error indication signal. The result processing module 153 stops the execution of the target interrupt service routine according to the first error indication signal and returns to the interrupt point to continue executing the main program, so as to achieve the purpose of timely response to the abnormality in the operation of the target interrupt service routine.

[0048] When the target interrupt service routine is the second target interrupt service routine, the error indication signal output by the signal output module 152 is the second error indication signal. In this case, the result processing module 153 sets the watchdog timer to an overflow state according to the second error indication signal, so that the watchdog timer sends a reset signal to the reset terminal, so that the chip 10 is restored to initialization, thereby stopping the execution of the target interrupt service routine and achieving the purpose of timely response to the abnormality in the operation of the target interrupt service routine.

[0049] It is understood that the embodiments listed above only illustrate different handling methods for exceptions occurring during the execution of interrupt service routines, depending on whether chip 10 needs to be initialized. In practice, interrupt service routines can also be divided from other dimensions, and different handling methods can be set according to the division results to address exceptions occurring during the execution of different interrupt service routines, thereby achieving the goal of timely response to exceptions during the execution of interrupt service routines.

[0050] Therefore, the embodiments of this disclosure can set different error indication signals for different interrupt service routines, so that the handling method for abnormalities in the operation of interrupt service routines is no longer simply to reset the MCU by setting a watchdog and feeding the watchdog to the main program. This effectively avoids the problem that in some cases, due to the long watchdog feeding cycle, it is impossible to respond to abnormalities in the operation of interrupt service routines in a timely manner, which leads to a long processing time for such abnormalities. This achieves the goal of timely response to abnormalities in the operation of interrupt service routines.

[0051] If the timing result is less than or equal to the target timing threshold corresponding to the target interrupt entry address, it indicates that the target interrupt service routine is running normally. In this case, the signal output module 152 does not output an error indication signal.

[0052] In some embodiments, there can be multiple target interrupt service routines. In this case, the interrupt handling monitoring device 15 may include multiple threads, each thread corresponding to one target interrupt service routine, thereby enabling simultaneous monitoring of the execution process of multiple target interrupt service routines. Furthermore, the monitoring processes of the multiple target interrupt service routines are independent of each other. For any one of the multiple target interrupt service routines, the monitoring process for that target interrupt service routine will not be affected by the monitoring processes of other target interrupt service routines.

[0053] To record relevant data and status during the execution of interrupt service routines, in some embodiments, such as... Figure 2 As shown, the interrupt handling monitoring device 15 may also include a data recording module 154.

[0054] The data recording module 154 is used to record the running data of the target interrupt service routine after the monitoring and processing module 151 starts timing; and to record the timing result in response to a second event in which the timing result is greater than the preset execution duration threshold of the target interrupt service routine.

[0055] In some embodiments, the above-mentioned runtime data includes: the interrupt entry address, the interrupt exit address, and the number of interrupt execution instructions of the target interrupt service routine.

[0056] Interrupt exit address, for example, the address that the target interrupt service routine will call to terminate the execution.

[0057] Interrupt execution instructions are used to specify a jump to a target interrupt service routine. In some cases, the target interrupt service routine executes cyclically, so multiple interrupt execution instructions need to be issued to specify a jump to the target interrupt service routine for execution. In this case, the number of interrupt execution instructions can represent the number of times the target interrupt service routine is executed cyclically.

[0058] In some embodiments, such as Figure 3 As shown, the interrupt handling monitoring device 15 further includes: a sending module 155, which is used to send the error indication signal to the main program before jumping to the target interrupt service program after the result processing module performs the stop operation corresponding to the error indication signal on the target interrupt service program so as to stop the execution of the target interrupt service program, so that the main program can obtain the recording result of the data recording module according to the error indication signal, and output the error analysis result after performing error analysis on the running process of the target interrupt service program according to the recording result.

[0059] In order to enable or disable the function of the interrupt handling monitoring device 15, in some embodiments, such as Figure 4 As shown, the interrupt handling monitoring device 15 also includes a function configuration module 156.

[0060] Specifically, the function configuration module 156 is used to enable the interrupt handling monitoring device when a preset enabling event is detected, and to disable the interrupt handling monitoring device when a preset disabling event is detected. For example, when a preset enabling event is detected, the interrupt handling monitoring device 15 is decoupled from the internal bus 14; for example, when a preset disabling event is detected, the interrupt handling monitoring device 15 is coupled to the internal bus 14.

[0061] The preset enabling events and preset disabling events can be set by those skilled in the art according to the actual situation, and this disclosure does not limit this.

[0062] The embodiments of this disclosure will be described in detail below through some examples.

[0063] like Figure 2 As shown, interrupt interface I1 corresponds to the first counter ( Figure 2 The interrupt function (not shown in the image) is provided, and the interrupt interface I2 corresponds to the second counter (…). Figure 2 The interrupt function (not shown in the image) is provided by interrupt interface I3, which corresponds to the serial communication module (…). Figure 2 Interrupt function (not shown in the image).

[0064] Interrupt interface I1 corresponds to the first interrupt entry address, which in turn corresponds to the first interrupt service routine. Interrupt interface I2 corresponds to the second interrupt entry address, which in turn corresponds to the second interrupt service routine. Interrupt interface I3 corresponds to the third interrupt entry address, which in turn corresponds to the third interrupt service routine. The first and third interrupt service routines are, for example, the first target interrupt service routine, both with a preset execution time threshold of 1ms. The second interrupt service routine is, for example, the first target interrupt service routine, with a preset execution time threshold of 0.5ms.

[0065] Taking interrupt interface I1 as an example, when the first interrupt entry address is called, the monitoring and processing module 151 starts timing, and the signal output module 152 monitors the timing result in real time. If the timing result is greater than the preset execution time threshold of the first interrupt service routine, the signal output module 152 obtains the timing result from the monitoring and processing module 151 in real time. If the timing result is less than or equal to 1ms, no error indication signal is output; if the timing result is greater than 1ms, a first error indication signal is output. The result processing module 153 forcibly stops the execution of the first interrupt service routine according to the first error indication signal and returns to the interrupt point to continue executing the main program.

[0066] Taking interrupt interface I3 as an example, when the second interrupt entry address is called, the monitoring and processing module 151 starts timing, and the signal output module 152 monitors the timing result in real time. If the timing result is greater than the preset execution duration threshold of the second interrupt service routine, the signal output module 152 obtains the timing result from the monitoring and processing module 151 in real time. If the timing result is less than or equal to 0.5ms, no error indication signal is output; if the timing result is greater than 0.5ms, a second error indication signal is output. The result processing module 153 outputs an overflow signal to the watchdog timer 11 according to the second error indication signal, so that the watchdog timer 11 changes its current state to an overflow state according to the overflow signal, and sends a reset signal to the reset terminal 13.

[0067] Therefore, in this embodiment of the present disclosure, different processing methods can be set for the abnormal operation of the interrupt service routine corresponding to the interrupt interface according to the different interrupt interfaces, so as to achieve the purpose of timely response to the abnormalities in the operation of the interrupt service routine.

[0068] The chip 10 in this embodiment may be, for example, an MCU, a central processing unit (CPU), etc.

[0069] <Method Implementation>

[0070] Figure 5 This is a flowchart illustrating a chip testing and monitoring method provided in this embodiment. The chip includes a memory, an internal bus, and an interrupt handling monitoring device. The memory is coupled to the interrupt handling monitoring device via the internal bus. The memory stores multiple interrupt entry addresses, each corresponding to a different interrupt service routine. This method is applied to the interrupt handling monitoring device, such as... Figure 5 As shown, the method includes the following steps S510~S530:

[0071] Step S510: In response to the first event that the interrupt entry address of the target interrupt service routine is called, start timing; wherein, the target interrupt service routine is any one of multiple interrupt service routines.

[0072] Step S520: If the timing result is greater than the preset execution duration threshold of the target interrupt service routine, output the error indication signal corresponding to the target interrupt service routine.

[0073] Step S530: Perform the stop operation corresponding to the error indication signal on the target interrupt service routine in order to stop the execution of the target interrupt service routine.

[0074] Optionally, the error indication signal includes a first error indication signal. Executing a stop operation corresponding to the error indication signal on the target interrupt service routine to stop the execution of the target interrupt service routine includes: stopping the target interrupt service routine according to the first error indication signal and returning to the interrupt point to continue executing the main program.

[0075] Optionally, the chip also includes a watchdog timer and a reset terminal coupled to the watchdog timer. The interrupt handling monitoring device is coupled to the watchdog timer via an internal bus. The error indication signal includes a second error indication signal. The target interrupt service routine is executed with a stop operation corresponding to the error indication signal to stop the execution of the target interrupt service routine. This includes: setting the watchdog timer to an overflow state according to the second error indication signal, and causing the watchdog timer to send a reset signal to the reset terminal.

[0076] Optionally, the method further includes: recording the execution data of the target interrupt service routine after the timing starts; and recording the timing result in response to a second event in which the timing result is greater than a preset execution duration threshold of the target interrupt service routine.

[0077] Optionally, the above-mentioned runtime data includes: the interrupt entry address, the interrupt exit address, and the number of interrupt execution instructions of the target interrupt service routine.

[0078] Optionally, after performing the stop operation corresponding to the error indication signal on the target interrupt service routine to stop the execution of the target interrupt service routine, the method further includes: sending the error indication signal to the main program before jumping to the target interrupt service routine, so that the main program can obtain the recording result of the data recording module according to the error indication signal, and output the error analysis result after performing error analysis on the running process of the target interrupt service routine according to the recording result.

[0079] The specific implementation of the above method steps can be found in the corresponding description in the embodiment of chip 10 described above, and will not be repeated here.

[0080] One beneficial effect of this embodiment is that it can respond to the first event of a target interrupt entry address being called among multiple interrupt entry addresses, start timing, and obtain the target timing threshold corresponding to the target interrupt entry address from the timing thresholds corresponding to multiple preset interrupt interface addresses. The result processing module is used to output an error indication signal to the watchdog timer when the timing result is greater than the target timing threshold corresponding to the target interrupt entry address, so as to put the watchdog timer into an overflow state and cause the watchdog timer to send a reset signal to the reset terminal. This solves the problem that due to the long watchdog feeding cycle and the main program execution cycle, it is impossible to respond to exceptions occurring during the operation of the interrupt service routine in a timely manner, resulting in a long processing time for such exceptions. This achieves the goal of timely response to exceptions occurring during the operation of the interrupt service routine.

[0081] Figure 6 This is a schematic diagram of the hardware structure of a chip according to an embodiment of the present disclosure.

[0082] like Figure 6 As shown, the interrupt handling monitoring device 600 includes a processor 610 and a memory 620. The memory 620 is used to store an executable computer program, and the processor 610 is used to execute the method as described in any of the above method embodiments under the control of the computer program.

[0083] Each module of the interrupt handling monitoring device 15 described above can be implemented by the processor 610 in this embodiment executing the computer program stored in the memory 620, or it can be implemented by other circuit structures, which are not limited here.

[0084] One beneficial effect of this embodiment is that it can respond to the first event of a target interrupt entry address being called among multiple interrupt entry addresses, start timing, and obtain the target timing threshold corresponding to the target interrupt entry address from the timing thresholds corresponding to multiple preset interrupt interface addresses. The result processing module is used to output an error indication signal to the watchdog timer when the timing result is greater than the target timing threshold corresponding to the target interrupt entry address, so as to put the watchdog timer into an overflow state and cause the watchdog timer to send a reset signal to the reset terminal. This solves the problem that due to the long watchdog feeding cycle and the main program execution cycle, it is impossible to respond to exceptions occurring during the operation of the interrupt service routine in a timely manner, resulting in a long processing time for such exceptions. This achieves the goal of timely response to exceptions occurring during the operation of the interrupt service routine.

[0085] This disclosure can be a system, method, and / or computer program product. A computer program product may include a computer-readable storage medium having computer-readable program instructions loaded thereon for causing a processor to implement various aspects of this disclosure.

[0086] Computer-readable storage media can be tangible devices capable of holding and storing instructions for use by an instruction execution device. Computer-readable storage media can be, for example—but not limited to—electrical storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of computer-readable storage media include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices, such as punch cards or recessed protrusions storing instructions thereon, and any suitable combination of the foregoing. The computer-readable storage media used herein are not to be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires.

[0087] The computer-readable program instructions described herein can be downloaded from computer-readable storage media to various computing / processing devices, or downloaded via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external computer or external storage device. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to the computer-readable storage media in the respective computing / processing device.

[0088] Computer program instructions used to perform the operations of this disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry, such as programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), is personalized by utilizing the status information of the computer-readable program instructions to implement various aspects of this disclosure.

[0089] Various aspects of this disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0090] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processor of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner; thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0091] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0092] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions. It will be known to those skilled in the art that implementation in hardware, implementation in software, and implementation in a combination of software and hardware are equivalent.

[0093] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, and are not limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein. The scope of this disclosure is defined by the appended claims.

Claims

1. A chip, characterized in that, The chip includes a memory, an internal bus, and an interrupt handling monitoring device. The memory is coupled to the interrupt handling monitoring device via the internal bus. The memory stores multiple interrupt entry addresses, each corresponding to a different interrupt service routine. The interrupt handling monitoring device includes: The monitoring and processing module is used to start timing in response to the first event that the interrupt entry address of the target interrupt service routine is called; wherein, the target interrupt service routine is any one of the plurality of interrupt service routines; The signal output module is used to output an error indication signal corresponding to the target interrupt service routine when the timing result is greater than the preset execution duration threshold of the target interrupt service routine. The result processing module is used to perform a stop operation corresponding to the error indication signal on the target interrupt service routine, so as to stop the execution of the target interrupt service routine.

2. The chip according to claim 1, characterized in that, The error indication signal includes a first error indication signal, and the result processing module is specifically used for: The target interrupt service routine is stopped according to the first error indication signal, and the main program is returned to the interrupt point to continue execution.

3. The chip according to claim 1, characterized in that, The chip also includes a watchdog timer and a reset terminal coupled to the watchdog timer. The interrupt handling monitoring device is coupled to the watchdog timer through the internal bus. The error indication signal includes a second error indication signal, and the result processing module is specifically used for: The watchdog timer is set to overflow state according to the second error indication signal, causing the watchdog timer to send a reset signal to the reset terminal.

4. The chip according to any one of claims 1-3, characterized in that, The interrupt handling monitoring device also includes: The data recording module is used to record the running data of the target interrupt service routine after the start of timing; and to record the timing result in response to a second event in which the timing result is greater than a preset execution duration threshold of the target interrupt service routine.

5. The chip according to claim 4, characterized in that, The runtime data includes: the interrupt entry address, interrupt exit address, and number of interrupt execution instructions of the target interrupt service routine.

6. The chip according to claim 1, characterized in that, The interrupt handling monitoring device also includes: The sending module is configured to send the error indication signal to the main program before jumping to the target interrupt service routine after the result processing module performs the stop operation corresponding to the error indication signal on the target interrupt service routine to stop the execution of the target interrupt service routine, so that the main program can obtain the recording result of the data recording module according to the error indication signal, and output the error analysis result after performing error analysis on the running process of the target interrupt service routine according to the recording result.

7. A method for testing and monitoring a chip, characterized in that, The chip includes a memory, an internal bus, and an interrupt handling monitoring device. The memory is coupled to the interrupt handling monitoring device via the internal bus. The memory stores multiple interrupt entry addresses, each corresponding to a multiple interrupt service routine. The method is applied to the interrupt handling monitoring device, and the method includes: The timer starts when the first event of the interrupt entry address of the target interrupt service routine being called occurs; wherein, the target interrupt service routine is any one of the plurality of interrupt service routines. If the timing result is greater than the preset execution time threshold of the target interrupt service routine, an error indication signal corresponding to the target interrupt service routine is output. The target interrupt service routine is executed with the stop operation corresponding to the error indication signal in order to stop the execution of the target interrupt service routine.

8. The method according to claim 7, characterized in that, The error indication signal includes a first error indication signal; The step of performing the stop operation corresponding to the error indication signal on the target interrupt service routine to stop the execution of the target interrupt service routine includes: The target interrupt service routine is stopped according to the first error indication signal, and the main program is returned to the interrupt point to continue execution.

9. The method according to claim 7, characterized in that, The chip also includes a watchdog timer and a reset terminal coupled to the watchdog timer. The interrupt handling monitoring device is coupled to the watchdog timer through the internal bus. The error indication signal includes a second error indication signal, and the step of performing a stop operation corresponding to the error indication signal on the target interrupt service routine to stop the execution of the target interrupt service routine includes: The watchdog timer is set to overflow state according to the second error indication signal, causing the watchdog timer to send a reset signal to the reset terminal.

10. A computer-readable storage medium, characterized in that, A computer program is stored on the computer-readable storage medium, which, when executed by a processor, implements the method according to any one of claims 7-9.

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