An LDPC bit selection method, device and LDPC bit selector

Abstract

The application discloses an LDPC bit selection method and device and an LDPC bit selector, and is used for solving the technical problem that the current LDPC bit selector uses more storage spaces to store the mask corresponding to a data packet, and the consumption of the FPGA on-chip resource is increased. The method comprises the following steps: according to the current capacity information of a cyclic storage module, storing the data packet output by an LDPC encoder into the address of the corresponding cyclic storage module; based on the parameter information of the data packet, obtaining the first address and the second address corresponding to the data packet, and determining the number and the starting bit of the effective bits included in the first address and the second address; storing the effective bits included in the first address and the second address into a shift register bit by bit, and storing the effective bits corresponding to the low bit width in the shift register into the storage module of an LDPC bit interleaver bit by bit; and until the effective bits included in the data packet are all stored into the shift register.

Description

Technical Field

[0001] This invention relates to the field of communications, and more particularly to an LDPC bit selection method, apparatus, and LDPC bit selector. Background Technology

[0002] In New Radio (NR) systems as defined by the 3rd Generation Partnership Project (3GPP) protocol, the Low Density Parity Check Code (LDPC) encoder on the transmitting side encodes the original bit data according to specific block sizes and code rate variations, generating parity bit data corresponding to the original bit data. Since the LDPC encoder on the transmitting side does not need to be aware of the time-frequency resource information on the receiving side, rate matching acts as a bridge between the transmitting and receiving sides, and its performance is crucial. The LDPC bit selector is the primary component of rate matching. The LDPC bit selector can punch unnecessary bits according to the specifications in 3GPP R15 38.212. The remaining bits are then stitched and aligned as much as possible by the LDPC bit interleaver based on the corresponding bit mask, thereby saving on-chip storage resources of the Field Programmable Gate Array (FPGA) and improving the efficiency of rate matching.

[0003] Currently, the LDPC bit selector uses a ping-pong buffering mechanism to store the data packets output by the LDPC encoder. Since smaller data packets consume the same amount of storage space as larger data packets, the storage efficiency for smaller data packets is low. At the same time, when processing the data after bit selection, more storage space is used to store the mask corresponding to the data packet, which increases the consumption of on-chip FPGA resources.

[0004] It is evident that current LDPC bit selectors consume a significant amount of storage space to store the masks corresponding to data packets, thereby increasing the consumption of on-chip resources in the FPGA. Summary of the Invention

[0005] This application provides an LDPC bit selection method, apparatus, and LDPC bit selector to address the technical problem that current LDPC bit selectors use a large amount of storage space to store the mask corresponding to the data packet, which increases the consumption of on-chip resources of the FPGA.

[0006] Firstly, to address the aforementioned technical problems, embodiments of this application provide an LDPC bit selection method applied to a low-density parity-check code LDPC bit selector. The LDPC bit selector includes a circular storage module composed of at least two address units, each address unit including at least one address. The method includes:

[0007] Based on the current capacity information of the circular storage module, the data packets output by the LDPC encoder are stored in the corresponding address of the circular storage module; wherein, the capacity information is used to indicate unused addresses in the circular storage module;

[0008] Based on the parameter information of the data packet, obtain the first address and the second address corresponding to the data packet, and determine the number of valid bits and the start bit included in the first address and the second address; wherein, the first address is the address where the start bit of the valid bits included in the data packet is located, and the second address is the address adjacent to the first address;

[0009] Based on the number of valid bits included in the first address and the second address and the start bit, the valid bits included in the first address and the second address are stored bit by bit into a shift register, and the valid bits corresponding to the low bit width in the shift register are stored bit by bit into the storage module of the LDPC bit interleaver; wherein, the shift register is used to merge the valid bits included in the first address and the second address, and the low bit width is the bit width corresponding to the bit width of the circular storage module;

[0010] The bit corresponding to the high-width bit in the shift register is determined as the new first address, and the address adjacent to the second address is determined as the new second address. The valid bits included in the new first address and the new second address are stored bit by bit into the shift register until all valid bits included in the data packet are stored into the shift register.

[0011] In this embodiment, the data packets output by the LDPC encoder can be stored in the address unit of the circular storage module based on the current capacity information of the circular storage module. This allows smaller data packets to consume different amounts of storage space than larger data packets, enabling flexible storage of variable-length data packets and effectively improving the storage efficiency for smaller data packets. After storing the data packet in the address unit of the circular storage module, two addresses are first selected for concatenation, and then another address is selected and concatenated with the concatenated address. This process continues until all addresses corresponding to the data packet in the storage module have been concatenated. The LDPC bit selector then aligns the valid bits in the data packet and sends the aligned valid bits to the LDPC bit interleaver. This avoids the need for excessive storage space to store the mask corresponding to the data packet when processing the bit-selected data, allowing the LDPC bit interleaver to align the valid bits in the data packet based on the mask, thus reducing the consumption of on-chip FPGA resources.

[0012] Optionally, based on the current capacity information of the circular storage module, the data packets output by the LDPC encoder are stored in the corresponding address of the circular storage module, including:

[0013] Obtain the indication information output by the circular storage module; wherein, the indication information is used to indicate the length of the data packets read from the circular storage module and / or the length of the data packets stored in the circular storage module;

[0014] Based on the instruction information and the initial capacity information of the circular storage module, determine the current capacity information of the circular storage module;

[0015] Determine whether the current capacity information matches the length of the data packet output by the LDPC encoder;

[0016] If a match is found, the data packet output by the LDPC encoder is stored in the address of the corresponding circular storage module.

[0017] If they do not match, the new capacity information of the circular storage module is determined after a preset period, until the new capacity information matches the length of the data packet output by the LDPC encoder, and the data packet output by the LDPC encoder is stored in the corresponding address of the circular storage module.

[0018] In this embodiment, the indication information output by the circular storage module can be obtained. This indication information indicates the length of the data packets already read from the circular storage module and / or the length of the data packets already stored in the circular storage module. Based on the indication information and the initial capacity information of the circular storage module, the current capacity information of the circular storage module is determined. It is then determined whether the current capacity information matches the length of the data packets output by the LDPC encoder. If they match, the data packets output by the LDPC encoder are stored in the address of the corresponding circular storage module. If they do not match, a new capacity information for the circular storage module is determined after a preset interval, until the new capacity information matches the length of the data packets output by the LDPC encoder, and the data packets output by the LDPC encoder are stored in the address of the corresponding circular storage module. By obtaining the indication information output by the circular storage module, the current capacity information of the circular storage module is determined in real time, and the data packets output by the LDPC encoder are stored in the address unit of the circular storage module based on the current capacity information. This ensures that smaller data packets consume different amounts of storage space than larger data packets, achieving flexible storage of variable-length data packets and effectively improving the storage efficiency for smaller data packets.

[0019] Optionally, based on the number of valid bits included in the first address and the second address and the start bit, the valid bits included in the first address and the second address are stored bit by bit into a shift register, including:

[0020] The first address is subjected to a first shift operation, and the effective bits included in the first address after the first shift operation are stored bit by bit into the shift register; wherein, the starting bit of the effective bits included in the first address after the first shift operation is the starting bit of the low-width bit in the shift register.

[0021] Based on the number of valid bits included in the first address and the second address and the start bit, a first signed number is determined; wherein, the first signed number is the two's complement of the difference between the value corresponding to the start bit of the valid bits included in the second address and the number of valid bits in the first address;

[0022] If the value corresponding to the sign bit of the first signed number is a first preset threshold, then the second address is subjected to a second shift process and a third shift process, and the effective bits included in the second address after the second shift process and the third shift process are stored bit by bit into the shift register; wherein, the start bit of the effective bits included in the second address after the second shift process is the start bit of the high-width bit in the shift register, and the start bit of the effective bits included in the second address after the third shift process is the bit after the stop bit of the effective bits included in the first address after the first shift process.

[0023] Optionally, after performing the first shift operation on the first address, the method further includes:

[0024] Determine a first mask; wherein the first mask is used to indicate the bit position in the shift register corresponding to the effective bit of the first address after the first shift processing;

[0025] According to the first mask, the effective bits included in the first address after the first shift processing are stored bit by bit into the shift register;

[0026] After performing a second shift operation and a third shift operation on the second address, the first mask is updated to determine the second mask; wherein, the second mask is used to indicate the bit position in the shift register corresponding to the effective bits of the first address after the first shift operation and the effective bits of the second address after the second shift operation and the third shift operation.

[0027] According to the second mask, the effective bits included in the second address after the second shift processing and the third shift processing are stored bit by bit into the shift register.

[0028] Optionally, the effective bits corresponding to the low-width bits in the shift register are stored bit by bit into the storage module of the LDPC bit interleaver, including:

[0029] A second signed number is determined based on the number of valid bits included in the first address and the second address; wherein, the second signed number is the original code corresponding to the sum of the number of valid bits included in the first address and the number of valid bits included in the second address;

[0030] If the value corresponding to the bit width indicator bit of the second signed number is the second preset threshold, then the effective bits corresponding to the low bit width in the shift register are stored bit by bit into the storage module of the LDPC bit interleaver; wherein, the bit width indicator bit is the bit in the second signed number that indicates the bit width of the circular storage module.

[0031] Optionally, after all the valid bits included in the data packet have been stored in the shift register, the method further includes:

[0032] Determine whether there are still valid bits in the high-width bits of the shift register;

[0033] If so, the effective bits corresponding to the high bit width are stored bit by bit into the storage module of the LDPC bit interleaver.

[0034] Secondly, embodiments of this application also provide an LDPC bit selection device applied to a low-density parity check (LDPC) bit selector. The LDPC bit selector includes a circular storage module composed of at least two address units, each address unit including at least one address. The device includes:

[0035] The first processing module is used to store the data packets output by the LDPC encoder into the corresponding address of the circular storage module according to the current capacity information of the circular storage module; wherein, the capacity information is used to indicate unused addresses in the circular storage module;

[0036] The determining module is used to obtain a first address and a second address corresponding to the data packet based on the parameter information of the data packet, and to determine the number of valid bits and the start bit included in the first address and the second address; wherein, the first address is the address where the start bit of the valid bits included in the data packet is located, and the second address is the address adjacent to the first address;

[0037] The second processing module is used to store the effective bits included in the first address and the second address bit by bit into a shift register based on the number of effective bits included in the first address and the second address and the start bit, and to store the effective bits corresponding to the low bit width in the shift register bit by bit into the storage module of the LDPC bit interleaver; wherein, the shift register is used to merge the effective bits included in the first address and the second address, and the low bit width is the bit width corresponding to the bit width of the circular storage module;

[0038] The third processing module is used to determine that the bit corresponding to the high-width bit in the shift register is the new first address, and the address adjacent to the second address is the new second address, and to store the valid bits included in the new first address and the new second address into the shift register bit by bit, until all the valid bits included in the data packet are stored into the shift register.

[0039] Optionally, the first processing module is specifically used for:

[0040] Obtain the indication information output by the circular storage module; wherein, the indication information is used to indicate the length of the data packets read from the circular storage module and / or the length of the data packets stored in the circular storage module;

[0041] Based on the instruction information and the initial capacity information of the circular storage module, determine the current capacity information of the circular storage module;

[0042] Determine whether the current capacity information matches the length of the data packet output by the LDPC encoder;

[0043] If a match is found, the data packet output by the LDPC encoder is stored in the address of the corresponding circular storage module.

[0044] If they do not match, the new capacity information of the circular storage module is determined after a preset period, until the new capacity information matches the length of the data packet output by the LDPC encoder, and the data packet output by the LDPC encoder is stored in the corresponding address of the circular storage module.

[0045] Optionally, the second processing module is specifically used for:

[0046] The first address is subjected to a first shift operation, and the effective bits included in the first address after the first shift operation are stored bit by bit into the shift register; wherein, the starting bit of the effective bits included in the first address after the first shift operation is the starting bit of the low-width bit in the shift register.

[0047] Based on the number of valid bits included in the first address and the second address and the start bit, a first signed number is determined; wherein, the first signed number is the two's complement of the difference between the value corresponding to the start bit of the valid bits included in the second address and the number of valid bits in the first address;

[0048] If the value corresponding to the sign bit of the first signed number is a first preset threshold, then the second address is subjected to a second shift process and a third shift process, and the effective bits included in the second address after the second shift process and the third shift process are stored bit by bit into the shift register; wherein, the start bit of the effective bits included in the second address after the second shift process is the start bit of the high-width bit in the shift register, and the start bit of the effective bits included in the second address after the third shift process is the bit after the stop bit of the effective bits included in the first address after the first shift process.

[0049] Optionally, the second processing module is specifically used for:

[0050] Determine a first mask; wherein the first mask is used to indicate the bit position in the shift register corresponding to the effective bit of the first address after the first shift processing;

[0051] According to the first mask, the effective bits included in the first address after the first shift processing are stored bit by bit into the shift register;

[0052] After performing a second shift operation and a third shift operation on the second address, the first mask is updated to determine the second mask; wherein, the second mask is used to indicate the bit position in the shift register corresponding to the effective bits of the first address after the first shift operation and the effective bits of the second address after the second shift operation and the third shift operation.

[0053] According to the second mask, the effective bits included in the second address after the second shift processing and the third shift processing are stored bit by bit into the shift register.

[0054] Optionally, the second processing module is specifically used for:

[0055] A second signed number is determined based on the number of valid bits included in the first address and the second address; wherein the second signed number is the original code corresponding to the sum of the number of valid bits included in the first address and the number of valid bits included in the second address;

[0056] If the value corresponding to the bit width indicator bit of the second signed number is the second preset threshold, then the effective bits corresponding to the low bit width in the shift register are stored bit by bit into the storage module of the LDPC bit interleaver; wherein, the bit width indicator bit is the bit in the second signed number that indicates the bit width of the circular storage module.

[0057] Optionally, the device further includes a determination module, the determination module being used to:

[0058] Determine whether there are still valid bits in the high-width bits of the shift register;

[0059] If so, the effective bits corresponding to the high bit width are stored bit by bit into the storage module of the LDPC bit interleaver.

[0060] Thirdly, embodiments of this application also provide an LDPC bit selector, comprising:

[0061] Memory, used to store program instructions;

[0062] A processor is configured to invoke program instructions stored in the memory and execute the steps included in any embodiment of the first aspect according to the obtained program instructions.

[0063] Fourthly, embodiments of this application also provide a storage medium storing computer-executable instructions for causing a computer to perform the steps included in any of the embodiments of the first aspect. Attached Figure Description

[0064] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application.

[0065] Figure 1a A schematic diagram of an LDPC bit selector provided in an embodiment of this application;

[0066] Figure 1b This is a schematic diagram of the structure of a circular storage module provided in an embodiment of this application;

[0067] Figure 2a A flowchart illustrating an LDPC bit selection method provided in an embodiment of this application;

[0068] Figure 2b A schematic diagram of data packets stored in a circular storage module provided in an embodiment of this application;

[0069] Figure 2c This is a schematic diagram illustrating a first displacement operation on a first address, provided in an embodiment of this application.

[0070] Figure 2d This application provides a schematic diagram illustrating a second displacement process and a third displacement process for a second address, as provided in an embodiment of the present application.

[0071] Figure 2e A schematic diagram illustrating the merging of valid bits included in the first and second addresses of a shift register, provided as an embodiment of this application;

[0072] Figure 3 A schematic diagram of the structure of an LDPC bit selection device provided in an embodiment of this application;

[0073] Figure 4 This is a schematic diagram of another LDPC bit selector provided in an embodiment of this application. Detailed Implementation

[0074] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. Unless otherwise specified, the embodiments and features in the embodiments of this application can be arbitrarily combined with each other. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described can be performed in a different order than that shown here.

[0075] The terms "first" and "second" in the specification, claims, and accompanying drawings of this application are used to distinguish different objects and not to describe a specific order. Furthermore, the term "comprising" and any variations thereof are intended to cover non-exclusive protection. For example, a process, method, system, product, or apparatus that comprises a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to such processes, methods, products, or apparatus.

[0076] In this application embodiment, "at least one" can mean at least two, such as two, three or more, and this application embodiment does not impose any restrictions.

[0077] Furthermore, the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article, unless otherwise specified, generally indicates that the preceding and following related objects have an "or" relationship.

[0078] Currently, LDPC bit selectors use a ping-pong buffering mechanism to store the data packets output by the LDPC encoder. Since smaller data packets consume the same amount of storage space as larger ones, the storage efficiency for smaller packets is low. Furthermore, when processing the bit-selected data, a significant amount of storage space is used to store the corresponding mask for each data packet, increasing the consumption of on-chip FPGA resources. Therefore, current LDPC bit selectors suffer from the technical problem of using excessive storage space to store the mask for each data packet, thus increasing the consumption of on-chip FPGA resources.

[0079] Therefore, embodiments of this application provide an LDPC bit selection method applied to low-density parity check codes. The LDPC bit selector includes a circular storage module consisting of at least two address units, each address unit containing at least one address. This method uses the current capacity information of the circular storage module to store data packets output by the LDPC encoder into the address units of the circular storage module. This allows smaller data packets to consume different amounts of storage space than larger ones, enabling flexible storage of variable-length data packets and effectively improving storage efficiency for smaller packets. After storing the data packet into the address units of the circular storage module, two addresses are first concatenated, then another address is concatenated with the concatenated address, and so on, until all addresses corresponding to the data packet in the storage module have been concatenated. The LDPC bit selector aligns the valid bits in the data packet and sends the aligned valid bits to the LDPC bit interleaver. This avoids the need for excessive storage space to store the mask corresponding to the data packet when processing the bit-selected data, allowing the LDPC bit interleaver to align the valid bits in the data packet based on the mask, thus reducing the consumption of on-chip FPGA resources.

[0080] To better understand the above technical solutions, the technical solutions of this application will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the embodiments of this application and the specific features in the embodiments are simple descriptions of the technical solutions of this application, rather than limitations on the technical solutions of this application. Unless otherwise specified, the embodiments of this application and the technical features in the embodiments can be combined with each other.

[0081] Figure 1a This is a schematic diagram of the structure of an LDPC bit selector to which the method provided in this application embodiment is applicable. It should be understood that the method provided in this application embodiment can be applied to various LDPC bit selectors. Figure 1a The LDPC bit selector shown is a simple illustration of an LDPC bit selector applicable to the methods provided in the embodiments of this application, and not a limitation thereof.

[0082] Figure 1a The LDPC bit selector shown includes a circular storage module 100, a control module 101, an address calculation module 102, a bit calculation module 103, a mask calculation module 104, a data merging module 105, and a shift data module 106.

[0083] It should be noted that, in this embodiment of the application, the circular storage module 100 includes at least two address units, each address unit including at least one address, for example, such as... Figure 1b The diagram shown is a schematic of a circular storage module provided in an embodiment of this application. The circular storage module 100 includes 32 address units, each address unit including 16 addresses. The bit width of the circular storage module 100 is 128 bits, meaning each address can store 128 bits of data, and each address unit can store 2048 bits of data. The circular storage module 100 is used to store data packets output by the LDPC encoder.

[0084] The control module 101 is used to read the parameter information of the data packet stored in the circular storage module 100, obtain the first address and the second address corresponding to the data packet based on the parameter information of the data packet, and start the bit selection of the data packet. The first address is the address where the start bit of the effective bits included in the data packet is located, and the second address is the address adjacent to the first address.

[0085] The address calculation module 102 is used to calculate the number of valid bits and the start bit included in the first address and the second address.

[0086] The bit calculation module 103 is used to calculate a first signed number and a second signed number. The first signed number is the complement of the difference between the value of the start bit of the effective bits included in the second address and the number of effective bits in the first address. The second signed number is the original code of the sum of the number of effective bits included in the first address and the number of effective bits included in the second address.

[0087] The mask calculation module 104 is used to calculate the mask corresponding to the address, wherein the mask is used to indicate the bits in the shift register corresponding to the effective bits included in the address.

[0088] The data merging module 105 includes a shift register, which is used to merge the valid bits included in the first address and the second address that are stored bit by bit in the shift register.

[0089] The shift data module 106 is used to store the valid bits corresponding to the low bit width in the shift register into the storage module of the LDPC bit interleaver, wherein the low bit width is the bit width corresponding to the bit width of the circular storage module 100.

[0090] Figure 2a This is a flowchart illustrating an LDPC bit selection method provided in an embodiment of this application. The method can be derived from the aforementioned... Figure 1a and Figure 1b The LDPC bit selector shown is executed. The specific process of this method is described below.

[0091] Step 201: Based on the current capacity information of the circular storage module, store the data packets output by the LDPC encoder into the address of the corresponding circular storage module.

[0092] In this embodiment of the application, the data packets output by the LDPC encoder can be stored in the address of the corresponding circular storage module according to the current capacity information of the circular storage module in the LDPC bit selector. The capacity information is used to indicate the unused address in the circular storage module.

[0093] Specifically, the system obtains the indication information output by the circular storage module. This indication information indicates the length of the data packets read from the circular storage module and / or the length of the data packets already stored in the circular storage module. Based on the indication information and the initial capacity information of the circular storage module, the system determines the current capacity information of the circular storage module. It then checks whether the current capacity information matches the length of the data packets output by the LDPC encoder. If they match, the data packets output by the LDPC encoder are stored in the address of the corresponding circular storage module. If they do not match, the system determines the new capacity information of the circular storage module after a preset interval, until the new capacity information matches the length of the data packets output by the LDPC encoder. Finally, the data packets output by the LDPC encoder are stored in the address of the corresponding circular storage module.

[0094] For example, if the circular storage module initially includes 32 address units, each address unit includes 16 addresses, and each address can store 128 bits of data, then the initial capacity information of the circular storage module will indicate that there are 512 unused addresses in the circular storage module.

[0095] When the indication information output by the circular storage module only indicates that the length of the data packet stored in the circular storage module is 2500 bits, it can be determined that storing the data packet in the circular storage module will consume ceil(2500, 128) = 20 addresses, where ceil is a rounding function. Then the current capacity information of the circular storage module is that there are 512-20 = 492 unused addresses in the circular storage module.

[0096] When the indication information output by the circular storage module only indicates that the length of the data packet read from the circular storage module is 1500 bits, it can be determined that storing the read data packet in the circular storage module will consume ceil(1500, 128) = 12 addresses. Then the current capacity information of the circular storage module will indicate that there are 512 + 12 = 524 unused addresses in the circular storage module.

[0097] When the indication information output by the circular storage module only indicates that the length of the data packet stored in the circular storage module is 2500 bits and the length of the data packet read from the circular storage module is 1500 bits, it can be determined that storing the data packet in the circular storage module will consume ceil(2500, 128) = 20 addresses, and storing the data packet read from the circular storage module will consume ceil(1500, 128) = 12 addresses. Therefore, the current capacity information of the circular storage module will indicate that there are 512-20+12 = 504 unused addresses in the circular storage module.

[0098] If the current capacity information of the circular storage module indicates that there are 512 unused addresses in the circular storage module (i.e., the circular storage module can store 512*128=65536 bits of data), and the length of the data packet output by the LDPC encoder is 2500 bits, then it is determined that the current capacity information matches the length of the data packet output by the LDPC encoder, and the data packet output by the LDPC encoder is stored in the corresponding address of the circular storage module.

[0099] If the current capacity information of the circular storage module indicates that there are 20 unused addresses in the circular storage module (i.e., the circular storage module can store 20 * 128 = 25606 bits of data), and the length of the data packet output by the LDPC encoder is 3500 bits, then it is determined that the current capacity information does not match the length of the data packet output by the LDPC encoder. After a preset interval, the new capacity information of the circular storage module is determined, until the new capacity information matches the length of the data packet output by the LDPC encoder, and the data packet output by the LDPC encoder is stored in the corresponding address of the circular storage module.

[0100] Step 202: Based on the parameter information of the data packet, obtain the first address and the second address corresponding to the data packet, and determine the number of valid bits and the start bit included in the first address and the second address.

[0101] In this embodiment, after storing the data packet output by the LDPC encoder into the address of the corresponding circular storage module, the control module in the LDPC bit selector can first read the parameter information of the data packet stored in the circular storage module. This parameter information is used to parse the data packet. Based on the parameter information, a first address and a second address corresponding to the data packet are obtained. The first address is the address where the start bit of the valid bits included in the data packet is located, and the second address is the address adjacent to the first address. Then, the address calculation module in the LDPC bit selector determines the number of valid bits included in the first address and the start bit of the second address.

[0102] For example, such as Figure 2bThe diagram shown is a schematic of a data packet stored in a circular storage module provided in an embodiment of this application. The circular storage module has a bit width of 16 bits, that is, each address can store 128 bits of data. The first address is the address where the start bit of the effective bits included in the data packet is located. The first address includes 10 effective bits and the start bit of the effective bits is bit 6. The second address is the address adjacent to the first address. The second address includes 16 effective bits and the start bit of the effective bits is bit 0.

[0103] Step 203: Based on the number of valid bits included in the first address and the second address and the start bit, store the valid bits included in the first address and the second address bit by bit into the shift register, and store the valid bits corresponding to the low bit width in the shift register bit by bit into the storage module of the LDPC bit interleaver.

[0104] In this embodiment of the application, after determining the number of valid bits and the start bit included in the first address and the second address, the valid bits included in the first address and the second address can be stored bit by bit into the shift register of the merging data module in the LDPC bit selector based on the number of valid bits included in the first address and the second address and the start bit, so that the shift register can perform merging processing on the valid bits included in the first address and the second address stored bit by bit into the shift register.

[0105] Specifically, a first bit shift is performed on the first address, and the effective bits of the first address after the first bit shift are stored bit by bit into a shift register. The start bit of the effective bits of the first address after the first bit shift is the start bit of the low-width shift register, and the low-width shift register corresponds to the width of the circular storage module. Based on the number of effective bits and the start bit of the first and second addresses, a first signed number is determined. The first signed number is the two's complement of the difference between the value corresponding to the start bit of the effective bits of the second address and the number of effective bits of the first address. If the value corresponding to the sign bit of the first signed number is a first preset threshold, a second bit shift and a third bit shift are performed on the second address. The effective bits of the second address after the second bit shift and the third bit shift are stored bit by bit into a shift register. The start bit of the effective bits of the second address after the second bit shift is the start bit of the high-width shift register, and the start bit of the effective bits of the second address after the third bit shift is the bit after the stop bit of the effective bits of the first address after the first bit shift.

[0106] For example, Figure 2b The first address in the code includes 10 valid bits, with bit 6 as the starting bit. The second address includes 16 valid bits, with bit 0 as the starting bit. Figure 2c The diagram shown is a schematic diagram of performing a first displacement operation on a first address according to an embodiment of this application. Figure 2c The shift register in the middle is 32 bits wide. Figure 2b The effective bits included in the first address are in the shift register starting bit 6. Figure 2b The first address in the shift register is subjected to a first shift operation, such that the starting bit of the effective bits included in the first address after the first shift operation is bit 0 (the starting bit of the low-width shift register). That is, the first shift operation is to shift the starting bit of the effective bits included in the first address to the right by 6 bits.

[0107] Sure Figure 2b The value corresponding to the start bit of the effective bits included in the second address is the same as... Figure 2b The difference in the number of effective bits at the first address is 6 - 10 = -4. The two's complement of -4 is 10110, meaning the first signed number is 10110, where the sign bit of the first signed number corresponds to a value of 1. If the first preset threshold is 1, then for... Figure 2b The second address in the memory is used for the second displacement process and the third displacement process.

[0108] like Figure 2d The diagram shown is a schematic diagram illustrating a second displacement process and a third displacement process for a second address provided in an embodiment of this application. Figure 2d The shift register in the middle is 32 bits wide. Figure 2b The effective bits included in the second address are starting at bit 0 in the shift register. Figure 2b The second address is subjected to a second shift operation, such that the starting bit of the effective bits included in the second address after the second shift operation is bit 16 (the starting bit of the high-width bits in the shift register). That is, the second shift operation is to shift the starting bit of the effective bits included in the second address to the left by 16 bits. The second address after the second shift operation is subjected to a third shift operation, such that the starting bit of the effective bits included in the second address after the second shift operation and the third shift operation is bit 10 (the bit after the stop bit 9 of the first address after the first shift operation). That is, the third shift operation is to shift the starting bit of the effective bits included in the second address after the second shift operation to the right by 6 bits.

[0109] It should be noted that, in this embodiment, after performing a first bit shift on the first address, the first mask can be determined by the mask calculation module in the LDPC bit selector. The first mask indicates the bits in the shift register corresponding to the valid bits included in the first address after the first bit shift, so that the valid bits included in the first address after the first bit shift can be stored bit by bit in the shift register according to the first mask. For example, Figure 2c The mask corresponding to the effective bits included in the first address after the first bit shift is 0x0000_03ff.

[0110] After performing the second and third shift operations on the second address, the first mask can be updated using the mask calculation module in the LDPC bit selector to determine the second mask. The second mask indicates the corresponding bits in the shift register of the effective bits of the first address after the first shift operation and the effective bits of the second address after the second and third shift operations, so that the effective bits of the second address after the second and third shift operations can be stored bit-by-bit in the shift register according to the second mask. For example, for... Figure 2c The mask 0x0000_03ff corresponding to the effective bits included in the first address after the first bit shift is updated to determine the position. Figure 2c The effective bits included in the first address after the first bit shifting are Figure 2d The mask corresponding to the effective bits after merging the effective bits included in the second address after the second and third shift processing is 0x03ff_ffff.

[0111] After storing the valid bits included in the first and second addresses into the shift register of the merged data module in the LDPC bit selector, the valid bits corresponding to the low bit width in the shift register can be stored into the storage module of the LDPC bit interleaver through the shift data module in the LDPC bit selector.

[0112] Specifically, based on the number of valid bits included in the first address and the second address, a second signed number is determined, wherein the second signed number is the original code corresponding to the sum of the number of valid bits included in the first address and the number of valid bits included in the second address. If the value corresponding to the bit width indicator bit of the second signed number is a second preset threshold, then the valid bits corresponding to the low bit width in the shift register are stored bit by bit into the storage module of the LDPC bit interleaver, wherein the bit width indicator bit is the bit in the second signed number that indicates the bit width of the circular storage module.

[0113] For example, determine Figure 2b The number of valid bits included in the first address and Figure 2b The sum of the number of valid bits included in the second address is 10 + 16 = 26. The original code corresponding to 26 is 11010, that is, the second signed number is 11010. Among them, the bit indicating the bit width (16 bits) of the circular storage module in the second signed number is bit 4. Then the value corresponding to the bit width indicator bit of the second signed number is 1. If the second preset threshold is 1, then after storing the valid bits included in the first address after the first shift processing into the shift register, and after storing the valid bits included in the second address after the second shift processing and the third shift processing into the shift register, the valid bits corresponding to the low bit width in the shift register are stored into the storage module of the LDPC bit interleaver.

[0114] like Figure 2e The diagram shown is a schematic representation of an embodiment of this application that combines the valid bits included in the first and second addresses of a shift register stored bit by bit. Figure 2e The shift register in the shift register has a bit width of 32 bits. After the effective bits of the first address after the first shift processing are stored bit by bit into the shift register, the effective bits of the first address after the first shift processing are bit 0 (the start bit of the low bit width in the shift register). After the effective bits of the second address after the second and third shift processing are stored bit by bit into the shift register, the start bit of the effective bits of the second address after the second and third shift processing is bit 10 (the bit after the stop bit 9 of the shift register for the effective bits of the first address after the first shift processing). This allows the shift register to merge the effective bits of the first address and the second address stored bit by bit into the shift register. Then, the effective bits corresponding to the low bit width in the shift register are stored bit by bit into the storage module of the LDPC bit interleaver, and the bits corresponding to the high bit width in the shift register are determined as the new first address.

[0115] Step 204: Determine the bit corresponding to the high-width bit in the shift register as the new first address, and the address adjacent to the second address as the new second address. Store the valid bits included in the new first address and the new second address into the shift register bit by bit until all valid bits included in the data packet are stored into the shift register.

[0116] In this embodiment, after storing the valid bits corresponding to the low bit width in the shift register into the storage module of the LDPC bit interleaver, the bits corresponding to the high bit width in the shift register are determined as the new first address, and the address adjacent to the second address is determined as the new second address. The valid bits included in the new first address and the new second address are then stored into the shift register bit by bit until all valid bits included in the data packet are stored into the shift register.

[0117] It should be noted that, in this embodiment of the application, after all the valid bits included in the data packet are stored in the shift register, it can be determined whether there are still corresponding valid bits in the high-width bits of the shift register. If so, the valid bits corresponding to the high-width bits are stored bit by bit in the storage module of the LDPC bit interleaver.

[0118] The above scheme uses the current capacity information of the circular storage module to store the data packets output by the LDPC encoder into the address unit of the circular storage module. This allows smaller data packets to consume different amounts of storage space than larger data packets, enabling flexible storage of variable-length data packets and effectively improving the storage efficiency for smaller data packets. After storing the data packet into the address unit of the circular storage module, two addresses are first selected for concatenation, and then another address is selected and concatenated with the concatenated address. This process continues until all addresses corresponding to the data packet in the storage module have been concatenated. The LDPC bit selector then aligns the valid bits in the data packet and sends the aligned valid bits to the LDPC bit interleaver. This avoids the need for excessive storage space to store the mask corresponding to the data packet when processing the bit-selected data, allowing the LDPC bit interleaver to align the valid bits in the data packet based on the mask, thus reducing the consumption of on-chip FPGA resource storage.

[0119] Based on the same inventive concept, embodiments of this application provide an LDPC bit selection device, which can be applied to the aforementioned... Figure 1a and Figure 1b The LDPC bit selector shown is capable of implementing the aforementioned... Figure 2a The illustrated LDPC bit selection method corresponds to the following function. This LDPC bit selection device can be a hardware structure, a software module, or a hardware structure plus a software module. This LDPC bit selection device can be implemented by a chip system, which can consist of chips or include chips and other discrete components. Figure 3 A schematic diagram of an LDPC bit selection device provided in an embodiment of this application is shown below. Figure 3 As shown, the LDPC bit selection device includes a first processing module 301, a determination module 302, a second processing module 303, and a third processing module 304, wherein:

[0120] The first processing module 301 is used to store the data packets output by the LDPC encoder into the corresponding address of the circular storage module according to the current capacity information of the circular storage module; wherein the capacity information is used to indicate unused addresses in the circular storage module.

[0121] The determining module 302 is used to obtain a first address and a second address corresponding to the data packet based on the parameter information of the data packet, and to determine the number of valid bits and the start bit included in the first address and the second address; wherein, the first address is the address where the start bit of the valid bits included in the data packet is located, and the second address is the address adjacent to the first address;

[0122] The second processing module 303 is used to store the effective bits included in the first address and the second address bit by bit into a shift register based on the number of effective bits included in the first address and the second address and the start bit, and to store the effective bits corresponding to the low bit width in the shift register bit by bit into the storage module of the LDPC bit interleaver; wherein, the shift register is used to perform merging processing on the effective bits included in the first address and the second address, and the low bit width is the bit width corresponding to the bit width of the circular storage module;

[0123] The third processing module 304 is used to determine that the bit corresponding to the high-width bit in the shift register is the new first address, and the address adjacent to the second address is the new second address, and to store the valid bits included in the new first address and the new second address into the shift register bit by bit, until all the valid bits included in the data packet are stored into the shift register.

[0124] Optionally, the first processing module 301 is specifically used for:

[0125] Obtain the indication information output by the circular storage module; wherein, the indication information is used to indicate the length of the data packets read from the circular storage module and / or the length of the data packets stored in the circular storage module;

[0126] Based on the instruction information and the initial capacity information of the circular storage module, determine the current capacity information of the circular storage module;

[0127] Determine whether the current capacity information matches the length of the data packet output by the LDPC encoder;

[0128] If a match is found, the data packet output by the LDPC encoder is stored in the address of the corresponding circular storage module.

[0129] If they do not match, the new capacity information of the circular storage module is determined after a preset period, until the new capacity information matches the length of the data packet output by the LDPC encoder, and the data packet output by the LDPC encoder is stored in the corresponding address of the circular storage module.

[0130] Optionally, the second processing module 303 is specifically used for:

[0131] The first address is subjected to a first shift operation, and the effective bits included in the first address after the first shift operation are stored bit by bit into the shift register; wherein, the starting bit of the effective bits included in the first address after the first shift operation is the starting bit of the low-width bit in the shift register.

[0132] Based on the number of valid bits included in the first address and the second address and the start bit, a first signed number is determined; wherein, the first signed number is the two's complement of the difference between the value corresponding to the start bit of the valid bits included in the second address and the number of valid bits in the first address;

[0133] If the value corresponding to the sign bit of the first signed number is a first preset threshold, then the second address is subjected to a second shift process and a third shift process, and the effective bits included in the second address after the second shift process and the third shift process are stored bit by bit into the shift register; wherein, the start bit of the effective bits included in the second address after the second shift process is the start bit of the high-width bit in the shift register, and the start bit of the effective bits included in the second address after the third shift process is the bit after the stop bit of the effective bits included in the first address after the first shift process.

[0134] Optionally, the second processing module 303 is specifically used for:

[0135] Determine a first mask; wherein the first mask is used to indicate the bit position in the shift register corresponding to the effective bit of the first address after the first shift processing;

[0136] According to the first mask, the effective bits included in the first address after the first shift processing are stored bit by bit into the shift register;

[0137] After performing a second shift operation and a third shift operation on the second address, the first mask is updated to determine the second mask; wherein, the second mask is used to indicate the bit position in the shift register corresponding to the effective bits of the first address after the first shift operation and the effective bits of the second address after the second shift operation and the third shift operation.

[0138] According to the second mask, the effective bits included in the second address after the second shift processing and the third shift processing are stored bit by bit into the shift register.

[0139] Optionally, the second processing module 303 is specifically used for:

[0140] A second signed number is determined based on the number of valid bits included in the first address and the second address; wherein, the second signed number is the original code corresponding to the sum of the number of valid bits included in the first address and the number of valid bits included in the second address;

[0141] If the value corresponding to the bit width indicator bit of the second signed number is the second preset threshold, then the effective bits corresponding to the low bit width in the shift register are stored bit by bit into the storage module of the LDPC bit interleaver; wherein, the bit width indicator bit is the bit in the second signed number that indicates the bit width of the circular storage module.

[0142] Optionally, the device further includes a determination module, the determination module being used to:

[0143] Determine whether there are still valid bits in the high-width bits of the shift register;

[0144] If so, the effective bits corresponding to the high bit width are stored bit by bit into the storage module of the LDPC bit interleaver.

[0145] Based on the same inventive concept, this application also provides an LDPC bit selector. Figure 4 A schematic diagram of an LDPC bit selector provided in an embodiment of this application is shown below. Figure 4 As shown, the LDPC bit selector includes at least one processor 402 and a memory 401 connected to the at least one processor. In this embodiment, the specific connection medium between the processor 402 and the memory 401 is not limited. Figure 4 Taking the connection between processor 402 and memory 401 via bus 400 as an example, bus 400 in Figure 4 The connections between other components are indicated by thick lines and are for illustrative purposes only, not as a limitation. The 400 bus can be divided into address bus, data bus, control bus, etc., for ease of representation. Figure 4 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0146] In this embodiment, the memory 401 stores instructions executable by at least one processor 402. The processor 402 can execute the steps included in the aforementioned LDPC bit selection method by calling the instructions stored in the memory 401. The processor 402 is the control center of the LDPC bit selector and can connect to various parts of the LDPC bit selector using various interfaces and lines. By executing the instructions stored in the memory 401, it realizes various functions of the LDPC bit selector. Optionally, the processor 402 may include one or more processing units. The processor 402 may integrate an application processor and a modem processor. The application processor mainly handles the operating system, user interface, and applications, while the modem processor mainly handles wireless communication. It is understood that the modem processor may not be integrated into the processor 402. In some embodiments, the processor 402 and the memory 401 can be implemented on the same chip; in some embodiments, they can also be implemented on separate chips.

[0147] Memory 401, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules. Optionally, memory 401 may include at least one type of storage medium, such as flash memory, hard disk, multimedia card, card-type memory, random access memory (RAM), static random access memory (SRAM), programmable read-only memory (PROM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), magnetic memory, magnetic disk, optical disk, etc. Memory 401 can be any other medium capable of carrying or storing desired program code in the form of instructions or data structures that can be accessed by a computer, but is not limited thereto. Memory 401 in the embodiments of this application may also be a circuit or any other device capable of implementing storage functions for storing program instructions and / or data.

[0148] Processor 402 can be a general-purpose processor, such as a central processing unit (CPU), digital signal processor, application-specific integrated circuit, field-programmable gate array or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component, capable of implementing or executing the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the LDPC bit selection method disclosed in the embodiments of this application can be directly manifested as being executed by a hardware processor, or executed by a combination of hardware and software modules within the processor.

[0149] By designing and programming the processor 402, the code corresponding to the LDPC bit selection method described in the foregoing embodiments can be embedded into the chip, so that the chip can execute the steps of the aforementioned LDPC bit selection method during operation. How to design and program the processor 402 is a well-known technique to those skilled in the art, and will not be described in detail here.

[0150] Based on the same inventive concept, embodiments of this application also provide a storage medium storing computer instructions that, when executed on a computer, cause the computer to perform the steps of the LDPC bit selection method as described above.

[0151] Optionally, various aspects of the LDPC bit selection method provided in this application can also be implemented as a program product, which includes program code. When the program product is run on an LDPC bit selector, the program code is used to cause the LDPC bit selector to perform the steps in the LDPC bit selection method described in the foregoing embodiments.

[0152] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0153] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in one or more blocks of the flowchart illustrations and / or one or more blocks of the block diagrams.

[0154] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means that implement the functions specified in one or more flowcharts and / or one or more block diagrams.

[0155] These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, such that the instructions, which execute on the computer or other programmable apparatus, provide steps for implementing the functions specified in one or more flowcharts and / or one or more block diagrams.

[0156] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. An LDPC bit selection method, characterized in that, An application to a low-density parity-check (LDPC) bit selector, the LDPC bit selector comprising a circular storage module consisting of at least two address units, each address unit including at least one address, the method comprising: Based on the current capacity information of the circular storage module, the data packets output by the LDPC encoder are stored in the corresponding address of the circular storage module; wherein, the capacity information is used to indicate unused addresses in the circular storage module; Based on the parameter information of the data packet, obtain the first address and the second address corresponding to the data packet, and determine the number of valid bits and the start bit included in the first address and the second address; wherein, the first address is the address where the start bit of the valid bits included in the data packet is located, and the second address is the address adjacent to the first address; Based on the number of valid bits included in the first address and the second address and the start bit, the valid bits included in the first address and the second address are stored bit by bit into a shift register, and the valid bits corresponding to the low bit width in the shift register are stored bit by bit into the storage module of the LDPC bit interleaver; wherein, the shift register is used to merge the valid bits included in the first address and the second address, and the low bit width is the bit width corresponding to the bit width of the circular storage module; The bit corresponding to the high-width bit in the shift register is determined as the new first address, and the address adjacent to the second address is determined as the new second address. The valid bits included in the new first address and the new second address are stored bit by bit into the shift register until all valid bits included in the data packet are stored into the shift register.

2. The method as described in claim 1, characterized in that, Based on the current capacity information of the circular storage module, the data packets output by the LDPC encoder are stored into the corresponding address of the circular storage module, including: Obtain the indication information output by the circular storage module; wherein, the indication information is used to indicate the length of the data packets read from the circular storage module and / or the length of the data packets stored in the circular storage module; Based on the instruction information and the initial capacity information of the circular storage module, determine the current capacity information of the circular storage module; Determine whether the current capacity information matches the length of the data packet output by the LDPC encoder; If a match is found, the data packet output by the LDPC encoder is stored in the address of the corresponding circular storage module. If they do not match, the new capacity information of the circular storage module is determined after a preset period, until the new capacity information matches the length of the data packet output by the LDPC encoder, and the data packet output by the LDPC encoder is stored in the corresponding address of the circular storage module.

3. The method as described in claim 1 or 2, characterized in that, Based on the number of valid bits included in the first address and the second address, and the start bit, the valid bits included in the first address and the second address are stored bit by bit into the shift register, including: The first address is subjected to a first shift operation, and the effective bits included in the first address after the first shift operation are stored bit by bit into the shift register; wherein, the starting bit of the effective bits included in the first address after the first shift operation is the starting bit of the low-width bit in the shift register. Based on the number of valid bits included in the first address and the second address and the start bit, a first signed number is determined; wherein, the first signed number is the two's complement of the difference between the value corresponding to the start bit of the valid bits included in the second address and the number of valid bits in the first address; If the value corresponding to the sign bit of the first signed number is a first preset threshold, then the second address is subjected to a second shift process and a third shift process, and the effective bits included in the second address after the second shift process and the third shift process are stored bit by bit into the shift register; wherein, the start bit of the effective bits included in the second address after the second shift process is the start bit of the high-width bit in the shift register, and the start bit of the effective bits included in the second address after the third shift process is the bit after the stop bit of the effective bits included in the first address after the first shift process.

4. The method as described in claim 3, characterized in that, After performing the first bitwise shift operation on the first address, the method further includes: Determine a first mask; wherein the first mask is used to indicate the bit position in the shift register corresponding to the effective bit of the first address after the first shift processing; According to the first mask, the effective bits included in the first address after the first shift processing are stored bit by bit into the shift register; After performing a second shift operation and a third shift operation on the second address, the first mask is updated to determine the second mask; wherein, the second mask is used to indicate the bit position in the shift register corresponding to the effective bits of the first address after the first shift operation and the effective bits of the second address after the second shift operation and the third shift operation. According to the second mask, the effective bits included in the second address after the second shift processing and the third shift processing are stored bit by bit into the shift register.

5. The method as described in claim 4, characterized in that, The process of storing the effective bits corresponding to the low-width bits in the shift register into the storage module of the LDPC bit interleaver includes: A second signed number is determined based on the number of valid bits included in the first address and the second address; wherein, the second signed number is the original code corresponding to the sum of the number of valid bits included in the first address and the number of valid bits included in the second address; If the value corresponding to the bit width indicator bit of the second signed number is the second preset threshold, then the effective bits corresponding to the low bit width in the shift register are stored bit by bit into the storage module of the LDPC bit interleaver; wherein, the bit width indicator bit is the bit in the second signed number that indicates the bit width of the circular storage module.

6. The method as described in claim 4, characterized in that, After all valid bits included in the data packet have been stored in the shift register, the following steps are also included: Determine whether there are still valid bits in the high-width bits of the shift register; If so, the effective bits corresponding to the high bit width are stored bit by bit into the storage module of the LDPC bit interleaver.

7. An LDPC bit selection device, characterized in that, An LDPC bit selector for low-density parity-check codes is provided, the LDPC bit selector comprising a circular storage module consisting of at least two address units, each address unit including at least one address, the device comprising: The first processing module is used to store the data packets output by the LDPC encoder into the corresponding address of the circular storage module according to the current capacity information of the circular storage module; wherein, the capacity information is used to indicate unused addresses in the circular storage module; The determining module is used to obtain a first address and a second address corresponding to the data packet based on the parameter information of the data packet, and to determine the number of valid bits and the start bit included in the first address and the second address; wherein, the first address is the address where the start bit of the valid bits included in the data packet is located, and the second address is the address adjacent to the first address; The second processing module is used to store the effective bits included in the first address and the second address bit by bit into a shift register based on the number of effective bits included in the first address and the second address and the start bit, and to store the effective bits corresponding to the low bit width in the shift register bit by bit into the storage module of the LDPC bit interleaver; wherein, the shift register is used to merge the effective bits included in the first address and the second address, and the low bit width is the bit width corresponding to the bit width of the circular storage module; The third processing module is used to determine that the bit corresponding to the high-width bit in the shift register is the new first address, and the address adjacent to the second address is the new second address, and to store the valid bits included in the new first address and the new second address into the shift register bit by bit, until all the valid bits included in the data packet are stored into the shift register.

8. The apparatus as claimed in claim 7, characterized in that, The first processing module is specifically used for: Obtain the indication information output by the circular storage module; wherein, the indication information is used to indicate the length of the data packets read from the circular storage module and / or the length of the data packets stored in the circular storage module; Based on the instruction information and the initial capacity information of the circular storage module, determine the current capacity information of the circular storage module; Determine whether the current capacity information matches the length of the data packet output by the LDPC encoder; If a match is found, the data packet output by the LDPC encoder is stored in the address of the corresponding circular storage module. If they do not match, the new capacity information of the circular storage module is determined after a preset period, until the new capacity information matches the length of the data packet output by the LDPC encoder, and the data packet output by the LDPC encoder is stored in the corresponding address of the circular storage module.

9. An LDPC bit selector, characterized in that, include: Memory, used to store program instructions; A processor is configured to invoke program instructions stored in the memory and execute the steps of the method according to any one of claims 1-6.

10. A storage medium, characterized in that, The storage medium stores computer-executable instructions for causing a computer to perform the steps included in the method of any one of claims 1-6.

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