Test method of general input-output interface and related device

Abstract

The application discloses a test method of a general input and output interface and related devices, comprising: obtaining pin information of a target general input and output GPIO interface, numbering all pins according to a preset order according to the pin information, and generating a pin set; performing pin matching according to a preset rule in the pin set to generate a plurality of pin combinations; electrically connecting all pins in each pin combination, setting an input mode and an output mode in each pin combination according to the numbering; when detecting that the level of the input mode and the level of the output mode in a target pin combination are inconsistent, separately detecting the target pin combination to determine an abnormal pin; and through detecting the pin combination, the effect of quickly obtaining a small group in which the abnormal pin is located is achieved, and further, through separately detecting the small group of abnormal pins, the fast positioning of the abnormal pin is achieved.

Description

Technical Field

[0001] This application relates to the field of testing general-purpose input / output interfaces, and in particular to a testing method and related apparatus for general-purpose input / output interfaces. Background Technology

[0002] The pins on a microcontroller unit (MCU) chip are generally divided into four categories: power supply, clock, control, and I / O. I / O ports are further divided into General Purpose Input Output (GPIO) and multiplexed I / O (such as SPI / I2C / UART).

[0003] In industrial control computer applications, industrial control systems are typically equipped with dozens of GPIO ports for outputting control signals or detecting external input signals. While the output or input signals are simply high or low voltage levels, these signals are crucial in industrial control systems. (For example, a GPIO might output a high voltage level to open an access control system and a low voltage level to close it; a GPIO might input a high voltage level to trigger a smoke alarm and a low voltage level to indicate that the smoke alarm is functioning normally.) Therefore, ensuring the proper functioning of the GPIOs is extremely important.

[0004] Currently, to ensure the proper functioning of GPIOs in industrial control computers, the common method is to test by inputting high / low levels to the corresponding pins of the GPIO, then reading the pin status through software and comparing the results. Conversely, the method involves outputting high / low levels to the corresponding pins of the GPIO, then measuring the pin levels with a multimeter and comparing the results. This method is extremely inefficient and inconvenient for testing or on-site troubleshooting. While it's manageable for a single GPIO, testing 30 GPIOs becomes very time-consuming and labor-intensive. Especially in factory production testing, manual step-by-step setup and measurement are required, consuming a considerable amount of time for this single test.

[0005] Therefore, how to quickly detect abnormal interfaces of general input and output has become a technical problem that urgently needs to be solved. Summary of the Invention

[0006] To enable rapid detection of abnormal interfaces of general-purpose input / output interfaces, this application provides a testing method and related apparatus for general-purpose input / output interfaces.

[0007] Firstly, the testing method for a general input / output interface provided in this application adopts the following technical solution: A testing method for a general-purpose input / output interface includes obtaining pin information of a target general-purpose input / output (GPIO) interface, numbering all pins according to a preset order based on the pin information, and generating a pin set. A number of pin combinations are generated by matching pins in the pin set according to preset rules; In each pin combination, all pins are electrically connected, and the input mode and output mode are set in each pin combination according to the numbering. When the level of the input mode and the level of the output mode in the target pin combination are found to be inconsistent, the target pin combination is individually detected to identify the abnormal pin.

[0008] Optionally, the step of obtaining the pin information of the target general-purpose input / output (GPIO) interface, numbering all pins according to a preset order based on the pin information, and generating a pin set includes: Obtain the pin information of the target general purpose input / output (GPIO) interface; Obtain the weight information of all pins from the pin information; Determine if there are pins that meet the preset weight; If so, the pins that meet the preset weights will be removed and the pin information will be updated; The remaining pins are sequentially numbered based on the pin information, and a pin set is generated.

[0009] Optionally, the step of generating a number of pin combinations by matching pins in the pin set according to preset rules includes: Obtain the position labels of all pins from the pin information; Based on the location label, pins belonging to different labels in the pin set are randomly paired into several groups to generate pin combinations.

[0010] Optionally, after the step of randomly pairing pins belonging to different labels in the pin set according to the location labels to generate several pin combinations, the method further includes: If there is one pin remaining, it is marked as the remaining pin and randomly combined with any other set of pins.

[0011] Optionally, the step of electrically connecting all pins in each pin combination and setting the input and output modes in each pin combination according to the numbering includes: In each pin combination, all pins are electrically connected; In each pin combination, the pin with the smallest number is set to input mode, and the pin with the largest number is set to output mode.

[0012] Optionally, the step of individually detecting the target pin combination to determine the abnormal pin when the level of the input mode and the level of the output mode in the target pin combination are detected to be inconsistent includes: When the level of the input mode and the level of the output mode in the target pin combination are found to be inconsistent, the target pin combination is determined to be an abnormal pin combination. The MCU is used to perform high and low level tests on all pins in the abnormal pin combination according to the numbering. The abnormal pin is determined based on the high and low level test results.

[0013] Optionally, the step of using the MCU to sequentially perform high and low level tests on all pins in the abnormal pin combination according to the numbering includes: The test order is determined based on the numbering; The current detection pin is determined according to the test sequence; The current detection pin is set to output mode, and a command is sent to the MCU through a preset port to cause the MCU to output a high level to the current detection pin; The output level of the currently detected pin is obtained through the industrial control computer, and it is determined whether the currently detected pin is qualified in the high-level output mode based on the obtained result; If the condition is qualified in high-level output mode, a low-level command is sent to the MCU to cause the MCU to output a low level to the currently detected pin; Determine whether the current detection pin is qualified in low-level output mode; If the current detection pin is qualified in the low-level output mode, set the current detection pin to the input mode and obtain the first level information of the current detection pin; Send a low-level or high-level instruction to the MCU to cause the MCU to input a level to the current detection pin, thereby obtaining the second level information; Based on the second level information and the first level information, determine whether the current detection pin information is qualified; If the currently tested pin is qualified, then the currently tested pin is updated according to the test sequence.

[0014] Secondly, this application provides a testing apparatus for a general-purpose input / output interface, the testing apparatus comprising: The pin set generation module is used to obtain the pin information of the target general-purpose input / output (GPIO) interface, number all the pins according to the pin information in a preset order, and generate a pin set. The pin combination module is used to generate a number of pin combinations by matching pins in the pin set according to preset rules. The mode setting module is used to electrically connect all pins in each pin combination and set the input mode and output mode in each pin combination according to the number. A separate detection module is used to perform separate detection on the target pin combination to identify abnormal pins when the level of the input mode and the level of the output mode in the target pin combination are inconsistent.

[0015] Thirdly, this application provides a computer device, the device comprising: a memory and a processor, wherein the processor, when executing computer instructions stored in the memory, performs the method described above.

[0016] Fourthly, this application provides a computer-readable storage medium including instructions that, when executed on a computer, cause the computer to perform the method described above.

[0017] In summary, this application includes the following beneficial technical effects: This application obtains the pin information of the target general-purpose input / output (GPIO) interface, numbers all pins according to a preset order based on the pin information, and generates a pin set; within the pin set, pins are matched according to preset rules to generate a number of pin combinations; in each pin combination, all pins are electrically connected, and an input mode and an output mode are set in each pin combination according to the number; when the level of the input mode and the level of the output mode in the target pin combination are detected to be inconsistent, the target pin combination is individually detected to identify abnormal pins; by detecting pin combinations, the effect of quickly obtaining the group to which the abnormal pin belongs is achieved, and by individually detecting abnormal pin groups, the rapid location of abnormal pins is further realized. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the computer device structure of the hardware operating environment involved in the embodiments of the present invention; Figure 2 This is a flowchart illustrating the first embodiment of the test method for the universal input / output interface of the present invention; Figure 3 This is a flowchart illustrating the second embodiment of the test method for the universal input / output interface of the present invention; Figure 4 This is a schematic diagram of the automatic testing GPO / GPI function of the second embodiment of the test method for the general input / output interface of the present invention; Figure 5 This is a structural block diagram of the first embodiment of the test device for the universal input / output interface of the present invention. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0020] Reference Figure 1 , Figure 1 This is a schematic diagram of the computer device structure of the hardware operating environment involved in the embodiments of the present invention.

[0021] like Figure 1 As shown, the computer device may include: a processor 1001, such as a central processing unit (CPU), a communication bus 1002, a user interface 1003, a network interface 1004, and a memory 1005. The communication bus 1002 is used to enable communication between these components. The user interface 1003 may include a display screen or an input unit such as a keyboard; optionally, the user interface 1003 may also include a standard wired interface or a wireless interface. The network interface 1004 may optionally include a standard wired interface or a wireless interface (such as a Wireless-Fidelity (Wi-Fi) interface). The memory 1005 may be high-speed random access memory (RAM) or stable non-volatile memory (NVM), such as a disk drive. The memory 1005 may also optionally be a storage device independent of the aforementioned processor 1001.

[0022] Those skilled in the art will understand that Figure 1 The structure shown does not constitute a limitation on the computer device and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0023] like Figure 1 As shown, the memory 1005, which serves as a storage medium, may include an operating system, a network communication module, a user interface module, and a test program for a general-purpose input / output interface.

[0024] exist Figure 1In the computer device shown, the network interface 1004 is mainly used for data communication with the network server; the user interface 1003 is mainly used for data interaction with the user; the processor 1001 and the memory 1005 in the computer device of the present invention can be set in the computer device, and the computer device calls the test program of the general input / output interface stored in the memory 1005 through the processor 1001 and executes the test method of the general input / output interface provided in the embodiment of the present invention.

[0025] This invention provides a testing method for a general input / output interface, referring to... Figure 2 , Figure 2 This is a flowchart illustrating the first embodiment of the testing method for the universal input / output interface of the present invention.

[0026] In this embodiment, the testing method for the general-purpose input / output interface includes the following steps: Step S10: Obtain the pin information of the target general-purpose input / output (GPIO) interface, number all pins according to the pin information in a preset order, and generate a pin set.

[0027] Understandably, GPIO (General-purpose input / output) is similar in function to P0-P3 of the 8051 microcontroller. Its pins can be freely used by the user through programmable logic. Depending on practical considerations, the pins can be used as general-purpose inputs (GPI), general-purpose outputs (GPO), or general-purpose input and outputs (GPIO), such as in a clk generator or chip select. Since a pin can be used for input, output, or other special functions, there must be registers to select these functions. For input, the pin's potential can be determined by reading a register; for output, the pin can be made to output a high or low potential by writing to a register; and for other special functions, there are separate registers to control them.

[0028] It should be noted that numbering according to a preset order means generating corresponding numbers after confirming the specific number of pins. For example, if there are 24 pins, then pins numbered 1 to 24 will be generated. "Preset order" means numbering from smallest to largest.

[0029] It is understood that the pin set is a set used to store the pins that have been numbered.

[0030] Furthermore, in order to eliminate pre-marked abnormal pins and reduce computational load, the steps of obtaining the pin information of the target general-purpose input / output (GPIO) interface, numbering all pins in a preset order according to the pin information, and generating a pin set include: obtaining the pin information of the target general-purpose input / output (GPIO) interface; obtaining the weight information of all pins in the pin information; determining whether there are pins that meet the preset weight; if so, eliminating the pins that meet the preset weight and updating the pin information; and numbering the remaining pins in sequence according to the pin information and generating a pin set.

[0031] It should be noted that the weight information in the pin information is used to identify abnormal pins marked manually. If the system administrator has marked abnormal pins in advance, the weight value of the corresponding pin will increase. After the weight is identified, the abnormal pins can be obtained, reducing the computer's computation.

[0032] Step S20: Generate a number of pin combinations by matching pins in the pin set according to preset rules.

[0033] It should be noted that the pin combination refers to a combination formed by one or more pins. Power-on testing of pin combinations is faster than power-on testing of individual pins.

[0034] It is understood that the preset rule in this embodiment refers to grouping pins that physically process different sides into pairs. Depending on the specific application, it can also be set to a group of four or more pins.

[0035] Furthermore, in order to improve the speed of pin detection, the step of generating a number of pin combinations by matching pins in the pin set according to preset rules includes: obtaining the position labels of all pins in the pin information; and randomly combining pins belonging to different labels in the pin set in pairs according to the position labels to generate a number of pin combinations.

[0036] It should be noted that after the step of randomly combining pins belonging to different labels in the pin set according to the position label to generate several pin combinations, the method further includes: if there is a remaining pin, it is marked as the remaining pin and the remaining pin is randomly combined with any of the pin combinations.

[0037] It should be noted that if the number of pins of the target GPIO is odd, the extra pins will be randomly added to another pin combination.

[0038] Step S30: Electrically connect all pins in each pin combination, and set the input mode and output mode in each pin combination according to the number.

[0039] Furthermore, in order to standardize the pin testing process, all pins in each pin combination are electrically connected; in each pin combination, the pin with the smallest number is set to input mode, and the pin with the largest number is set to output mode.

[0040] Step S40: When the input mode level and output mode level in the target pin combination are detected to be inconsistent, the target pin combination is individually detected to identify the abnormal pin.

[0041] This embodiment acquires the pin information of the target general-purpose input / output (GPIO) interface, numbers all pins according to a preset order based on the pin information, and generates a pin set. Within the pin set, pins are matched according to preset rules to generate several pin combinations. All pins in each pin combination are electrically connected, and an input mode and output mode are set in each pin combination according to the pin number. When an inconsistency is detected between the input mode level and the output mode level in the target pin combination, the target pin combination is individually detected to identify the abnormal pin. Detecting pin combinations achieves the effect of quickly identifying the group to which the abnormal pin belongs, and individually detecting abnormal pins within the abnormal pin group further enables rapid pin location.

[0042] refer to Figure 3 , Figure 3 This is a flowchart illustrating the second embodiment of the testing method for the general input / output interface of the present invention.

[0043] Based on the first embodiment described above, step S40 of the test method for the general input / output interface in this embodiment includes: Step S401: When the level of the output mode in the target pin combination is found to be inconsistent with the level of the output mode, the target pin combination is determined to be an abnormal pin combination.

[0044] It should be noted that in this embodiment, only one cable is needed to connect the GPIO to the test device. Running the test program, through a preset program, the test program can automatically complete the input and output signal tests and return the test results. If any pin fails the test, the program automatically reports the specific GPIO that failed.

[0045] Step S402: Use the MCU to perform high and low level tests on all pins in the abnormal pin combination according to their numbers.

[0046] In specific implementation, the step of using the MCU to sequentially perform high and low level tests on all pins in the abnormal pin combination according to the numbering includes: determining the test order according to the numbering; determining the current detection pin according to the test order; setting the current detection pin to output mode, and sending an instruction to the MCU through a preset port to make the MCU output a high level to the current detection pin; acquiring the output level set by the current detection pin through the industrial control unit, and judging whether the current detection pin is qualified in the high-level output mode based on the acquisition result; if so, when qualified in the high-level output mode, sending a low-level instruction to the MCU. The process involves instructing the MCU to output a low level to the currently detected pin; determining whether the currently detected pin is qualified in the low-level output mode; if the currently detected pin is qualified in the low-level output mode, setting the currently detected pin to input mode and acquiring the first level information of the currently detected pin; sending a low-level or high-level instruction to the MCU to cause the MCU to input a level to the currently detected pin and acquiring the second level information; determining whether the information of the currently detected pin is qualified based on the second level information and the first level information; if the currently detected pin is qualified, updating the currently detected pin according to the test sequence.

[0047] In specific implementation, the specific implementation steps of this embodiment are as follows: Figure 4As shown, the industrial control unit's program automatically sets PIN1 to GP0 and sets its output to a high level. It sends a command to the MCU via serial port to set PIN1 to GP0 and output a high level. Upon receiving the command, the MCU sets PIN1 to GP0 for testing via the control bus, then detects the PIN1 output level via the test bus and feeds the detection result back to the industrial control unit via serial port. Upon receiving the feedback, the industrial control unit compares it with the initial settings to complete the test of PIN1 as a GP0 output high level. The industrial control unit program continues automatically, setting PIN1 to GP0 and setting its output to a low level. It then sends a command to the MCU via serial port to set PIN1 to GP0 and output a low level. Upon receiving the command, the MCU sets PIN1 to GP0 for testing via the control bus, then detects the PIN1 output level via the test bus and feeds the detection result back to the industrial control unit via serial port. Upon receiving the feedback, the industrial control unit compares it with the initial settings to complete the test of PIN1 as a GP0 output low level. The industrial control unit program continues automatically, setting PIN1 to GP0. The program first checks the level of PIN1; then, via serial port, it sends a command to the MCU to set PIN1 as GPI; upon receiving the command, the MCU sets PIN1 to GPI test via the control bus, then inputs a high level to PIN1 via the test bus, and feeds back the setting result to the industrial control unit via serial port; upon receiving the feedback, the industrial control unit compares the actual detected value to complete the PIN1 as GPI input high level test; the industrial control unit program continues automatically, sending a command to the MCU via serial port to perform the next test item for PIN1 as GPI; upon receiving the command, the MCU sets PIN1 to GPI test via the control bus, then inputs a low level to PIN1 via the test bus, and feeds back the setting result to the industrial control unit via serial port; upon receiving the feedback, the industrial control unit compares the actual detected value to complete the PIN1 as GPI input low level test; the above is a complete test of the PIN1 GPO / GPI function. Through the negotiation between the industrial control unit program and the MCU, all test items can be automatically completed and the test results fed back. After completing the PIN1 test, the program can automatically complete the tests of PIN2-PIN24 according to the above steps.

[0048] Step S403: Determine the abnormal pin based on the high and low level test results.

[0049] This embodiment determines that a target pin combination is an abnormal pin combination when the input mode level and the output mode level in the target pin combination are inconsistent. The MCU performs high and low level tests on all pins in the abnormal pin combination according to the number. The abnormal pin is determined based on the high and low level test results. This enables the determination of abnormal pins within a small range of abnormal pin combinations, improving the speed and accuracy of pin determination.

[0050] Furthermore, embodiments of the present invention also propose a computer-readable storage medium storing a program for testing a general-purpose input / output interface (GPIO), wherein when the GPIO testing program is executed by a processor, it implements the steps of the GPIO testing method described above.

[0051] Reference Figure 5 , Figure 5 This is a structural block diagram of the first embodiment of the test device for the universal input / output interface of the present invention.

[0052] like Figure 5 As shown, the testing apparatus for a universal input / output interface proposed in this embodiment of the invention includes: The set generation module 10 is used to obtain the pin information of the target general-purpose input / output (GPIO) interface, number all the pins according to the pin information in a preset order, and generate a pin set. Pin combination module 20 is used to generate a number of pin combinations by matching pins in the pin set according to preset rules; The mode setting module 30 is used to electrically connect all the pins in each pin combination and set the input mode and output mode in each pin combination according to the number. The separate detection module 40 is used to perform separate detection on the target pin combination to identify abnormal pins when the level of the input mode and the level of the output mode in the target pin combination are inconsistent.

[0053] It should be understood that the above are merely illustrative examples and do not constitute any limitation on the technical solution of the present invention. In specific applications, those skilled in the art can make settings as needed, and the present invention does not impose any restrictions on this.

[0054] This embodiment acquires the pin information of the target general-purpose input / output (GPIO) interface, numbers all pins according to a preset order based on the pin information, and generates a pin set. Within the pin set, pins are matched according to preset rules to generate several pin combinations. All pins in each pin combination are electrically connected, and an input mode and output mode are set in each pin combination according to the pin number. When an inconsistency is detected between the input mode level and the output mode level in the target pin combination, the target pin combination is individually detected to identify the abnormal pin. Detecting pin combinations achieves the effect of quickly identifying the group to which the abnormal pin belongs, and individually detecting abnormal pins within the abnormal pin group further enables rapid pin location.

[0055] In one embodiment, the set generation module 10 is further configured to obtain pin information of the target general-purpose input / output (GPIO) interface; obtain weight information of all pins in the pin information; determine whether there are pins that meet the preset weight; if so, remove the pins that meet the preset weight and update the pin information; number the remaining pins sequentially according to the pin information and generate a pin set.

[0056] In one embodiment, the pin combination module 20 is further configured to obtain the position labels of all pins in the pin information; and to randomly combine pins belonging to different labels in the pin set in pairs according to the position labels to generate several pin combinations.

[0057] In one embodiment, the pin combination module 20 is further configured to, if there is one remaining pin, mark it as the remaining pin and randomly combine the remaining pin with any group of pins.

[0058] In one embodiment, the mode setting module 30 is further configured to electrically connect all pins in each pin combination; and in each pin combination, set the pin with the smallest number to the input mode, while setting the pin with the largest number to the output mode.

[0059] In one embodiment, the separate detection module 40 is further configured to determine that the target pin combination is an abnormal pin combination when the level of the input mode and the level of the output mode in the target pin combination are inconsistent; to use the MCU to perform high and low level tests on all pins in the abnormal pin combination in sequence according to the number; and to determine the abnormal pins based on the high and low level test results.

[0060] In one embodiment, the separate detection module 40 is further configured to: determine the test order according to the number; determine the current detection pin according to the test order; set the current detection pin to output mode and send an instruction to the MCU through a preset port to make the MCU output a high level to the current detection pin; obtain the output level set by the current detection pin through the industrial control unit, and determine whether the current detection pin is qualified in the high-level output mode according to the acquisition result; if so, when qualified in the high-level output mode, send a low-level instruction to the MCU to make the MCU output a low level to the current detection pin; determine whether the current detection pin is qualified in the low-level output mode; if the current detection pin is qualified in the low-level output mode, set the current detection pin to input mode and obtain the first level information of the current detection pin; send a low-level or high-level instruction to the MCU to make the MCU input a level to the current detection pin and obtain the second level information; determine whether the current detection pin information is qualified according to the second level information and the first level information; if the current detection pin is qualified, update the current detection pin according to the test order.

[0061] It should be noted that the workflow described above is merely illustrative and does not limit the scope of protection of this invention. In practical applications, those skilled in the art can select some or all of the workflow to achieve the purpose of this embodiment according to actual needs, and no restrictions are imposed here.

[0062] In addition, for technical details not described in detail in this embodiment, please refer to the testing method of the general input / output interface provided in any embodiment of the present invention, which will not be repeated here.

[0063] Furthermore, it should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or system. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or system that includes that element.

[0064] The sequence numbers of the above embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0065] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as read-only memory (ROM) / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0066] The above are merely preferred embodiments of the present invention and do not limit the scope of the patent. Any equivalent structural or procedural transformations made based on the description and drawings of the present invention, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of the present invention.

Claims

1. A test method for a general input / output interface, characterized in that, include: Obtain the pin information of the target general-purpose input / output (GPIO) interface, number all pins according to the pin information in a preset order, and generate a pin set; A number of pin combinations are generated by matching pins in the pin set according to preset rules; In each pin combination, all pins are electrically connected, and the input mode and output mode are set in each pin combination according to the numbering. When the level of the input mode and the level of the output mode in the target pin combination are found to be inconsistent, the target pin combination is individually detected to identify the abnormal pins. The step of individually detecting the target pin combination to determine the abnormal pin when the level of the input mode and the level of the output mode in the target pin combination are detected to be inconsistent includes: When the level of the input mode and the level of the output mode in the target pin combination are found to be inconsistent, the target pin combination is determined to be an abnormal pin combination. The MCU is used to perform high and low level tests on all pins in the abnormal pin combination according to the numbering. Determine the abnormal pin based on the high and low level test results; The step of using the MCU to sequentially perform high and low level tests on all pins in the abnormal pin combination according to the specified number includes: The test order is determined based on the numbering; The current detection pin is determined according to the test sequence; The current detection pin is set to output mode, and a command is sent to the MCU through a preset port to cause the MCU to output a high level to the current detection pin; The output level of the currently detected pin is obtained through the industrial control computer, and it is determined whether the currently detected pin is qualified in the high-level output mode based on the obtained result; If the condition is qualified in high-level output mode, a low-level command is sent to the MCU to cause the MCU to output a low level to the currently detected pin; Determine whether the current detection pin is qualified in low-level output mode; If the current detection pin is qualified in the low-level output mode, set the current detection pin to the input mode and obtain the first level information of the current detection pin; Send a low-level or high-level instruction to the MCU to cause the MCU to input a level to the current detection pin, thereby obtaining the second level information; Based on the second level information and the first level information, determine whether the current detection pin information is qualified; If the currently tested pin is qualified, then the currently tested pin is updated according to the test sequence.

2. The test method for a general input / output interface according to claim 1, characterized in that, The steps of obtaining the pin information of the target general-purpose input / output (GPIO) interface, numbering all pins according to a preset order based on the pin information, and generating a pin set include: Obtain the pin information of the target general purpose input / output (GPIO) interface; Obtain the weight information of all pins from the pin information; Determine if there are pins that meet the preset weight; If so, the pins that meet the preset weights will be removed and the pin information will be updated; The remaining pins are sequentially numbered based on the pin information, and a pin set is generated.

3. The test method for a general input / output interface according to claim 1, characterized in that, The step of generating a number of pin combinations by matching pins in the pin set according to preset rules includes: Obtain the position labels of all pins from the pin information; Based on the location label, pins belonging to different labels in the pin set are randomly paired into several groups to generate pin combinations.

4. The test method for a general input / output interface according to claim 3, characterized in that, After the step of randomly pairing pins belonging to different labels in the pin set according to the position labels to generate several pin combinations, the method further includes: If there is one pin remaining, it is marked as the remaining pin and randomly combined with any other set of pins.

5. The test method for a general input / output interface according to claim 1, characterized in that, The step of electrically connecting all pins in each pin combination and setting the input and output modes in each pin combination according to the numbering includes: In each pin combination, all pins are electrically connected; In each pin combination, the pin with the smallest number is set to input mode, and the pin with the largest number is set to output mode.

6. A testing device for a universal input / output interface, characterized in that, The testing device for the general-purpose input / output interface includes: The pin set generation module is used to obtain the pin information of the target general-purpose input / output (GPIO) interface, number all the pins according to the pin information in a preset order, and generate a pin set. The pin combination module is used to generate a number of pin combinations by matching pins in the pin set according to preset rules. The mode setting module is used to electrically connect all pins in each pin combination and set the input mode and output mode in each pin combination according to the number. A separate detection module is used to perform separate detection on the target pin combination to identify abnormal pins when the level of the input mode and the level of the output mode in the target pin combination are inconsistent. The step of individually detecting the target pin combination to determine the abnormal pin when the level of the input mode and the level of the output mode in the target pin combination are detected to be inconsistent includes: When the level of the input mode and the level of the output mode in the target pin combination are found to be inconsistent, the target pin combination is determined to be an abnormal pin combination. The MCU is used to perform high and low level tests on all pins in the abnormal pin combination according to the numbering. Determine the abnormal pin based on the high and low level test results; The step of using the MCU to sequentially perform high and low level tests on all pins in the abnormal pin combination according to the specified number includes: The test order is determined based on the numbering; The current detection pin is determined according to the test sequence; The current detection pin is set to output mode, and a command is sent to the MCU through a preset port to cause the MCU to output a high level to the current detection pin; The output level of the currently detected pin is obtained through the industrial control computer, and it is determined whether the currently detected pin is qualified in the high-level output mode based on the obtained result; If the condition is qualified in high-level output mode, a low-level command is sent to the MCU to cause the MCU to output a low level to the currently detected pin; Determine whether the current detection pin is qualified in low-level output mode; If the current detection pin is qualified in the low-level output mode, set the current detection pin to the input mode and obtain the first level information of the current detection pin; Send a low-level or high-level instruction to the MCU to cause the MCU to input a level to the current detection pin, thereby obtaining the second level information; Based on the second level information and the first level information, determine whether the current detection pin information is qualified; If the currently tested pin is qualified, then the currently tested pin is updated according to the test sequence.

7. A computer device, characterized in that, The device includes a memory and a processor, wherein the processor, when executing computer instructions stored in the memory, performs the method as described in any one of claims 1 to 5.

8. A computer-readable storage medium, characterized in that, Includes instructions that, when executed on a computer, cause the computer to perform the method as described in any one of claims 1 to 5.

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