Memory system and chip

Abstract

The embodiment of the application provides a memory system and a chip, and relates to the technical field of chips. The system comprises: a conflict detection module, which is used for sending a data access request to a read-write control module through a BYPASS channel if the service type of the data access request belongs to a specified type; performing address conflict detection on the data access request if the service type of the data access request does not belong to the specified type; caching the request information of the data access request in a management queue if the address conflict detection passes; and caching the request information of the data access request in a conflict queue if the address conflict detection does not pass; the read-write control module is used for determining the processing sequence of each received data access request and sending the data access request to an interface conversion module according to the processing sequence; and the interface conversion module is used for accessing a memory module based on the received data access request. The memory system access performance can be improved.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a memory system and chip. Background Technology

[0002] The connectivity and resource sharing of computer network systems depend on data exchange. Network processing (processor) chips, commonly known as network chips, are microprocessors used in computer network systems to send and receive data. Network chip technology is a new chip technology developed to adapt to modern high-speed networks, improve network service quality control, develop new network management models, and meet new network functional requirements.

[0003] Network chips include a memory system, and all service processing involves read and write operations to this memory. Currently, network chip memory systems can use the Advanced Dextensible Interface (AXI) bus protocol. AXI offers advantages such as high performance, high bandwidth, and low latency; however, AXI has separate read and write channels, thus lacking the ability to resolve data consistency issues. Data consistency issues refer to the potential for data errors when multiple requests access the same memory address simultaneously. For example, a Read After Write (RAW) operation targeting the same memory address might incorrectly execute a read operation before a write operation, resulting in the data not being read. Similarly, a Write After Read (WAR) operation targeting the same memory address might incorrectly execute a write operation before a read operation, resulting in the latest data being read; and the execution order of the two write operations in a Write After Write (WAW) operation targeting the same memory address might be incorrect, causing the data to not be updated to the latest version.

[0004] To address data consistency issues, a management queue can be established. Each received data access request is added to the management queue, and its address is compared with the addresses of other data access requests in the queue. If no address conflict exists, the request is sent to the AXI interface for processing; otherwise, it waits in the queue. The corresponding data access request is only released from the management queue after receiving a data read / write response from the AXI interface.

[0005] However, in the above process, if the depth of the management queue is too large, it will consume too much logical resources of the memory system, and the more data access requests participating in the comparison in the management queue, the longer the comparison time will be. If the queue depth is too small, the data access requests will not be processed in time, affecting the execution efficiency and resulting in poor memory system access performance. Summary of the Invention

[0006] The purpose of this application is to provide a memory system and chip to improve memory system access performance. The specific technical solution is as follows:

[0007] In a first aspect, embodiments of this application provide a memory system, including a conflict detection module, a read / write control module, an interface conversion module, and a memory module connected in sequence, wherein the conflict detection module includes a bypass BYPASS path;

[0008] The conflict detection module is used to receive data access requests. If the service type of the data access request belongs to a specified type, the data access request is sent to the read / write control module through the BYPASS path. If the service type of the data access request does not belong to the specified type, the data access request is subjected to address conflict detection based on the request information cached in the management queue and the conflict queue. If the address conflict detection passes, the request information of the data access request is cached in the management queue, and the data access request is sent to the read / write control module. If the address conflict detection fails, the request information of the data access request is cached in the conflict queue, and the data access request is cached. After the address conflict is resolved, the data access request is sent to the read / write control module.

[0009] The read / write control module is used to determine the processing order of data access requests and send data access requests to the interface conversion module according to the processing order.

[0010] The interface conversion module is used to access the memory module based on the received data access request.

[0011] In one possible implementation,

[0012] The read / write control module is also used to determine whether the received data access request includes a data write request and whether the processing order of the data write request has been determined. When the determination results are both yes, the module replies with a data write response to the conflict detection module.

[0013] The conflict detection module is also used to receive the data write response and delete the request information of the data access request corresponding to the data write response cached in the management queue or the conflict queue.

[0014] In one possible implementation,

[0015] The interface conversion module is specifically used to determine whether a data write response has been received for all data write requests that have been initiated if the received data access request is a data read request. If the determination result is yes, a read operation is performed on the memory module based on the received data read request.

[0016] In one possible implementation,

[0017] The read / write control module is specifically used to determine the processing order of received data read requests if the current window is a read window and the received data access requests include data read requests; and to determine the processing order of received data write requests if the current window is a write window and the received data access requests include data write requests.

[0018] In one possible implementation, the memory module is an external storage module;

[0019] The read / write control module is further configured to alternately switch between the read window and the write window according to a preset read cycle duration and a preset write cycle duration; or, switch between the read window and the write window according to a polling (RR) algorithm or a weighted round-robin scheduling (WRR) algorithm; or, when the duration of the write window reaches a preset duration threshold, if the number of currently unprocessed data read requests is greater than the number of data write requests, then switch to the read window; when the duration of the read window reaches a preset duration threshold, if the number of currently unprocessed data write requests is greater than the number of data read requests, then switch to the write window; or, alternately switch between the read window and the write window of the read / write control module according to the read window and the write window of the external storage module.

[0020] In one possible implementation,

[0021] The read / write control module is specifically used to determine the processing order of the received data read requests according to the bank address corresponding to the request address of the received data read request, and according to the preset scheduling order of each bank address; and to determine the processing order of the received data write requests according to the bank address corresponding to the request address of the received data write request, and according to the preset scheduling order of each bank address.

[0022] In one possible implementation, the read / write control module is specifically configured to, for multiple data read requests that correspond to the same bank address, determine the processing order of the multiple data read requests according to the business type of the multiple data read requests and the WRR algorithm; and for multiple data write requests that correspond to the same bank address, determine the processing order of the multiple data write requests according to the business type of the multiple data write requests and the WRR algorithm.

[0023] In one possible implementation, the request information cached in the management queue and the conflict queue includes the request address and the business type;

[0024] The conflict detection module is specifically used to determine whether there is a target request information in the management queue and the conflict queue that has the same service type as the received data access request; if not, the address conflict detection is determined to be passed; if it exists, it is determined whether the request address in the target request information is the same as the request address of the data access request; if they are the same, the address conflict detection is determined to be failed; if they are not the same, the address conflict detection is determined to be passed.

[0025] In one possible implementation, the memory system further includes a system balancing module, and the memory system includes multiple memory modules, each memory module corresponding to a set of conflict detection modules, read / write control modules and interface conversion modules;

[0026] The system balancing module is used to receive data access requests, determine the target memory module that matches the request address of the data access request, and send the data access request to the conflict detection module corresponding to the target memory module.

[0027] Secondly, embodiments of this application provide a chip including the memory system described in the first aspect above.

[0028] Using the above technical solution, the conflict detection module can determine whether an address conflict detection is required for a data access request based on its business type. If the business type of the data access request does not belong to a specified type, address conflict detection is performed based on the request information cached in the management queue and the conflict queue. This ensures that data access requests with the same request address are not processed out of order, thus resolving data consistency issues. If the business type of the data access request belongs to a specified type, address conflict detection is unnecessary, and therefore, there is no need to cache data access requests of that type in the management queue. This reduces the workload on the management queue, thereby lowering the required queue depth and preventing the management queue from consuming excessive memory system resources. Furthermore, it reduces the time required for address conflict detection, improving the efficiency of data access request processing. Furthermore, the read / write control module can send data access requests to the interface conversion module according to a predetermined processing order. This allows the interface conversion module to access the memory module in the order determined by the read / write control module. Since the memory module operates in simplex mode, it can only perform one write operation or one read operation at a time. Therefore, by sending data access requests to the interface conversion module in a specific processing order, the read / write control module can improve the processing efficiency of data access requests. Thus, this embodiment can improve the performance of the memory system while addressing the data consistency problem and balancing the resource consumption of the management queue on the memory system with the processing efficiency of data access requests.

[0029] Of course, implementing any product or method of this application does not necessarily require achieving all of the advantages described above at the same time. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other embodiments can be obtained based on these drawings.

[0031] Figure 1 This is a schematic diagram of the structure of a network chip provided in an embodiment of this application;

[0032] Figure 2 This application provides a schematic diagram of the structure of a memory system according to an embodiment of the present application.

[0033] Figure 3 This is a flowchart of a data access request processing method provided in an embodiment of this application. Detailed Implementation

[0034] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art based on this application are within the scope of protection of this application.

[0035] To facilitate understanding of the embodiments of this application, the concepts involved in the embodiments of this application will be introduced below.

[0036] like Figure 1 As shown, Figure 1 This is a schematic diagram of the structure of a network chip provided in an embodiment of this application. The network chip includes: an interface module 101, a receive direct memory access (RxDMA) module 102, a transmit direct memory access (TxDMA) module 103, a buffer management unit (BMU) 104, a programmable task optimized processor (CTOP) module 105, a traffic management (TM) module 106, and a memory system 107.

[0037] The memory system 107 includes internal storage and external storage. The internal storage can be static random-access memory (SRAM) embedded in the network chip, and the external storage can be commonly used memory chips such as double data rate synchronous dynamic random access memory (DDR) or high bandwidth memory (HBM). Due to the size limitations of the network chip itself, the network chip can use external storage to increase the cache capacity.

[0038] Figure 1In this configuration, interface module 101 can receive request messages from other devices and send them to RxDMA module 102. RxDMA module 102 can then send the request message to memory system 107. After processing the request message, memory system 107 returns the processing result to TxDMA module 103. TxDMA module 103 then sends a response message to interface module 101 based on the processing result, enabling interface module 101 to return a response message to other devices. CTOP module 105 can also send the request message sent by RxDMA module 102 to TM module 106, which schedules the request message. TM module 106 also needs to send the scheduling result to TxDMA module 103 so that TxDMA module 103 can correctly process the response message. BMU 104 manages the addresses accessed by RxDMA module 102 and TxDMA module 103.

[0039] In addition to processing request messages from other devices, Figure 1 The Rx DMA module 102, Tx DMA module 103, BMU 104, CTOP module 105 and TM module 106 can all perform data read and write operations on the memory system 107.

[0040] Figure 1 This is merely an example. In actual implementation, the number of modules included in a network chip is not limited to this, and the network chip may also include other modules. This application embodiment does not limit this.

[0041] To improve the access performance of the memory system, embodiments of this application provide a memory system, such as... Figure 2 As shown, the system includes: a conflict detection module 201, a read / write control module 202, an interface conversion module 203, and a memory module 204 connected in sequence. The conflict detection module 201 includes a BYPASS path 2011.

[0042] In this embodiment of the application, the memory system may include multiple memory modules 204, each memory module 204 corresponding to a set of conflict detection module 201, read / write control module 202 and interface conversion module 203.

[0043] In this embodiment, the access of the memory module 204 by one of the conflict detection modules 201, read / write control modules 202 and interface conversion modules 203 is used as an example for illustration.

[0044] The conflict detection module 201 receives data access requests. If the service type of the data access request belongs to a specified type, it sends the data access request to the read / write control module 202 through the BYPASS channel 2011. If the service type of the data access request does not belong to the specified type, it performs address conflict detection on the data access request based on the request information cached in the management queue and the conflict queue. If the address conflict detection passes, it caches the request information of the data access request in the management queue and sends the data access request to the read / write control module 202. If the address conflict detection fails, it caches the request information of the data access request in the conflict queue and caches the data access request. After the address conflict is resolved, it sends the data access request to the read / write control module 202.

[0045] In this embodiment of the application, the data access request can be Figure 1 The Rx DMA module 102, Tx DMA module 103, BMU 104, CTOP module 105 or TM module 106 send data access requests to the memory system 107.

[0046] Figure 2 After any conflict detection module 201 receives a data access request, it can determine whether address conflict detection is required for the data access request.

[0047] The service types in the memory system include: unspecified types that may have address conflict issues, and specified types that do not have address conflict issues.

[0048] For data access requests of non-specified types, address conflict detection is required. For example, a non-specified data access request could be a CPU instruction type request sent by the CTOP module 105.

[0049] For data access requests of a specified type, address conflict detection is not required. The conflict detection module 201 can be pre-configured with a specified type, which is the type of service that does not require address conflict detection. It can be configured based on the actual situation. For example, the specified type of service can be a table lookup service, a statistical service, a DMA service, etc.

[0050] Specifically, the conflict detection module 201 can obtain the field representing the service type from the header of the data access request, and determine the service type of the data access request based on this field. It then determines whether the service type belongs to a specified type. If so, it determines that address conflict detection is not required for the data access request, and the data access request can be directly sent to the read / write control module 202 through the BYPASS channel 2011. Since address conflict detection is not required, there is no need to retain the request information for the data access request.

[0051] Conversely, if the business type of the data access request does not belong to the specified type, it means that address conflict detection needs to be performed on the data access request, and then the conflict detection module 201 can continue to perform address conflict detection on the data access request.

[0052] For data access requests that fail address detection, they can be cached first. After the conflict detection module 201 determines that the request information that conflicts with the data access request has been deleted, the address conflict can be determined to be eliminated, and then the data access request can be sent to the read / write control module 202.

[0053] The read / write control module 202 is used to determine the processing order of data access requests and send data access requests to the interface conversion module 203 according to the processing order.

[0054] The interface conversion module 203 is used to access the memory module 204 based on the received data access request.

[0055] Specifically, the interface conversion module 203 can be an AXI interface conversion module.

[0056] In this embodiment, the conflict detection module can determine whether an address conflict detection is required for a data access request based on its business type. If the business type of the data access request does not belong to a specified type, address conflict detection is performed based on the request information cached in the management queue and the conflict queue. This ensures that data access requests with the same request address are not processed out of order, thus resolving data consistency issues. If the business type of the data access request belongs to a specified type, address conflict detection is unnecessary, and therefore, there is no need to cache data access requests of that type in the management queue. This reduces the workload on the management queue, lowers the required queue depth, avoids excessive memory resource consumption by the management queue, and reduces the time required for address conflict detection, thereby improving the efficiency of data access request processing. Furthermore, the read / write control module can send data access requests to the interface conversion module according to a predetermined processing order. This allows the interface conversion module to access the memory module in the order determined by the read / write control module. Since the memory module operates in simplex mode, it can only perform one write operation or one read operation at a time. Therefore, by sending data access requests to the interface conversion module in a specific processing order, the read / write control module can improve the processing efficiency of data access requests. Thus, this embodiment can improve the performance of the memory system while addressing the data consistency problem and balancing the resource consumption of the management queue on the memory system with the processing efficiency of data access requests.

[0057] In the embodiments of this application, such as Figure 2 As shown, the memory system also includes a system balancing module 205.

[0058] The system load balancing module 205 is used to receive data access requests, determine the target memory module that matches the request address of the data access request, and send the data access request to the conflict detection module 201 corresponding to the target memory module.

[0059] Specifically, the system balancing module 205 can use a hash algorithm to perform a hash operation on the request address of the data access request, and then perform a division operation on the result. Based on the pre-defined correspondence between the result of the division operation and the memory modules, the data access request is mapped to one of the memory modules in the memory system. This ensures that the number of requests allocated to each memory module is relatively balanced, and that the request addresses mapped to the same memory module are contiguous.

[0060] In another embodiment of this application, the request information cached in the aforementioned management queue and conflict queue includes the request address and business type.

[0061] The conflict detection module 201 is specifically used to determine whether there is a target request information in the management queue and the conflict queue that has the same business type as the received data access request; if not, the address conflict detection is determined to be passed; if it exists, it is determined whether the request address in the target request information is the same as the request address of the data access request; if they are the same, the address conflict detection is determined to be failed; if they are not the same, the address conflict detection is determined to be passed.

[0062] In this embodiment, if there is no target request information in the management queue and the conflict queue, it means that the service type of the received data access request is different from the service type of the request information in the management queue and the conflict queue. Therefore, it can be determined that the request address of the received data access request will not conflict with the request address corresponding to the request information in the management queue and the conflict queue. Thus, it can be directly determined that the address conflict detection has passed without further comparing the request address of the data access request with the request address in the management queue and the conflict queue. This can save the time required for address conflict detection and improve processing efficiency.

[0063] If target request information exists in the management queue and the conflict queue, it is necessary to further determine whether the request address in the target request information is the same as the request address of the data access request, so as to avoid data consistency issues.

[0064] For example, the received data access request is called data access request A, the request information of data access request A is called request information A, and the management queue and the conflict queue include request information B, request information C and request information D.

[0065] Assuming that the business type included in request information A is different from the business types in request information B, request information C, and request information D, then the address conflict detection for data access request A is confirmed to be successful.

[0066] Alternatively, assuming that the business type included in request information A and the business type included in request information B are the same, then request information B is the target request information. In this case, it is necessary to determine whether the request address included in request information A and the request address included in request information B are the same. If the request address included in request information A and the request address included in request information B are the same, then it is determined that the address conflict detection of data access request A has failed. If the request address included in request information A and the request address included in request information B are different, then it is determined that the address conflict detection of data access request A has passed.

[0067] It is understood that there may be multiple target request information in this application embodiment. That is, there may be multiple request information in the management queue and the conflict queue with the same business type as the currently received data access request. In this case, it is necessary to compare the request address of the currently received data access request with the request address included in each target request information. If the comparison results are all different, the address conflict detection passes. If any comparison result is different, the address conflict detection fails.

[0068] For example, if the business type included in request information A is the same as the business type in request information B and request information C, then both request information B and request information C are target request information. It is necessary to determine whether the request address included in request information A is the same as the request address included in request information B and request information C. When the request address included in request information A is different from the request addresses included in both request information B and request information C, it is determined that data access request A passes the address conflict detection; when the request address included in request information A is the same as the request address included in request information B or request information C, it is determined that data access request A fails the address conflict detection.

[0069] Data access requests that pass address conflict detection and those that do not require address conflict detection are all transmitted to the read / write control module 202, which determines the processing order of each data access request.

[0070] In another embodiment of this application, the memory module 204 is an external storage module, such as a storage module in a DDR or HBM connected to the chip. Optionally, the memory system may also include an internal storage module, such as SRAM inside the chip. Access to the memory module in this embodiment refers to access to the external storage module.

[0071] In one embodiment, the read / write control module 202 is further configured to alternately switch between the read window and the write window according to a preset read cycle duration and a preset write cycle duration.

[0072] In this embodiment, the preset read cycle duration and preset write cycle duration can be set according to the actual business scenario.

[0073] For example, the preset read cycle duration and the preset write cycle duration can be set to the same value, such as 10 clock cycles, and then the read and write windows can be switched every 10 clock cycles.

[0074] For example, the preset read cycle duration and preset write cycle duration can be set to different values, such as a preset read cycle duration of 15 clock cycles and a preset write cycle duration of 10 clock cycles. Then, the window switches to the write window after 15 clock cycles of reading, and switches to the read window after 10 clock cycles of writing.

[0075] In another embodiment, the read / write control module 202 can control the alternating switching of the write window and the read window through a round-robin (RR) algorithm or a weighted round-robin (WRR) algorithm.

[0076] For example, if using the RR algorithm, the length of the time slice is set. One time slice is the read window, the next time slice is the write window, and the read window switches again in the next time slice, thus rotating between read and write windows. Alternatively, the number of requests processed within a single window can be set. For example, after processing a specified number of data read requests in the read window, it switches to the write window; after processing a specified number of data write requests in the write window, it switches back to the read window.

[0077] During the polling process described above, if there are no data read requests to be processed in the read window, the process will switch directly to the write window; similarly, if there are no data write requests to be processed in the write window, the process will switch directly to the read window.

[0078] If the WRR algorithm is used, the weights of the read window and the write window can be set based on the business characteristics of the memory system.

[0079] For example, based on statistics, if read operations in the memory system are typically more frequent than write operations, the weight of the read window can be set to 2, and the weight of the write window to 1. The read / write control module 202 can process two data read requests in the read window, then switch to the write window; process one data write request in the write window, then switch back to the read window, and so on, switching between the read and write windows in a round-robin fashion. During this round-robin process, if there are no data read requests to process in the read window, it will directly switch to the write window; similarly, if there are no data write requests to process in the write window, it will directly switch to the read window.

[0080] In another embodiment, the read / write control module 202 is further configured to switch to the read window if the number of currently unprocessed data read requests is greater than the number of data write requests when the duration of the write window reaches a preset duration threshold; and to switch to the write window if the number of currently unprocessed data write requests is greater than the number of data read requests when the duration of the read window reaches a preset duration threshold.

[0081] The preset duration threshold can be set in advance based on actual business needs.

[0082] For example, if you are currently in a write window and the duration of the write window reaches a preset duration threshold, and there are currently 3 unprocessed data write requests and 20 unprocessed data read requests, you can immediately switch to the read window.

[0083] In this way, the switching between the read window and the write window can be matched with the actual number of data read requests and data write requests received, avoiding situations where there are no data read requests to be processed in the read window or no data write requests to be processed in the write window, thereby improving the processing efficiency of data access requests.

[0084] In another embodiment, the read / write control module 202 can also alternately switch the read window and write window of the read / write control module 202 according to the read window and write window of the external storage module.

[0085] The read / write control module 202 can switch the read window and write window according to the scheduling algorithm of the external storage controller, so that the switching of the read window and write window matches the read window and write window of the external storage module, thereby improving processing efficiency.

[0086] In the embodiments of this application, since the memory module operates in simplex mode and can only perform one read or write operation at a time, switching between the read and write windows through the read / write control module will not affect the working efficiency of the AXI interface in full-duplex mode. Furthermore, it can make the switching between the read and write windows more in line with the characteristics of the memory module, thereby improving the processing efficiency of data access requests and thus enhancing the performance of the memory system.

[0087] Based on the determination of the read window and the write window, the processing order of data read requests in the read window and the processing order of data write requests in the write window can be further determined.

[0088] The read / write control module 202 is specifically used to determine the processing order of received data read requests if the current window is a read window and the received data access requests include data read requests; and to determine the processing order of received data write requests if the current window is a write window and the received data access requests include data write requests.

[0089] Optionally, the read / write control module 202 is specifically used to determine the processing order of the received data read request according to the bank address corresponding to the request address of the received data read request and according to the preset scheduling order of each bank address; and to determine the processing order of the received data write request according to the bank address corresponding to the request address of the received data write request and according to the preset scheduling order of each bank address.

[0090] In this embodiment, the memory units of the external storage module are divided into bank addresses, row addresses, and column addresses. A bank can be viewed as a storage matrix, with each bank containing multiple rows and multiple columns. The read / write efficiency of the external storage module is related to the timing design of the external storage module itself. For example, for DDR chips, scheduling can be performed according to banks. For instance, if the external storage module includes banks 0 to 5, data access requests with addresses belonging to bank 0 can be processed first, then data access requests with addresses belonging to bank 1 can be processed, and so on. This maximizes the access efficiency of the DDR chips.

[0091] It should be noted that different external memories are designed with different scheduling orders for bank addresses. Each external memory has an ideal scheduling order that can achieve maximum read and write efficiency. In this embodiment, the ideal scheduling order of external memories in the memory system can be obtained in advance, so that the read and write control module can determine the processing order of data read requests and the processing order of data write requests according to the ideal scheduling order of external memories for bank addresses, thereby improving the processing efficiency of the memory system.

[0092] In another embodiment of this application, based on the above embodiments, the read / write control module 202 can also determine the processing order of data access requests in combination with the service type of the data access request.

[0093] The read / write control module 202 is specifically used to determine the processing order of multiple data read requests that correspond to the same bank address, based on the business type of the multiple data read requests and according to the WRR algorithm; and to determine the processing order of multiple data write requests that correspond to the same bank address, based on the business type of the multiple data write requests and according to the WRR algorithm.

[0094] In this embodiment of the application, the weight of each service type can be set according to the bandwidth of each service type. The larger the bandwidth, the greater the corresponding weight.

[0095] For example, assuming there are three business types, A, B, and C, with a weight ratio of 2:1:1, then according to the WRR algorithm, for multiple data write requests with the same bank address, the algorithm will first process two data write requests of business type A, then one data write request of business type B, then one data write request of business type C, and then process two more data write requests of business type A, and so on in a loop. If there are no data write requests of a certain type, the algorithm will automatically process the next type of data write request. For example, after processing two data write requests of business type A, if there are no data write requests of business type B, the algorithm will directly begin processing one data write request of business type C.

[0096] This allows for more diverse and flexible application scenarios for memory systems, enabling chips to handle data access requests from different service types in a balanced manner, thus meeting the requirements of various network services.

[0097] In another embodiment of this application, in order to further improve the processing efficiency of the memory system for data access requests, the read / write control module 202 also has an early response mechanism for data write requests.

[0098] The read / write control module 202 is also used to determine whether the received data access request includes a data write request and whether the processing order of the data write request has been determined. When the determination results are both yes, it replies to the conflict detection module 201 with a data write response.

[0099] In this embodiment of the application, when the read / write control module 202 receives multiple data access requests including data write requests, after determining the processing order of each data access request, the read / write control module 202 can reply to the conflict detection module 201 with a data write response for each data write request.

[0100] The conflict detection module 201 is also used to receive data write responses and delete the request information of the data access request corresponding to the data write response cached in the management queue or conflict queue.

[0101] If the conflict detection module 201 deletes the data cached in the conflict queue and writes the corresponding data access request information to the response, then the conflict detection module 201 also needs to send the data access request corresponding to the request information that conflicts with the deleted request information in the conflict queue to the read-write control module 202.

[0102] Optionally, the conflict queue is a first-in-first-out queue. When the request information at the head of the queue is deleted, the next request information in the conflict queue will be at the head of the queue, and then the data access request corresponding to the latest request information at the head of the queue can be sent to the read-write control module 202.

[0103] In this embodiment of the application, since the data write response to a data write request does not need to carry business data, the read / write control module can reply to the conflict detection module with the data write response in advance after determining the processing order of the data write request. After receiving the data write response, the conflict detection module can delete the request information of the data write request from the management queue or the conflict queue, thereby releasing the queue space in the management queue or the conflict queue, so that more data access requests can be sent to the conflict detection module in a timely manner, thereby improving the processing efficiency of the memory system.

[0104] Because the read / write control module 202 has an early response mechanism for data write requests, the interface conversion module 203 also needs to check whether the data write request has been processed before processing the data read request. This is to avoid data consistency issues at the AXI interface after the conflict detection module 201, the data read / write control module 202, and the interface conversion module 203 have processed the data.

[0105] For example, the read / write control module 202 replies to the conflict detection module 201 in advance with a data write response for the data write request for memory address A. After receiving the data write response, the conflict detection module 201 sends a data read request for memory address A to the read / write control module 202. If there is backpressure on the write channel of the AXI interface, the data read request for memory address A may be processed before the data write request for memory address A. This would cause the data read request for memory address A to read outdated data, resulting in incorrect data being carried in the data read response.

[0106] To avoid the data consistency problem of the above-mentioned write-after-read operation, in another embodiment of this application, the interface conversion module 203 is specifically used to determine whether the data write response of all data write requests that have been started has been received if the received data access request is a data read request. If the determination result is yes, the memory module 204 is read based on the received data read request.

[0107] In this embodiment of the application, the interface conversion module 203 can determine whether it has received the data write response of all data write requests that have been initiated for processing by using the write count value.

[0108] Specifically, the interface conversion module 203 is used to perform a write operation on the memory module 204 based on the received data write request if the received data access request is a data write request. The write count is incremented by 1 for each write operation and decremented by 1 for each received data write response. The initial value of the write count is a preset value.

[0109] The preset value can be a pre-set constant, for example, it can be 0.

[0110] In this embodiment, the AXI IDs of the write operations initiated by the interface conversion module 203 to the memory module 204 based on the data write request are all 0 or the same constant. Since the AXI protocol stipulates that write operations with the same AXI ID must be processed sequentially and cannot be out of order, this embodiment uses the same AXI ID for each write operation. This ensures that the interface conversion module 203 receives the data write response in the order in which the write operations are executed, thereby updating the write count. It is understood that when the write count is a preset value, it indicates that there is no ongoing write operation.

[0111] Furthermore, the interface conversion module 203 is specifically used to determine whether the write count value is a preset value if the received data access request is a data read request, and if the determination result is yes, to perform a read operation on the memory module 204 based on the received data read request.

[0112] Before processing each data read request, the interface conversion module 203 needs to determine whether the write count value is the preset value. If the write count value is the preset value, it can be determined that all data write requests that have been started have been processed, and the data read request can be processed at this time.

[0113] If the write count value is not the preset value, the interface conversion module 203 needs to wait for the write count value to be updated to the preset value before processing the data read request.

[0114] In this way, out-of-order processing of data write and read requests for the same request address by the interface conversion module can be avoided. Combined with the conflict detection operation of the conflict module, data consistency issues in write-after-read operations can be avoided.

[0115] It should be noted that after the interface conversion module 203 completes processing each data read request, it needs to reply with a data read response to the conflict detection module 201. The data read response carries the read data. After receiving the data read response, the conflict detection module 201 can delete the data access request information corresponding to the data read response cached in the management queue or conflict queue, and send the data access request corresponding to the request information that conflicts with the deleted request information in the conflict queue to the read-write control module 202.

[0116] Figure 3 This is a flowchart of the data access request processing provided in the embodiments of this application. The following is in conjunction with... Figure 3 The method for handling data access requests in the memory system provided in this application is described.

[0117] S301. The conflict detection module receives a data access request and sends the data access request to the read / write control module through the BYPASS path, or performs address conflict detection on the data access request and sends the data access request that has passed the address conflict detection to the read / write control module.

[0118] If the business type of the data access request is the specified type, the data access request is sent to the read / write control module through the BYPASS channel. If the business type of the data access request is not the specified type, the conflict detection module performs address conflict detection on the data access request.

[0119] The method for the conflict detection module to perform address conflict detection on data access requests can be referred to the relevant description in the above embodiments, and will not be repeated here.

[0120] S302, The read / write control module performs read / write control on the received data access requests.

[0121] The read / write control module can determine the read window and the write window. Within the read window, it determines the processing order of data read requests and sends data read requests to the interface conversion module according to the determined processing order. Within the write window, it determines the processing order of data write requests and sends data write requests to the interface conversion module according to the determined processing order.

[0122] S303. The read / write control module determines whether a data access request with a determined processing order is a data write request. If so, it replies to the conflict detection module with a data write response in advance. If not, it does not perform any additional processing.

[0123] Specifically, the conflict detection module can send the data write response to the system balancing module, so that the system balancing module can reply with the data write response to the module that issued the data write request.

[0124] S304. The interface conversion module receives data access requests from the read / write control module.

[0125] S305 The interface conversion module selects whether to process a data read request or a data write request through a data selector (multiplexer, MUX).

[0126] If the interface conversion module receives a data write request and selects to process the data write request through the MUX, then S306 is executed; if the interface conversion module receives a data read request and selects to process the data read request through the MUX, then S308 is executed.

[0127] S306. Initiate an AXI write operation, and all write operations use the same AXI ID.

[0128] The interface conversion module increments the write counter by 1 for each AXI write operation it initiates, and decrements the write counter by 1 for each write response it receives.

[0129] S307, the interface conversion module accesses the memory write interface to perform AXI write operations.

[0130] S308, the interface conversion module initiates an AXI read operation.

[0131] S309. The interface conversion module determines whether the write count value is 0. If not, it returns to S308; if so, it executes S310.

[0132] When the write counter is not 0, the interface conversion module needs to wait for all ongoing AXI write operations to be completed and the write counter to be updated to 0 before executing the AXI read operation.

[0133] S310, the interface conversion module accesses the memory read interface to perform AXI read operations.

[0134] It is understandable that after the interface conversion module receives a read response, it can send a data read response to the read / write control module. The data read / write control module then sends the data read response upwards layer by layer until it reaches the module that issued the data read request. It is also understandable that both the read response and the data read response include the data that has been read.

[0135] By adopting the above technical solution, the conflict detection module does not perform address conflict detection for specified types of data access requests, thus eliminating the need to cache these requests in the management queue. Compared to existing technologies that perform address conflict detection on all data access requests, this application reduces the time required for address conflict detection, improves its efficiency, and reduces the queue depth requirement for the management queue, thereby minimizing memory system resource consumption. Furthermore, by determining the processing order of data access requests through the read / write control module, the efficiency of the memory system in handling data access requests is improved. This allows for balanced processing of data access requests from different business types, making the memory system more flexible and meeting the requirements of various network services. Additionally, the read / write control module has an early response mechanism for data write requests. With this mechanism, the interface conversion module can process data read requests according to the write count, improving memory system processing efficiency while avoiding out-of-order read operations and ensuring data consistency.

[0136] As can be seen, this application can improve the performance and stability of the memory system while solving the data consistency problem, and can be flexibly applied to various business scenarios. That is, the memory system provided by this application has the characteristics of high performance, high stability and high flexibility.

[0137] This application also provides a testing method for the above-described memory system.

[0138] Testing of memory systems includes module-level testing and system-level testing.

[0139] Among them, module-level testing refers to testing the interface conversion module and the memory module. In other words, data read and write requests are input into the interface conversion module to test the read and write performance of the interface conversion module on the memory module.

[0140] System-level testing refers to testing the conflict detection module, read / write control module, interface conversion module, and memory module. In other words, data read / write requests are input into the conflict detection module to test the processing performance of the conflict detection module, read / write control module, and interface conversion module on the data read / write requests.

[0141] Furthermore, the above tests include functional tests and performance tests. Functional tests are used to test the correctness of reading and writing data, while performance tests are used to test whether the memory system is performing at its best.

[0142] The performance testing method for the module level is to continuously initiate N (N>10000) individual read operations, individual write operations, or mixed read and write operations on the interface conversion module.

[0143] Similarly, the system-level performance testing method is to continuously initiate N (N>10000) separate read operations, separate write operations, or mixed read-write operations on the conflict detection module.

[0144] If the effective data for each operation is B bits, and the time required from the start of the first operation to the end of the last operation is T, then the data transmission rate is N*B / T.

[0145] The theoretical transfer rate of memory is D*G, where G is the data transfer clock frequency and D is the effective data bit width.

[0146] System performance efficiency is the ratio of data transfer rate to the theoretical memory transfer rate, and can be expressed by the following formula: N*B / (T*D*G)*100%. By comparing the calculated efficiency with the expected efficiency of the memory system, it can be determined whether the memory system's efficiency has met expectations.

[0147] The functional testing method for system-level or module-level systems is as follows: Read and write tests are performed on the memory module. Data consistency is checked by comparing the read and written data. Read and write tests mainly include read-after-write tests, write-after-read tests, and write-after-write tests. Since read operations do not change the memory data, read-after-read tests are not performed.

[0148] The write-after-read test involves performing a write-before-read test on a specific memory address. Multiple write operations to other addresses are inserted between write and read operations to that specific memory address, and this process is repeated multiple times. Each time a write operation is performed on the specific memory address, the data written is incremented by 1. The data read from that specific memory address each time is compared to the data written to that address previously. If they match, no data consistency issue is identified; otherwise, a data consistency issue is identified. By comparing the results, the functionality of each module in the memory system can be determined.

[0149] Read-after-write testing involves performing a read-then-write test on a specific memory address. Since read operations lack a pre-response mechanism, the write operation to that specific memory address must wait until the data is read before proceeding. This allows the system to determine if the read and written data match. If they match, it indicates an incorrect write-then-read sequence; if they don't match, it means no out-of-order read / write occurred. Read-after-write testing is used for system-level testing to determine if the conflict detection module is functioning correctly.

[0150] Write-after-write test involves performing a write-after-write test on a specific memory address. Multiple read or write operations on other addresses are inserted between write operations at the specific memory address, and this process is repeated multiple times. For each write operation performed on the specific memory address, the written data is incremented by 1. For each write operation performed on the specific memory address, a backdoor technique is used to retrieve the data at that specific memory address. The retrieved backdoor data is then compared with the written data to determine whether the data written during the write operation matches the expected data, thereby determining whether the functions of each module in the memory system are normal.

[0151] As can be seen, the memory system provided in this application embodiment can be functionally and performancely tested through the above simple read and write tests, that is, the memory system provided in this application embodiment has the effect of being simple and easy to test.

[0152] This application also provides a chip that includes the memory system described in the above embodiments. This chip can be any type of chip with a memory system, such as a network chip, a graphics processing unit (GPU) chip, a data processing unit (DPU) chip, or a central processing unit (CPU) chip.

[0153] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid state disk (SSD)).

[0154] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0155] The various embodiments in this specification are described in a related manner, and the same or similar parts between the various embodiments can be referred to each other.

[0156] The above description is merely a preferred embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application are included within the scope of protection of this application.

Claims

1. A memory system, characterized in that, The memory system is located in the network chip. The memory system includes a conflict detection module, a read / write control module, an interface conversion module, and a memory module connected in sequence. The conflict detection module includes a bypass BYPASS path. The conflict detection module is used to receive data access requests. If the service type of the data access request belongs to a specified type, the data access request is sent to the read / write control module through the BYPASS channel. If the service type of the data access request does not belong to the specified type, the data access request is checked for address conflict based on the request information cached in the management queue and the conflict queue. If the address conflict detection passes, the request information of the data access request is cached in the management queue, and the data access request is sent to the read / write control module. If the address conflict detection fails, the request information of the data access request is cached in the conflict queue, and the data access request is cached. After the address conflict is resolved, the data access request is sent to the read / write control module. The read / write control module is used to determine the processing order of data access requests and send data access requests to the interface conversion module according to the processing order. The interface conversion module is used to access the memory module based on the received data access request.

2. The memory system according to claim 1, characterized in that, The read / write control module is also used to determine whether the received data access request includes a data write request and whether the processing order of the data write request has been determined. When the determination results are both yes, the module replies with a data write response to the conflict detection module. The conflict detection module is also used to receive the data write response and delete the request information of the data access request corresponding to the data write response cached in the management queue or the conflict queue.

3. The memory system according to claim 2, characterized in that, The interface conversion module is specifically used to determine whether a data write response has been received for all data write requests that have been initiated if the received data access request is a data read request. If the determination result is yes, a read operation is performed on the memory module based on the received data read request.

4. The memory system according to any one of claims 1-3, characterized in that, The read / write control module is specifically used to determine the processing order of received data read requests if the current window is a read window and the received data access requests include data read requests. If the current window is a write window and the received data access requests include data write requests, then determine the processing order of the received data write requests.

5. The memory system according to claim 4, characterized in that, The memory module is an external storage module; The read / write control module is further configured to alternately switch between the read window and the write window according to a preset read cycle duration and a preset write cycle duration; or, switch between the read window and the write window according to a polling (RR) algorithm or a weighted round-robin scheduling (WRR) algorithm; or, when the duration of the write window reaches a preset duration threshold, if the number of currently unprocessed data read requests is greater than the number of data write requests, then switch to the read window; when the duration of the read window reaches a preset duration threshold, if the number of currently unprocessed data write requests is greater than the number of data read requests, then switch to the write window; or, alternately switch between the read window and the write window of the read / write control module according to the read window and the write window of the external storage module.

6. The memory system according to claim 4, characterized in that, The read / write control module is specifically used to determine the processing order of the received data read requests according to the bank address corresponding to the request address of the received data read request, and according to the preset scheduling order of each bank address; and to determine the processing order of the received data write requests according to the bank address corresponding to the request address of the received data write request, and according to the preset scheduling order of each bank address.

7. The memory system according to claim 6, characterized in that, The read / write control module is specifically used to determine the processing order of multiple data read requests that have the same bank address corresponding to the request address, according to the business type of the multiple data read requests and the WRR algorithm. For multiple data write requests that correspond to the same bank address, the processing order of the multiple data write requests is determined according to the business type of the multiple data write requests and the WRR algorithm.

8. The memory system according to claim 1, characterized in that, The request information cached in the management queue and the conflict queue includes the request address and the service type; The conflict detection module is specifically used to determine whether there is a target request information in the management queue and the conflict queue that is the same as the service type of the received data access request; If the address conflict does not exist, the address conflict detection is considered successful. If the address conflict exists, it is determined whether the request address in the target request information is the same as the request address of the data access request. If they are the same, the address conflict detection is considered unsuccessful. If they are different, the address conflict detection is considered successful.

9. The memory system according to claim 1, characterized in that, The memory system also includes a system balancing module, and the memory system includes multiple memory modules, each of which corresponds to a set of conflict detection modules, read / write control modules and interface conversion modules; The system balancing module is used to receive data access requests, determine the target memory module that matches the request address of the data access request, and send the data access request to the conflict detection module corresponding to the target memory module.

10. A chip, characterized in that, Includes the memory system described in any one of claims 1-9.

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