Directional signal driver network circuit and directional signal cascade circuit

Abstract

The invention relates to the technical field of integrated circuits, and particularly to a directional signal driving network circuit and a directional signal cascade circuit. The invention comprises eight controllable inverters, each of which is arranged in a closed loop in a head-to-tail manner along four sides of an equivalent rectangle, two inverters on each side of the rectangle, four external connection terminals at the four corners of the rectangle, a connection point between the two inverters on the same side of the rectangle being referred to as a midpoint, each midpoint being connected to a same central connection point through a switch, and the central connection point and each midpoint each having an external connection terminal.

Description

Technical Field

[0001] This invention relates to integrated circuit technology. Background Technology

[0002] As prior art, US Patent US20040133750A1 discloses a directional signal driving network circuit, see [link / reference]. Figure 1 The current method uses four multiplexers (350) to select the data source for east, south, west, and north directions, resulting in a complex structure. Even if the 2-to-1 multiplexer (350) is equivalent to two switches, it still requires eight switches and eight inverters. Furthermore, this technology only offers four directions (east, south, west, and north), which would lead to excessive area and resource consumption for highly integrated chips. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a directional signal driving network circuit with simple structure, low power consumption and low latency.

[0004] The technical solution adopted by the present invention to solve the aforementioned technical problem is a directional signal driving network circuit, characterized in that it includes 8 enableable and controllable inverters. Each inverter is arranged in a closed loop manner with the ends connected to each other on the four sides of an equivalent rectangle. Each side of the rectangle has two inverters. The four vertices of the rectangle are four external connection terminals. The connection point of two inverters on the same side of the rectangle is called the midpoint. Each midpoint is connected to the same central connection point through a switch, and the central connection point and each midpoint have their own external connection terminals.

[0005] The present invention also provides a directional signal cascade circuit, characterized in that it includes two directional signal driving network circuits, wherein the directional signal driving network circuit includes eight enableable and controllable inverters, each inverter is arranged in a closed loop manner with the head and tail connected to the four sides of an equivalent rectangle, each side of the rectangle has two inverters, the four vertices of the rectangle are four external connection terminals, the connection point of two inverters on the same side of the rectangle is called the midpoint, each midpoint is connected to the same central connection point through a switch, and the central connection point and each midpoint each have an external connection terminal;

[0006] Each of the two directional signal driving network circuits uses an external connection terminal as a cascade terminal, and the cascade terminals of the two directional signal driving network circuits are connected to each other.

[0007] The present invention also provides a second type of directional signal cascaded circuit, characterized in that it includes five directional signal driving network circuits.

[0008] The directional signal drive network circuit includes eight enableable and controllable inverters. Each inverter is arranged in a closed loop with the ends connected to each other on the four sides of an equivalent rectangle. Each side of the rectangle has two inverters. The four vertices of the rectangle are four external connection terminals. The connection point of two inverters on the same side of the rectangle is called the midpoint. Each midpoint is connected to the same central connection point through a switch. The central connection point and each midpoint have their own external connection terminals.

[0009] The westward vertex of the fifth directional signal driven network circuit is connected to the southeastward midpoint of the first directional signal driven network circuit.

[0010] The south vertex of the fifth directional signal driving network circuit is connected to the northeast midpoint of the second directional signal driving network circuit.

[0011] The eastward vertex of the fifth directional signal driving network circuit is connected to the northwestward midpoint of the third directional signal driving network circuit.

[0012] The north vertex of the fifth directional signal driven network circuit is connected to the southwest midpoint of the fourth directional signal driven network circuit.

[0013] The directional signal drive network circuit of this invention requires only 4 switches and 8 inverters to achieve 8 directional selections, and can achieve even more directional selections after cascading. This invention features a simple circuit, small footprint, and significantly reduced latency and power consumption. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of the existing technology.

[0015] Figure 2 This is a schematic diagram of the structure of the present invention.

[0016] Figure 3 This is a schematic diagram of the structure of Embodiment 1 of the present invention.

[0017] Figure 4 This is a schematic diagram of the structure of Embodiment 2 of the present invention. Detailed Implementation

[0018] See Figure 2 The present invention includes eight enableable and controllable inverters. Each inverter is arranged in a closed loop with the ends connected to each other on the four sides of an equivalent rectangle. Each side of the rectangle has two inverters. The four vertices of the rectangle are four external connection terminals. The connection point of two inverters on the same side of the rectangle is called the midpoint. Each midpoint is connected to the same central connection point through a switch. The central connection point and each midpoint are each external connection terminals.

[0019] In this invention, all inverters are arranged in a ring, forming a closed loop according to the current direction, which is called end-to-end connection. The current direction can be either clockwise or counterclockwise. Figure 2 It shows the method of connecting the two ends in a counterclockwise direction.

[0020] The inverters are not strictly arranged in a rectangular pattern; they can be circular rings or other closed curves, but from a topological perspective, they are all equivalent to... Figure 2 The closed rectangle shown.

[0021] Specifically, this implementation method includes:

[0022] The first inverter 201 has its current input terminal connected to the west vertex 220 and its current output terminal connected to the southwest midpoint 221.

[0023] The second inverter 202 has its current input terminal connected to the southwest midpoint 221 and its current output terminal connected to the south vertex 222.

[0024] The third inverter 203 has its current input terminal connected to the south-facing vertex 222 and its current output terminal connected to the southeast-facing midpoint 223.

[0025] The fourth inverter 204 has its current input terminal connected to the southeast midpoint 223 and its current output terminal connected to the east vertex 224.

[0026] The fifth inverter 205 has its current input terminal connected to the east-facing vertex 224 and its current output terminal connected to the northeast-facing midpoint 225.

[0027] The sixth inverter 206 has its current input terminal connected to the northeast midpoint 225 and its current output terminal connected to the north apex 226.

[0028] The seventh inverter 207 has its current input terminal connected to the north-facing vertex 226 and its current output terminal connected to the northwest-facing midpoint 227.

[0029] The eighth inverter 208 has its current input terminal connected to the northwest midpoint 227 and its current output terminal connected to the west vertex 220.

[0030] The midpoints in the southwest, southeast, northwest, and northeast directions are each connected to the central connection point O via a controllable switch.

[0031] The enable signals for the first to eighth inverters are en1 to en8, respectively, and each inverter is an enable-controllable inverter.

[0032] This circuit can be cascaded multiple times, allowing clock signals, data signals, and other signals to be transmitted in the specified direction as configured.

[0033] The four switches (209, 210, 211, 212) are enabled and controlled by control signals SW1, SW2, SW3, and SW4, respectively.

[0034] The eight inverters (201, 202, 203, 204, 205, 206, 207, 208) are enabled and disabled by control signals en1, en2, en3, en4, en5, en6, en7, and en8, respectively.

[0035] For a directional signal driving circuit of the present invention, the respective control signals SW1, SW2, SW3, SW4, en1, en2, en3, en4, en5, en6, en7, and en8 can be controlled independently, or multiple control signals can be directly connected in series, or the signals can be coupled together by inversion, thereby reducing the complexity of the control circuit.

[0036] For a cascaded network of two or more directional signal drive circuits of the present invention, the respective control signals SW1, SW2, SW3, SW4, en1, en2, en3, en4, en5, en6, en7, and en8 can be controlled independently, or multiple control signals can be directly connected in series, or the signals can be coupled together by inversion, thereby reducing the complexity of the control circuit.

[0037] Here, it is assumed that the switch is on when the control signal is 1, and the switch is off when the control signal is 0.

[0038] Here, it is assumed that the inverter is enabled when the control signal is 1 and disabled when the control signal is 0. When the control signal is x, it means that the control signal is not relevant and the function is unaffected when the control signal is 1 or 0.

[0039] When there are more than one control signal that can achieve the same function, only one of them is listed here.

[0040] The circuit of this invention has one function: to enable communication in four directions (east, south, west, and north), with a one-input, one-output direction control table, as shown in Table 1.

[0041] Table 1 Signal Direction Control Table (One Input, One Output)

[0042] 1 0 1 0 1 0 0 0 0 1 0 0 West→North 1 1 0 0 1 0 0 1 0 0 0 0 West → East 0 0 0 0 1 1 0 0 0 0 0 0 West→South 0 1 0 1 0 0 1 0 0 0 0 1 South→West 0 1 1 0 0 0 1 0 0 1 0 0 south→north 0 0 0 0 0 0 1 1 0 0 0 0 South → East 1 0 1 0 0 1 0 0 1 0 0 0 East → South 0 0 1 1 0 0 0 0 1 0 0 1 East → West 0 0 0 0 0 0 0 0 1 1 0 0 East → North 0 0 0 0 0 0 0 0 0 0 1 1 North→West 1 0 0 1 0 1 0 0 0 0 1 0 north→south 0 1 0 1 0 0 0 1 0 0 1 0 North → East

[0043] As can be seen from Table 1, different combinations of control signals can be used to obtain different directions of the signal.

[0044] The second function of the circuit in this invention is to achieve the effect of outputting from two or three directions when inputting from one direction.

[0045] For example, according to the combination in Table 2, multiple output results can be achieved from input in the west (220) to output in the north (226), east (224), and south (222), and the signal driving capability is enhanced.

[0046] This section only describes the case of one-way input and three-way output. Similarly, the case of one-way input and two-way output can also be implemented.

[0047] Table 2 Signal Direction Control Table (One Input, Multiple Outputs)

[0048] 1 1 1 0 1 1 0 1 0 1 0 0 West → North, West → East, West → South 0 1 1 1 0 0 1 1 0 1 0 1 South → East, South → North, South → West 1 0 1 1 0 1 0 0 1 0 0 1 East → South, East → North, East → West 1 1 0 1 0 1 0 1 0 0 1 1 North → South, North → East, North → West

[0049] The third function of the circuit in this invention is to achieve signal transmission in some directions without interference, namely, two-way input and two-way output.

[0050] Table 3 Signal Direction Control Table (Two Inputs, Two Outputs)

[0051] 0 0 0 0 1 1 0 0 1 1 0 0 West → South, East → North 0 0 0 0 0 0 1 1 0 0 1 1 North → West, South → East

[0052] The circuit of this invention has four functions, realizing one input and four-way output. After directional expansion, it can support up to one-way input and eight-way output.

[0053] This function is suitable for omnidirectional signal distribution, and is especially suitable for the distribution of internal clock and reset signals within a chip.

[0054] The signal input point for this function is point O (213).

[0055] Table 4 Signal Direction Control Table (O Point Input)

[0056] 1 1 1 1 0 1 0 1 0 1 0 1 O→East, O→South, O→West, O→North

[0057] The circuit of this invention has five functions, which are expanded to include eight-directional signal interconnection.

[0058] Based on the existing directions of West (220), South (222), East (224), and North (226), four new directions are added: Southwest (221), Southeast (223), Northeast (225), and Northwest (227).

[0059] The extended eight directions can also achieve the above four functions. The difference is that when one of the southwest (221), southeast (223), northeast (225), and northwest (227) is used as input, and one of the southwest (221), southeast (223), northeast (225), and northwest (227) is used as output, only interconnection is achieved, and there is no enhanced driving capability function.

[0060] To enhance driving capability, each inverter of the present invention can also be constructed by connecting multiple inverters in series, in parallel, or otherwise.

[0061] Two directional signal drive circuits connected in parallel are particularly suitable for directional signal drive circuit networks.

[0062] Parallel connection of directional signal drive circuit networks with a wider bit width is particularly suitable for data bus and address bus signal drive networks.

[0063] The circuit of this invention is well-suited for enhancing the driving capability of long-distance signals between modules within a chip, and can flexibly achieve directional signal driving by controlling the direction of the signal through an enable control signal.

[0064] The circuit of this invention can also realize the function of input in one direction and output in multiple directions.

[0065] The circuit of this invention is very suitable for integrating intellectual property module circuits (generally referred to as IP cores) inside chips.

[0066] Example 1

[0067] See Figure 3 Both module 301 and module 302 are Figure 1 The simplified circuit block diagram.

[0068] Input signal 303 is input to module 301 from the west. Module 301 distributes the signal to the south 304, east 305, and north 306. The east 305 signal output by module 301 serves as the west 307 input signal of module 302, which then distributes the signal again to the south 308, east 309, and north 310.

[0069] The cascading method in this embodiment is particularly suitable for applications such as long-distance signal transmission.

[0070] Example 2

[0071] See Figure 4 Modules 401, 402, 403, 404, and 405 are all... Figure 1 Simplified block diagram of the circuit. Input signal 406 is input from point O1 of module 405, and module 405 distributes the signal to directions such as west 407, south 408, east 409, and north 410.

[0072] The output signal of module 405 (West 407) serves as the input signal of module 401 (O1).

[0073] The output signal of module 405 (south 408) is used as the O2 input signal of module 402.

[0074] The output signal of module 405 (East 409) serves as the input signal of module 403 (O3).

[0075] The North 410 output signal of module 405 serves as the O4 input signal of module 404.

[0076] Modules 401, 402, 403, and 404 redistribute the input signal to their respective east, south, west, and north directions.

[0077] Module 401 distributes the signal to West 411, South 412, East 413, and North 414.

[0078] Module 402 distributes the signal to West 415, South 416, East 417, and North 418.

[0079] Module 403 distributes the signal to West 419, South 420, East 421, and North 422.

[0080] Module 404 distributes the signal to West 423, South 424, East 425, and North 426.

[0081] The second cascading method is particularly suitable for signal distribution and synchronization in a regional setting.

[0082] The second cascading method allows input signals in the first, second, third, and fourth quadrant circuits to achieve characteristics such as simultaneous arrival, synchronous rise, and synchronous fall.

Claims

1. A directional signal driving network circuit, characterized in that, It includes 8 enableable and controllable inverters, which are arranged in a closed loop on the four sides of an equivalent rectangle. Each side of the rectangle has two inverters, and the four vertices of the rectangle are four external connection terminals. The connection point of two inverters on the same side of the rectangle is called the midpoint. Each midpoint is connected to the same central connection point through a switch, and the central connection point and each midpoint have their own external connection terminals.

2. A directional signal cascade circuit, characterized in that, Includes two directional signal drive network circuits, The directional signal drive network circuit includes eight enableable and controllable inverters. Each inverter is arranged in a closed loop with the ends connected to each other on the four sides of an equivalent rectangle. Each side of the rectangle has two inverters. The four vertices of the rectangle are four external connection terminals. The connection point of two inverters on the same side of the rectangle is called the midpoint. Each midpoint is connected to the same central connection point through a switch. The central connection point and each midpoint have their own external connection terminals. Each of the two directional signal driving network circuits uses an external connection terminal as a cascade terminal, and the cascade terminals of the two directional signal driving network circuits are connected to each other.

3. A directional signal cascade circuit, characterized in that, Includes 5 directional signal drive network circuits, The directional signal drive network circuit includes eight enableable and controllable inverters. Each inverter is arranged in a closed loop with the ends connected to each other on the four sides of an equivalent rectangle. Each side of the rectangle has two inverters. The four vertices of the rectangle are four external connection terminals. The connection point of two inverters on the same side of the rectangle is called the midpoint. Each midpoint is connected to the same central connection point through a switch. The central connection point and each midpoint have their own external connection terminals. The westward vertex of the fifth directional signal driven network circuit is connected to the southeastward midpoint of the first directional signal driven network circuit. The south vertex of the fifth directional signal driving network circuit is connected to the northeast midpoint of the second directional signal driving network circuit. The eastward vertex of the fifth directional signal driving network circuit is connected to the northwestward midpoint of the third directional signal driving network circuit. The north vertex of the fifth directional signal driven network circuit is connected to the southwest midpoint of the fourth directional signal driven network circuit.

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