Data-driven integrated circuit and operational amplifier circuit

Abstract

The present disclosure relates to data-driven integrated circuits and operational amplifier circuits. The data-driven integrated circuits of the present embodiments can include a digital-to-analog converter configured to change a digital signal to an analog signal, and an amplifier configured to receive the analog signal through an input terminal and output a data voltage to a pixel connected to a data line, wherein the amplifier can receive one of a plurality of output signals from a plurality of output terminals as feedback.

Description

Technical Field

[0001] This embodiment relates to a data driver integrated circuit for driving a panel and a display device including the data driver integrated circuit. Background Technology

[0002] The display device may include a panel, a data driving circuit for driving the panel, and a timing controller for controlling the driving of the data driving circuit.

[0003] The timing controller can transmit drive control data and image data to the data drive circuit, and can control the drive timing of the panel of the data drive circuit based on the drive control data.

[0004] A data drive circuit can drive multiple pixels in a row. It generates image signals from image data to drive multiple pixels on the panel. The data drive circuit may include a digital-to-analog converter (DAC) and a buffer. The DAC generates data voltages (i.e., analog signals) by receiving image data. The buffer outputs the data voltages to the pixels through multiple data lines connected to the panel.

[0005] Traditional data drive circuits control the output of the data drive circuit by using an external switch connected to the output of the buffer to block or connect the output of the data voltage transmitted to the pixel through the buffer.

[0006] In traditional data drive circuits, the output drive of the buffer may be limited because switches or multiplexers need to be installed separately outside the buffer.

[0007] Furthermore, in conventional data drive circuits, the output is blocked by an external switch of the amplifier to achieve high impedance during timing after the drive buffer, thus generating a quiescent current in the buffer. Summary of the Invention

[0008] In this context, in one aspect, various embodiments relate to providing a data driving circuit and a display device including the data driving circuit, the data driving circuit being able to reduce the size of the buffer within the data driving circuit and reduce the generation of quiescent current in the buffer.

[0009] In this context, on the other hand, various embodiments relate to providing a data driving circuit and a display device including the data driving circuit, which is capable of providing high impedance functionality while maintaining existing buffer functionality by including a switch or multiplexer of the data driving circuit arranged outside the buffer in the amplifier.

[0010] In one aspect, this embodiment can provide a data-driven integrated circuit, including: a digital-to-analog converter (DAC) configured to convert a digital signal into an analog signal; and an amplifier configured to generate a data voltage using an analog signal received via an input terminal, via a folded cascode gain circuit and an inverting gain circuit, and to output the data voltage. The folded cascode gain circuit can receive one of a plurality of output voltages of the amplifier. The inverting gain circuit can receive the output signal of the folded cascode gain circuit and can modify the signal transmitted to a transistor connected to the output terminal by a multiplexer arranged within the inverting gain circuit. In the data-driven integrated circuit, the multiplexer within the inverting gain circuit can be connected to the transistor in a manner forming a common node and can control the source voltage, drain voltage, or gate voltage of the transistor.

[0011] In a data-driven integrated circuit, the multiplexer can change the gate voltage delivered to the transistor and the output voltage of the amplifier based on a set criterion.

[0012] In a data-driven integrated circuit, the multiplexer may include a first multiplexer and a second multiplexer. The first multiplexer may be connected to a P-type transistor. The second multiplexer may be connected to an N-type transistor. The first and second multiplexers can independently control the output voltage of the amplifier.

[0013] In a data-driven integrated circuit, the inverting gain circuit may include P-type transistors and N-type transistors, and the output voltage of the amplifier can be changed by controlling the current between the P-type transistors and the N-type transistors. A multiplexer connected to the N-type transistor can transmit ground voltage to the N-type transistor.

[0014] In data-driven integrated circuits, the inverting gain circuit can form multiple output terminals by connecting multiple transistor groups in parallel.

[0015] The data-driven integrated circuit may also include an external multiplexer configured to select one or more voltages output from the output of the amplifier and to provide a feedback voltage to the input of the amplifier.

[0016] In a data-driven integrated circuit, the amplifier may include a first output terminal and a second output terminal. A line connected to the first output terminal transmits a data voltage to a pixel, and another line transmits the data voltage to an external multiplexer. A line connected to the second output terminal transmits the data voltage to the external multiplexer. The external multiplexer can select either the voltage received from the first output terminal or the voltage received from the second output terminal.

[0017] In another aspect, an operational amplifier may include a plurality of output terminals configured to transmit data voltages. Each of the plurality of output terminals may include: a P-type transistor having a source electrode connected to a first line and a gate electrode connected to a second line; and an N-type transistor having a source electrode connected to a third line and a gate electrode connected to a fourth line. The plurality of output terminals may form an output voltage path to a node to which the P-type transistor and the N-type transistor are connected. The output voltages of the plurality of output terminals may be controlled by a multiplexer respectively arranged in the second line and the fourth line and disposed within the operational amplifier.

[0018] In an operational amplifier, the multiplexer can control the output voltage at the output terminal by receiving signals for controlling the P-type transistor or the N-type transistor.

[0019] In the operational amplifier, the multiplexer can be connected to the P-type transistor or the N-type transistor, and the voltage delivered to the P-type transistor or the N-type transistor can be selected.

[0020] In an operational amplifier, the output voltage path formed by the operational amplifier may include a first output voltage path and a second output voltage path, wherein the first output voltage path is used to transmit the feedback voltage to the input terminal of the amplifier, and the second output voltage path is used to transmit the data voltage to the pixel.

[0021] In the operational amplifier, one of the plurality of output terminals can be electrically connected to an external multiplexer disposed outside the operational amplifier. Another of the plurality of output terminals can be electrically connected to the external multiplexer, and also connected to multiple pixels, and transmits data voltage.

[0022] In another aspect, an operational amplifier circuit may include: a first multiplexer configured to select an input voltage delivered to the operational amplifier via a negative terminal of the input; a folded cascode gain circuit connected to the negative and positive terminals of the input and configured to change the gain of the input voltage; a first inverting gain circuit configured to generate an output voltage by delivering a voltage delivered by the folded cascode gain circuit to a first transistor; and a second inverting gain circuit configured to share a voltage node with the first inverting gain circuit and including a multiplexer for changing the voltage delivered to the second transistor.

[0023] In the operational amplifier, the output voltage at the output terminal of the operational amplifier can be controlled by a third multiplexer connected to the first transistor.

[0024] As described above, according to this embodiment, by including a multiplexer in the amplifier of the buffer within the data drive circuit, the limitation on the output drive of the amplifier can be reduced, and the size of the data drive circuit can be reduced.

[0025] As described above, according to this embodiment, the static current consumed in the data drive circuit can be reduced.

[0026] As described above, according to this embodiment, a buffer that provides high impedance functionality in a data driving circuit can be provided. Attached Figure Description

[0027] Figure 1 This is a configuration diagram of a typical display device.

[0028] Figure 2 It is a diagram used to describe the configuration in which data voltage is transmitted to the panel in a conventional data drive circuit.

[0029] Figure 3 It is a block diagram used to describe the configuration of a conventional data-driven circuit.

[0030] Figure 4 This is a block diagram illustrating the construction of amplifiers and switches within a conventional data drive circuit.

[0031] Figure 5 This is a first example block diagram illustrating an amplifier within a data drive circuit according to an embodiment.

[0032] Figure 6 This is a second example block diagram illustrating an amplifier within a data drive circuit according to an embodiment.

[0033] Figure 7 This is a diagram used to compare the configurations of a conventional data drive circuit and a data drive circuit according to an embodiment.

[0034] Figure 8 This is a first example circuit diagram illustrating an operational amplifier within a data drive circuit according to an embodiment.

[0035] Figure 9 This is a second example circuit diagram illustrating an operational amplifier within a data drive circuit according to an embodiment.

[0036] Figure 10 This is a third example circuit diagram illustrating an operational amplifier within a data drive circuit according to an embodiment.

[0037] Figure 11 This is a first example diagram illustrating the operation type of a data driving circuit according to an embodiment.

[0038] Figure 12 This is a second example diagram illustrating the operation type of the data driving circuit according to an embodiment.

[0039] Figure 13 This is a diagram used to compare the operation of the data drive circuit and the gate drive circuit.

[0040] Figure 14 This is a diagram used to describe a high-impedance driving method according to an embodiment. Detailed Implementation

[0041] Figure 1 This is a configuration diagram of a typical display device.

[0042] Reference Figure 1 The display device 100 may include a panel 110, a data driving circuit 120, a gate driving circuit 130, a touch sensing circuit 140, a control circuit 150, etc.

[0043] Multiple data lines DL connected to the data driving circuit 120 can be formed in the panel 110. Multiple gate lines GL connected to the gate driving circuit 130 can be formed in the panel 110. In addition, multiple pixels P corresponding to the intersections of the multiple data lines DL and the multiple gate lines GL can be defined in the panel 110.

[0044] A transistor having a first electrode (e.g., a source electrode or a drain electrode) connected to a data line DL, a gate electrode connected to a gate line GL, and a second electrode (e.g., a drain electrode or a source electrode) connected to a display electrode can be formed in each pixel P.

[0045] Panel 110 may include a display panel and a touch screen panel (TSP). In this case, the display panel and the TSP may share some components.

[0046] The data drive circuit 120 can supply data signals to the data line DL to display images in each pixel P of the panel 110.

[0047] The data driver circuit 120 may include at least one data driver integrated circuit. The at least one data driver integrated circuit may be directly formed in the panel 110. In some cases, the at least one data driver integrated circuit may be integrated and formed in the panel 110. If desired, the data driver circuit 120 may be defined as a source driver or a source driver integrated circuit.

[0048] The gate drive circuit 130 can sequentially supply scan signals to the gate line GL to turn on or off the transistors arranged in each pixel P. When a scan signal with an on voltage is supplied to pixel P, pixel P can be connected to the data line DL. When a scan signal with an off voltage is supplied to pixel P, pixel P can be disconnected from the data line DL.

[0049] The touch sensing circuit 140 can obtain touch sensing data by applying a drive signal to some or all of the multiple touch electrodes TE connected to the sensing line SL.

[0050] The control circuit 150 can supply various types of control signals to the data driving circuit 120, the gate driving circuit 130, and the touch sensing circuit 140.

[0051] The control circuit 150 can transmit a data control signal DCS for controlling the data driving circuit 120 to supply data voltages to each pixel P at various timings, can transmit a gate control signal GCS to the gate driving circuit 130, or can transmit a sensing signal to the touch sensing circuit 140. The control circuit 150 can be a timing controller T-Con, or can include a timing controller and also perform other control functions.

[0052] Figure 2 It is a diagram used to describe the configuration in which data voltage is transmitted to the panel in a conventional data drive circuit.

[0053] refer to Figure 2 The data drive circuit 120 may include a DAC 121, a buffer 122, a switch 123, etc.

[0054] The DAC 121 can receive image data in digital form and convert the image data into analog signals.

[0055] Buffer 122 can receive analog signals from DAC 121, amplify the analog signals, and supply the amplified signals to data line DL. Furthermore, buffer 122 can receive bias current from bias control circuitry (not shown) and output data voltage.

[0056] If needed, buffer 122 can be defined as a buffer amplifier or an amplifier. For example, the amplifier can be an operational amplifier (OP-amplifier).

[0057] Switch 123 can be electrically connected to the output of buffer 122, and the output of buffer 122 can be transmitted to panel 110 or the output of buffer 122 can be blocked via data line DL. Switch 123 can be driven based on a control signal received from control circuit 150.

[0058] Switch 123 is connected at a timing following the output drive of buffer 122. Therefore, although the output of buffer 122 is transmitted to panel 110, quiescent current is always present.

[0059] Furthermore, the switch 123 includes a resistor, so a quiescent current is generated even under high impedance conditions, such as when the switch is open or when the resistance of the switch is increased or when a small amount of current is allowed.

[0060] Switch 123 can be formed by integrating multiple switches. Switch 123 can be replaced by a multiplexer that receives various types of signals and selects one or more signals. If needed, the multiplexer can be defined as a MUX.

[0061] In order to transmit the output voltage from the conventional data drive circuit 120 to the panel 110, the buffer 122 and the external switch or external multiplexer connected to the buffer 122 must be combined and driven. Therefore, the size of the data drive circuit is limited.

[0062] Figure 3 It is a block diagram used to describe the configuration of a conventional data-driven circuit.

[0063] Reference Figure 3 The conventional data driving circuit 120 may include multiple operational amplifiers 122-1, 122-2, 122-3 and 122-4, a first switch group 123-1, 123-2, 123-3 and 123-4, a second switch group 124-1 and 124-2, etc.

[0064] Multiple operational amplifiers 122-1, 122-2, 122-3 and 122-4 may include a first operational amplifier 122-1 to a fourth operational amplifier 122-4, and may be connected to correspond to a first output terminal “SDIC Output 1” to a fourth output terminal “SDIC Output 4”, respectively.

[0065] Channels CH1 to CH4 can be connected to the corresponding data lines via their output terminals.

[0066] Operational amplifiers 122-1, 122-2, 122-3, and 122-4 can transmit data voltages to the data lines via channels CH1 to CH4.

[0067] The first switch group 123-1, 123-2, 123-3 and 123-4 and the second switch group 124-1 and 124-2 can be arranged between the multiple operational amplifiers 122-1, 122-2, 122-3 and 122-4 and multiple output terminals, and can be turned on / off.

[0068] The first switch group 123-1, 123-2, 123-3, and 123-4 may include the first switch 123-1 through the fourth switch 123-4. Each switch may be controlled by a control circuit (not shown). The switch signal SW1 transmitted by the control circuit (not shown) may be the source output enable signal SOE or the inverted signal of the source output enable signal SOE.

[0069] The second switch groups 124-1 and 124-2 may include a first charge-sharing switch 124-1 and a second charge-sharing switch 124-2. Each charge-sharing switch may be controlled by a control circuit (not shown).

[0070] The second switch groups 124-1 and 124-2 can connect multiple channels CH1 to CH4, wherein data voltages of the same polarity are provided through multiple channels CH1 to CH4. For example, the first charge-sharing switch 124-1 can be connected between the first channel CH1 and the third channel CH3. The second charge-sharing switch 124-2 can be connected between the second channel CH2 and the fourth channel CH4.

[0071] The first charge-sharing switch 124-1 and the second charge-sharing switch 124-2 can be turned on / off in response to the second switch signal SW2, depending on the operating interval. For example, in the first interval (e.g., the normal display interval), both the first charge-sharing switch 124-1 and the second charge-sharing switch 124-2 can be turned off. Furthermore, in the second interval (e.g., the blanking interval), both the first charge-sharing switch 124-1 and the second charge-sharing switch 124-2 can be turned on. That is, the first charge-sharing switch 124-1 can electrically disconnect the first channel CH1 and the third channel CH3. The second charge-sharing switch 124-2 can electrically disconnect the second channel CH2 and the fourth channel CH4.

[0072] The conventional data driver circuit 120 also has the above-mentioned problems because the conventional data driver circuit 120 needs to include a first switch group 123-1, 123-2, 123-3 and 123-4, a second switch group 124-1 and 124-2, etc., outside the operational amplifier circuit or outside the data driver integrated circuit, in order to prevent charge sharing.

[0073] Figure 4 This is a block diagram illustrating the construction of amplifiers and switches within a conventional data drive circuit.

[0074] Reference Figure 4 Amplifier 210 may include bias power supply circuit 211, folded cascode gain circuit 212, inverting gain circuit 213, feedback circuit 214, etc.

[0075] The bias power supply circuit 211 can independently supply bias voltage or current to the amplifier in the data drive circuit.

[0076] The folded cascode gain circuit 212 may include a cascode current mirror, a cascode current source, etc., and can be connected to the (-) input terminal and (+) input terminal of the amplifier, and can receive analog signals.

[0077] A folded cascode gain circuit can have Figure 8 The disclosed form includes a folded cascode gain circuit with multiple P-type and N-type transistors.

[0078] The inverting gain circuit 213 can be connected to the folded cascode gain circuit 212 and can transmit the inverting gain to the outside of the amplifier. The inverting gain circuit can be a circuit that connects P-type transistors and N-type transistors.

[0079] The conventional inverting gain circuit 213 forms only one output, thus generating the output voltage only through a pair of P-type and N-type transistors.

[0080] The feedback circuit 214 can receive the output of the inverting gain circuit 213 and transmit the output to the input of the amplifier.

[0081] The problem with the conventional feedback circuit 214 is that, because the feedback circuit only sends one output to the input of the amplifier, the type of feedback voltage cannot be selected, and because the feedback circuit responds sensitively to changes in the voltage at the output, it has low stability.

[0082] Multiplexer 220 is connected to the output of an amplifier external to amplifier 210 and is configured as a separate circuit, including resistors. Multiplexer 220 is disposed external to a data driver integrated circuit (not shown) and receives or blocks the amplifier's output. Multiplexer 220 can receive output signals from multiple amplifiers and can operate as a switch when receiving an output signal from one amplifier. Multiplexer 220 can be defined as a MUX if desired.

[0083] The condition in which the multiplexer 220 blocks the output by turning off the switch can be defined as a high impedance state.

[0084] The amplifier 210 and multiplexer 220 within the data drive circuit are treated as separate components and require separate control signals from the timing controller. Furthermore, when the data voltage is not transmitted to the panel outside the data drive circuit, or even under high impedance conditions, the total power consumption of the display device increases due to the generation of quiescent current within the amplifier 210.

[0085] Figure 5 This is a first example block diagram illustrating an amplifier within a data drive circuit according to an embodiment.

[0086] Reference Figure 5 The amplifier 310 may include a bias power supply circuit 311, a folded cascode gain circuit 312, an inverting gain circuit 313, a high-impedance drive circuit 314, an output selection circuit 315, a feedback circuit 316, etc.

[0087] The bias power supply circuit 311 can independently supply bias voltage or bias current to the amplifier in the data drive circuit.

[0088] The folded cascode gain circuit 312 may include a cascode current mirror, a cascode current source, etc., and may be a reference. Figure 4 Describes a folded cascode gain circuit that changes the gain of the input voltage.

[0089] The inverting gain circuit 313 can be connected to the folded cascode gain circuit 312 and can transmit the inverting gain to the outside of the amplifier. The inverting gain circuit can be a circuit that connects P-type transistors and N-type transistors.

[0090] The inverting gain circuit 313 according to the embodiment can generate multiple outputs. A plurality of P-type transistor and N-type transistor pairs can constitute multiple output terminals of amplifier 310. For example, the multiple output terminals can be terminals for transmitting output signals from amplifier 310.

[0091] Because one or more of the output voltages transmitted from multiple output terminals are selectively fed back or selectively transmitted to the pixel, the output of amplifier 310 can be transmitted more stably.

[0092] The inverting gain circuit 313 may include a first inverting gain circuit and a second inverting gain circuit, wherein the first inverting gain circuit is configured to generate an output voltage by transmitting a voltage received from the folded cascode gain circuit to the first transistor, and the second inverting gain circuit is configured to share a voltage node with the first inverting gain circuit and includes a multiplexer that changes the voltage transmitted to the second transistor.

[0093] The high-impedance drive circuit 314 can distinguish between normal operating signals and high-impedance operating signals and change the output of the data drive circuit under high-impedance conditions.

[0094] The high-impedance drive circuit 314 may also include an additional drive transistor (not shown) configured to receive a normal operation signal. The additional drive transistor (not shown) may be a circuit configuration formed separately from the high-impedance drive circuit 314. Alternatively, the additional drive transistor may be integrated with the high-impedance drive circuit 314.

[0095] An additional drive transistor (not shown) can control the current between the NMOS transistor and the PMOS transistor.

[0096] If needed, the high-impedance drive circuit 314 can be a circuit configuration formed separately from the amplifier 310 and can be controlled by a timing controller (not shown).

[0097] The output selection circuit 315 can individually select the output based on normal operation and high-impedance operation. The output selection circuit 315 may include one or more multiplexers (not shown) and select the output signal.

[0098] The feedback circuit 316 can receive the output selected by the output selection circuit 315 and transmit the output to the input of the amplifier.

[0099] The feedback circuit 316 can selectively receive the output signal of the high-impedance drive circuit 314 and the output signal of the additional drive transistor (not shown).

[0100] If the external OUT MUX function is included within the amplifier as a circuit configuration, the area of ​​the data drive circuitry can be reduced from a circuit layout perspective. Furthermore, communication efficiency can be improved by transmitting control signals from the timing controller T-Con to a single buffer or amplifier without separately transmitting control signals to the OUT MUX and amplifier.

[0101] Figure 6 This is a second example block diagram illustrating an amplifier within a data drive circuit according to an embodiment.

[0102] refer to Figure 6The buffer 410 may include an operational amplifier 411 and a multiplexer 415.

[0103] Operational amplifier 411 can transmit the first output OUT3 and the second output OUT4 to multiplexer 415 through the first output line 412 and the second output line 413, respectively.

[0104] The multiplexer 415 can select the first output OUT3 received through the first output line 412 and the second output OUT4 received through the second output line 413, and can transmit the selected output to the input of the amplifier 411.

[0105] The multiplexer 415 can be connected to the (-) input of the amplifier and can feed the selected input back to the (-) input of the amplifier.

[0106] If the multiplexer 415 is configured to connect to both the first output line 412 and the second output line 413, a high impedance state can be stably maintained compared to a structure where the output is fed back to the amplifier via a single output line from the second output line 413. In the amplifier's feedback processing, the operating speed of the circuitry used for feedback based on the target set value can be rapidly improved.

[0107] Figure 7 This is a diagram used to compare the configurations of a conventional data drive circuit and a data drive circuit according to an embodiment.

[0108] refer to Figure 7 The configurations of the conventional data drive circuit 400A and the data drive circuit 400B according to the embodiment can be compared.

[0109] The conventional data drive circuit 400A transmits the data voltage to the pixels of the panel (not shown) via buffer 410A and OUT MUX 420A.

[0110] The OUT MUX 420A, connected to the output of amplifier 411A within buffer 410A, transmits the output signal to the panel or blocks the output signal via a switch connection.

[0111] The buffer 410A and the OUT MUX 420A are configured as separate circuits, with the OUT MUX 420A connected to the buffer 410A at a timing after the output drive of the amplifier 411A. Therefore, the amplifier 411A operates regardless of whether the OUT MUX 420A is switched.

[0112] Regardless of whether amplifier 411A is used, current exists within the conventional data drive circuit 400A due to the combination of buffer 410A and output OUT MUX420A. Furthermore, increased power consumption arises because quiescent current flows even under high impedance conditions.

[0113] Conversely, the data driving circuit 400B according to the embodiment can control the output of the data voltage through one or more MUXs (not shown) present in the buffer 410B.

[0114] The buffer 410B according to the embodiment may include an amplifier 411B, a multiplexer 415B, etc.

[0115] The output signal transmitted to the panel can be adjusted by a separate MUX (not shown) included within amplifier 411B. When amplifier 411B does not transmit data voltage to the panel, the amount of quiescent current used can be reduced.

[0116] Amplifier 411B can also have a structure in which the output is fed back by multiplexer 415B.

[0117] The multiplexer 415B can select the first output OUT3 and the second output OUT4 of the amplifier 411B, and can output the selected output. The type and number of outputs output by the amplifier 411B are not limited to... Figure 7 Examples.

[0118] Because the second output OUT4 is also fed back compared to the case where only the first output OUT3 of the amplifier 411B is fed back, the stability and efficiency of the buffer 410B can be improved.

[0119] If the circuit configuration associated with the first output OUT3 is damaged or becomes unstable, maintaining the connection with the second output OUT4 improves circuit stability. Conversely, circuit stability is also improved in the opposite case.

[0120] If the first output OUT3 and the second output OUT4 are selected and fed back, or if the output values ​​of the first output OUT3 and the second output OUT4 are averaged and fed back, the processing speed of the circuit can be improved. For example, the speed at which it converges to the target output value can be increased.

[0121] Figure 8 This is a first example circuit diagram illustrating an operational amplifier within a data drive circuit according to an embodiment.

[0122] refer to Figure 8 The operational amplifier 620 may include a folded cascode gain circuit 621, an inverting gain circuit 622, etc.

[0123] The voltage transmitted to the (-) input terminal of the operational amplifier 620 can be either the first output voltage OUT3 transmitted from the first output terminal or the second output voltage OUT4 transmitted from the second output terminal.

[0124] The voltage transmitted to the (-) input terminal of the operational amplifier 620 can be a voltage signal selected by a multiplexer 625 separately arranged outside the operational amplifier.

[0125] The folded cascode gain circuit 621 can be used with Figure 4 and Figure 5 The folded cascode gain circuit is the same as or similar to the folded cascode gain circuit. The folded cascode gain circuit 621 can represent a circuit configuration connecting multiple P-type metal-oxide-semiconductor field-effect transistors (MOSFETs) and multiple N-type MOSFETs. If desired, the P-type MOSFETs and N-type MOSFETs can be defined as P-type transistors and N-type transistors, respectively.

[0126] The folded cascode gain circuit 621 may have one end connected to either a first voltage VDD or a second voltage GND, and may convert the voltage gain and transmit the converted voltage gain to the inverting gain circuit 622. For example, the first voltage VDD may be higher than the second voltage GND. Furthermore, the second voltage GND may represent a voltage with a ground state.

[0127] The inverting gain circuit 622 can represent a circuit configuration connecting P-type transistors and N-type transistors. A single P-type transistor and an N-type transistor can constitute an inverting gain circuit, but the inverting gain circuit 622 can include several pairs of P-type and N-type transistors.

[0128] The inverting gain circuit 622 can be formed by connecting the folded cascode gain circuit 621 to the gate, source, and drain electrodes of each transistor.

[0129] The inverting gain circuit 622 can be connected to the leads that form the first voltage VDD or the second voltage GND, and can provide the source voltage. In this case, the source voltage and drain voltage can be defined with different names depending on the magnitude of the voltage.

[0130] If necessary, the line connected to the source electrode of the P-type transistor can be defined as the first line LN1, the line connected to the gate electrode of the P-type transistor can be defined as the second line LN2, the line connected to the source electrode of the N-type transistor can be defined as the third line LN3, and the line connected to the gate electrode of the N-type transistor can be defined as the fourth line LN4.

[0131] The inverting gain circuit 622 can be electrically connected to one or more nodes within the folded cascode gain circuit 621, and can provide gate voltages to one or more nodes. The node to which the gate electrode of the P-type transistor of the inverting gain circuit 622 and the folded cascode gain circuit 621 are connected can be defined as node 1. The node to which the gate electrode of the N-type transistor of the inverting gain circuit 622 and the folded cascode gain circuit 621 are connected can be defined as node 2.

[0132] The inverting gain circuit 622 can form multiple outputs by connecting multiple transistor groups in parallel with the folded cascode gain circuit 621. In this case, the parallel connection can mean that the nodes to which the folded cascode gain circuit 621 and the inverting gain circuit 622 are connected are common.

[0133] The inverting gain circuit 622 can adjust the output voltage of the amplifier's output terminal using multiplexers 623a and 623b arranged within it, thereby selecting the signal to be transmitted to the transistor connected to the output terminal. In this case, "arranged within the inverting gain circuit 622" can refer to a circuit configuration arranged within a given range of integrated circuits, or it can refer to a circuit configuration arranged on wires that do not form electrical ends.

[0134] For example, multiplexer 623a can be physically or electrically connected between node 1 and node 3. Such an arrangement can be defined as an arrangement within inverting gain circuit 622.

[0135] In another example, the multiplexer 623b can be physically or electrically connected between node 2 and node 4.

[0136] Multiplexers 623a and 623b can be independently controlled by a timing controller (not shown) and can be driven to select the required voltage according to preset criteria. For example, preset criteria can be used to turn off the drive of P-type transistors or N-type transistors or to reduce the output voltage.

[0137] The multiplexers 623a and 623b in the inverting gain circuit 622 can be connected to the transistor in a manner that forms a common node "node 3" and "node 4", respectively.

[0138] The type of voltage regulated can vary depending on the location of the multiplexers 623a and 623b. If the multiplexer is connected to the source electrode of the transistor, it can change the source voltage. If the multiplexer is connected to the drain electrode of the transistor, it can change the drain voltage. If the multiplexer is connected to the gate electrode of the transistor, it can control the gate voltage.

[0139] As the source voltage, drain voltage, or gate voltage changes, the output voltages OUT3 and OUT4 at the output terminals of the operational amplifier formed between the P-type transistor and the N-type transistor can be changed.

[0140] Multiplexer 623a can select either the voltage at node 1 or the first voltage VDD. Multiplexer 623b can select either the voltage at node 2 or the second voltage GND.

[0141] The multiplexer within the inverting gain circuit 622 can be defined as a first multiplexer 623a and a second multiplexer 623b, and the type and number of multiplexers are not limited thereto.

[0142] The first multiplexer 623a can be connected to a P-type transistor. The second multiplexer 623b can be connected to an N-type transistor. The first multiplexer 623a and the second multiplexer 623b can independently control the amplifier's output voltage.

[0143] When the voltages at nodes "Node 3" and "Node 4" of the first multiplexer 623a and the second multiplexer 623b are changed respectively, the current between the P-type transistor and the N-type transistor can be controlled. The operational amplifier's output voltages OUT3 and OUT4 can be output in different ways.

[0144] For example, such as Figure 12 As disclosed, the input voltage of each node can be applied in different ways for high impedance operation.

[0145] Figure 9 This is a second example circuit diagram illustrating an operational amplifier within a data drive circuit according to an embodiment.

[0146] refer to Figure 9 The operational amplifier 720 may include an inverting gain circuit 722, etc.

[0147] The multiplexer 723a arranged between node 1 and node 3 and the multiplexer 723b arranged between node 2 and node 4 can be respectively connected to Figure 8 The multiplexers 623a and 623b are the same.

[0148] According to an embodiment, multiplexers 724a and 724b can be arranged between the respective transistors and the output terminal. In this case, even without changing the gate voltage of the transistor, the output voltage OUT3 of the operational amplifier 720 can be controlled by controlling the source or drain voltage of the transistor. For example, multiplexers 724a and 724b can act as switches, and can reduce the power consumption within the operational amplifier 720 in a simpler way by blocking the voltage or current delivered to the output terminal.

[0149] According to the embodiment, multiplexers 723a and 723b can control the output voltage OUT4, and multiplexers 724a and 724b can control the output voltage OUT3.

[0150] If the other output is in a high-impedance state, then multiplexers 724a and 724b are not required.

[0151] Because the output voltages OUT3 and OUT4 are mainly controlled by multiplexers 723a, 723b and 724a, 724b, and secondarily by multiplexer 725 outside the operational amplifier 720, more efficient high-impedance drive can be achieved.

[0152] Figure 10 This is a third example circuit diagram illustrating an operational amplifier within a data drive circuit according to an embodiment.

[0153] refer to Figure 10 The operational amplifier 820 may include an inverting gain circuit 822, etc.

[0154] The multiplexer 823a arranged between node 1 and node 3 and the multiplexer 823b arranged between node 2 and node 4 can be respectively connected to Figure 8 The multiplexers 623a and 623b are the same.

[0155] In an embodiment, in the inverting gain circuit 822 with a parallel structure, the transistor groups can have a circuit configuration with the same arrangement. Multiplexers 824a and 824b can be connected to the gate electrodes of the P-type transistor and the N-type transistor, respectively, and can control the gate voltage.

[0156] According to the embodiment, multiplexers 823a and 823b can control the output voltage OUT4, and multiplexers 824a and 824b can control the output voltage OUT3.

[0157] Figure 11 This is a first example diagram illustrating the operation type of a data driving circuit according to an embodiment.

[0158] Reference Figure 11 The operation of the inverting gain circuit of the data drive circuit 900 can be divided into normal operation and high impedance operation.

[0159] For example, Figure 11 It can be shown Figures 8 to 10 The voltage changes at nodes 1 and 2 in the circuit diagram are shown, but this disclosure is not limited thereto.

[0160] exist Figure 8 and Figure 9In this case, because the gate electrode of the transistor generating the output voltage OUT3 is not connected to the multiplexer, the voltage transmitted to node 1 and node 2 cannot be freely changed. Figure 10 In this case, because the gate electrode of the transistor is connected to the multiplexer, the voltage transmitted to node 1 and node 2 can be changed through the multiplexer.

[0161] According to a conventional inverting gain circuit with a pair of P-type and N-type transistors, the following situation will not occur: a voltage with a high (H) state in node 1 is applied to the P-type transistor, and a voltage with a low (L) state in node 2 is applied to the N-type transistor.

[0162] The reason is that if a voltage with a high (H) state is applied to a P-type transistor in node 1, the state of the P-type transistor corresponds to the off state, and if a voltage with a low (L) state is applied to an N-type transistor in node 2, the state of the N-type transistor also corresponds to the off state.

[0163] The inverting gain circuit according to the embodiment has a circuit configuration with multiple output terminals, so even if a voltage with a high (H) state in node 1 is applied to the P-type transistor and a voltage with a low (L) state in node 2 is applied to the N-type transistor, it is possible to perform the operation in nodes 3 and 4. Figure 12 High impedance operation.

[0164] If a voltage with a low (L) state in node 1 is applied to the P-type transistor and a voltage with a low (L) state in node 2 is applied to the N-type transistor, the existing drive can be maintained. Similarly, if a voltage with a low (L) state in node 1 is applied to the P-type transistor and a voltage with a high (H) state in node 2 is applied to the N-type transistor, the existing drive can be maintained.

[0165] According to an embodiment, the voltage transmitted to nodes 1 and 2 in a high (H) state can be a first voltage VDD, and according to an embodiment, the voltage transmitted to nodes 1 and 2 in a low (L) state can be a second voltage GND, but this disclosure is not limited thereto.

[0166] The voltage transmitted to node 1 and node 2 can vary depending on the type and state of the voltage transmitted to the input.

[0167] Figure 12 This is a second example diagram illustrating the operation type of the data driving circuit according to an embodiment.

[0168] refer to Figure 12 The operation of the inverting gain circuit of the data drive circuit can be divided into normal operation and high impedance operation.

[0169] The inverting gain circuit according to the embodiment has a circuit configuration with multiple output terminals, so even if a voltage with a high (H) state in node 1 is applied to the P-type transistor and a voltage with a low (L) state in node 2 is applied to the N-type transistor, it is possible to perform the operation in nodes 3 and 4. Figure 12 High impedance operation.

[0170] According to another embodiment, an inverting gain circuit having multiple pairs of P-type and N-type transistors can achieve high impedance based on the state of the voltages transmitted to nodes 3 and 4 in response to individual control signals.

[0171] If a voltage with a high (H) state in node 3 is applied to a P-type transistor and a voltage with a high (H) state in node 4 is applied to an N-type transistor, the quiescent current can be blocked by outputting a ground voltage or a low voltage.

[0172] Unnecessary current can only be blocked by controlling the output of the other pair of transistors when any one pair in the transistor group is operating normally.

[0173] In the inverting gain circuit, the voltage with a high (H) state in node 3 can be applied to the P-type transistor through the multiplexer only when the voltage with a high (H) state in node 1 is applied to the P-type transistor and the voltage with a low (L) state in node 2 is applied to the N-type transistor, and the voltage with a high (H) state in node 4 can be applied to the N-type transistor through the multiplexer.

[0174] Figure 13 This is a diagram used to compare the operation of the data drive circuit and the gate drive circuit.

[0175] refer to Figure 13 The operation of the data drive circuit 1100A and the operation of the gate drive circuit 1100B can be compared.

[0176] In operation 1100A of the data drive circuit, the data drive circuit can receive differential signals of a specific protocol format with a predetermined format. In this case, the differential signals received by the data drive circuit may include information related to clock, output data, and whether high-impedance operation is used.

[0177] In contrast, in the operation 1100B of the gate drive circuit, the required specific signals (such as the gate signal clock GSC and the gate start pulse GSP) are directly input.

[0178] Figure 14 This is a diagram used to describe a high-impedance driving method according to an embodiment.

[0179] refer to Figure 14 The data drive circuit can receive control signals with different information for each time interval.

[0180] For example, the data-driven circuit can receive information for each divided time interval (such as clock training (CT), control packet (CTR), and protocol information).

[0181] The control package (CTR) can include amplifier control signals, high-impedance drive signals, etc.

[0182] The source output enable signal (SOE) can include a high-impedance use signal.

[0183] According to the embodiment, if the high-impedance function is used, since the high-impedance function is executed after the rise timing of the signal, the output of the data drive circuit can be omitted. After the fall timing of the high-impedance signal, the output of the data drive circuit can be generated in the form of a logarithmic function.

[0184] Cross-references to related applications

[0185] This application claims priority to Korean Patent Application 10-2021-0076541, filed on June 14, 2021, the entire contents of which are incorporated herein by reference.

Claims

1. A data-driven integrated circuit, comprising: A digital-to-analog converter, or DAC, is configured to convert digital signals into analog signals; as well as An amplifier is configured to generate a data voltage using an analog signal received via its input, through a folded cascode gain circuit and an inverting gain circuit, and to output the data voltage at its output. The folded cascode gain circuit receives one of multiple output voltages from multiple output terminals of the amplifier as feedback. The inverting gain circuit receives the output signal of the folded cascode gain circuit and modifies the output signal from the multiplexer, which is then transmitted to the transistor connected to the output of the amplifier, via a multiplexer arranged in the inverting gain circuit. The amplifier transmits a first output and a second output to the multiplexer via a first output line and a second output line. The multiplexer selects the first output received via the first output line and the second output received via the second output line. The multiplexer is connected to the -input terminal of the amplifier and feeds a selection input and transmits the selected output to the input terminal of the amplifier. The multiplexer is also connected to the -input terminal of the amplifier and feeds the selection input back to the -input terminal.

2. The data-driven integrated circuit according to claim 1, wherein, The multiplexer in the inverting gain circuit is connected to the transistor in a manner that shares a node with the transistor, and the output signal from the multiplexer controls the source voltage, drain voltage, or gate voltage of the transistor.

3. The data-driven integrated circuit according to claim 1, wherein, The multiplexer changes the gate voltage delivered to the transistor and the output voltage of the amplifier based on a set criterion.

4. The data-driven integrated circuit according to claim 1, wherein, The multiplexer includes a first multiplexer and a second multiplexer, wherein the first multiplexer is connected to a P-type transistor, the second multiplexer is connected to an N-type transistor, and the first multiplexer and the second multiplexer independently control the output voltage of the amplifier.

5. The data-driven integrated circuit according to claim 1, wherein, The inverting gain circuit includes a P-type transistor and an N-type transistor, and changes the output voltage of the amplifier by controlling the current between the P-type transistor and the N-type transistor, wherein a multiplexer connected to the N-type transistor transmits a ground voltage to the N-type transistor.

6. The data-driven integrated circuit according to claim 1, wherein, The inverting gain circuit includes multiple output terminals formed by multiple groups of transistors connected in parallel.

7. The data-driven integrated circuit of claim 1 further includes an external multiplexer configured to select one or more voltages output through the output of the amplifier and to provide a feedback voltage to the input of the amplifier.

8. The data-driven integrated circuit according to claim 1, in, The amplifier includes a first output terminal and a second output terminal. One line connected to the first output terminal transmits the data voltage to the pixel, and the other line transmits the data voltage to an external multiplexer. The line connected to the second output terminal transmits the data voltage to the external multiplexer, and The external multiplexer selects either the data voltage transmitted from the first output terminal or the data voltage transmitted from the second output terminal.

9. An operational amplifier circuit, comprising an operational amplifier, wherein, The operational amplifier includes multiple outputs configured to transmit data voltages, and Each of the plurality of output terminals includes: A P-type transistor having a source electrode connected to a first line and a gate electrode connected to a second line; and An N-type transistor has a source electrode connected to a third line and a gate electrode connected to a fourth line. The node formed by the connection between the P-type transistor and the N-type transistor constitutes the output voltage path. The output voltage of each output terminal is controlled by multiplexers arranged in the second line and the fourth line respectively. The output voltage path formed by the operational amplifier includes a first output voltage path and a second output voltage path. The multiplexer is connected to the - input terminal of the operational amplifier and feeds a selection input and transmits the selected output to the input terminal of the operational amplifier. The multiplexer is also connected to the - input terminal of the operational amplifier and feeds the selection input back to the - input terminal.

10. The operational amplifier circuit according to claim 9, wherein, The multiplexer controls the output voltage at its output terminal by receiving signals used to control the P-type transistor or the N-type transistor.

11. The operational amplifier circuit according to claim 9, wherein, A multiplexer is connected to the P-type transistor or the N-type transistor and selects the voltage delivered to the P-type transistor or the N-type transistor.

12. The operational amplifier circuit according to claim 9, wherein, The operational amplifier includes a first output voltage path and a second output voltage path, wherein the first output voltage path is used to transmit the feedback voltage to the input terminal of the operational amplifier, and the second output voltage path is used to transmit the data voltage to the pixel.

13. The operational amplifier circuit according to claim 9, wherein, One of the plurality of output terminals is electrically connected to an external multiplexer located outside the operational amplifier, and Another output of the plurality of output terminals is electrically connected to the external multiplexer and is also connected to the plurality of pixels to transmit data voltage.

14. An operational amplifier circuit, comprising: A first multiplexer is configured to select the input voltage transmitted to the operational amplifier circuit via one end of its input terminal; A folded cascode gain circuit is connected to the - and + terminals of the input terminal and is configured to change the gain of the input voltage. A first inverting gain circuit is configured to generate an output voltage by transmitting a voltage from the folded cascode gain circuit to a first transistor. as well as The second inverting gain circuit is configured to share a voltage node with the first inverting gain circuit and includes a second multiplexer for changing the voltage delivered to the second transistor. The operational amplifier circuit transmits a first output and a second output to a first multiplexer via a first output line and a second output line. The first multiplexer selects the first output received via the first output line and the second output received via the second output line. The first multiplexer is connected to one end of the input terminal of the operational amplifier circuit, and feeds a selection input and transmits the selected output to the input terminal of the operational amplifier circuit. The first multiplexer is also connected to one end of the input terminal of the operational amplifier circuit and feeds the selection input back to one end of the input terminal.

15. The operational amplifier circuit according to claim 14, wherein, The output voltage of the operational amplifier circuit is controlled by a third multiplexer connected to the first transistor.

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