Display device and driving method thereof

Abstract

A display device and a driving method thereof are provided. The display device includes a display panel including pixels emitting light based on a data voltage, a current limiting part comparing a previous frame load with a pre-set critical load to decide a scale factor, and applying the scale factor to current image data which is input image data of a current frame to generate compensation image data in order to adjust the data voltage, and a data driving part converting the compensation image data into the data voltage to supply it to the display panel.

Description

Technical Field

[0001] This invention relates to a display device and a method for driving the display device. Background Technology

[0002] The display device includes multiple pixels, and the multiple image frames displayed by the multiple pixels can each have a frame load corresponding to the image data of the corresponding frame.

[0003] For example, image frames of bright images can have large frame load values, while image frames of dark images can have small frame load values. Alternatively, the more luminous pixels there are among all pixels, the greater the frame load can be.

[0004] The higher the frame load, the more current can be required per pixel. Conversely, the lower the frame load, the less current can be required per pixel. Summary of the Invention

[0005] One object of the present invention is to provide a display device that adjusts the scale factor of the input image data applicable to the current frame based on the result of comparing the load of the previous frame with the critical load.

[0006] Another object of the present invention is to provide a driving method for the display device.

[0007] However, the purpose of this invention is not limited to the above-described purpose, and various extensions can be made without departing from the spirit and scope of this invention.

[0008] To achieve an objective of the present invention, an embodiment of the present invention relates to a display device that may include: a display panel including pixels that emit light based on data voltage; a current limiting unit that compares the load of a previous frame with a preset critical load to determine a scaling factor, and applies the scaling factor to current image data, which is input image data of the current frame, to generate compensated image data in order to adjust the data voltage; and a data driving unit that converts the compensated image data into the data voltage and provides it to the display panel.

[0009] According to one embodiment, if the load of the previous frame is less than the critical load and the load of the current frame is greater than the critical load, the scaling factor of the current frame may be less than the scaling factor of the previous frame.

[0010] According to one embodiment, the current limiting unit may generate a time weight value based on the previous frame load and frame elapsed time, and the time weight value may also be applied to the scaling factor.

[0011] According to one embodiment, the scaling factor and the time weight value may be greater than 0 and less than 1.

[0012] According to one embodiment, when the frame load of the first frame is below the critical load, and the frame load of the second frame to the kth frame (where k is an integer greater than 2) is greater than the critical load, the magnitude of the data voltage corresponding to the same grayscale gradually decreases from the second frame closer to the kth frame.

[0013] According to one embodiment, the scaling factor applied to the time weight value may gradually decrease as the frame approaches the k-th frame, starting from the second frame.

[0014] According to one embodiment, the current limiting unit may include: a load calculation unit that calculates the load of the previous frame based on the input image data of the previous frame; a signal control unit that compares the load of the previous frame with the critical load and outputs a first control signal based on the comparison result; and a scaling factor adjustment unit that adjusts the scaling factor based on the load of the previous frame and the first control signal.

[0015] According to one embodiment, if the previous frame load is less than the critical load, the signal control unit activates the first control signal, and the scaling factor adjustment unit responds to the first control signal by applying a compensation coefficient to the load scaling factor corresponding to the previous frame load to generate the current scaling factor.

[0016] According to one embodiment, when the load of the previous frame exceeds the critical load, the signal control unit may not activate the first control signal. Alternatively, the scaling factor adjustment unit may output the previous scaling factor from the previous frame as the current scaling factor.

[0017] According to one embodiment, if the load of the previous frame is less than the critical load, the signal control unit may also output a second control signal that is activated during the buffer period including multiple frames.

[0018] According to one embodiment, the current limiting unit may further include: a counting unit that counts frames during the buffer period to output a count value; a weight value generation unit that generates a variable time weight value during the buffer period in response to the second control signal and the count value; and a calculation unit that applies the time weight value to the current scaling factor.

[0019] According to one embodiment, the current limiting unit may further include a reset unit that outputs a count reset signal when both the first control signal and the second control signal are activated. Alternatively, the counting unit may reset the count value in response to the count reset signal.

[0020] According to one embodiment, the weight value generation unit may output a first time weight value corresponding to the first frame during the buffering period based on the count reset signal.

[0021] According to one embodiment, the signal control unit may include: a lookup table including a load scaling factor corresponding to the previous frame load; and a comparison unit that compares the previous frame load with the critical load, thereby outputting the first control signal and a second control signal generated by the control time weight value.

[0022] According to one embodiment, the current limiting unit may apply the current scaling factor, which has the time weight value applied, to the current image data to generate the compensated image data.

[0023] To achieve an objective of the present invention, the driving method of the display device according to embodiments of the present invention may include: step 1, comparing a previous frame load with a preset critical load; step 2, activating a first control signal and a second control signal if the previous frame load is less than the critical load; step 3, applying a compensation coefficient to a load scaling factor corresponding to the previous frame load based on the first control signal to generate a first scaling factor; step 4, generating a time weight value based on the activation of the second control signal; step 5, applying the time weight value generated in step 4 to the first scaling factor to output a current scaling factor; and step 6, applying the current scaling factor output in step 5 to the current image data to provide a data voltage to the display panel.

[0024] According to one embodiment, the second control signal may be activated during a buffer period that includes multiple frames.

[0025] According to one embodiment, the driving method for the display device may further include: step 2', not activating the first control signal when the previous frame load is above the critical load; step 3', generating a time weight value based on the second control signal; step 4', applying the time weight value generated in step 3' to a scaling factor output in the previous frame to output a current scaling factor; and step 5', applying the current scaling factor output in step 4' to the current image data to provide the data voltage to the display panel.

[0026] According to one embodiment, the time weight value generated in step 3′ may be determined by counting frames during the buffering period.

[0027] According to one embodiment, when the load of the previous frame is less than the critical load and the load of the current frame is greater than the critical load, the current scaling factor of the current frame is less than the scaling factor of the previous frame.

[0028] (Invention Effects)

[0029] The display device and driving method of the present invention can adjust the scaling factor applicable to the current image data based solely on the previous frame load without using the comparison of image data (or frame load) of adjacent frames in the frame memory.

[0030] Therefore, the degradation in display quality caused by delaying the generation of a scaling factor by one frame and applying such a scaling factor when comparing image data using a frame memory can be improved in the prior art, and power consumption can be further reduced. In addition, since the scaling factor adjustment is reflected immediately (in real time) based on the previous frame load, overcurrent (current overshoot) can be prevented in the event of a sharp increase in frame load (and current of the display panel).

[0031] Furthermore, based on the time weight values ​​provided over several frames (e.g., during the buffering period), the scaling factor gradually decreases toward the target scaling factor for the current image data, thus improving image distortion caused by current limitations corresponding to abrupt changes in frame load.

[0032] However, the effects of the present invention are not limited to those described above, and various extensions can be made without departing from the spirit and scope of the present invention. Attached Figure Description

[0033] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the present invention.

[0034] Figure 2a and Figure 2b It is shown that includes Figure 1 A circuit diagram of an example of the pixels of a display device.

[0035] Figure 3 It is shown that includes Figure 1 A block diagram of an example of the current limiting section of a display device.

[0036] Figure 4 It is shown that includes Figure 3 A block diagram of an example of the signal control unit of the current limiting section.

[0037] Figure 5 This shows the scaling factor adjusted according to the frame load. Figure 3 A timing diagram of an example of the operation of the current limiting section.

[0038] Figure 6 This shows the scaling factor adjusted according to the frame load. Figure 3 A timing diagram of an example of the operation of the current limiting section.

[0039] Figure 7 This shows the scaling factor adjusted according to the frame load. Figure 3 A timing diagram of an example of the operation of the current limiting section.

[0040] Figure 8 This is a sequence diagram illustrating a driving method for a display device according to an embodiment of the present invention. Detailed Implementation

[0041] Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the accompanying drawings. The same reference numerals are used for the same constituent elements in the drawings, and repeated descriptions of the same constituent elements are omitted.

[0042] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the present invention.

[0043] Reference Figure 1 The display device 1000 may include a display panel 100, a timing control unit 200, a scan drive unit 300, a data drive unit 400, and a current limiting unit 500.

[0044] The display panel 100 may include scan lines S1 to Sn and data lines D1 to Dm, and may include pixels PX (where m and n are integers greater than 1) connected to the scan lines S1 to Sn and the data lines D1 to Dm. Each pixel PX may include a driving transistor and at least one switching transistor. For example, a pixel PX may be connected to the i-th scan line Si (where i is a positive integer less than or equal to n) and the j-th data line Dj (where j is a positive integer less than or equal to m), and may emit light based on a data voltage (data signal).

[0045] The timing control unit 200 can generate a scan control signal SCS and a data control signal DCS corresponding to a synchronization signal supplied from an external source. The scan control signal SCS can be supplied to the scan drive unit 300, and the data control signal DCS can be supplied to the data drive unit 400. Furthermore, the timing control unit 200 can supply compensated image data CDATA, which is rearranged based on input image data IDATA supplied from an external source, to the data drive unit 400. In one embodiment, the timing control unit 200 may include at least a portion of the functions of the current limiting unit 500.

[0046] The current limiting unit 500 can calculate the load of the previous frame using the input image data IDATA of the previous frame. Based on the load of the previous frame, the current limiting unit 500 can control the amount of current flowing to the display panel 100 in the current frame. If the amount of current to the display panel 100 decreases, the brightness of the image in the corresponding frame can be reduced.

[0047] As described above, the current limiting unit 500 performs a current limiting function that reduces the brightness of the image and reduces the current amount, thereby reducing the power consumption of the display device 1000 and reducing or preventing the degradation of the pixel PX.

[0048] In one embodiment, the current limiting unit 500 may adjust the scaling factor of the current image data, which is the input image data IDATA of the current frame, based on the previous frame load. The previous frame load may be the frame load of the previous frame calculated from the previous input image data. For example, the frame load may be numerically quantified from 0% to 100% based on the image data of the corresponding frame. A 0% frame load may be a completely black image, and a 100% frame load may be a full-white image, which is the brightest image of the display device 1000.

[0049] Frame load can be determined based on a representative value calculated from the grayscale values ​​of the corresponding frame and / or the ratio of the illuminated pixels to all pixels in the corresponding frame.

[0050] The compensated image data CDATA of the current frame, with the scaling factor applied, can have values ​​lower than those of the current image data. Therefore, the frame load of the current frame can be reduced, and the current and brightness of the display panel 100 of the current frame can become lower than the expected values ​​corresponding to the current image data.

[0051] The current limiting unit 500 can determine the scaling factor based on a comparison between the previous frame load and a preset critical load. In one embodiment, if the previous frame load is less than the critical load and the current frame load is greater than the critical load, the scaling factor of the current frame can be less than the scaling factor of the previous frame.

[0052] In cases where the frame load increases sharply (e.g., when a bright image changes from black to white), the sudden increase in current may cause a momentary overcurrent exceeding the current corresponding to the frame load. This can result in a transient image quality anomaly. Furthermore, in display devices equipped with overcurrent protection, the overcurrent caused by the increased frame load may activate the protection function, potentially shutting down the image display.

[0053] In existing technologies, to address this overcurrent problem, a comparison between previous and current image data can be used to detect abrupt changes in frame load. However, this requires a frame memory for storing image data or comparing image data from adjacent frames, which leads to other problems such as increased manufacturing costs and increased power consumption.

[0054] The current limiting unit 500 according to embodiments of the present invention can adjust the scaling factor by analyzing only the previous frame load without a frame memory. In the event of a sharp increase in frame load, the current limiting unit 500 can reduce the scaling factor, thereby mitigating rapid changes in brightness and current.

[0055] In one embodiment, the current limiting unit 500 can generate a time weight value based on the previous frame load and the frame elapsed time. The time weight value can also be applied to a scaling factor. Thus, the frame load can gradually decrease towards the target frame load based on the elapsed frame. The scaling factor and the time weight value can be greater than 0 and less than 1.

[0056] For example, if the frame load of the first frame is below the critical load, and the image data of the second to kth frames (where k is an integer greater than 2) have the same frame load greater than the critical load, the magnitude of the data voltage can be gradually reduced corresponding to the second to kth frames respectively.

[0057] The current limiting unit 500 can provide the compensated image data CDATA to the data driving unit 400. For example... Figure 1 As shown, the current limiting unit 500 may be included in the timing control unit 200. However, this is an example, and at least a portion of the functions of the current limiting unit 500 may be provided in the display device 1000 as a physical configuration independent of the timing control unit 200.

[0058] The scan drive unit 300 can receive a scan control signal SCS from the timing control unit 200 and supply scan signals to scan lines S1 to Sn based on the scan control signal SCS. For example, the scan drive unit 300 can sequentially supply scan signals to scan lines S1 to Sn.

[0059] The transistor included in the pixel PX and receiving the scan signal can be turned on in response to the gate conduction level of the scan signal.

[0060] The data driving unit 400 can receive the data control signal DCS and the compensation image data CDATA from the timing control unit 200. It can also directly provide the compensation image data CDATA from the current limiting unit 500. The data driving unit 400 can convert the compensation image data CDATA into an analog data signal. The data driving unit 400 can supply data voltage (data signal) to the data lines D1 to Dm in correspondence with the data control signal DCS. The data voltage can be supplied to the pixel PX selected by the scan signal.

[0061] In addition, Figure 1 The diagram shows n scan lines S1 to Sn, but the invention is not limited thereto. As an example, additional scan lines and / or light emission control lines (not shown) may be additionally formed on the display panel 100.

[0062] In addition, Figure 1 The diagram shows a case where the data driving unit 400 and the timing control unit 200 are configured separately, but at least a portion of the functions of the data driving unit 400, the timing control unit 200, and the current limiting unit 500 can be integrated into an IC (integrated circuit) form.

[0063] Figure 2a and Figure 2b It is shown that includes Figure 1 A circuit diagram of an example of the pixels of a display device.

[0064] For ease of explanation, Figure 2a and Figure 2b The image shows pixels PX1 and PX2 located in the i-th pixel row (or the i-th horizontal line) and connected to the j-th data line Dj (where i and j are positive integers).

[0065] First, refer to Figure 2a Pixel PX1 may include pixel circuit PXC1 and light-emitting element LD. Pixel circuit PXC1 may include transistors T1, T2, T3 and energy storage capacitor Cst.

[0066] exist Figure 2a The circuit described herein uses an N-type transistor as an example. However, those skilled in the art should be able to design a circuit using a P-type transistor by changing the polarity of the voltage applied to the gate terminal. Similarly, those skilled in the art should be able to design a circuit using a combination of P-type and N-type transistors. Transistors can be configured in various forms, such as thin-film transistors (TFTs), field-effect transistors (FETs), and bipolar junction transistors (BJTs).

[0067] The first transistor T1 can be connected between the first power supply line VDDL and the energy storage capacitor Cst. The gate electrode of the first transistor T1 can be connected to the first electrode of the energy storage capacitor Cst. The first transistor T1 can be a driving transistor.

[0068] The second transistor T2 can be connected between the j-th data line Dj and the gate electrode of the first transistor T1 (e.g., the first node N1). The gate electrode of the second transistor T2 can be connected to the i-th scan line Si. The second transistor T2 can be turned on when a scan signal is supplied to the i-th scan line Si, thereby transmitting the data signal (data voltage) from the j-th data line Dj to the first node N1.

[0069] A third transistor T3 can be connected between the j-th lead Rj and an electrode (e.g., the second node N2) of the first transistor T1. In one embodiment, the gate electrode of the third transistor T3 can be connected to the i-th sensing scan line SSi. The third transistor T3 can transmit a sensing current to the j-th lead Rj in response to a sensing scan signal supplied to the i-th sensing scan line SSi. For example, the sensing current can be used to calculate the change in mobility and threshold voltage of the first transistor T1. Mobility and threshold voltage information can be calculated based on the relationship between the sensing current and the voltage used for sensing. In one embodiment, the sensing current can also be converted into a voltage form for use in compensation operations.

[0070] The light-emitting element LD can be connected between one electrode of the first transistor T1 (e.g., the second node N2) and the second power line VSSL. In one embodiment, the light-emitting element LD can be an organic light-emitting diode including an organic light-emitting layer. In other embodiments, the light-emitting element LD can be an inorganic light-emitting element formed of inorganic materials. In other embodiments, the light-emitting element LD can also be a light-emitting element composed of a composite of inorganic and organic materials. In other embodiments, the anode of the light-emitting element LD can be connected to the first power line VDDL, and the cathode of the light-emitting element LD can be connected to the other electrode of the first transistor T1.

[0071] A first power supply voltage can be applied to the first power supply line VDDL, and a second power supply voltage can be applied to the second power supply line VSSL. For example, the first power supply voltage can be greater than the second power supply voltage.

[0072] A drive current, corresponding to the voltage difference between the first and second electrodes of the energy storage capacitor Cst, flows between one electrode and the other of the first transistor T1. As a result, the light-emitting element LD emits light with a brightness corresponding to the data voltage. Since the magnitude of the data voltage is adjusted based on a scaling factor, the drive current of the pixel PX1 can be adjusted.

[0073] In one embodiment, reference is made to Figure 2b Pixel PX2 may include pixel circuit PXC2 and light-emitting element LD. Pixel circuit PXC2 may include transistors T1 to T7 and energy storage capacitor Cst.

[0074] exist Figure 2b The circuit described herein uses a P-type transistor as an example. However, those skilled in the art should be able to design a circuit using an N-type transistor by changing the polarity of the voltage applied to the gate terminal. Similarly, those skilled in the art should be able to design a circuit using a combination of P-type and N-type transistors.

[0075] The first electrode (e.g., anode) of the light-emitting element LD can be connected to the fourth node N4, and the second electrode (e.g., cathode) of the light-emitting element LD can be connected to the second power supply line VSSL. The light-emitting element LD can generate light of a predetermined brightness in accordance with the amount of current (drive current) supplied from the first transistor T1.

[0076] The first transistor T1 (or driving transistor) may be electrically connected between the first power line VDDL and the first electrode of the light-emitting element LD. The first transistor T1 may include a gate electrode connected to the first node N1.

[0077] The second transistor T2 can be connected between the j-th data line (hereinafter referred to as data line) Dj and the second node N2. The gate electrode of the second transistor T2 can be connected to the i-th first scan line (hereinafter referred to as first scan line) S1i. The second transistor T2 can be turned on when a first scan signal is supplied to the first scan line S1i, thereby electrically connecting the data line Dj and the second node N2.

[0078] The third transistor T3 can be connected between the first node N1 and the third node N3. The gate electrode of the third transistor T3 can be connected to the first scan line S1i. The third transistor T3 and the second transistor T2 can be turned on simultaneously.

[0079] A fourth transistor T4 can be connected between the first node N1 and the initialization power line IPL that transmits the voltage of the initialization power supply. The gate electrode of the fourth transistor T4 can be connected to the i-th second scan line (hereinafter referred to as the second scan line) S2i. The fourth transistor T4 can be turned on by a second scan signal supplied to the second scan line S2i. When the fourth transistor T4 is turned on, the voltage of the initialization power supply can be supplied to the first node N1 (i.e., the gate electrode of the first transistor T1). In one embodiment, the timing of the second scan signal supplied to the second scan line S2i can be the same as the timing of the scan signal supplied to the (i-1)-th first scan line (e.g., labeled S1i-1).

[0080] The fifth transistor T5 can be connected between the first power supply line VDDL and the second node N2. The gate electrode of the fifth transistor T5 can be connected to the i-th light-emitting control line (hereinafter referred to as the light-emitting control line) Ei. The sixth transistor T6 can be connected between the third node N3 and the light-emitting element LD (or, the fourth node N4). The gate electrode of the sixth transistor T6 can be connected to the light-emitting control line Ei. The fifth transistor T5 and the sixth transistor T6 can be turned off when a light-emitting control signal is supplied to the light-emitting control line Ei, and turned on under other conditions.

[0081] According to the embodiment, if the fifth transistor T5 and the sixth transistor T6 are turned on, the current flowing through the first transistor T1 can be transferred to the light-emitting element LD, and the light-emitting element LD can emit light.

[0082] The seventh transistor T7 can be connected between the first electrode (i.e., the fourth node N4) of the light-emitting element LD and the initialization power line IPL. The gate electrode of the seventh transistor T7 can be connected to the i-th third scan line (hereinafter referred to as the third scan line) S3i. The seventh transistor T7 can be turned on by a third scan signal supplied to the third scan line S3i, thereby supplying the voltage of the initialization power supply to the first electrode of the light-emitting element LD. In one embodiment, the timing of the third scan signal supplied to the third scan line S3i can be the same as the timing of the scan signals supplied to one of the first scan line S1i, the (i-1)-1 first scan line S1i-1, and the (i+1)-1 first scan line (e.g., labeled S1i+1).

[0083] The energy storage capacitor Cst can be connected between the first power line VDDL and the first node N1.

[0084] In one embodiment, the first scan signal may be supplied after the second scan signal. For example, the second scan signal and the first scan signal may be supplied with a 1-level interval difference.

[0085] In one embodiment, the third scan signal may be supplied simultaneously with the first scan signal. However, this is merely an example; the first scan signal may be supplied after the third scan signal. For example, the interval between the supply of the third scan signal and the first scan signal may be a horizontal period of 1. Alternatively, the third scan signal may be supplied after the first scan signal.

[0086] Figure 2a and Figure 2b The pixels PX1 and PX2 are examples, and the embodiments of the present invention can also be applied to pixels in other circuits.

[0087] Figure 3 It is shown that includes Figure 1 A block diagram of an example of the current limiting section of a display device. Figure 4It is shown that includes Figure 3 A block diagram of an example of the signal control unit of the current limiting section.

[0088] Reference Figure 1 , Figure 3 and Figure 4 The current limiting unit 500 may include a load calculation unit 510, a signal control unit 520, and a scaling factor adjustment unit 530. In one embodiment, the current limiting unit 500 may further include a weight value generation unit 540, a counting unit 550, a calculation unit 560, and a reset unit 570.

[0089] The load calculation unit 510 can calculate the previous frame load P_FL based on the input image data IDATA of the previous frame. In one embodiment, the load calculation unit 510 can analyze the grayscale value information and / or pixel luminance ratio information included in the input image data IDATA to calculate the previous frame load P_FL. Alternatively, the input image data IDATA may also include information related to the frame load. For example, the previous frame load P_FL may include information quantified to a range of 0% to 100%.

[0090] The load calculation unit 510 may include hardware circuitry and / or software algorithms for outputting the previous frame load P_FL based on the input image data IDATA of the previous frame. The load calculation unit 510 may provide the previous frame load P_FL to the signal control unit 520.

[0091] The signal control unit 520 can compare the previous frame load P_FL with the critical load LTH, and output a first control signal LLD1 based on the comparison result. For example, the critical load LTH can be determined as a value selected from the range of 1% to 10%. However, this is just an example, and the value of the critical load LTH is not limited to this.

[0092] In one embodiment, when the previous frame load P_FL is less than the critical load LTH, the signal control unit 520 may activate the first control signal LLD1. The first control signal LLD1 may be provided to the scaling factor adjustment unit 530. When the previous frame load P_FL is greater than the critical load LTH, the signal control unit 520 may not activate the first control signal LLD1.

[0093] In one embodiment, when the previous frame load P_FL is less than the critical load LTH, the signal control unit 520 may also output a second control signal LLD2 that is activated during the buffer period including multiple frames. The second control signal LLD2 is a signal used to output the time weight value WT. The second control signal LLD2 may be provided to the weight value generation unit 540 and the counting unit 550.

[0094] Furthermore, the signal control unit 520 can output the load scaling factor LSF corresponding to the previous frame load P_FL as a first scaling factor SF1. The first scaling factor SF1 can be provided to the scaling factor adjustment unit 530.

[0095] In one embodiment, such as Figure 4 As shown, the signal control unit 520 may include a lookup table 522 and a comparison unit 524.

[0096] Lookup table 522 can output the load scaling factor LSF corresponding to the previous frame load P_FL. For example, lookup table 522 can include scaling factor values ​​corresponding to preset frame loads, and output the scaling factor value corresponding to the previous frame load P_FL among multiple scaling factor values ​​as the load scaling factor LSF. The scaling factor value can be in the range of greater than 0 and less than 1. For example, the larger the previous frame load P_FL, the smaller the scaling factor value can be.

[0097] The comparison unit 524 can compare the previous frame load P_FL with the critical load LTH. Based on the comparison result, the comparison unit 524 can output a first control signal LLD1 and a second control signal LLD2. For example, both the first control signal LLD1 and the second control signal LLD2 can transition from an inactive level to an active level when the previous frame load P_FL is less than the critical load LTH. Therefore, the first control signal LLD1 and the second control signal LLD2 can also be understood as low load detection signals.

[0098] The comparator 524 can be implemented using various known types of comparator circuits and / or comparator algorithms.

[0099] The scaling factor adjustment unit 530 can adjust the scaling factor based on the load scaling factor LSF and the first control signal LLD1. For example, the scaling factor adjustment unit 530 can select one of the load scaling factor LSF (e.g., the first scaling factor SF1) and the previous scaling factor output in the previous frame (e.g., the third scaling factor SF3 of the previous frame) based on the first control signal LLD1 and output it as the current scaling factor (e.g., the second scaling factor SF2).

[0100] In one embodiment, the scaling factor adjustment unit 530 may respond to the first control signal LLD1 (e.g., the activation level of the first control signal LLD1) by adjusting the compensation coefficient (e.g., in...). Figure 5The second scaling factor SF2 (represented as CC) is applied to the load scaling factor LSF to generate the second scaling factor SF2 (e.g., SF2 = LSF × CC). For example, if the arithmetic unit 560 is not working or the time weight value WT is 1, the second scaling factor SF2 can be the same as the third scaling factor SF3. In this case, the second scaling factor SF2 can be applied to the input image data IDATA of the current frame.

[0101] In one embodiment, when the first control signal LLD1 is not activated (i.e., when the previous frame load P_FL is above the critical load LTH), the scaling factor adjustment unit 530 can output the previous scaling factor as the second scaling factor SF2. For example, the scaling factor adjustment unit 530 can receive a third scaling factor SF3 generated corresponding to the previous frame and store it during one frame.

[0102] Alternatively, in one embodiment, when the first control signal LLD1 is not activated (i.e., when the previous frame load P_FL is above the critical load LTH), the scaling factor adjustment unit 530 may output the load scaling factor LSF as the second scaling factor SF2.

[0103] The counting unit 550 can count the frames during the buffer period of the activated second control signal LLD2. According to an embodiment, the counting unit 550 can be a frame counter. For example, the counting unit 550 can count the number of frames in which the second control signal LLD2 is output corresponding to the vertical synchronization signal output in each frame. The buffer period can correspond to the number of consecutive frames utilized until the frame load reaches the target frame load according to the time weight value WT. The output scaling factor can be gradually reduced to the target scaling factor during the buffer period.

[0104] For example, the buffer period can be set to six consecutive frames, and the second control signal LLD2 can be activated during these six frames. However, this is just an example, and the length of the buffer period is not limited to this.

[0105] The counting unit 550 can provide the count value CV to the weight value generation unit 540.

[0106] The weight value generation unit 540 can generate a variable time weight value WT during the buffer period in response to the second control signal LLD2 and the count value CV. For example, the weight value generation unit 540 may include a first time weight value to a sixth time weight value corresponding to the first to sixth frames included in the buffer period, respectively. For example, the first weight value may be output in the first frame, and the sixth weight value may be output in the sixth frame.

[0107] In one embodiment, when the second control signal LLD2 is not activated, the weight value generation unit 540 may not output the time weight value WT, or the time weight value WT may be 1. When the time weight value WT is not output, the calculation unit 560 does not operate.

[0108] For example, the weight value generation unit 540 can be activated in response to the second control signal LLD2 and output a time weight value WT corresponding to the count value CV. The weight value generation unit 540 may include a memory or lookup table storing the values ​​of the time weight values ​​WT.

[0109] The arithmetic unit 560 can apply the time weight value WT to the second scaling factor SF2 to generate a third scaling factor SF3. For example, the arithmetic unit 560 may include a multiplier. The third scaling factor SF3 can be applied to the current image data. The current image data with the third scaling factor SF3 applied can be provided to the data driving unit 400 as compensated image data CDATA.

[0110] The reset unit 570 can output a count reset signal RS based on the first control signal LLD1 and the second control signal LLD2. The signal control unit 520 can provide the first control signal LLD1 and the second control signal LLD2 to the reset unit 570.

[0111] When both the first control signal LLD1 and the second control signal LLD2 are activated, the reset unit 570 can output a count reset signal RS. The count reset signal RS can be provided to the counting unit 550.

[0112] The counting unit 550 can reset the count value CV in response to the count reset signal RS. The weight value generation unit 540 can output a first time weight value corresponding to the first frame during the buffering period based on the count reset signal RS. For example, the counting unit 550 can output the count value CV indicating the first frame during the buffering period in response to the count reset signal RS, and the weight value generation unit 540 can output the first time weight value in response to this.

[0113] As described above, the display device 1000 according to embodiments of the present invention can adjust the scaling factor applicable to the current image data solely based on the previous frame load P_FL without comparing image data (or frame load) of adjacent frames that utilize the frame memory. For example, if the previous frame load P_FL is less than the critical load LTH while the current frame load is greater than the critical load LTH, the scaling factor of the current frame (e.g., the third scaling factor SF3) can become less than the scaling factor of the previous frame.

[0114] This improves the display quality caused by delaying the generation of a scaling factor by one frame and applying such a scaling factor when comparing image data using a frame memory, and further reduces power consumption. Furthermore, since the scaling factor adjustment is immediately reflected based on the previous frame load P_FL, overcurrent (current overshoot) can be prevented in cases where the frame load (and the current of the display panel 100) increases sharply.

[0115] Furthermore, by providing a time weight value WT across several frames (e.g., during the buffer period), the third scaling factor SF3 gradually decreases toward the target scaling factor, thus improving image distortion caused by current limitations corresponding to abrupt changes in frame load.

[0116] Figure 5 This shows the scaling factor adjusted according to the frame load. Figure 3 A timing diagram of an example of the operation of the current limiting section.

[0117] Reference Figure 3 and Figure 5 It can control the first control signal LLD1, the second control signal LLD2, and the scaling factor SF based on the frame load FL of the previous frame.

[0118] In one embodiment, frames F1 to Fk+1 (where k is an integer greater than 5) may each include a vertical blank period (VBP) and an active period (AP). During the vertical blank period (VBP), no data voltage regarding the image may be output, and during the active period (AP), the data voltage of the image for the corresponding frame may be output.

[0119] Figure 5 This illustrates an example of an image changing from a low frame load to a high frame load. The frame load FL of the first frame F1 can be 0% (e.g., a black image). The frame load FL of the first frame F1 can be less than the critical load LTH. The frame load FL of the second frame F2 to the (k+1)th frame Fk+1 can be 100% (e.g., a completely white image). The frame load FL of the second frame F2 to the (k+1)th frame Fk+1 can be greater than the critical load LTH.

[0120] The scaling factor SF applicable to the current frame can be determined based on the frame load FL of the previous frame. For the image data (input image data) of the first frame F1, a predetermined scaling factor SFa can be applied according to the frame load FL of the previous frame.

[0121] Since the frame load FL of the first frame F1 is less than the critical load LTH, the first control signal LLD1 and the second control signal LLD2 can be activated in the second frame F2. In response to the first control signal LLD1, a compensation coefficient CC (e.g., SFa × CC) can be applied to the scaling factor SFa of the first frame F1. The compensation coefficient CC can be greater than 0 and less than or equal to 1.

[0122] The compensation factor CC can be an inherent value set according to the characteristics of the display panel 100. Alternatively, the compensation factor CC can also vary additionally based on the value of the frame load FL of the previous frame.

[0123] In one embodiment, the second control signal LLD2 can be activated within a pre-defined buffer period BP. For example, the buffer period BP can be a time comprising k-1 frames.

[0124] The second frame F2 is the first frame in which the second control signal LLD2 is activated. Therefore, in the second frame F2, the scaling factor SFa of the first frame F1 can also be applied with a first time weight value WT1 (e.g., SFa × CC × WT1). The first time weight value WT1 can be greater than 0 and less than 1. Thus, the scaling factor SF applicable to the image data of the second frame F2 can be less than the scaling factor SFa of the first frame F1.

[0125] The scaling factor SF (SFa×CC×WT1) of the second frame F2 can be determined during the vertical blank period VBP. Therefore, the scaling factor SF (SFa×CC×WT1) of the second frame F2 can be applied to the image data of the second frame F2, and during the active period of the second frame F2, the AP can provide the display panel 100 with a data voltage reflecting the scaling factor SF (SFa*CC*WT1) of the second frame F2.

[0126] Since the frame load FL of the second frame F2 is greater than the critical load LTH, the first control signal LLD1 may not be activated in the third frame F3. Furthermore, the second control signal LLD2 can maintain its active level in the third frame F3. Therefore, the scaling factor adjustment unit 530 can provide the scaling factor SF (e.g., SFa × CC × WT1) output in the second frame F2 to the calculation unit 560 as the second scaling factor SF2. The weight value generation unit 540 can output the second time weight value WT2 in response to the count value CV of the second control signal LLD2, which is counted as 2 (i.e., 2 frames have been counted).

[0127] Therefore, the arithmetic unit 560 applies the second time weight value WT2 to the second scaling factor SF2, thereby applying a new scaling factor SF (e.g., SFa×CC×WT1×WT2) to the image data of the third frame F3.

[0128] Similarly, for the image data of the fourth frame F4, the scaling factor SF (e.g., SFa×CC×WT1×WT2) of the third frame F3 can also be applied to the scaling factor SF (e.g., SFa×CC×WT1×WT2×WT3) of the third time weight value WT3.

[0129] As described above, the scaling factor SF can be gradually decreased until the k-th frame Fk ends during the buffering period BP. In this case, the value of the first grayscale G1 can be gradually decreased, and the data voltage DV corresponding to the first grayscale G1 can also be gradually decreased. As a result, the current of the display panel 100 and the actual frame load can be gradually reduced as the frame passes.

[0130] Then, for the (k+1)th frame Fk+1 after the buffer period BP, a scaling factor SF with the same value as the scaling factor SF of the kth frame Fk can be applied.

[0131] Figure 6 This shows the scaling factor adjusted according to the frame load. Figure 3 A timing diagram of an example of the operation of the current limiting section.

[0132] Reference Figure 3 and Figure 6 During the buffering period, frames with a frame load FL smaller than the critical load LTH can be inserted into the BP path.

[0133] In one embodiment, the reset unit 570 can output a count reset signal RS when both the first control signal LLD1 and the second control signal LLD2 are activated. For example, as Figure 6 As shown, during the vertical blank period VBP of the second frame F2 and the vertical blank period VBP of the fifth frame F5, a count reset signal RS can be output.

[0134] The counting unit 550 can reset the count value CV in response to the count reset signal RS. Based on the reset count value CV, the buffer period BP can be restarted. For example, the frame that outputs the count reset signal RS can be used as the first frame of the buffer period BP to output the first time weight value WT1.

[0135] Operations and references from frame F1 to frame F4 (first frame F1) Figure 5 The operations described are essentially the same, so repeated explanations are omitted. That is, the scale factor SF can be gradually decreased up to the fourth frame (F4).

[0136] In one embodiment, the buffer period BP can be set to substantially comprise six consecutive frames. Thus, if the second control signal LLD2 is activated, it can remain active for six frames unless otherwise specified.

[0137] In one embodiment, the frame load FL of the fourth frame F4 is 10%, which can be less than the critical load LTH. Corresponding to the 10% frame load FL, a lookup table (e.g., in...) is stored... Figure 4 The scaling factor in (represented as 522) can be defined as SFa′.

[0138] Since the frame load FL of the fourth frame (F4) is less than the critical load LTH, the first control signal LLD1 can be activated again in the fifth frame (F5). At this time, since both the first control signal LLD1 and the second control signal LLD2 are active, the count reset signal RS can be output again. This resets the previous buffer period BP, allowing a new buffer period BP to begin. For example, a new buffer period BP can be started over a period of 6 frames, beginning from the fifth frame (F5).

[0139] Furthermore, in the fifth frame F5, in response to the first control signal LLD1, a compensation coefficient CC (e.g., SFa′ × CC) can be applied to the load scaling factor LSF (e.g., SFa′ × CC) corresponding to the frame load FL (e.g., 10%) of the fourth frame F4. Additionally, based on the reset count value CV for the second control signal LLD2, the first time weight value WT1 can be output again. Therefore, in the fifth frame F5, a new scaling factor SF (e.g., SFa′ × CC × WT1) can be generated. For example, the scaling factor SF can be increased in the fifth frame F5 compared to the fourth frame F4.

[0140] Then, the frame load FL of the fifth frame F5 and the sixth frame F6 can again exceed the critical load LTH, and the scaling factor SF can be gradually reduced.

[0141] Figure 7 This shows the scaling factor adjusted according to the frame load. Figure 3 A timing diagram of an example of the operation of the current limiting section.

[0142] Reference Figure 3 and Figure 7 Frames with a frame load FL that is smaller than the critical load LTH can be continuous.

[0143] The frame load FL from the first frame F1 to the fourth frame F4 can be less than the critical load LTH. In addition, the scaling factor SF of the first frame F1 can have a value of SFb.

[0144] From frame F2 in the second frame to frame F5 in the fifth frame, execution and reference can be performed respectively. Figure 5The driving mechanism for the second frame F2 is the same as described. For example, based on the 0% frame load FL of the first frame F1, the first control signal LLD1 and the second control signal LLD2 can be activated in the second frame F2. Thus, during the vertical blank period of the second frame F2, VBP can output a count reset signal RS, and a compensation coefficient CC and a first time weight value WT1 can be applied to the load scaling factor LSF corresponding to the frame load FL of the first frame F1 (i.e., 0% frame load). At this time, the load scaling factor LSF can be the same as or different from SFb, depending on the frame load FL prior to the first frame F1.

[0145] Similarly, based on the 0% frame load FL of the second frame F2, the activation levels of the first control signal LLD1 and the second control signal LLD2 can be maintained in the third frame F3. Therefore, during the vertical blank period of the third frame F3, VBP can output a count reset signal RS, and a compensation coefficient CC and a first time weight value WT1 can be applied to the load scaling factor LSF corresponding to the frame load FL of the second frame F2 (i.e., 0% frame load).

[0146] like Figure 7 As shown, the frame loads FL, which are lower than the critical load LTH, are the same for the first frame F1 to the fourth frame F4. Therefore, the scaling factor SF for the second frame F2 to the fifth frame F5 can be the same.

[0147] In the fifth frame (F5), a frame load FL that is 100% larger than the critical load LTH can be output. Therefore, in the sixth frame (F6), the first control signal LLD1 is not activated, and the value of the scaling factor SF in the fifth frame (F5), which also applies the second time weight value WT2, can be output as the scaling factor SF in the sixth frame (F6). During the buffer period, BP can be counted starting from the fifth frame (F5).

[0148] Therefore, when continuously outputting low-load images, the scaling factor SF will not decrease to an excessively low value, and can be maintained at a certain level based on the frame load FL of the previous frame.

[0149] Figure 8 This is a sequence diagram illustrating a driving method for a display device according to an embodiment of the present invention.

[0150] Reference Figure 8 The driving method of the display device can calculate the current scaling factor applicable to the current image data based on the result of comparing the previous frame load with the critical load (S100).

[0151] In one embodiment, if the load of the previous frame is less than the critical load (S100: Yes), the first control signal and the second control signal can be activated (S210). Based on the first control signal, a compensation coefficient can be applied to the load scaling factor corresponding to the load of the previous frame to generate a first scaling factor (S220).

[0152] Furthermore, a time weight value can be generated based on the activation of the second control signal (S230). The second control signal can be activated during a buffer period comprising multiple consecutive frames. The time weight value is variable during the buffer period. For example, a time weight value corresponding to the result of counting frames during the buffer period can be determined.

[0153] Then, a time weight value can be applied to the first scaling factor to output the current scaling factor (S240). In addition, the current scaling factor can be applied to the current image data to generate compensated image data, and a data voltage corresponding to the compensated image data can be provided to the display panel (S250).

[0154] In one embodiment, when the load of a previous frame is less than the critical load and the load of the current frame is greater than the critical load (e.g., when the load of a frame increases sharply), the scaling factor of the current frame may become less than the scaling factor of the previous frame.

[0155] In one embodiment, the first control signal may not be activated if the previous frame load is above the critical load (S100: No). Furthermore, a time weight value may be generated based on the second control signal and the frame count value during the buffering period (S320).

[0156] The current scaling factor can be output by applying a time weight value to the scaling factor output in the previous frame (S330). Here, the scaling factor output in the previous frame has a different meaning than the load scaling factor described earlier. That is, the load scaling factor may be independent of the scaling factor output in the previous frame and can be determined solely based on the load of the previous frame.

[0157] Then, the current scaling factor can be applied to the current image data to generate compensated image data, and a data voltage corresponding to the compensated image data can be provided to the display panel (S340).

[0158] However, since it has been referenced Figures 3 to 7 The driving method of the display device has been described in detail, so repeated descriptions are omitted.

[0159] As described above, the display device and driving method of the present invention can adjust the scaling factor applicable to the current image data for current limiting based solely on the previous frame load without comparing the image data (or frame load) of adjacent frames in the frame memory.

[0160] This improves the display quality caused by delaying the generation of a scaling factor by one frame and applying it when comparing image data using a frame memory, and further reduces power consumption. Furthermore, since the scaling factor adjustment is reflected immediately (in real-time) based on the previous frame load, overcurrent (current overshoot) can be prevented in cases where the frame load (and the current to the display panel) increases sharply.

[0161] Furthermore, based on the time weight values ​​provided over several frames (e.g., during the buffering period), the scaling factor gradually decreases toward the target scaling factor for the current image data, thus improving image distortion caused by current limitations corresponding to abrupt changes in frame load.

[0162] The above description refers to embodiments of the present invention. However, those skilled in the art should understand that various modifications and alterations can be made to the present invention without departing from the spirit and scope of the present invention.

Claims

1. A display device, comprising: The display panel includes pixels that emit light based on data voltage; The current limiting unit compares the load of the previous frame with a preset critical load to determine a scaling factor, and in order to adjust the data voltage, applies the scaling factor to the current image data, which is the input image data of the current frame, to generate compensated image data. as well as The data driving unit converts the compensated image data into the data voltage and provides it to the display panel. Wherein, the scaling factor is greater than 0 and less than 1. If the load of a previous frame is less than the critical load and the load of a current frame is greater than the critical load, the scaling factor of the current frame is less than the scaling factor of the previous frame.

2. The display device according to claim 1, wherein, The current limiting unit generates a time weight value based on the previous frame load and frame elapsed time, and also applies the time weight value to the scaling factor.

3. The display device according to claim 2, wherein, The time weight value is greater than 0 and less than 1.

4. The display device according to claim 2, wherein, When the frame load of the first frame is below the critical load, and the frame load of the second to kth frames is greater than the critical load, the magnitude of the data voltage corresponding to the same grayscale gradually decreases from the second frame to the kth frame, where k is an integer greater than 2.

5. The display device according to claim 4, wherein, Starting from the second frame, the scaling factor applied to the k-th frame gradually decreases.

6. The display device according to claim 1, wherein, The current limiting unit includes: The load calculation unit calculates the load of the previous frame based on the input image data of the previous frame; The signal control unit compares the previous frame load with the critical load and outputs a first control signal based on the comparison result; and The scaling factor adjustment unit adjusts the scaling factor based on the previous frame load and the first control signal.

7. The display device according to claim 6, wherein, If the load of the previous frame is less than the critical load, the signal control unit activates the first control signal. The scaling factor adjustment unit responds to the first control signal by applying a compensation coefficient to the load scaling factor corresponding to the previous frame load to generate the current scaling factor.

8. The display device according to claim 7, wherein, When the load of the previous frame exceeds the critical load, the signal control unit does not activate the first control signal. The scaling factor adjustment unit outputs the previous scaling factor output in the previous frame as the current scaling factor.

9. The display device according to claim 8, wherein, If the load of the previous frame is less than the critical load, the signal control unit also outputs a second control signal that is activated during the buffer period including multiple frames.

10. The display device according to claim 9, wherein, The current limiting unit further includes: The counting unit counts the frames during the buffering period and outputs a count value; The weight value generation unit, in response to the second control signal and the count value, generates a variable time weight value during the buffer period; and The calculation unit applies the time weight value to the current scaling factor.

11. The display device according to claim 10, wherein, The current limiting unit further includes a reset unit that outputs a count reset signal when both the first control signal and the second control signal are activated. The counting unit resets the count value in response to the count reset signal.

12. The display device according to claim 11, wherein, The weight value generation unit outputs a first time weight value corresponding to the first frame during the buffering period based on the count reset signal.

13. The display device according to claim 6, wherein, The signal control unit includes: A lookup table, including a load scaling factor corresponding to the load of the previous frame; and The comparison unit compares the previous frame load with the critical load, thereby outputting the first control signal and a second control signal generated by the control time weight value.

14. The display device according to claim 10, wherein, The current limiting unit applies the current scaling factor, which has the time weight value applied, to the current image data to generate the compensated image data.

15. A method for driving a display device, comprising: Step 1: Compare the load of the previous frame with the preset threshold load; Step 2: If the load of the previous frame is less than the critical load, activate the first control signal and the second control signal. Step 3: Based on the first control signal, apply a compensation coefficient to the load scaling factor corresponding to the previous frame load to generate a first scaling factor; Step 4: Generate time weight values ​​based on the activation of the second control signal; Step 5: Apply the time weight value generated in step 4 to the first scaling factor to output the current scaling factor; as well as Step 6: Apply the current scaling factor output in step 5 to the current image data to provide data voltage to the display panel. in, Wherein, the scaling factor is greater than 0 and less than 1. If the load of the previous frame is less than the critical load and the load of the current frame is greater than the critical load, the current scaling factor of the current frame is less than the scaling factor of the previous frame.

16. The driving method for a display device according to claim 15, wherein, The second control signal is activated during a buffer period that includes multiple frames.

17. The driving method for the display device according to claim 16, further comprising: Step 2 The first control signal is not activated when the load of the previous frame is above the critical load. Step 3 A time weight value is generated based on the second control signal; Step 4 In step 3 The time weight value generated in the process is used to output the current scaling factor based on the scaling factor output in the previous frame; as well as Step 5 The current image data is applicable to step 4. The current scaling factor output from the output is used to provide the data voltage to the display panel.

18. The driving method for a display device according to claim 17, wherein, Counting the frames during the buffering period to determine in step 3 The time weight value generated in the process.

Images