A circuit and memory for improving the stability of non-volatile memristor type memory.

Abstract

This invention discloses a circuit and a memory for improving the stability of non-volatile memristor-type memory, relating to the field of memory technology. The circuit includes a control module, the input terminal of which is connected to a power supply V. Forming The output terminal is connected to the BL terminal of the memory to power the memristors in each branch of the BL terminal. The memristors are connected to the SL terminal of the memory via a protection switch. The SL terminal of the memory is connected to the control terminal of the control module. When the control terminal of the control module detects that the electrical signal at the SL terminal of the memory is at a first preset threshold, it increases the supply voltage at the BL terminal of the memory. When the control terminal of the control module detects that the electrical signal at the SL terminal of the memory is at a second preset threshold, it decreases the supply voltage at the BL terminal of the memory. The first preset threshold is less than the second preset threshold. This application can solve the technical problems of high inrush current and poor scalability in traditional memory.

Description

Technical Field

[0001] This invention relates to the field of memory technology, and in particular to a circuit and memory for improving the stability of non-volatile memristor type memory. Background Technology

[0002] Currently, among the memristor-type non-volatile memories on the market, some memories do not have corresponding protection circuits, which leads to a large voltage value that the memory can withstand, greatly affecting the stability of the memory; some memories have corresponding protection circuits, but the components in the circuits have poor miniaturization, making it difficult to further improve the integration density with the advancement of technology; some memories have corresponding protection circuits and have better miniaturization and higher integration density, but the surge current amplitude is very high and the time required for stabilization is also relatively long, so there are still some hidden dangers to the stability of the memory. Summary of the Invention

[0003] The purpose of this invention is to provide a circuit and memory that improve the stability of non-volatile memristor type memory, so as to solve the technical problems of high surge current and poor scalability in the prior art.

[0004] To solve the above-mentioned technical problems, the present invention adopts the following technical solution:

[0005] A first aspect of this invention provides a circuit for improving the stability of a non-volatile memristor-type memory, the circuit comprising: a control module, wherein the input terminal of the control module is connected to a power supply V. Forming The output terminal is connected to the BL terminal of the memory and is used to supply power to each branch memristor on the BL terminal of the memory. The memristor is connected to the SL terminal of the memory through a protection switch. The SL terminal of the memory is connected to the control terminal of the control module. When the control terminal of the control module detects that the electrical signal at the SL terminal of the memory is a first preset threshold, it increases the supply voltage at the BL terminal of the memory. When the control terminal of the control module detects that the electrical signal at the SL terminal of the memory is a second preset threshold, it decreases the supply voltage at the BL terminal of the memory. The first preset threshold is less than the second preset threshold.

[0006] In some embodiments, the circuit further includes a data selector disposed between the control module and the memory. One input terminal of the data selector is connected to the output terminal of the control module, and the other output terminal is connected to the control terminal of the control module. The other output terminal of the data selector is connected to the BL terminal of the memory, and the other input terminal is connected to the SL terminal of the memory. The output terminal of the control module supplies power to the BL terminal of the memory through the data selector, and the SL terminal of the memory outputs an electrical signal to the control terminal of the control module through the data selector.

[0007] In some embodiments, the control module includes a first switch, the input terminal of which is connected to a power supply V. Forming The output terminal is connected to the input terminal on one side of the data selector, and the control terminal is connected to the output terminal on one side of the data selector.

[0008] In some embodiments, the control module further includes a second switch, which is preset to a set opening degree and is connected to the control terminal of the first switch and the output terminal on the data selector side.

[0009] In some embodiments, the control module further includes a third switch, the control terminal and the input terminal of the third switch being interconnected and connected to the control terminal of the second switch and the reference power supply. The output terminals of the second switch and the third switch are grounded, and the input terminal of the second switch is connected to the control terminal of the first switch and the output terminal on one side of the data selector.

[0010] In some embodiments, the first switch is a PMOS transistor, and the source of the PMOS transistor is connected to the power supply V. Forming The drain of the PMOS transistor is connected to the input terminal on one side of the data selector, and the gate of the PMOS transistor is connected to the second switch and the output terminal on one side of the data selector. When the gate of the PMOS transistor detects an electrical signal of a first preset threshold, the output of the drain is increased; when the gate of the PMOS transistor detects an electrical signal of a second preset threshold, the output of the drain is decreased.

[0011] In some embodiments, the second switch is a first NMOS transistor, the drain of the first NMOS transistor is connected to the gate of the PMOS transistor and the output terminal on one side of the data selector, the source of the first NMOS transistor is grounded, and the gate of the first NMOS transistor is given a voltage according to the set opening degree so that the first NMOS transistor reaches the set opening degree.

[0012] In some embodiments, the second switch is a variable resistor, which is preset to a set opening degree. The input terminal of the variable resistor is connected to the gate of the PMOS transistor and the output terminal on one side of the data selector, and the output terminal of the variable resistor is grounded.

[0013] In some embodiments, the third switch is a second NMOS transistor, the gate of which is connected to the gate of the first NMOS transistor, the drain of the second NMOS transistor, and a reference power supply, respectively, and the source of the second NMOS transistor is grounded.

[0014] A second aspect of the present invention provides a non-volatile memristor-type memory, the memory including the circuit described above.

[0015] According to an embodiment of the present invention, a circuit and memory for improving the stability of a non-volatile memristor type memory have at least the following beneficial effects: First, the inrush current is very small throughout the entire operation process and will not affect the stability of the memory; second, the MOS transistor used in this application is a core device, and the miniaturization of core devices is much greater than that of I / O devices, which greatly improves the overall integration density of the system.

[0016] It should be understood that the above general description and the following detailed description are merely exemplary and do not limit this disclosure. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of a memory array circuit according to an embodiment;

[0019] Figure 2 The voltage and current distribution curves over time according to the embodiment;

[0020] Figure 3 This is a comparison diagram of the area of ​​the core device array and the IO device array according to an embodiment. Detailed Implementation

[0021] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] In the description of this invention, it should be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0023] The terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0024] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "connection," "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0025] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that the description of this disclosure will be more complete and fully convey the concept of the exemplary embodiments to those skilled in the art. The drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted.

[0026] The technical solutions of the embodiments of this application are briefly described below:

[0027] This application provides a circuit for improving the stability of non-volatile memristor type memory, such as... Figure 1 As shown, Figure 1 A schematic diagram 100 of a memory array circuit is shown. The circuit includes a first MOSFET Q1, a second MOSFET Q2, and a third MOSFET Q3. The first MOSFET Q1 is a PMOS transistor, while the second MOSFET Q2 and the third MOSFET Q3 are NMOS transistors. The source of the first MOSFET Q1 is connected to the power supply V. Forming The drain is connected to the BL terminal of the memory via a data selector. The BL terminal of the memory is connected to the SL terminal of the memory via a memristor (RRAM) and an internal protection switch. The SL terminal of the memory is connected to the gate of the first MOSFET Q1 and the drain of the second MOSFET Q2 via a data selector. The source of the second MOSFET Q2 is grounded. The gate of the second MOSFET Q2 is connected to the gate, drain, and reference power supply of the third MOSFET Q3. The source of the third MOSFET Q3 is grounded. The reference power supply, the second MOSFET Q2, and the third MOSFET Q3 form a current mirror. A monitoring circuit can be used with the current mirror to implement the write termination process.

[0028] Its working principle is as follows:

[0029] Initially, the voltage at point Q is 0, and the first MOSFET Q1 is fully turned on.

[0030] Before successful formation, the resistance of the memristor RRAM was very high, and the loop current I... cell The voltage drop across each MOSFET is very small;

[0031] After successful forming, the resistance of the memristor RRAM decreases, and the loop current I... cell The resistance of the first MOSFET Q1 gradually increases, thus gradually raising the voltage at point Q. This reduces the turn-on degree of Q1, meaning the resistance of Q1 increases, the voltage drop increases, and the power supply V... Forming Most of the voltage is distributed across the first MOSFET Q1, with a smaller portion distributed across the subsequent circuitry, thus ensuring the voltage across each I in the subsequent stages. cell The voltage on the segment is very small, ensuring its stability; furthermore, because the parasitic capacitance of the first MOSFET Q1 is very small, the peak value of the surge current will also be smaller.

[0032] like Figure 2 As shown, Figure 2 The voltage and current distribution curves over time are shown in Figure 200. Curve 1 in the figure represents the voltage V. RRAM Curve 2 represents the loop current I of the memristor RRAM segment. cell Curve 3 represents voltage V SEL Before the formation is successful, the resistance of the memristor RRAM is very large, and the forming voltage drops almost entirely across the memristor RRAM, with the loop current close to 0.

[0033] After successful forming, the resistance of the memristor RRAM decreases, and the forming voltage, after stabilizing, will mostly drop across the first MOSFET Q1, with voltage V... SEL and voltage V RRAM The current is relatively small, and eventually stabilizes at around the externally set Iref; moreover, throughout the entire process, I... cell The surge current is very small and will not affect the stability of the unit.

[0034] The following is in conjunction with the appendix to this instruction manual. Figures 1 to 3 The preferred embodiments of this disclosure will be further described in detail below.

[0035] According to some embodiments, this application provides a circuit for improving the stability of non-volatile memristor type memory, the circuit comprising:

[0036] The control module, whose input terminal is connected to the power supply V Forming The output terminal is connected to the BL terminal of the memory and is used to supply power to each branch memristor on the BL terminal of the memory. The memristor is connected to the SL terminal of the memory through a protection switch. The SL terminal of the memory is connected to the control terminal of the control module.

[0037] When the control terminal of the control module detects that the electrical signal at the SL terminal of the memory is at a first preset threshold, the power supply voltage at the BL terminal of the memory is increased. When the control terminal of the control module detects that the electrical signal at the SL terminal of the memory is at a second preset threshold, the power supply voltage at the BL terminal of the memory is decreased. The first preset threshold is less than the second preset threshold.

[0038] Based on the above embodiments, when the control terminal of the control module detects a low electrical signal, i.e., when the electrical signal at the SL terminal of the memory is at a first preset threshold, the supply voltage at the BL terminal of the memory is increased; when the control terminal of the control module detects a high electrical signal, i.e., when the electrical signal at the SL terminal of the memory is at a second preset threshold, the supply voltage at the BL terminal of the memory is decreased. This prevents the circuit voltage from being too high or too low, ensuring the stability of the entire circuit operation.

[0039] According to some embodiments, the circuit further includes a data selector disposed between the control module and the memory. One input terminal of the data selector is connected to the output terminal of the control module, and the other output terminal of the data selector is connected to the control terminal of the control module. The other output terminal of the data selector is connected to the BL terminal of the memory, and the other input terminal of the data selector is connected to the SL terminal of the memory. The output terminal of the control module supplies power to the BL terminal of the memory through the data selector, and the SL terminal of the memory outputs an electrical signal to the control terminal of the control module through the data selector.

[0040] Based on the above embodiments, the data selector adopts a MUX data selector for signal switching. Its advantages include: fast switching speed, no jitter, low power consumption, small size, reliable operation, and easy control.

[0041] According to some embodiments, the control module includes a first switch, the input terminal of which is connected to a power supply V. Forming The output terminal is connected to the input terminal on one side of the data selector, and the control terminal is connected to the output terminal on one side of the data selector.

[0042] Based on the above embodiments, when the control terminal of the first switch detects through the data selector that the electrical signal at the SL terminal of the memory is a first preset threshold, the output terminal of the first switch increases the output, the resistance of the first switch decreases, the voltage drop across the first switch decreases, and the voltage at the BL terminal of the memory increases; when the control terminal of the first switch detects through the data selector that the electrical signal at the SL terminal of the memory is a second preset threshold, the output terminal of the first switch decreases the output, the resistance of the first switch increases, the voltage drop across the first switch increases, and the voltage at the BL terminal of the memory decreases.

[0043] According to some embodiments, the control module further includes a second switch, which is preset to a set opening degree, and the second switch is connected to the control terminal of the first switch and the output terminal on the data selector side.

[0044] Based on the above embodiments, when the control terminal of the first switch is at the second preset threshold and the output needs to be reduced, the control terminal of the first switch detects that the electrical signal is at the second preset threshold and reduces the output of the control terminal so that the electrical signal at the control terminal of the first switch is lower than the second preset threshold and returns to the normal value, where the first preset threshold < normal value < second preset threshold. At this time, although the output of the first switch is reduced, the internal energy storage element will discharge, causing the electrical signal at the control terminal of the first switch to remain at the second preset threshold and unable to quickly return to the normal value. Therefore, it is necessary to add a discharge circuit element and pre-set the second switch to a set opening degree so that when the internal energy storage element discharges, the energy flows to the location through the second switch, reducing the delay caused by the energy storage element. In other embodiments, the second switch can also be configured as a resistor for a discharge circuit, and the resistance value of the discharge circuit is determined according to the size of the set opening degree.

[0045] The opening degree, the first preset threshold, and the second preset threshold can be set according to actual needs.

[0046] According to some embodiments, the control module further includes a third switch, the control terminal and input terminal of the third switch are interconnected, and the control terminal of the second switch and the reference power supply are connected. The output terminals of the second switch and the third switch are grounded, and the input terminal of the second switch is connected to the control terminal of the first switch and the output terminal on one side of the data selector.

[0047] Based on the above embodiments, the reference power supply, the second switch, and the third switch form a current mirror, which facilitates the implementation of the write termination process when combined with monitoring circuits, and also facilitates circuit initialization.

[0048] According to some embodiments, the first switch is a PMOS transistor, i.e. Figure 1 The first MOS transistor Q1 shown has its source connected to the power supply V. Forming The drain of the PMOS transistor is connected to the input terminal on one side of the data selector, and the gate of the PMOS transistor is connected to the second switch and the output terminal on one side of the data selector. When the gate of the PMOS transistor detects an electrical signal of the first preset threshold, the output of the drain is increased; when the gate of the PMOS transistor detects an electrical signal of the second preset threshold, the output of the drain is decreased.

[0049] Based on the above embodiments, the first switch is not limited to a PMOS transistor, but can also be a PNP transistor or other components that have amplification function or can adjust the opening degree. In this application, it is preferred to set the first switch as a PMOS transistor, but the selection of a PMOS transistor is not a limitation of this application.

[0050] According to some embodiments, the second switch employs a first NMOS transistor, i.e. Figure 1The second MOS transistor Q2 shown has its drain connected to the gate of the PMOS transistor and the output terminal on one side of the data selector. The source of the first NMOS transistor is grounded. The gate of the first NMOS transistor is given a voltage according to the set opening degree so that the first NMOS transistor reaches the set opening degree.

[0051] Based on the above embodiments, the second switch can also be a variable resistor, which is preset to a set opening degree. The input terminal of the variable resistor is connected to the gate of the PMOS transistor and the output terminal on one side of the data selector, and the output terminal of the variable resistor is grounded.

[0052] Furthermore, the second switch is not limited to NMOS transistors and variable resistors. The second switch can also be a transistor or other components that have amplification function or can adjust the opening degree. In this application, it is preferred to set the second switch as an NMOS transistor, but the selection of an NMOS transistor is not a limitation of this application.

[0053] According to some embodiments, the third switch employs a second NMOS transistor, i.e., as shown below. Figure 1 The third MOS transistor Q3 shown is connected to the gate of the first NMOS transistor, the drain of the second NMOS transistor, and the reference power supply. The source of the second NMOS transistor is grounded.

[0054] Based on the above embodiments, when the second switch is an NMOS transistor, the third switch also uses an NMOS transistor. The device selection of the second and third switches needs to be the same to facilitate the formation of a current mirror, to facilitate the implementation of the write termination process with monitoring circuits, and to facilitate circuit initialization.

[0055] According to other embodiments, this application provides a non-volatile memristor-type memory, which includes the circuitry described above. This ensures minimal inrush current throughout operation, preventing impact on memory stability. Furthermore, the MOSFETs used are core devices, which offer significantly greater miniaturization than I / O devices, greatly improving the overall system integration density. Figure 3 As shown, Figure 3 Figure 300 shows an area comparison between core device arrays and I / O device arrays. As process nodes advance, the miniaturization of core devices is far greater than that of I / O devices. The figure shows that when the process node drops below 40nm, it can result in nearly 50% area savings, significantly improving the overall system integration density. In other words, using core devices in or around the memory can increase the overall memory integration density and make it easier to integrate.

[0056] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0057] Although this disclosure has been described with reference to several typical embodiments, it should be understood that the terminology used is descriptive and exemplary, and not restrictive. Because this disclosure can be embodied in many forms without departing from the spirit or essence of the invention, it should be understood that the above embodiments are not limited to any of the foregoing details, but should be interpreted broadly within the spirit and scope defined by the appended claims. Therefore, all variations and modifications falling within the scope of the claims or their equivalents should be covered by the appended claims.

Claims

1. A circuit for improving the stability of non-volatile memristor-type memory, characterized in that, The circuit includes: The control module, whose input terminal is connected to the power supply V Forming The output terminal is connected to the BL terminal of the memory and is used to supply power to each branch memristor on the BL terminal of the memory. The memristor is connected to the SL terminal of the memory through a protection switch. The SL terminal of the memory is connected to the control terminal of the control module. When the control terminal of the control module detects that the electrical signal at the SL terminal of the memory is at a first preset threshold, the power supply voltage at the BL terminal of the memory is increased; when the control terminal of the control module detects that the electrical signal at the SL terminal of the memory is at a second preset threshold, the power supply voltage at the BL terminal of the memory is decreased. The first preset threshold is less than the second preset threshold. The circuit also includes a data selector, which is disposed between the control module and the memory. One input terminal of the data selector is connected to the output terminal of the control module, and the other output terminal is connected to the control terminal of the control module. The other output terminal of the data selector is connected to the BL terminal of the memory, and the other input terminal is connected to the SL terminal of the memory. The output terminal of the control module supplies power to the BL terminal of the memory through the data selector, and the SL terminal of the memory outputs an electrical signal to the control terminal of the control module through the data selector.

2. The circuit according to claim 1, characterized in that, The control module includes a first switch, the input terminal of which is connected to a power supply V. Forming The output terminal is connected to the input terminal on one side of the data selector, and the control terminal is connected to the output terminal on one side of the data selector.

3. The circuit according to claim 2, characterized in that, The control module also includes a second switch, which is preset to a set opening degree. The second switch is connected to the control terminal of the first switch and the output terminal on the data selector side.

4. The circuit according to claim 3, characterized in that, The control module also includes a third switch, the control terminal and input terminal of the third switch are connected to each other, and the control terminal of the second switch and the reference power supply are connected. The output terminals of the second switch and the third switch are grounded. The input terminal of the second switch is connected to the control terminal of the first switch and the output terminal on one side of the data selector.

5. The circuit according to claim 4, characterized in that, The first switch uses a PMOS transistor, and the source of the PMOS transistor is connected to the power supply V. Forming The drain of the PMOS transistor is connected to the input terminal on one side of the data selector, and the gate of the PMOS transistor is connected to the second switch and the output terminal on one side of the data selector. When the gate of the PMOS transistor detects an electrical signal of the first preset threshold, the output of the drain is increased; when the gate of the PMOS transistor detects an electrical signal of the second preset threshold, the output of the drain is decreased.

6. The circuit according to claim 5, characterized in that, The second switch uses a first NMOS transistor. The drain of the first NMOS transistor is connected to the gate of the PMOS transistor and the output terminal on one side of the data selector. The source of the first NMOS transistor is grounded. The gate of the first NMOS transistor is given a voltage according to the set opening degree so that the first NMOS transistor reaches the set opening degree.

7. The circuit according to claim 5, characterized in that, The second switch uses a variable resistor, which is preset to a set opening degree. The input terminal of the variable resistor is connected to the gate of the PMOS transistor and the output terminal on one side of the data selector, and the output terminal of the variable resistor is grounded.

8. The circuit according to claim 6, characterized in that, The third switch uses a second NMOS transistor. The gate of the second NMOS transistor is connected to the gate of the first NMOS transistor, the drain of the second NMOS transistor, and the reference power supply, respectively. The source of the second NMOS transistor is grounded.

9. A non-volatile memristor-type memory, characterized in that, The memory includes the circuitry as described in any one of claims 1 to 8.

Images