Semiconductor memory device and method of writing for the same

Abstract

The present application provides a semiconductor memory device capable of achieving low power consumption and high integration, and a write method thereof. A nonvolatile semiconductor memory of the present application includes an array of memory cells that forms a NOR-type array having a NOR-type flash memory structure and a resistance change-type array having a resistance change-type memory structure on a substrate. A read / write control section charges a selected global bit line in the case of a set write to a selected memory cell of the resistance change-type array, and thereafter applies a set write voltage to the selected memory cell using a voltage charged to the selected global bit line.

Description

Technical Field

[0001] This invention relates to a semiconductor memory device integrating a Not OR (NOR) type flash memory and a resistance-varying type memory, and a writing method thereof. Background Technology

[0002] NOR flash memory is a non-volatile memory that has a memory cell configured between the bit line and the source line, and can perform random access to the memory cell.

[0003] On the other hand, as a non-volatile memory that replaces NOR-type flash memory, a resistance-changing memory that utilizes a variable resistor element stores data by applying a pulse voltage to the variable resistor element, making the variable resistor element reversibly and non-volatilely change to a high resistance state or a low resistance state. Summary of the Invention

[0004] Unlike NOR flash memory, resistive variable memory does not require erasure, so data can be rewritten at low voltage. However, the size of the memory cell in resistive variable memory is smaller than that of NOR memory cell. If the integration density is increased, the cost-performance ratio will decrease.

[0005] The purpose of this invention is to provide a semiconductor memory device that can achieve low power consumption and high integration.

[0006] The semiconductor memory device of the present invention includes: a memory cell array, a first memory cell array having a resistance-varying memory structure and a second memory cell array having a NOR flash memory structure formed on the same substrate; a plurality of global bit lines extending along the column direction of the memory cell array and shared by the first memory cell array and the second memory cell array; and a read / write control unit for reading and writing selected memory cells of the first memory cell array or the second memory cell array, wherein the read / write control unit applies a set write voltage to the selected memory cell using a write voltage charged to the selected global bit line.

[0007] In one embodiment, the semiconductor memory device further includes a connection component that selectively connects a plurality of global bit lines to the first memory cell array at the boundary between the first and second memory cell arrays. The connection component applies a set-write voltage to the selected memory cell based on the voltage charged to the selected global bit line. In one embodiment, after the read / write control unit charges the selected global bit line, it makes the selected global bit line float, and the connection component electrically connects the floating selected global bit line to a local bit line. In one embodiment, the connection component includes a plurality of transistors that connect a global bit line to a plurality of local bit lines, and the connection component connects the selected global bit line to the selected local bit line by turning on the selected transistor, the transistor generating a set-write voltage. In one embodiment, a clamping voltage for generating the set-write voltage is applied to the gate of the selected transistor, and the voltage charged to the selected global bit line is greater than the clamping voltage. In one embodiment, the memory cell includes a variable resistor element and an access transistor connected to the variable resistor element, the gate of the access transistor being connected to a word line, and a set-write voltage is applied to the variable resistor element when the access transistor is turned on. In one embodiment, when the read / write control unit performs a reset write to the selected memory cell, it applies a reset write voltage to the source line and applies a ground (GND) level to the selected global bit line.

[0008] The writing method of the present invention is a writing method for a semiconductor memory device. The semiconductor memory device includes: a memory cell array, a first memory cell array having a resistance-varying memory structure and a second memory cell array having a NOR flash memory structure formed on the same substrate; and a plurality of global bit lines extending along the column direction of the memory cell array and shared by the first memory cell array and the second memory cell array. When a set write is performed on a selected memory cell of the first memory cell array, the selected global bit line is charged, and then the set write voltage is applied to the selected memory cell using the voltage charged to the selected global bit line.

[0009] In one embodiment, with the transistor connecting the global bit line to the local bit line turned off, the global bit line is charged. Then, by turning on the transistor, the global bit line is electrically connected to the local bit line, thereby applying a set write voltage to the selected memory cell. In another embodiment, a clamping voltage for generating the set write voltage is applied to the gate of the transistor, and the voltage charged to the global bit line is greater than the clamping voltage.

[0010] The effects of the invention

[0011] According to the present invention, the memory cell array includes a first memory cell array having a resistance-varying memory structure and a second memory cell array having a NOR flash memory structure, thereby achieving high integration and low power consumption in the semiconductor memory device. Furthermore, by utilizing the voltage charged to the global bit line for setting and writing of the resistance-varying memory, power consumption can be reduced. Attached Figure Description

[0012] Figure 1 This is a diagram illustrating the overall structure of a non-volatile memory according to an embodiment of the present invention;

[0013] Figure 2A , 2B This is a schematic diagram illustrating the structure of a storage cell array according to an embodiment of the present invention;

[0014] Figure 3 This is a circuit diagram of a portion of a NOR-type memory cell array according to an embodiment of the present invention;

[0015] Figure 4 This is a circuit diagram of a portion of a resistance-varying memory cell array according to an embodiment of the present invention;

[0016] Figure 5 This is a schematic partial cross-sectional view of a NOR-type memory cell array according to an embodiment of the present invention;

[0017] Figure 6 This is a schematic partial cross-sectional view of a resistance-variable memory cell array according to an embodiment of the present invention;

[0018] Figure 7 This is a flowchart illustrating the write operation of a resistance-varying memory according to an embodiment of the present invention;

[0019] Figure 8 This is a diagram showing examples of operating waveforms of various parts of a resistance-varying memory according to an embodiment of the present invention;

[0020] Figure 9 This is a table showing an example of the bias voltage during operation of a resistive variable type memory in an embodiment of the present invention.

[0021] Explanation of symbols

[0022] 100: Non-volatile memory (non-volatile semiconductor memory)

[0023] 110: Memory cell array

[0024] 110A: NOR array (first memory cell array)

[0025] 110B: Resistance Variation Array (Second Memory Cell Array)

[0026] 110C: Entering the gate

[0027] 110D: Sector Selection Grille

[0028] 120: Address Buffer

[0029] 130: Gate Selection Circuit

[0030] 140: Word Line Decoder

[0031] 150: Y Decoder

[0032] 160: Input / Output Circuit

[0033] 170: Read / Write Control Department

[0034] 200: P-well region

[0035] GBL0~GBLm: Global Bit Line

[0036] LBL0~LBL3: Local bit lines

[0037] Ma, Mb, MC0, MC1: Storage units

[0038] Q0~Q3: Transistors

[0039] SEL_Q[0:3], SEL_P[0:3]...SEL_1[0:3], SEL_0[0:3]: Select signal lines

[0040] SEL0~SEL3: Select signal lines

[0041] SL00, SL01, SLQ0~SLQk: Source lines

[0042] S_LBL0~S_LBL3: Sacrifice local bit lines

[0043] S100, S110, S120, S130, S140, S150, S160, S170: Steps

[0044] t1~t5: Time points

[0045] V0~V3: Contact through holes

[0046] V GBL Select the voltage of the global bit line GBL.

[0047] V LBL Select the voltage of the local bit line LBL.

[0048] Vp: Writing charging voltage

[0049] VR0, VR1, VR2: Variable resistive elements

[0050] V SET Set write voltage

[0051] V SL Select the voltage of the source line SL.

[0052] V WL Select the voltage of the word line.

[0053] V WRITE Write pulse voltage (write voltage)

[0054] WL00~WL0n, WL10~WL1n, WLQ0~WLQj, WLP0~WLPn: Word lines Detailed Implementation

[0055] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings. The semiconductor memory device of the present invention integrates a memory cell array having a NOR flash memory structure and a memory cell array having a resistance-varying memory structure on a common substrate.

[0056] Example

[0057] Next, details of the non-volatile memory according to an embodiment of the present invention will be described. Figure 1 This is a block diagram showing the overall structure of the non-volatile memory 100 of this embodiment. As shown in this figure, the non-volatile memory 100 is constructed by integrating, for example, a memory cell array 110, an address buffer 120, a sector / gate selection circuit 130, a word line decoder 140, a Y decoder 150, an input / output circuit 160, and a read / write control unit 170 on a substrate such as silicon. Each part is connected via an internal bus capable of transmitting and receiving address, data, control signals, etc. The main structure is shown in this figure; voltage generation circuits, etc., are omitted.

[0058] The memory cell array 110 includes: a first memory cell array (hereinafter referred to as the NOR array) 110A having a NOR flash memory structure; and a second memory cell array (hereinafter referred to as the resistance-varying array) 110B having a resistance-varying memory structure. Compared with the resistance-varying array 110B, the NOR array 110A can achieve higher integration, and compared with the NOR array 110A, the resistance-varying array 110B can achieve lower power operation.

[0059] Figure 2AThis is a schematic plan view illustrating the structure of a memory cell array. The memory cell array 110 includes a NOR-type array 110A and a resistance-variable array 110B along the column direction. The memory size of the NOR-type array 110A or the resistance-variable array 110B is not particularly limited; for example, the NOR-type array 110A is 16MB and the resistance-variable array 110B is 1Mb.

[0060] NOR array 110A includes multiple sectors (or blocks) 0, 1, ... P along the column direction as erase units. Each sector includes an LBL selection gate 110D, which selects a local bit line LBL extending along the column direction within the sector. An entry gate 110C is formed between the last sector P of NOR array 110A and resistance-varying array 110B. The entry gate 110C selects a local bit line extending along the column direction within resistance-varying array 110B and, when NOR array 110A is accessed, causes resistance-varying array 110B to separate from NOR array 110A.

[0061] Multiple global bit lines GBL0, GBL1, GBL2, ..., GBLm (collectively referred to as global bit lines GBL) are formed along the column direction of the memory cell array 110. The global bit lines GBL are connected to the LBL selection gate 110D of each sector of the NOR array 110A and to the entry gate 110C. That is, the global bit lines GBL are shared by the NOR array 110A and the resistance-variable array 110B.

[0062] Figure 2B Is Figure 2A The plan view shows the word lines and select signal lines. Multiple word lines are formed along the row direction of the memory cell array 110. Word lines WL00 to WL0n are formed along the row direction of sector 0, word lines WL10 to WL1n are formed along the row direction of sector 1, similarly, word lines WLP0 to WLPn are formed along the row direction of sector P, and word lines WLQ0 to WLQj are formed along the row direction of the resistance-varying array 110B.

[0063] For the LBL select gate 110D of sector 0, a 4-bit select signal line SEL_0[0:3] is supplied from the sector / gate select circuit 130; for the LBL select gate 110D of sector 1, a select signal line SEL_1[0:3] is supplied; similarly, for the LBL select gate 110D of sector P, a select signal line SEL_P[0:3] is supplied; and for the entry gate 110C, a select signal line SEL_Q[0:3] is supplied. As described later, the sector / gate select circuit 130 selects a sector of the NOR array 110A or a resistance-variable array 110B by a portion of the row address (the upper bit), supplying a select signal line to the LBL select gate 110D corresponding to the selected sector or resistance-variable array 110B, or supplying a select signal line to the entry gate 110C.

[0064] Figure 3 The diagram shows a portion of the circuit structure for sector 0. Figure 4 The diagram shows a portion of the circuit structure of the gate 110C and the resistance-varying array 110B. (See diagram for reference.) Figure 3 As shown, the LBL selection gate 110D extends along the row direction to divide a global bit line GBL into four local bit lines LBL0 to LBL3. That is, m global bit lines GBL are divided into m×4 lines by the LBL selection gate 110D.

[0065] Four NMOS transistors Q0, Q1, Q2, and Q3 are connected in parallel between a global bit line GBL and four local bit lines LBL0 to LBL3. A row-extending select signal line SEL0 is connected to the gates of transistors Q0, SEL1 to SEL2 to SEL3 to SEL3 to SEL3 to SEL4 to Q3.

[0066] The sector / gate selection circuit 130 selects a sector according to the upper bit of the row address, and drives any one of the selection signal lines SEL_0[0:3] connected to the LBL selection gate 110D of the sector selected according to the column address to a high level (H), and drives the remaining selection signal lines to a low level (L). For example, if the selection signal line SEL0 is driven to a high level (H), and the remaining selection signal lines SEL1 to SEL3 are driven to a low level (L), then the m transistors Q0 of the LBL selection gate 110D are turned on, and the m global bit lines GBL are selectively connected to the corresponding m local bit lines LBL0. On the other hand, transistors Q1 to Q3 are turned off, and the local bit lines LBL1 to LBL3 are separated from the global bit lines.

[0067] Within each sector, multiple memory cells are formed in a matrix. The drain regions of adjacent memory cells along the column direction are connected together and connected to the local bit line. Furthermore, the gates of memory cells in the row direction are connected together to the word line in the row direction, and the source regions of memory cells in the row direction are connected together to the source line in the row direction. For example, the gates of memory cells MC0 and MC1 are connected to word lines WL00 and WL01, the common drain region of memory cells MC0 and MC1 is connected to the local bit line LBL0, the source region of memory cell MC0 is connected to the source line SL00, and the source region of memory cell MC1 is connected to the source line SL01. The sector / gate selection circuit 130 selects the source line of the sector selected according to the column address and applies an operating voltage to the source line selected by the read / write control unit 170.

[0068] The memory cell, for example, includes an oxide-nitride-oxide (ONO) film on the substrate surface, which functions as an accumulation region for trapping charge, and includes a conductive gate such as polysilicon or metal thereon. The memory cell can be programmed, for example, by trapping hotelectons generated when current flows between the source and drain regions into the ONO film. However, alternatively, charge can also be trapped into the ONO film via Fowler-Nordheim (FN) tunneling. The trapped charge can be erased, for example, via FN tunneling or hot hole injection.

[0069] Figure 5 The diagram shows a schematic cross-section of memory cells MC0 and MC1 in the column direction. Within a P-type silicon substrate or P-well region 200, memory cells MC0 and MC1 are formed in an active region formed by field oxide or trench isolation. The gates of memory cells MC0 and MC1 constitute word lines WL00 and WL01 in the row direction. The drain regions of memory cells MC0 and MC1 are shared and electrically connected to a localized bit line LBL0 in the column direction via a via contact V0. The source regions of memory cells MC0 and MC1 are electrically connected to source lines SL00 and SL01 in the row direction via a via contact V1. In this example, the source lines are formed by a conductive layer on the substrate, but this is not a limitation; source lines can also be formed by an embedded diffusion region within the substrate. In this case, the source regions of the memory cells in the row direction are interconnected.

[0070] Furthermore, in the active region adjacent to the memory cell MC0, a transistor Q0 forms the LBL select gate 110D. The gate of transistor Q0 constitutes the row-direction select signal line SEL0, the drain region is electrically connected to the column-direction global bit line GBL0 via contact via V2, and the source region is electrically connected to the local bit line LBL0 via contact via V0.

[0071] The multiple local bit lines LBL0 to LBL3 formed by the LBL selection gate 110D are connected to the common drain region of the last memory cell WL0n-1 and memory cell WL0n in sector 0, and terminate here. Other sectors 1 to P are constructed in the same way as sector 0.

[0072] Next, the entry gate 110C will be described. The entry gate 110C is as follows... Figure 2A , Figure 2B As shown, the boundary between the last sector P of the NOR array 110A and the resistance variation array 110B is formed. The gate 110C is composed of transistors Q0 to Q3 of the same size as the gate width and gate length of the LBL select gate 110D. However, unlike the LBL select gate 110D, it is connected to the global bit line GBL by dividing a global bit line GBL into two local bit lines LBL0 and LBL1.

[0073] Figure 4 The circuit structure of a portion of the entry gate 110C and the resistance-varying array 110B is shown. The entry gate 110C includes transistors Q0 to Q3 connected in parallel between a global bit line GBL and four sacrificial local bit lines S_LBL0 to S_LBL3. At the gates of transistors Q0 to Q3, select signal lines SEL_Q[0:3] from the sector / gate select circuit 130 are connected.

[0074] Local bit line LBL0 is formed by short-circuiting the sacrificial local bit line S_LBL0 and its adjacent sacrificial local bit line S_LBL1, and local bit line LBL1 is formed by short-circuiting the sacrificial local bit line S_LBL2 and its adjacent sacrificial local bit line S_LBL3.

[0075] With this structure, the spacing between local bit lines LBL0 / LBL1 of the resistance-varying array 110B is twice that of the spacing between local bit lines LBL0 / LBL1 and LBL2 / LBL3 of the NOR array 110A. Furthermore, since two transistors are connected in parallel on each local bit line leading to the gate 110C, the current that can be supplied to a local bit line of the resistance-varying array 110B is twice that that can be supplied to a local bit line of the NOR array 110A. The reason for making the spacing between the local bit lines of the resistance-varying array 110B larger than that of the NOR array 110A is that the size of the resistance-varying memory cell is difficult to reduce to the size of a NOR memory cell. Moreover, the reason for increasing the current supplied to the local bit lines of the resistance-varying array 110B is that the maximum current flowing through the resistance-varying memory cell (e.g., tunneling hot electron current) may be approximately twice that of the maximum current flowing through the NOR memory cell.

[0076] In the resistance-variable array 110B, multiple memory cells are formed in a matrix. Each memory cell comprises an access transistor and a variable resistor. The gates of the access transistors in the row direction are connected to the word line in the row direction, and the source regions of a pair of adjacent access transistors in the column direction are connected to the corresponding source line. One electrode of the variable resistor is connected to the drain region of the access transistor, and the other electrode of the variable resistor is connected to the local bit line. For example, the gates of memory cells MC0 and MC1 are connected to word lines WLQ0 and WLQ1, the common source region of memory cells MC0 and MC1 is connected to the source line SLQ0, the drain region of memory cell MC0 is connected to the local bit line LBL0 via the variable resistor, and the drain region of memory cell MC1 is connected to the local bit line LBL0 via the variable resistor.

[0077] Variable resistance elements, such as thin-film oxides containing transition metals like hafnium oxide (HfOx), are set or reset according to the polarity and magnitude of the write pulse voltage. For example, a variable resistance element is set to a low-resistance state when current flows from the bit line side to the source line side, and reset to a high-resistance state when current flows from the source line side to the bit line side.

[0078] Figure 6The diagram shows a schematic cross-section of memory cells MC0 and MC1 along the column direction. Within a P-type silicon substrate or P-well region 200, memory cells MC0 and MC1 are formed in an active region isolated by a field oxide film or trench. The gates of the access transistors of memory cells MC0 and MC1 form word lines WLQ0 and WLQ1 in the row direction, respectively. The common source region of the access transistors is electrically connected to the source line SLQ0 in the row direction via a contact via V1. The drain region of the access transistor of memory cell MC0 is connected to a variable resistor element VR0 via a contact via V1, and furthermore, the variable resistor element VR0 is electrically connected to the local bit line LBL0 in the column direction via a contact via V3. The drain region of the access transistor of memory cell MC1 is connected to the variable resistor element VR1 via a contact via V1, and furthermore, the variable resistor element VR1 is electrically connected to the local bit line LBL0 via a contact via V3.

[0079] In the active region adjacent to the memory cell MC0, a transistor Q0 is formed that enters the gate 110C. The gate of transistor Q0 forms the row direction selection signal line SEL0, the drain region is electrically connected to the global bit line GBL0 via the contact via V2, and the source region is electrically connected to the local bit line LBL0 via the contact via V0.

[0080] The storage cell array 110 is formed by a multi-layer wiring structure, but as Figure 5 , Figure 6 As shown, it is understood that the resistance variation array 110B and the entry gate 110C are structures compatible with the NOR array 110A.

[0081] Refer again Figure 1 Address buffer 120 receives addresses from the address bus (not shown) and provides the received row and column addresses to sector / gate selection circuit 130 and Y decoder 150. Sector / gate selection circuit 130 selects a sector or entry gate 110C based on the row address, driving the selection signal lines SEL0 to SEL3 of the sector or entry gate 110C selected based on the column address to H or L levels. Furthermore, sector / gate selection circuit 130 applies an operating voltage to the source lines of the sector or resistance-varying array 110B selected according to the column address. This operating voltage is controlled by read / write control unit 170.

[0082] The Y decoder 150 selects global bit lines GBL0 to GBLm based on the column address. For the selected global bit line GBL, the read voltage, programming voltage, erase voltage, etc. are applied according to the control of the read / write control unit 170.

[0083] The word line decoder 140 receives the row address from the address buffer 120 and selects the word line WL based on the decoding result of the received row address. For word line selection, read voltage, programming (write) voltage, erase voltage, etc., are supplied according to the control of the read / write control unit 170. Furthermore, when all data in the memory cells within a sector of the NOR array 110A is erased, all word lines within the sector are selected.

[0084] The input / output circuit 160 outputs data read from the memory cell array 110 to an external terminal, or writes data received from the external terminal to the memory cell. Furthermore, it provides the address received from the external terminal to the address buffer 120 and provides commands to the read / write control unit 170.

[0085] The read / write control unit 170 includes, for example, a state machine or microcontroller, a read amplifier (S / A), a write amplifier (W / A), etc., and controls the overall operation of the non-volatile memory 100. The read / write control unit 170 interprets the commands received from the input / output circuit 160 and performs read, write, and erase operations based on the interpretation results.

[0086] The read / write control unit 170 can also control the read and write operations of the resistance-varying array 110B based on commands used for the NOR flash memory. However, in a resistance-varying memory, there is no concept of erasure. Therefore, the read / write control unit 170 recognizes access to the resistance-varying array 110B from a row address, and upon receiving an erase command, the resistance-varying array 110B performs a data overwrite that sets all memory cells to data "1". Of course, the user can also input the commands used when accessing the NOR array 110A and the commands used when accessing the resistance-varying array 110B separately into the non-volatile memory 100.

[0087] Next, the operation of the non-volatile memory 100 in this embodiment will be described.

[0088] Read the action:

[0089] When commands and addresses are read from external terminals, the word line decoder 140 selects the word line according to the row address, and the sector / gate selection circuit 130 selects the sector or the entry gate 110C based on the row address. It drives the selection signal lines SEL0 to SEL3 of the LBL selection gate 110D or the selection signal lines SEL0 to SEL3 of the entry gate 110C for the selected sector, and selects the source SL according to the column address. The Y decoder 150 selects the global bit line according to the column address. During access to the NOR array 110A, the sector / gate selection circuit 130 sets the entry gate 110C to non-select (all selection signal lines SEL0 to SEL3 are at L level), thus separating the resistance-varying array 110B from the NOR array 110A.

[0090] For example, in Figure 3 When the memory cell Ma is selected, a read voltage is applied to the select word line WL01, and GND is supplied to the source line SL01. Furthermore, the LBL select gate 110D drives the select signal line SEL2 to a high level, turning on transistor Q2. The Y decoder 150 selects the global bit line GBL0, and the read / write control unit 170 applies a read voltage to the global bit line GBL0. The memory cell Ma is turned on / off by a threshold corresponding to the stored data, and the read amplifier senses the voltage or current of the global bit line GBL0.

[0091] Moreover, in Figure 4 When the memory cell Mb shown is selected, a read voltage is applied to the select word line WLQ1, the access transistor is turned on, and GND is supplied to the source line SLQ0 selected by the sector / gate selection circuit 130. Furthermore, the sector / gate selection circuit 130 drives the select signal line SEL2 entering the gate 110C to a high level, turning on transistor Q2. The Y decoder 150 selects the global bit line GBL0, and the read / write control unit 170 applies a read voltage to the global bit line GBL0. Depending on whether the variable resistor element is in a low-resistance state or a high-resistance state, the current flowing from the global bit line GBL0 to the source line SLQ0 differs, and this voltage or current is sensed by the read amplifier.

[0092] Write action:

[0093] When writing data "0" to memory cell Ma of NOR array 110A, read / write control unit 170 applies a write voltage to select word line WL02, applies a write voltage to the selected global bit line GBL0, and applies GND to the selected source line SL01. Conversely, when writing data "0" to memory cell Mb of resistive variable array 110B, write voltage is applied to select word line WLQ2 to turn on the access transistor, a write voltage is applied to the selected global bit line GBL0, and GND is applied to the selected source line SLQ1. Details regarding the write operation to resistive variable array 110B will be described later.

[0094] Erasing action:

[0095] When erasing a sector of the NOR array 110A, all word lines of the selected sector are selected, and GND is applied to the selected word lines. Furthermore, the sector / gate selection circuit 130 turns off all transistors Q0 to Q3 of the selected LBL selection gate 110D, sets local bit lines LBL0 to LBL3 to a floating state, and applies an erase voltage to all source lines within the selected sector. As a result, a high voltage is applied between the gate and source regions of all memory cells within the sector, causing electrons in the memory cells to escape to the source side, lowering the threshold voltage of the memory cell, and changing the data to "1".

[0096] On the other hand, in the case of the resistance-variable array 110B, the word line decoder 140 selects all word lines of the resistance-variable array 110B, turning on all access transistors. Entering the gate 110C turns on all transistors Q0 to Q3, connecting all local bit lines LBL0 and LBL1 to the global bit line GBL. The read / write control unit 170 applies GND to the global bit line GBL, to which data "1" should be written to all variable resistance elements, and the sector / select gate 130 applies a write voltage to the source lines SLQ1 to SLQk.

[0097] Thus, according to this embodiment, when the NOR array 110A and the resistance-varying array 110B are integrated on the memory cell array 110, by setting an entry gate 110C at the boundary between the NOR array 110A and the resistance-varying array 110B, it is possible to prevent stress caused by unwanted voltage from affecting the resistance-varying array 110B via the global bit line GBL, etc., when the NOR array 110A is running.

[0098] Moreover, by incorporating both the NOR array 110A and the resistance-variable array 110B, it is possible to combine the advantages of high integration brought by the NOR array 110A with the advantages of low-power operation brought by the resistance-variable array 110B.

[0099] In the described embodiment, the LBL select gate 110D divides a global bit line into four local bit lines, but this is just one example; the number of local bit lines divided from a global bit line is arbitrary. Furthermore, the spacing between the local bit lines divided by the entry gate 110C is set to be twice the spacing between the local bit lines divided by the LBL select gate 110D, but this is just one example; the spacing between the local bit lines divided by the entry gate 110C only needs to be greater than the spacing between the local bit lines divided by the LBL select gate 110D. Furthermore, the size of the transistor entering the gate 110C is made equal to the size of the transistor in the LBL select gate, but this is just one example; the gate width of the transistor entering the gate 110C can also be greater than the gate width of the transistor in the LBL select gate 110D.

[0100] Next, the write operation of the resistance-varying array 110B in this embodiment will be described. The variable resistance element of the resistance-varying memory is, for example, a thin film oxide containing a transition metal such as hafnium oxide (HfOx), which is set or reset according to the polarity and magnitude of the write pulse voltage. When a set write pulse is applied, a filament-like current path is formed between the electrodes of the variable resistance element, and the variable resistance element becomes a low resistance state (LRS). On the other hand, when a reset write pulse of different polarity is applied, the filament between the electrodes of the variable resistance element breaks or decreases, and the variable resistance element becomes a high resistance state (HRS).

[0101] Regarding the operating current characteristics of this type of variable resistor element, it is known that when the variable resistor element is set, if the application time of the set write pulse is prolonged, excessive current flows through the variable resistor element, causing it to return to the reset state. This is because the continuous current flowing through the filament formed between the electrodes can cause the filament to break. Therefore, ideally, it is desirable that the application of the set write voltage should stop immediately upon setting the variable resistor element. Conversely, when the variable resistor element is reset, if the reset write voltage is continuously applied after reset, it may sometimes return to the set state. Therefore, it is desirable that the application of the reset write voltage should stop immediately upon reset.

[0102] In existing set-write operations, a set-write pulse voltage with a predefined pulse width is applied to the local bit line. However, it is not easy to ensure a consistent pulse width when the variable resistor element is in a low-resistance state. Therefore, in this embodiment, instead of applying a set-write pulse voltage as in the past, the selected global bit line is charged with voltage during the preset set operation. In subsequent set operations, the voltage charged to the selected global bit line is used to perform the set-write operation on the variable resistor element.

[0103] Figure 7 The flowchart illustrates the write operation of the resistance-varying memory in this embodiment. When the read / write control unit 170 receives a command from the outside (S100), it determines whether the command is a set write to the resistance-varying array 110B (S110). If it is a command other than a set write, the read / write control unit 170 executes the command using a normal method (S120).

[0104] When a set write command is executed, the read / write control unit 170 charges the global selection bit line GBL with the write charging voltage Vp from the write amplifier (W / A) as a preset operation (S130). At this time, all transistors Q0 to Q3 that enter the gate 110C and the LBL selection gate 110D are turned off, and the global selection bit line GBL is separated from the resistance-varying array 110B and the NOR array 110A.

[0105] A write amplifier is connected to one end of each of the multiple global bit lines (GBLs). The write amplifier supplies a write charging voltage Vp to the selected global bit line (GBL) at regular intervals, thereby charging the selected global bit line (GBL) with the write charging voltage Vp (the voltage of the global bit line V). GBL =Vp). Select the voltage V of the global bit line GBL. GBL (=Vp) is greater than the set / write voltage V applied to the variable resistor element. SET Larger. By integrating the NOR-type array 110A and the resistance-variable array 110B along the column direction of the memory cell array 110, the wiring length of the global bit line GBL in the column direction becomes larger, and the capacitance also becomes larger accordingly. Therefore, the global bit line GBL can be charged with sufficient power to set and write the variable resistance element.

[0106] After charging the global selection bit line GBL, the read / write control unit 170 disconnects the write amplifier from the global selection bit line GBL (for example, by turning off the transistor connected between the write amplifier and the global bit line), causing the global selection bit line GBL to float (S140). Thus, the voltage V charged to the global selection bit line GBL... GBL It was then used as the current source during set writes.

[0107] Next, the read / write control unit 170 turns on the selected transistor entering the gate 110C (S150), electrically connecting the global selection bit line GBL to the local selection bit line LBL. At this time, a set write voltage V is applied to the gate of the selected transistor. SET +Vth (the threshold voltage of the transistor), the transistor having a voltage for generating the set write voltage V. SET The throttling function. Therefore, the voltage V of the local bit line LBL is selected. LBL = Set / Write Voltage VSET .

[0108] On the other hand, the word line decoder 140 applies a write voltage to the selection word line WL, turning on the access transistor of the selection memory cell, and the sector / gate selection circuit 130 supplies GND to the selection source line corresponding to the selection memory cell. Thus, a set write voltage (V) is applied to the variable resistor element of the selection memory cell. LBL =V SET The variable resistor element is set by writing a voltage V as the bias voltage. SEL The set write operation ends when the variable resistor element transitions from the high resistance state (HRS) to the low resistance state (LRS) (S160). When the variable resistor element transitions to the low resistance state (LRS), the remaining voltage of the global selection bit line GBL is discharged to the selection source line all at once through the low resistance state variable resistor element (S170).

[0109] Thus, because the voltage charged to the global select bit line (GBL) discharges almost autonomously in response to the variable resistor element switching to a low-resistance state, the situation where current continues to flow through the variable resistor element beyond what is necessary, as was the case with conventional write pulses, is avoided after the variable resistor element is set. As a result, the current flowing through the variable resistor element after setting is reduced, thereby improving the reliability of set writes. At the same time, unnecessary current consumption during set writes is suppressed.

[0110] Next, we will... Figure 4 The waveforms of each part during the set-write operation of the selected memory cell Mb are illustrated in the figure. Figure 8 middle. Figure 9 This represents an example of the bias voltage (V) during various operating cycles of a resistive variable memory. LBL =Select the voltage, V of the local bit line LBL GBL =Select the voltage, V of the global bit line GBL SL = Select the voltage, V of the source line SL WL = Select word line voltage).

[0111] exist Figure 8 In this context, time t1 to time t2 is the preset period, and time t3 to time t5 is the set / write period. During the period from time t1 to time t2, the write amplifier of the read / write control unit 170 charges the global selection bit line GBL0 with a write charging voltage Vp. The write charging voltage Vp is, for example, 5V.

[0112] Next, at time t2, the read / write control unit 170 disconnects the write amplifier from the global selection bit line GBL0, making the global selection bit line GBL0 a floating state.

[0113] Next, at time t3, the read / write control unit 170 turns on transistor Q2, which enters gate 110C. A set write voltage V is applied to the gate of transistor Q2. SET +Vth. Set write voltage V SET For example, it is 2V. Therefore, the voltage V of the local bit line LBL1 is... LBL And the supply set / write voltage V SET On the other hand, a write voltage V is supplied to the select word line WLQ2. WRITE The voltage V of the select word line WL The access transistor for memory cell Mb is turned on. Write pulse voltage V WRITE For example, 2V. Applying GND to the non-select word line turns off the access transistor of the non-select memory cell. Furthermore, the voltage V, which serves as the source selection line SLQ1, is... SL And GND is applied. The non-selective source pole line is floating.

[0114] Thus, a set / write voltage V is applied to the variable resistor element that selects the memory cell Mb. SET The bias voltage is applied. The variable resistor element, through the application of the bias voltage, transitions from a high-resistance state (HRS) to a low-resistance state (LRS) at time t4. Since the variable resistor element becomes low-resistance, the remaining voltage of the global select bit line GBL0 discharges to the select source line SLQ1 via the local bit line LBL1, the variable resistor element, and the access transistor. Subsequently, at time t5, the voltage V of the select word line WLQ2... WL Once it becomes GND, the set-write operation ends. The time required for a set-write of the selected memory cell (Mb), including the default value, is approximately less than 100ns.

[0115] During the reset write operation for selecting memory cell Mb, a GND level is supplied to the global selection bit line GBL0 as a default setting. In subsequent reset write operations, transistor Q2, which enters gate 110C, is turned on, and the local bit line LBL1 becomes GND. A write voltage V is applied to the selection word line WLQ2. R_WRITE (e.g., 3V) Apply a reset write voltage V to the selected source line SLQ1. RESET (e.g., 2V) is used as the source voltage V SL .

[0116] Thus, in the variable resistor element that selects memory cell Mb, current flows from the selection source line SLQ1 towards the selection global bit line GBL0, and the variable resistor element transitions from a low resistance state (LRS) to a high resistance state (HRS). When the variable resistor element is in the high resistance state, the voltage V on the local bit line LBL1... LBLWhen the voltage drops to GND, transistor Q2 becomes non-conductive, and the global selection bit line GBL0 becomes floating. The time required for a reset write to the selected memory cell Mb, including the preset time, is approximately less than 100 ns. Thus, the reset write operation can also end almost autonomously in response to the variable resistor element switching to a high-resistance state.

[0117] Thus, according to the writing method of this embodiment, since the global bit line is charged with voltage and the set write is performed using the charged voltage, the set write time can be autonomously controlled, improving the reliability of the set write. Furthermore, when using a charge pump to generate the desired internal voltage from an externally supplied voltage, it is expected that unnecessary charge pump operation will be reduced, which allows for an increase in the number of bits that can be set / reset written in a single operation.

[0118] Preferred embodiments of the present invention have been described in detail, but the present invention is not limited to specific embodiments. Various modifications and alterations can be made within the scope of the spirit of the present invention as set forth in the claims.

Claims

1. A semiconductor memory device, comprising: A memory cell array, comprising a first memory cell array having a resistance-variable memory structure and a second memory cell array having a NOR flash memory structure, formed on the same substrate; Multiple global bit lines, extending along the column direction of the memory cell array, are shared by the first memory cell array and the second memory cell array; and The read / write control unit performs read and write operations on selected memory cells in the first or second memory cell array. The read / write control unit uses a write voltage charged to the global selection bit line to apply a set write voltage to the selected memory cell in the first memory cell array. The selected memory cell includes a variable resistor element. The write voltage switches the variable resistor element to a low resistance state, and the global selection bit line discharges the remaining voltage to the selection source line through the low resistance state of the variable resistor element.

2. The semiconductor memory device according to claim 1, wherein, The semiconductor memory device further includes a connection component that selectively connects the plurality of global bit lines to the first memory cell array at the boundary between the first memory cell array and the second memory cell array. The connection component applies the set write voltage to the selected memory cell based on the voltage charged to the selected global bit line.

3. The semiconductor memory device according to claim 2, wherein, After charging the selected global bit line, the read / write control unit causes the selected global bit line to become a floating state. The connecting component electrically connects the selected global bit line in the floating state to the local bit line.

4. The semiconductor memory device according to claim 3, wherein, The connection component includes multiple transistors that connect one global bit line to multiple local bit lines respectively, and The connection component connects the selected global bit line to the selected local bit line by turning on the selected transistor. The transistor generates the set write voltage.

5. The semiconductor memory device according to claim 4, wherein, A clamping voltage is applied to the gate of the selected transistor to generate the set write voltage, and the voltage at which the selected global bit line is charged is greater than the clamping voltage.

6. The semiconductor memory device according to claim 1, wherein, The memory cell further includes an access transistor connected to the variable resistor element, the gate of which is connected to the word line. When the access transistor is turned on, the set write voltage is applied to the variable resistor element.

7. The semiconductor memory device according to claim 1, wherein, When the read / write control unit performs a reset write to the selected memory cell, it applies a reset write voltage to the source line and applies a ground level to the selected global bit line.

8. A writing method, which is a writing method for a semiconductor memory device, the semiconductor memory device comprising: A memory cell array, comprising a first memory cell array having a resistance-variable memory structure and a second memory cell array having a NOR flash memory structure, formed on the same substrate; And multiple global bit lines, extending along the column direction of the memory cell array, shared by the first memory cell array and the second memory cell array. When a set write is performed on a selected memory cell in the first memory cell array, the select global bit line is charged. Then, the voltage charged to the select global bit line is used to apply a set write voltage to the selected memory cell in the first memory cell array. The selected memory cell includes a variable resistance element. The write voltage switches the variable resistance element to a low resistance state. The select global bit line discharges the remaining voltage to the select source line through the low resistance state of the variable resistance element.

9. The writing method according to claim 8, wherein, With the transistor that connects the global selection bit line to the local selection bit line turned off, the global selection bit line is charged. Then, by turning on the transistor, the global selection bit line is electrically connected to the local selection bit line, thereby applying the set write voltage to the selected memory cell.

10. The writing method according to claim 9, wherein, A clamping voltage is applied to the gate of the transistor to generate the set write voltage, and the voltage at which the selected global bit line is charged is greater than the clamping voltage.

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