Memory storage devices and their operation methods

Abstract

This invention provides a memory storage device and its operating method. The memory storage device includes a memory circuit and a memory controller. The memory circuit is used to store data. The memory controller is coupled to the memory circuit via a bus. The memory controller performs initial settings on the memory circuit in units of bus width.

Description

Technical Field

[0001] This invention relates to a memory storage device and its operation method. Background Technology

[0002] Electronic devices typically include non-volatile memory storage devices and volatile memory storage devices. The non-volatile memory storage devices store many important system settings. Upon power-on, the memory controller must read the system settings from the non-volatile memory storage devices and store them in external volatile memory storage devices for subsequent operations.

[0003] In existing technologies, memory cells typically require multiple NAND gates to receive setting and reset signals for initial setup. Therefore, the overall area of ​​the memory circuit is relatively large. Summary of the Invention

[0004] The memory storage device of the present invention includes a memory circuit and a memory controller. The memory circuit is used to store data. The memory controller is coupled to the memory circuit via a bus. The memory controller performs initial settings on the memory circuit in units of the bus width.

[0005] The operation method of the memory storage device of the present invention includes: receiving initial setting data via a bus; and performing initial settings on the memory circuit in units of the bus width.

[0006] Based on the above, in the embodiments of the present invention, the memory controller performs initial settings on the memory circuit in units of bus width, which can improve the efficiency of initial settings, simplify the architecture of the memory cell, and reduce the overall area occupied by the memory circuit. Attached Figure Description

[0007] The accompanying drawings are included to provide a further understanding of this disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0008] Figure 1 A schematic diagram of a memory storage device according to an embodiment of the present invention is shown;

[0009] Figure 2 A schematic diagram of a memory storage device according to another embodiment of the present invention is shown;

[0010] Figure 3 Show Figure 2 A schematic circuit diagram of the decoder in the embodiment;

[0011] Figure 4 Show Figure 2 A schematic circuit diagram of the memory cell in the embodiment;

[0012] Figure 5 This diagram illustrates the waveforms of various operation signals during the initial setup of a memory storage device according to an embodiment of the present invention.

[0013] Figure 6 A waveform diagram illustrating the initial setting data and initial setting signal according to an embodiment of the present invention is shown.

[0014] Figure 7 A flowchart illustrating the operation method of a memory storage device according to an embodiment of the present invention is shown.

[0015] [Explanation of Symbols]

[0016] 100, 200: Memory storage devices

[0017] 110: Memory controller

[0018] 120: Memory Circuit

[0019] 122: Memory cell

[0020] 124, 127_7: Memory cell group

[0021] 230: Decoder Circuit

[0022] 232, 232_0, 232_7: Decoders

[0023] 300: Digital Logic Circuits

[0024] 310: NAND gate

[0025] 320: NOT gate

[0026] 410: First Switch

[0027] 420: Second switch

[0028] 430: Buffer circuit

[0029] 900: Bus

[0030] DIO: Initial setting data

[0031] POD: Power-on complete signal

[0032] POR: Power-on reset signal

[0033] R: Read control signals

[0034] RB, WB: Inverted signals

[0035] T1: Power-on process

[0036] T2: Initial Setting Period

[0037] V1, V2, V3: Voltage signals

[0038] VDD: System voltage

[0039] W: Write control signal

[0040] WB_POR: Initial setting signal Detailed Implementation

[0041] Figure 1 A schematic diagram of a memory storage device according to an embodiment of the present invention is shown. Please refer to... Figure 1 The memory storage device 100 in this embodiment includes a memory controller 110 and a memory circuit 120. The memory circuit 120 is used to store data DIO to be written. The memory controller 110 is coupled to the memory circuit 120 via a bus 900. The memory controller 110 performs initial settings on the memory circuit 120 in units of the width of the bus 900.

[0042] For example, the width of bus 900 is, for instance, N bits, indicating that N bits of data can be written to memory circuit 120 at a time, where N is an integer greater than 1. In one embodiment, N equals 4. Therefore, memory controller 110 can simultaneously initialize N (e.g., 4) memory cells in memory circuit 120.

[0043] Specifically, electronic devices typically include non-volatile memory storage devices and volatile memory storage devices. In this embodiment, the memory storage device 100 is, for example, a volatile memory storage device within the electronic device. The non-volatile memory storage device stores many important system setting parameters. Before the power-on sequence of the electronic device is executed, the memory storage device 100 requires these system setting parameters as initial values ​​to facilitate subsequent operations. Therefore, the first setting performed on the memory storage device 100 before the power-on sequence is executed is the initial setting. Furthermore, the initial setting is completed before the power-on sequence is executed.

[0044] During the initial setup process, the memory controller 110 reads system setting parameters from the non-volatile memory storage device and stores them in the memory circuit 120. These system setting parameters include relevant parameters required for memory operations, such as the voltage setting and read time of the memory storage device 100. In other words, the initial setup involves setting parameters required for write operations to the memory circuit 120, and these parameters include, for example, voltage settings and read times.

[0045] In this embodiment, the memory controller 110 can be a processor with computing capabilities. Alternatively, the memory controller 110 can be a hardware circuit designed using a Hardware Description Language (HDL) or any other digital circuit design method well known to those skilled in the art, and implemented using a Field Programmable Gate Array (FPGA), Complex Programmable Logic Device (CPLD), or Application-Specific Integrated Circuit (ASIC).

[0046] Figure 2 A schematic diagram illustrating a memory storage device according to another embodiment of the present invention is shown. Please refer to... Figure 2 The memory storage device 200 of this embodiment includes a memory controller 110, a memory circuit 120, and a decoder circuit 230. In this embodiment, the memory circuit 120 includes a plurality of memory cells 122. For example, the width of the bus 900 is, for example, 4 bits, indicating that the bus 900 can transmit 4 bits in parallel at one time to perform read and write operations on 4 memory cells 122 simultaneously. Each group of 4 memory cells 122 is divided into groups, and the memory controller 110 initializes a group of memory cells (hereinafter referred to as memory cell group 124) at a time, that is, initializes 4 bits each time. Each memory cell group 124 is read and written by the memory controller 110 through the bus 900.

[0047] Decoder circuit 230 is coupled to memory circuit 120. Decoder circuit 230 includes multiple decoders 232. Decoder 232 initializes memory circuit 120 according to initial setting signal WB_POR. In this embodiment, decoder circuit 230 includes eight decoders 232_0 to 232_7. Each memory cell group 124 corresponds to one decoder 232. For example, memory cell group 124_7 corresponds to decoder 232_7. Decoder 232_7 decodes initial setting signal WB_POR to output control signals for reading and writing operations of memory cell group 124_7. Initial setting signal WB_POR is a decoding control signal that resets memory cell group at predetermined cycles. This reset operation is completed before power-on reset operation.

[0048] Figure 3 Show Figure 2 A schematic circuit diagram of the decoder in this embodiment. Please refer to... Figure 3The decoder 232 includes a digital logic circuit 300 formed by multiple logic gates and having decoding functionality. In this embodiment, the digital logic circuit 300 includes multiple NAND gates 310_1, 310_2, 310_3 and NOT gates 320_1, 320_2, 320_3, whose coupling relationship is as follows: Figure 3 As shown.

[0049] The output of the first NAND gate 310_1 is coupled to the first input of the third NAND gate 310_3. The output of the third NAND gate 310_3 is coupled to the input of the third NOT gate 320_3. The second and third inputs of the second NAND gate 310_2 are coupled to the second and third inputs of the first NAND gate 310_1, respectively. The output of the second NAND gate 310_2 is coupled to the input of the first NOT gate 320_1. The output of the first NOT gate 320_1 is coupled to the input of the second NOT gate 320_2.

[0050] The first NAND gate 310_1 receives the first control signal SELIN, the second control signal DECA, and the third control signal DECB at its first, second, and third input terminals, respectively. It performs an inverse AND operation on these signals and outputs the result from its output terminal to the third NAND gate 310_3. The third NAND gate 310_3 receives the result from its first NAND gate 310_1 and the initial setting signal WB_POR at its first and second input terminals, respectively. It performs an inverse AND operation on these signals and outputs the result from its output terminal as a write control signal W. Furthermore, the third NAND gate 310_3 also outputs the write control signal W from its output terminal to the third NOT gate 320_3. The input of the third NOT gate 320_3 receives the write control signal W, performs an inversion operation on the write control signal W, and outputs an inverted signal WB from the output of the third NOT gate 320_3.

[0051] The first, second, and third input terminals of the second NAND gate 310_2 receive the fourth control signal SELOUT, the second control signal DECA, and the third control signal DECB, respectively. The second NAND gate performs an inverse operation on these signals and outputs the result from its output terminal to the first NOT gate 320_1. The first NOT gate 320_1 receives the result from the second NAND gate 310_2, inverts it, and outputs the result as the read control signal R. Furthermore, the first NOT gate 320_1 also outputs the read control signal R from its output terminal to the second NOT gate 320_2. The second NOT gate 320_2 receives the read control signal R, inverts it, and outputs the inverted signal RB.

[0052] Therefore, decoder 232 decodes the initial setting signal WB_POR according to the control signals SELIN, SELOUT, DECA, and DECB to output a read control signal R and its inverted signal RB, and a write control signal W and its inverted signal WB. The read control signal R and its inverted signal RB are used to control the data read operation of the memory cell 122. The write control signal W and its inverted signal WB are used to control the data write operation of the memory cell 122. In other words, decoder 232 outputs either the read control signal R or the write control signal W according to the initial setting signal WB_POR to control the data read or data write operation of the memory cell 122.

[0053] Figure 4 Show Figure 2 A schematic circuit diagram of the memory cell in this embodiment. Please refer to... Figure 4 The memory cell 122 includes a first switch 410, a second switch 420, and a register circuit 430. The register circuit 430 is used to store data DIO written to the memory cell 122. The first switch 410 is coupled to the register circuit 430. The first switch 410 is controlled by a write control signal W and its inverted signal WB to control the data DIO to be written to the memory cell. The second switch 420 is coupled to the register circuit 430. The second switch 420 is controlled by a read control signal R and its inverted signal RB to control the data DIO to be read from the memory cell 122. In this embodiment, the first switch 410 and the second switch 420 are implemented, for example, as transmission gates.

[0054] In existing technologies, memory cells typically require multiple NAND gates for initial setup, resulting in a larger memory circuit area. In this embodiment, the memory cell 122 does not require additional NAND gates to receive the initial setup control signal; therefore, the cell structure can be optimized. Figure 4 As shown, the area of ​​the memory circuit 120 can be reduced.

[0055] Figure 5 This diagram illustrates the waveforms of various operation signals during the initial setup of a memory storage device according to an embodiment of the present invention. Please refer to... Figure 1 and Figure 5 Before the electronic device performs the power-on process T1, the memory storage device 100 performs initial settings during the initial setting period T2.

[0056] Specifically, before the electronic device initiates the power-on process T1, the memory storage device 100 receives the system voltage VDD and generates voltage signals V1, V2, and V3 required for the power-on process T1. After the voltage signals V1, V2, and V3 are generated, the power-on reset signal POR is pulled high to initiate the power-on process T1. Then, when the power-on done signal POD is pulled high, it indicates that the power-on process T1 has been completed. Therefore, the power-on process T1 is defined by the power-on reset signal POR and the power-on done signal POD.

[0057] Figure 6 This diagram illustrates the waveforms of initial setting data and initial setting signals according to an embodiment of the present invention. Please refer to... Figure 1 and Figure 6 Taking an initial setup data DIO with 16 entries as an example, the write time for each entry can reach nearly 7 microseconds (µs). In this embodiment, as long as the data packet of the initial setup signal WB_POR is aligned with the corresponding data in the initial setup data DIO in terms of timing, all initial values ​​can be written to the memory circuit 120 during the initial setup period T2. In this embodiment, the data of the initial setup signal WB_POR is 4 bits of data represented in hexadecimal.

[0058] Figure 7 A flowchart illustrating the operation method of a memory storage device according to an embodiment of the present invention is provided. Please refer to... Figure 1 and Figure 7 The operation method of this embodiment is at least applicable to Figure 1 The present invention includes a memory storage device 100, but is not limited thereto. Figure 1Taking the memory storage device 100 as an example, in step S100, the memory controller 110 receives initial setting data DIO through the bus 900. In step S110, the memory controller 110 performs initial settings on the memory circuit 120 in units of the width of the bus 900. Additionally, the operation method of this embodiment can be derived from... Figures 1 to 6 Sufficient teaching, advice and implementation instructions are provided in the description of the embodiments.

[0059] In summary, in the embodiments of the present invention, the memory controller performs initial settings on the memory circuit in units of bus width before the power-on process, which improves the efficiency of initial settings. Furthermore, the memory cell does not require additional NAND gates to receive setting and reset signals for initial settings, simplifying the memory cell architecture and reducing the overall area occupied by the memory circuit.

[0060] It will be understood by those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of this disclosure. In view of the foregoing, this disclosure is intended to cover any modifications and variations falling within the scope of the foregoing claims and their equivalents.

Claims

1. A memory storage device, comprising: A memory circuit for storing data, the memory circuit comprising multiple memory cells, with each N memory cells grouped into a cluster; as well as A memory controller is coupled to the memory circuit via a bus, wherein the memory controller performs initial settings on the memory circuit in units of the width of the bus, wherein the width of the bus is N bits, and the memory controller performs the initial settings on a group of memory cells at a time, wherein N is an integer greater than 1.

2. The memory storage device according to claim 1, further comprising: A decoder circuit is coupled to the memory circuit. The decoder circuit includes multiple decoders, wherein each group of memory cells corresponds to one decoder, and the multiple decoders perform the initial setting on the memory circuit according to the initial setting signal.

3. The memory storage device according to claim 2, wherein the plurality of decoders output a read control signal or a write control signal according to the initial setting signal to control the data read operation or data write operation of the plurality of memory cells.

4. The memory storage device according to claim 3, wherein each memory cell comprises: A buffer circuit is used to store the data written to the memory cell; A first switch is coupled to the cache circuit, wherein the first switch is controlled by the write control signal to control the data to be written to the memory cell; as well as A second switch is coupled to the cache circuit, wherein the second switch is controlled by the read control signal to control the data to be read from the memory cell.

5. The memory storage device according to claim 3, wherein each of the decoders comprises a first NAND gate, a second NAND gate, a third NAND gate, a first NOT gate, a second NOT gate, and a third NOT gate, wherein... The first input terminal, the second input terminal, and the third input terminal of the first NAND gate respectively receive the first control signal, the second control signal, and the third control signal, and perform an inverse operation on the first control signal, the second control signal, and the third control signal, and output the operation result from the output terminal of the first NAND gate to the third NAND gate; The first and second input terminals of the third NAND gate respectively receive the operation result output by the first NAND gate and the initial setting signal, and perform an inverse operation on the operation result output by the first NAND gate and the initial setting signal, and output the operation result from the output terminal of the third NAND gate as the write control signal. The third NAND gate also outputs the write control signal from the output terminal of the third NAND gate to the third NOT gate. as well as The input terminal of the third NOT gate receives the write control signal, performs an inversion operation on the write control signal, and outputs the inverted signal of the write control signal from the output terminal of the third NOT gate.

6. The memory storage device according to claim 5, wherein The first input terminal, the second input terminal, and the third input terminal of the second NAND gate respectively receive the fourth control signal, the second control signal, and the third control signal, and perform an inverse operation on the control signals, the fourth control signal, the second control signal, and the third control signal, and output the operation result from the output terminal of the second NAND gate to the first NOT gate; The input of the first NOT gate receives the operation result output by the second NAND gate, inverts the operation result output by the second NAND gate, and outputs the operation result from the output of the first NOT gate as the read control signal. The first NOT gate also outputs the read control signal from its output to the second NOT gate. The input terminal of the second NOT gate receives the read control signal, performs an inversion operation on the read control signal, and outputs the inverted signal of the read control signal from the output terminal of the second NOT gate.

7. The memory storage device according to claim 1, wherein the initial setting ends before a power-on process is executed, and the power-on process is defined by a power-on reset signal and a power-on completion signal.

8. The memory storage device according to claim 1, wherein the initial settings are parameters required for a write operation to the memory circuit, and the parameters required for the operation include voltage settings and read time.

9. A method of operating a memory storage device, wherein the memory storage device includes a memory circuit, and the memory circuit includes a plurality of memory cells, the method comprising: Receive initial setup data via bus; Divide the memory cells into groups of N, where N is an integer greater than 1; The memory circuit is initially configured using the width of the bus as the unit, wherein the width of the bus is N bits; and The initial settings are performed on a group of memory cells at a time.

10. The method of operating the memory storage device according to claim 9, wherein, In the step of initializing the memory circuit in units of the width of the bus, the initialization of the memory circuit is performed based on the initialization signal.

11. The method of operating the memory storage device according to claim 10, further comprising: Based on the initial setting signal, output a read control signal or a write control signal to control the data read operation or data write operation of the plurality of memory cells.

12. The method of operating the memory storage device according to claim 9, wherein the initial setting ends before the power-on process is executed, and the power-on process is defined by a power-on reset signal and a power-on completion signal.

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