memory devices

Abstract

This invention provides a memory device. The memory device includes a configuration memory array and a controller. The configuration memory array includes multiple flash memory strings coupled in parallel to each other. Each of the multiple flash memory strings includes multiple dummy memory cells and a single-bit trimmed memory cell. The trimmed memory cell stores operational data for the memory device. In the same flash memory string, the trimmed memory cell is connected in series between two of the multiple dummy memory cells. The controller performs a near-zero voltage read operation on the multiple trimmed memory cells to read the operational data.

Description

Technical Field

[0001] This invention relates to the field of memory, and more particularly to a memory device capable of storing at least operational data for a memory device. Background Technology

[0002] Generally, memory devices require access data to initiate a boot process. This access data is stored in other memory elements. However, taking ETOX flash memory as an example, current memory devices require a read voltage of 5 volts after power-on to read access data. Therefore, the read operation time is extended. Furthermore, the memory elements used to store the access data must have high reliability to ensure the memory device can perform the intended boot operation based on the correct access data. Therefore, shortening the read operation time and ensuring the memory device performs the correct boot operation are key research areas for those skilled in the art. Summary of the Invention

[0003] The present invention provides a memory device that can shorten the time of read operations and ensure that the memory device performs a correct boot operation.

[0004] The memory device of the present invention includes a setting memory array and a controller. The setting memory array includes a plurality of flash memory strings coupled in parallel to each other. Each of the plurality of flash memory strings includes a plurality of dummy memory cells and a single-bit trimmed memory cell. The trimmed memory cell stores operational data for the memory device. In the same flash memory string, the trimmed memory cell is coupled in series between two of the plurality of dummy memory cells. The controller is coupled to the setting memory array. The controller performs near-zero voltage read operations on the plurality of trimmed memory cells of the setting memory array to read operational data.

[0005] Based on the above, the setting memory array of the present invention includes multiple flash memory strings coupled in parallel to each other. Each of the multiple flash memory strings includes multiple dummy memory cells and a single-bit trimmed memory cell. The controller performs a near-zero voltage read operation on the multiple trimmed memory cells of the setting memory array to read the operation data. In this way, the read operation time for the setting memory array can be shortened. Furthermore, within the same flash memory string, the trimmed memory cells are connected in series between the multiple dummy memory cells. This provides the multiple trimmed memory cells with high reliability.

[0006] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0007] Figure 1 This is a schematic diagram of a memory device illustrated according to an embodiment of the present invention.

[0008] Figure 2 This is a schematic diagram illustrating a configured memory array according to an embodiment of the present invention.

[0009] Figure 3 This is a schematic diagram illustrating the data state of a trimmed storage unit according to an embodiment of the present invention.

[0010] Figure 4 This is a schematic diagram of a memory device according to another embodiment of the present invention. Detailed Implementation

[0011] Some embodiments of the present invention will now be described in detail with reference to the accompanying drawings. Component symbols used in the following description are considered identical or similar when they appear in different drawings. These embodiments are only a part of the present invention and do not disclose all possible implementations of the invention. More precisely, these embodiments are merely examples as described in the claims of the present invention.

[0012] Please refer to Figure 1 , Figure 1This is a schematic diagram of a memory device according to an embodiment of the present invention. In this embodiment, the memory device 100 includes a main memory array 110, a setup memory array 120, and a controller 130. The main memory array 110 is a flash memory array. The main memory array 110 stores user data DTA. For example, the main memory array 110 can store user data DTA in response to the operation of the controller 130. The setup memory array 120 includes flash memory strings ST1 to STm. Flash memory strings ST1 to STm each include a plurality of dummy memory cells and a trimmed memory cell of a single bit. For example, flash memory string ST1 includes dummy memory cells D11 to D1n and trimmed memory cell T1. Flash memory string ST2 includes dummy memory cells D21 to D2n and trimmed memory cell T2. Similarly, flash memory string STm includes dummy memory cells Dm1 to Dmn and trimmed memory cell Tm. In this embodiment, trimmed memory cells T1 to Tm store operating data OD for the memory device 100. Therefore, the configuration memory array 120 is capable of storing m bits of operation data OD. Taking m=3 as an example, the operation data OD can be, for example, an operation program selection code. The configuration memory array 120 can, for example, store 8 different selection codes associated with different operation programs. Therefore, the controller 130 can perform the operation program corresponding to the selection code stored in the configuration memory array 120 (e.g., start the program of the main memory array 110). Since the trimming memory cells T1 to Tm are flash memory cells, the trimming memory cells T1 to Tm can be programmed at least multiple times.

[0013] In this embodiment, within the same flash memory string, trimmed storage cells are connected in series between two of the dummy storage cells. Taking flash memory string ST1 as an example, trimmed storage cell T1 is connected in series with dummy storage cells D11 to D1n, and is also coupled between dummy storage cells D11 and D12. That is, trimmed storage cell T1 is not the first or last bit storage cell of flash memory string ST1. It should be noted that the first or last bit storage cells of flash memory strings ST1 to STm are boundary storage cells located on the boundary of the defined memory array 120. Boundary storage cells have relatively poor reliability. Since trimmed storage cells T1 to Tm are not boundary storage cells, they are not affected by the boundary conditions of the defined memory array 120 itself. Therefore, trimmed storage cells T1 to Tm have high reliability.

[0014] In this embodiment, controller 130 is coupled to main memory array 110 and setting memory array 120. Controller 130 is operated to perform access operations on main memory array 110 and setting memory array 120. Controller 130 performs near-zero voltage value read operations on trimmed memory cells T1 to Tm of setting memory array 120 to read operation data OD. Therefore, controller 130 does not need to raise the voltage value of the read judgment voltage to a high voltage level (e.g., 5 volts) at startup. Controller 130 can perform read operations on setting memory array 120 at startup. In this way, the time length for read operations on setting memory array 120 can be shortened.

[0015] In this embodiment, the trimmed memory cells T1 to Tm are flash memory cells. By changing the process parameters, the intrinsic threshold voltage of the trimmed memory cells T1 to Tm can be reduced. These process parameters include, for example, the design of the well (e.g., a common well) and / or the doping concentration of the well. In this embodiment, the negative threshold voltage of the trimmed memory cells T1 to Tm corresponds to a first logic value. The positive threshold voltage of the trimmed memory cells T1 to Tm corresponds to a second logic value. The first logic value is different from the second logic value. Therefore, the controller 130 can perform read operations on the trimmed memory cells T1 to Tm using a judgment voltage with a low voltage value (e.g., 0 to 1.2 volts).

[0016] In this embodiment, the layout of the dummy memory cells and trimmed memory cells in the configuration memory array 120 is approximately equal to the layout of the memory cells in the main memory array 110. Therefore, the boundary layout rules of the configuration memory array 120 also conform to the boundary layout rules of the main memory array 110. As a result, the configuration memory array 120 does not require an additional photomask. Thus, the design cost of the photomask is reduced.

[0017] In this embodiment, the configuration memory array 120 may be located in the peripheral area of ​​the memory device 100 and is independent of the main memory array 110. That is, the configuration memory array 120 and the main memory array 110 are respectively located in different areas. Therefore, the configuration memory array 120 does not occupy the storage space of the main memory array 110.

[0018] To further explain the implementation details of configuring the memory array, please refer to [link / reference needed]. Figure 1 as well as Figure 2 , Figure 2This is a schematic diagram illustrating a configured memory array according to an embodiment of the present invention. The configured memory array 220 can be applied to the memory device 100. In this embodiment, the configured memory array 220 is exemplified by three flash memory strings ST1 to ST3. The number of flash memory strings in the present invention can be multiple, and is not limited to the number of flash memory strings ST1 to ST3 in this embodiment.

[0019] In the memory array 220, flash memory string ST1 is located in the first row. Flash memory string ST1 includes dummy memory cells D11 to D13 and trimmed memory cell T1. Flash memory string ST2 is located in the second row. Flash memory string ST2 includes dummy memory cells D21 to D23 and trimmed memory cell T2. Flash memory string ST3 is located in the third row. Flash memory string ST3 includes dummy memory cells D31 to D33 and trimmed memory cell T3. In this embodiment, dummy memory cells D11 to D13 and trimmed memory cell T1 are connected in series with each other. Trimmed memory cell T1 is coupled between dummy memory cells D12 and D13. Dummy memory cells D21 to D23 and trimmed memory cell T2 are connected in series with each other. Trimmed memory cell T2 is coupled between dummy memory cells D22 and D23. Dummy memory cells D31 to D33 and trimmed memory cell T3 are connected in series with each other. The modified storage unit T3 is coupled between the dummy storage units D32 and D33.

[0020] In this embodiment, the control terminals of trimmed memory cells T1 to T3 are all connected to the same word line WL. Therefore, trimmed memory cells T1 to T3 are arranged in the same row. In this way, the memory array 220 can be configured with only a single word line WL.

[0021] In this embodiment, the first terminal of trimmed memory cell T1 is electrically connected to bit line BL1 without passing through at least one of the dummy memory cells D11 to D13. The first terminal of trimmed memory cell T2 is electrically connected to bit line BL2 without passing through at least one of the dummy memory cells D21 to D23. The first terminal of trimmed memory cell T3 is electrically connected to bit line BL3 without passing through at least one of the dummy memory cells D31 to D33. For example, the first terminal of trimmed memory cell T1 is directly electrically connected to bit line BL1. The first terminal of trimmed memory cell T2 is directly electrically connected to bit line BL2. The first terminal of trimmed memory cell T3 is directly electrically connected to bit line BL3.

[0022] In this embodiment, the second terminals of trimmed memory cells T1, T2, and T3 are electrically connected to the source line CSL (or common source line) without passing through at least one of the dummy memory cells D11-D13, D21-D23, and D31-D33. For example, the second terminals of trimmed memory cells T1, T2, and T3 are directly electrically connected to the source line CSL. In this way, the memory array 220 can have only a single source line CSL. Based on the above configuration, the controller 130 can perform a one-time erase operation on trimmed memory cells T1-T3, and then perform a programming operation on the selected trimmed memory cells that need to be programmed.

[0023] It is worth mentioning that, based on the above configuration, the controller 130 uses the word line WL, source line CSL, and bit lines BL1-BL3 to perform at least one of the erase and programming operations on trimmed memory cells T1-T3. Furthermore, the controller 130 uses the word line WL, source line CSL, and bit lines BL1-BL3 to perform read operations only on trimmed memory cells T1-T3. In this way, this embodiment avoids read interference caused by the over-erase phenomenon of dummy memory cells D11-D13, D21-D23, and D31-D33.

[0024] In some embodiments, the second terminals of trimmed storage unit T1, trimmed storage unit T2, and trimmed storage unit T3 are electrically connected to different source lines.

[0025] Please also refer to Figure 1 as well as Figure 3 , Figure 3 This is a schematic diagram illustrating the data state of a trimmed storage unit according to an embodiment of the present invention. In this embodiment, the controller 130 can perform at least one of an erase operation and a programming operation on trimmed storage units T1 to Tm to store operation data OD on trimmed storage units T1 to Tm. The controller 130 provides a large erase voltage and maintains it for 0.1 seconds to 1 second to perform an erase operation on at least one of the trimmed storage units T1 to Tm. Therefore, the threshold voltage value Vt of the trimmed storage unit to which the erase operation is performed will be less than or equal to -1 volt. A voltage value Vt less than or equal to -1 volt can correspond to a first logic value LG1, such as logic "1". In this embodiment, the erase operation can be a one-shot strong erase operation. Therefore, the controller 130 does not need to perform an erase verification operation after the erase operation.

[0026] Furthermore, the controller 130 can adjust at least one of the trimmed memory cells T1 to Tm so that the threshold voltage value Vt of the trimmed memory cell to which the programming operation is performed is greater than or equal to 2 volts. The voltage value Vt greater than or equal to 2 volts can correspond to a second logic value LG2, such as logic "0".

[0027] In this embodiment, the controller 130 can use a low voltage value (e.g., 0 volts to a preset voltage value VDD) to perform a read operation on the trimmed memory cell. Taking a trimmed memory cell undergoing an erase operation as an example, since the threshold voltage value Vt of the trimmed memory cell undergoing the erase operation is less than or equal to -1 volt, the judgment voltage is sufficient to turn on the trimmed memory cell, thereby generating a read current value greater than a current threshold (approximately 10 to 15 microamperes, but this invention is not limited thereto). Therefore, the trimmed memory cell can be known to store data with a first logic value LG1 (e.g., logic "1").

[0028] Taking a trimmed memory cell undergoing programming as an example, since the threshold voltage Vt of the trimmed memory cell undergoing programming is greater than or equal to 2 volts, it is determined that the voltage cannot turn the trimmed memory cell on. During the read operation, the trimmed memory cell undergoing programming is turned off. The read current value then approaches 0. The read current value will be lower than the current threshold. Therefore, the trimmed memory cell can be known to have stored data with the second logic value LG2 (e.g., logic "0").

[0029] In this embodiment, the preset voltage value VDD can be 1.2 volts. That is, the current judgment voltage value can have a margin M of 1.2 volts. By changing the process parameters, the threshold voltage value Vt of the memory cell in different logic states can be changed. Therefore, the margin M of the judgment voltage value can be wider.

[0030] Please refer to Figure 4 , Figure 4 This is a schematic diagram of a memory device according to another embodiment of the present invention. In this embodiment, the memory device 300 includes a main memory array 310, a setting memory array 320, and a controller 330. Figure 1 Unlike the memory device 100 shown, the setting memory array 320 is a subarray partitioned from the main memory array 310. Implementation details of the setting memory array 320 and the controller 330 can be found in [the following text is missing from the original] Figures 1 to 3 Sufficient teaching has been given to the various embodiments, and therefore they will not be repeated here.

[0031] In summary, the setting memory array of the present invention comprises multiple flash memory strings coupled in parallel to each other. Each of the multiple flash memory strings includes multiple dummy memory cells and a single-bit trimmed memory cell. The trimmed memory cell stores operation data for the memory device. The controller performs a near-zero voltage read operation on the multiple trimmed memory cells of the setting memory array to read the operation data. This shortens the read operation time for the setting memory array. Within the same flash memory string, the trimmed memory cells are coupled in series with the multiple dummy memory cells. Therefore, the trimmed memory cells are not affected by the boundary conditions of the setting memory array itself. This results in high reliability for the multiple trimmed memory cells. Furthermore, the memory device operates on the trimmed memory cells. Thus, the present invention avoids read interference caused by over-erasing of dummy memory cells.

[0032] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0033] [Symbol Explanation]

[0034] 100, 300: Memory devices

[0035] 110, 310: Main memory array

[0036] 120, 220, 320: Configure the memory array

[0037] 130, 330: Controller

[0038] BL1, BL2, BL3: Bit lines

[0039] CSL: Source Line

[0040] D11, D12, D13, D1n, D21, D22, D23, D2n, D31, D32, D33, Dm1, Dm2, Dmn: Virtual storage units

[0041] DTA: User Data

[0042] LG1: First logical value

[0043] LG2: Second logical value

[0044] M: Margin

[0045] OD: Operational Data

[0046] ST1, ST2, ST3, STm: Flash memory strings

[0047] T1, T2, T3, Tm: Adjusting storage units

[0048] VDD: Preset voltage value

[0049] Vt: Threshold voltage value

[0050] WL: Word Line

Claims

1. A memory device, comprising: A memory array is configured, comprising multiple flash memory strings coupled in parallel to each other, wherein each of the multiple flash memory strings comprises: Multiple virtual storage units; and A single-bit trimmed storage cell, configured to store operational data for the memory device, wherein, in the same flash memory string, the trimmed storage cell is serially coupled between two of the plurality of dummy storage cells; and A controller, coupled to the designated memory array, is configured to perform near-zero voltage read operations on a plurality of trimmed memory cells of the designated memory array to read the operation data.

2. The memory device according to claim 1, wherein: The negative threshold voltage values ​​of the plurality of trimmed memory cells correspond to the first logic value, and The positive threshold voltage values ​​of the plurality of trimmed memory cells correspond to the second logic value.

3. The memory device of claim 1, wherein the control terminals of the plurality of trimmed memory cells of the set memory array are commonly connected to the same word line.

4. The memory device according to claim 1, wherein: The first terminal of the first trimmed storage cell of the first flash memory string is electrically connected to the first bit line without passing through at least one of the plurality of dummy storage cells of the first flash memory string, and The first end of the second trimmed storage cell of the first flash memory string is electrically connected to the second bit line without passing through at least one of the plurality of dummy storage cells of the second flash memory string.

5. The memory device of claim 4, wherein the second end of the first trimmed memory cell and the second end of the second trimmed memory cell are electrically connected to the source line without passing through at least one of the plurality of dummy memory cells.

6. The memory device of claim 1, wherein the controller is further configured to perform at least one of an erase operation and a programming operation on the plurality of trimmed memory cells to cause the plurality of trimmed memory cells to store the operation data.

7. The memory device according to claim 6, wherein The erasure operation is a single-click strong erase operation, and The threshold voltage value of the trimmed memory cell to which the erase operation is performed is less than or equal to -1 volt.

8. The memory device of claim 6, wherein the threshold voltage value of the trimmed memory cell to which the programming operation is performed is greater than or equal to 2 volts.

9. The memory device according to claim 1, further comprising: Main memory array, configured to store user data. The layout of the plurality of dummy memory cells in the set memory array and the plurality of trimmed memory cells is approximately equal to the layout of the memory cells in the main memory array.

10. The memory device of claim 9, wherein the configured memory array is located in the peripheral region of the memory device and is independent of the main memory array.

11. The memory device of claim 9, wherein the configured memory array is a subarray partitioned from the main memory array.

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